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A B C D E

機密
1 1

Compal Confidential
2

HTW00 LA-2871 Schematics Document 2

Intel Dothan with 915PM(GM)/910GML + DDRII + ICH6M

(+VGA/B ATi M24C/M26P)


2005-08-22
3

REV: 1.0 3

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2005/08/22 Deciphered Date 2008/08/22 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Cover Sheet
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number R ev
1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
HTW00 M/B LA-2871
Date: Saturday, August 20, 2005 Sheet 1 of 41
A B C D E
A B C D E

Compal Confidential
Model Name : HTW00 Fan Control
page 4
Pentium-M/Celeron-M Processor
Thermal Sensor Clock Generator
File Name : LA-2871 uPGA-479 Package ADM1032ARM ICS 954226AG
page 4,5
1 page 4 page 13 1

H_A#(3..31) PSB H_D#(0..63)


LCD Conn. CRT & TV-out 400/533MHz
page 15 page 14
Memory BUS(DDRII) 200pin DDRII-SO-DIMM X2
Intel 915PM/GM, 910GML Dual Channel BANK 0, 1, 2, 3 page 11,12
ATI M24C/M26P 1.8V DDRII 400/533
with 64/128/256MB VGA/B Conn. uFCBGA-1257
page 6,7,8,9,10
VRAM page 15 PCI-Express
x16
LCD Conn. DMI x 4 New Card/B
Conn page 24
USB conn
page 32
PCI Express 2.5GHz
2 USB port 6 USB port 0, 2, 4 2
PCI BUS 3.3V 33 MHz Intel ICH6-M 3.3V 48MHz

IDSEL:AD18 IDSEL:AD17 IDSEL:AD20 3.3V 24.576MHz/48Mhz AC-Link


(PIRQ[G..H]#, (PIRQB#, (PIRQA#,B#,C#,D#, BGA-609
GNT#3/4, GNT#1, GNT#2, REQ#2) 3.3V ATA-100
REQ#3/4) REQ#1)
IDE
S-ATA
page 16,17,18,19
Mini PCI LAN TI Controller 1.5GHz
socket ODD AC97 Codec MDC Conn
RTL8100CL PCI7411/6411/4510 ALC250
page 26 page 21
page 22,23
Conn.page 20 page 27
page 27

S-ATA HDD
RJ45/RJ11 PCMCIA 5in1 Slot Conn. page 20 Audio AMP Audio/Mic
1394 3.3V 33 MHz
page 21
Conn. Slot 0 page 24 page 28
Jackpage 28
LPC BUS
page 23 page 25

3 RTC CKT. HTW00 Sub-board 3

page 19
ENE KB910Q
New Card/B
page 29 SW/B Conn. LS-2872
page 30
Power On/Off CKT.
page 33 New Card/FPC
Touch Pad Int.KBD LF-2873
page 31 page 30

DC/DC Interface CKT. SW/B


page 34 BIOS LS-2865
page 31

Power Circuit DC/DC VGA/B


LS-2871
page 34,35,36,37,38,39,40)

4 TP/B 4

LS-2866

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2005/08/22 Deciphered Date 2008/08/22 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Block Diagram
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number R ev
1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
HTW00 M/B LA-2871
Date: Monday, August 22, 2005 Sheet 2 of 41
A B C D E
A B C D E

SIGNAL
STATE SLP_S1# SLP_S3# SLP_S4# SLP_S5# +VALW +V +VS Clock
Voltage Rails
Full ON HIGH HIGH HIGH HIGH ON ON ON ON

Power Plane Description S1 S3 S5 S1(Power On Suspend) LOW HIGH HIGH HIGH ON ON ON LOW

VIN Adapter power supply (19V) N/A N/A N/A S3 (Suspend to RAM) LOW LOW HIGH HIGH ON ON OFF OFF
B+ AC or battery power rail for power circuit. N/A N/A N/A
1 S4 (Suspend to Disk) LOW LOW LOW HIGH ON OFF OFF OFF 1
+CPU_CORE Core voltage for CPU ON OFF OFF
+0.9VS 0.9V switched power rail for DDR terminator ON OFF OFF S5 (Soft OFF) LOW LOW LOW LOW ON OFF OFF OFF
+1.05VS 1.05V switched power rail ON OFF OFF
+1.5VALW 1.5V always on power rail ON ON ON*
+1.5VS 1.5V switched power rail ON OFF OFF Board ID / SKU ID Table for AD channel
+1.8V 1.8V power rail for DDR ON ON OFF Vcc 3.3V +/- 5%
+1.8VS 1.8V switched power rail ON OFF OFF Ra/Rc/Re 100K +/- 5%
+2.5VS 2.5V switched power rail ON OFF OFF Board ID Rb / Rd / Rf V AD_BID min V AD_BID typ V AD_BID max
+3VALW 3.3V always on power rail ON ON ON* 0 0 0 V 0 V 0 V
+3V 3.3V power rail ON ON OFF 1 8.2K +/- 5% 0.216 V 0.250 V 0.289 V
+3VS 3.3V switched power rail ON OFF OFF 2 18K +/- 5% 0.436 V 0.503 V 0.538 V
+5VALW 5V always on power rail ON ON ON* 3 33K +/- 5% 0.712 V 0.819 V 0.875 V
+5VS 5V switched power rail ON OFF OFF 4 56K +/- 5% 1.036 V 1.185 V 1.264 V
+12VALW 12V always on power rail ON ON ON* 5 100K +/- 5% 1.453 V 1.650 V 1.759 V
+RTCVCC RTC power ON ON ON 6 200K +/- 5% 1.935 V 2.200 V 2.341 V
2 7 NC 2.500 V 3.300 V 3.300 V 2

BOARD ID Table BTO Option Table


Note : ON* means that this power plane is ON only with AC power available, otherwise it is OFF.
Board ID PCB Revision BTO Item BOM Structure
External PCI Devices 0 0.1 VGA GM@
PM@
DEVICE PCI Device ID IDSEL # REQ/GNT # PIRQ 1
Card Reader 5IN1@
2
1394 D0 AD20 2 A,B,C,D Giga LAN 8100C@
3 8110S@
LAN D1 AD17 3 F
4 New Card NEWCARD@
C ARD BUS D4 AD20 2 A,B,C,D
5 IEEE1394 1394@
5IN1 D4 AD20 2 A,B,C,D
6 TV Tuner TUNER@
Mini-PCI D2 AD18 1 G,H
7 INT MIC. MIC@
KILL SW WLAN@
KB910 I2C / SMBUS ADDRESSING SKU ID Table CIR CIR@
3
DEVICE HEX ADDRESS HW EQ EQ@ 3

SKU ID SKU NOEQ@


SM1 24C16 A0H 1010000Xb 0
SM1 S MART BATTERY 16H 0001011Xb 1 (TBD)
SM2 ADM0132 98H 1001100Xb 2
CPU THERMAL MONITOR 3
SM2 GMT G781-1 9 AH 1001101Xb 4
VGA THERMAL MONITOR 5
6
ICH6M SM Bus address 7
Device Address

Clock Generator 1101 001Xb


( ICS 954226)

DDRII DIMM0 1001 000Xb


DDRII DIMM2 1001 010Xb

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2005/08/22 Deciphered Date 2008/08/22 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Notes
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number R ev
1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
HTW00 M/B LA-2871
Date: Saturday, August 20, 2005 Sheet 3 of 41
A B C D E
5 4 3 2 1

+3VS
1

1
H_D#[0..63] C212 R55
H_D#[0..63] 6
0.1U_0402_16V4Z @ 10K_0402_5%
2
1
JP18A C213

2
U6
H_A#[3..31] H_A#3 P4 A19 H_D#0 2200P_0402_50V7K THERMDA 2 1
6 H_A#[3..31]
H_A#4
H_A#5
U4
A3#
A4#
Dothan D0#
D1# A25 H_D#1
H_D#2
2
THERMDC
D+ VDD1
V3 A5# D2# A22 3 D- ALERT# 6
H_A#6 R3 B21 H_D#3
H_A#7 A6# D3# H_D#4
V2 A7# D4# A24 15,29 EC_SMB_CK2 8 SCLK THERM# 4
H_A#8 W1 B26 H_D#5
H_A#9 A8# D5# H_D#6
D T4 A9# D6# A21 15,29 EC_SMB_DA2 7 SDATA GND 5 D
H_A#10 W2 B20 H_D#7
H_A#11 A10# D7# H_D#8
Y4 A11# D8# C20
H_A#12 Y1 B24 H_D#9 ADM1032ARM_RM8
H_A#13 A12# D9# H_D#10
U1 A13# D10# D24
H_A#14 AA3 E24 H_D#11 +5VS
H_A#15 A14# D11# H_D#12
Y3 A15# D12# C26
H_A#16 AA2 B23 H_D#13
H_A#17 A16# D13# H_D#14
AF4 A17# D14# E23
H_A#18 AC4 C25 H_D#15 1
A18# D15#

1
H_A#19 AC7 H23 H_D#16 PU5B C480
A19# D16#

1
H_A#20 AC3 G25 H_D#17 5 LM358A_SO8 C D27
A20# D17# 29 EN_DFAN1 +
H_A#21 AD3 L23 H_D#18 7 FAN1_ON 1 2 2 Q36 10U_0805_10V4Z
H_A#22 A21# D18# H_D#19 0 P@ R378 100_0402_5% B 2
FMMT619_SOT23 1SS355_SOD323
AE4 A22# D19# M26 1 2 6 -
H_A#23 AD2 H24 H_D#20 R372 1 E

2
H_A#24 A23# D20# H_D#21 10K_0402_5%
AB4 A24# D21# F25
H_A#25 AC6 ADDR GROUP DATA GROUP G24 H_D#22 C484
A25# D22#

1
H_A#26 AD5 J23 H_D#23 0.1U_0402_16V4Z
H_A#27 A26# D23# H_D#24 2 D26
AE2 A27# D24# M23
H_A#28 AD6 J25 H_D#25 1 2 1N4148_SOT23
H_A#29 A28# D25# H_D#26 R373 8.2K_0402_5%
AF3 A29# D26# L26
H_A#30 AE1 N24 H_D#27 JP17

2
H_A#31 A30# D27# H_D#28 +FAN1_VOUT
AF1 A31# D28# M25 1
H26 H_D#29
H_REQ#[0..4] H_REQ#0 D29# H_D#30 2
6 H_REQ#[0..4] R2 REQ0# D30# N25 3
H_REQ#1 P3 K25 H_D#31 +3VS 1 2
H_REQ#2 REQ1# D31# H_D#32 R39 10K_0402_5% ACES_85205-0300
T2 REQ2# D32# Y26
H_REQ#3 P1 AA24 H_D#33
H_REQ#4 REQ3# D33# H_D#34
T1 REQ4# D34# T25 29 FANSPEED1 1
U23 H_D#35 1 @
D35# H_D#36 @ C145
6 H_ADSTB#0 U3 ADSTB0# D36# V23
AE5 R24 H_D#37 C144 1000P_0402_50V7K
C 6 H_ADSTB#1 ADSTB1# D37# 1000P_0402_50V7K 2 C
R26 H_D#38
D38# H_D#39 2
D39# R23
A16 AA23 H_D#40
ITP_CLK0 D40# H_D#41
A15 ITP_CLK1 D41# U26 Close to Fan Conn.
V24 H_D#42
D42# H_D#43
13 CLK_CPU_BCLK B15 BCLK0 D43# U25
B14 HOST CLK V26 H_D#44 +1.05VS
13 CLK_CPU_BCLK# BCLK1 D44#
Y23 H_D#45
D45# H_D#46 ITP_TDI R63 150_0402_1%
D46# AA26 2 1
Y25 H_D#47
D47# H_D#48 ITP_TDO R62
6 H_ADS# N2 ADS# D48# AB25 2 1 @ 54.9_0402_1%
L1 AC23 H_D#49
6 H_BNR# BNR# D49#
J3 AB24 H_D#50 H_CPURST# R61 2 1 @ 54.9_0402_1%
6 H_BPRI# BPRI# D50# H_D#51
6 H_BR0# N4 BR0# D51# AC20
L4 AC22 H_D#52 ITP_TMS R60 2 1 40.2_0402_1%
6 H_DEFER# DEFER# D52# H_D#53
6 H_D RDY# H2 DRDY# D53# AC25
K3 AD23 H_D#54 PRO_CHOT# R66 2 1 56_0402_5%
6 H_HIT# HIT# D54#
K4 CONTROL GROUP AE22 H_D#55
6 H_HITM# HITM# D55#
H_IERR# A4 AF23 H_D#56 H_PW RGOOD R56 2 1 200_0402_5%
IERR# D56# H_D#57
6 H_LOCK# J2 LOCK# D57# AD24
H_CPURST# B11 AF20 H_D#58 H_IERR# R57 2 1 56_0402_5%
6 H_CPURST# RESET# D58# H_D#59
D59# AE21
AD21 H_D#60 +3VS
H_RS#[0..2] H_RS#0 D60# H_D#61
6 H_RS#[0..2] H1 RS0# D61# AF25
H_RS#1 K1 AF22 H_D#62 ITP_DBRRESET# R59 2 1 @ 150_0402_1%
H_RS#2 RS1# D62# H_D#63
L2 RS2# D63# AF26
M3 ITP_TRST# R65 2 1 680_0402_5%
6 H_TRDY# TRDY#
D25 ITP_TCK R64 2 1 27.4_0402_1%
DINV0# H_DINV#0 6
DINV1# J26 H_DINV#1 6
C8 T24 TEST1 R58 2 1 @ 1K_0402_5%
B BPM0# DINV2# H_DINV#2 6 B
B8 BPM1# DINV3# AD20 H_DINV#3 6
A9 TEST2 R54 2 1 @ 1K_0402_5%
BPM2#
C9 BPM3#
DSTBN0# C23 H_DSTBN#0 6
ITP_DBRRESET# A7 K24
DBR# DSTBN1# H_DSTBN#1 6
M2 W25
6
17
H_DBSY#
H_DPSLP# B7
DBSY#
DPSLP#
DSTBN2#
DSTBN3# AE24
H_DSTBN#2
H_DSTBN#3
6
6
Reserve For Testability
17 H_DPRSLP# G1 DPRSTP# DSTBP0# C22 H_DSTBP#0 6
6 H_DPW R# C19 DPWR# DSTBP1# L24 H_DSTBP#1 6
A10 MISC W24 H_FERR# C204 1 2 180P_0402_50V8J
PRDY# DSTBP2# H_DSTBP#2 6
B10 PREQ# DSTBP3# AE25 H_DSTBP#3 6
PRO_CHOT# B17 H_CPUSLP# C210 1 2 180P_0402_50V8J
PROCHOT#
H_PW RGOOD E4 H_DPSLP# C211 1 2 180P_0402_50V8J
17 H_PW RGOOD PWRGOOD
H_CPUSLP# A6
6,17 H_CPUSLP# SLP#
ITP_TCK A13 H_STPCLK# C209 1 2 180P_0402_50V8J
ITP_TDI TCK H_A20M#
C12 TDI A20M# C2 H_A20M# 17
ITP_TDO A12 D3 H_INIT# C208 1 2 180P_0402_50V8J
TDO FERR# H_FERR# 17
TEST1 C5 A3
TEST1 IGNNE# H_IGNNE# 17
TEST2 F23 B5 H_SMI# C207 1 2 180P_0402_50V8J
TEST2 INIT# H_INIT# 17
ITP_TMS C11 D1 H_INTR
TMS LINT0 H_INTR 17
ITP_TRST# B13 D4 H_IG NNE# C206 1 2 180P_0402_50V8J
TRST# LINT1 H_NMI 17
LEGACY CPU
THERMAL H_NMI C205 1 2 180P_0402_50V8J
THERMDA B18 C6
THERMDC A18
THERMDA DIODE STPCLK#
B4
H_STPCLK# 17
H_PW RGOOD C203 1 2 180P_0402_50V8J
THERMDC SMI# H_SMI# 17
6,17 H_THERMTRIP# C17 THERMTRIP# H_A20M# C202 1 2 180P_0402_50V8J

TYCO_1612365-1_Dothan H_INTR C201 1 2 180P_0402_50V8J

A A

THERMDA & THERMDC Trace / Space = 10 / 10 mil

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2005/08/22 Deciphered Date 2008/08/22 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Dothan(1/2)
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number R ev
1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
HTW00 M/B LA-2871
Date: Saturday, August 20, 2005 Sheet 4 of 41
5 4 3 2 1
5 4 3 2 1

+CPU_CORE +CPU_CORE
JP18B JP18C
330U_D_2VM
R374 1 2 @ 54.9_0402_1% VCCSENSE AE7 A2 1 1 1 F20 T26
R375 1 @ 54.9_0402_1% VSSSENSE VCCSENSE VSS VCC VSS
2 AF6 VSSSENSE VSS A5 F22 VCC VSS U2
A8 + C498 + C521 + C188 G5 U6
VSS @ VCC VSS
VSS A11 G21 VCC VSS U22
F26 VCCA0 VSS A14 H6 VCC VSS U24
2 2 2
B1 VCCA1 VSS A17 H22 VCC VSS V1
N1 A20 330U_D_2VM 330U_D_2VM J5 V4
VCCA2 VSS VCC VSS
AC26 VCCA3 VSS A23 J21 VCC VSS V5
VSS A26 K22 VCC VSS V21
+1.05VS P23 VCCQ0 VSS B3 U5 VCC VSS V25
W4 B6 +CPU_CORE V6 W3
D VCCQ1 VSS VCC VSS D
VSS B9 V22 VCC VSS W6
B12 10U_0805_10V4Z 10U_0805_10V4Z 10U_0805_10V4Z W5 W22
D10 VCCP
Dothan VSS
VSS B16 1 1
C496
1
C494
1 1
C492
1 1 W21
VCC
VCC
VSS
VSS W23
D12 B19 Y6 W26
+1.5VS
D14
VCCP
VCCP
VSS
VSS B22
C497 C495 C493 C527
Y22
VCC
VCC
Dothan VSS
VSS Y2
D16 VCCP VSS B25 AA5 VCC VSS Y5
2 2 2 2 2 2 2
E11 VCCP VSS C1 AA7 VCC VSS Y21
20mils E13 C4 10U_0805_10V4Z 10U_0805_10V4Z 10U_0805_10V4Z 10U_0805_10V4Z AA9 Y24

POWER, GROUNG, RESERVED SIGNALS AND NC


VCCP VSS VCC VSS
1.5V FOR DOTHAN-B E15 VCCP VSS C7 AA11 VCC VSS AA1
F10 VCCP VSS C10 AA13 VCC VSS AA4
F12 C13 +CPU_CORE AA15 AA6
VCCP VSS VCC VSS
F14 VCCP VSS C15 AA17 VCC VSS AA8
1 1 F16 C18 10U_0805_10V4Z 10U_0805_10V4Z 10U_0805_10V4Z AA19 AA10
VCCP VSS VCC VSS
K6 VCCP VSS C21 1 1 1 1 1 1 1 AA21 VCC VSS AA12
L5 C24 C171 C173 C175 AB6 AA14
C536 C535 VCCP VSS VCC VSS
L21 VCCP VSS D2 AB8 VCC VSS AA16
2 2 C522 C172 C174 C195
M6 VCCP VSS D5 AB10 VCC VSS AA18
0.01U_0402_16V7K 2 2 2 2 2 2 2
M22 VCCP VSS D7 AB12 VCC VSS AA20
10U_0805_10V4Z N5 D9 10U_0805_10V4Z 10U_0805_10V4Z 10U_0805_10V4Z 10U_0805_10V4Z AB14 AA22
VCCP VSS VCC VSS
N21 VCCP VSS D11 AB16 VCC POWER, GROUND VSS AA25
P6 VCCP VSS D13 AB18 VCC VSS AB3
P22 D15 +CPU_CORE AB20 AB5
VCCP VSS VCC VSS
R5 VCCP VSS D17 AB22 VCC VSS AB7
R21 D19 10U_0805_10V4Z 10U_0805_10V4Z 10U_0805_10V4Z AC9 AB9
VCCP VSS VCC VSS
T6 VCCP VSS D21 1 1 1 1 1 1 1 AC11 VCC VSS AB11
T22 D23 C169 C191 C194 AC13 AB13
VCCP VSS VCC VSS
U21 VCCP VSS D26 AC15 VCC VSS AB15
E3 C170 C192 C193 C182 AC17 AB17
VSS 2 2 2 2 2 2 2 VCC VSS
VSS E6 AC19 VCC VSS AB19
D6 E8 10U_0805_10V4Z 10U_0805_10V4Z 10U_0805_10V4Z 10U_0805_10V4Z AD8 AB21
+CPU_CORE VCC VSS VCC VSS
D8 VCC VSS E10 AD10 VCC VSS AB23
C C
D18 VCC VSS E12 AD12 VCC VSS AB26
D20 E14 +CPU_CORE AD14 AC2
VCC VSS VCC VSS
D22 VCC VSS E16 AD16 VCC VSS AC5
E5 E18 10U_0805_10V4Z 10U_0805_10V4Z 10U_0805_10V4Z AD18 AC8
VCC VSS VCC VSS
E7 VCC VSS E20 1 1 1 1 1 1 1 AE9 VCC VSS AC10
E9 E22 C168 C499 C500 AE11 AC12
VCC VSS VCC VSS
E17 VCC VSS E25 AE13 VCC VSS AC14
E19 F1 C181 C196 C505 C504 AE15 AC16
VCC VSS 2 2 2 2 2 2 2 VCC VSS
E21 VCC VSS F4 AE17 VCC VSS AC18
F6 F5 10U_0805_10V4Z 10U_0805_10V4Z 10U_0805_10V4Z 10U_0805_10V4Z AE19 AC21
VCC VSS VCC VSS
F8 VCC VSS F7 AF8 VCC VSS AC24
F18 VCC VSS F9 AF10 VCC VSS AD1
F11 +CPU_CORE AF12 AD4
VSS VCC VSS
VSS F13 AF14 VCC VSS AD7
40 PSI# E1 F15 10U_0805_10V4Z 10U_0805_10V4Z 10U_0805_10V4Z AF16 AD9
PSI# VSS VCC VSS
VSS F17 1 1 1 1 1 1 1 AF18 VCC VSS AD11
+1.05VS E2 F19 C525 C523 C511 AD13
40 CPU_VID0 VID0 VSS VSS
40 CPU_VID1 F2 VID1 VSS F21 VSS AD15
F3 F24 C526 C524 C512 C197 AD17
40 CPU_VID2 VID2 VSS VSS
1

2 2 2 2 2 2 2
40 CPU_VID3 G3 VID3 VSS G2 VSS AD19
R382 G4 G6 10U_0805_10V4Z 10U_0805_10V4Z 10U_0805_10V4Z 10U_0805_10V4Z AD22
1K_0402_1% 40 CPU_VID4 VID4 VSS VSS
40 CPU_VID5 H4 VID5 VSS G22 M4 VSS VSS AD25
VSS G23 M5 VSS VSS AE3
G26 M21 AE6
2

GTL_REF0 VSS VSS VSS


1 2 AD26 GTLREF VSS H3 M24 VSS VSS AE8
R381 2K_0402_1% H5 Vcc-core C,uF ESR, mohm ESL,nH N3 AE10
VSS VSS VSS
TRACE 55ohm length< 0.5' VSS H21 Decoupling N6 VSS VSS AE12
13 CPU_BSEL0 C16 BSEL0 VSS H25 N22 VSS VSS AE14
13 CPU_BSEL1 C14 BSEL1 VSS J1 SPCAP,Polymer 2X330uF 7m ohm/2 3.5nH/2 N23 VSS VSS AE16
VSS J4 N26 VSS VSS AE18
COMP0 P25 J6 MLCC 0805 X5R 35X10uF 5m ohm/35 0.6nH/35 P2 AE20
B COMP1 COMP0 VSS VSS VSS B
P26 COMP1 VSS J22 P5 VSS VSS AE23
COMP2 AB2 J24 P21 AE26
COMP3 COMP2 VSS VSS VSS
AB1 COMP3 VSS K2 P24 VSS VSS AF2
VSS K5 R1 VSS VSS AF5
VSS K21 R4 VSS VSS AF9
VSS K23 R6 VSS VSS AF11
B2 RSVD VSS K26 R22 VSS VSS AF13
C3 RSVD VSS L3 R25 VSS VSS AF15
E26 RSVD VSS L6 T3 VSS VSS AF17
AF7 RSVD VSS L22 T5 VSS VSS AF19
AC1 RSVD VSS L25 T21 VSS VSS AF21
VSS M1 T23 VSS VSS AF24

TYCO_1612365-1_Dothan +1.05VS TYCO_1612365-1_Dothan

0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z


1 1
1 1 1 1 1 1 1 1 1 1
+ +
C502 C501 C176 C177 C178 C180 C184 C179 C183 C186 C187 C190
R384 1 2 27.4_0402_1% COMP0
2 2 2 2 2 2 2 2 2 2 2 2
R383 1 2 54.9_0402_1% COMP1
150U_D2_6.3VM 150U_D2_6.3VM 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z
R376 1 2 27.4_0402_1% COMP2

R377 1 2 54.9_0402_1% COMP3

TRACE CLOSELY CPU < 0.5'


A A
COMP0, COMP2 layout : Width 18mils and Space 25mils
COMP1, COMP3 layout : Space 25mils

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2005/08/22 Deciphered Date 2008/08/22 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Dothan(2/2)
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number R ev
1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
HTW00 M/B LA-2871
Date: Saturday, August 20, 2005 Sheet 5 of 41
5 4 3 2 1
5 4 3 2 1

H_RS#[0..2] +1.5VS
H_RS#[0..2] 4
H_A#[3..31]
4 H_A#[3..31] CLK_DREF_SSC R340 1 2 PM@ 0_0402_5%
H_REQ#[0..4] H_D#[0..63]
4 H_REQ#[0..4] H_D#[0..63] 4
CLK_DREF_SSC# R337 1 2 PM@ 0_0402_5%
U5A
U5B
H_A#3 G9 E4 H_D#0
H_A#4 C9
HA3#
HA4#
Alviso HD0#
HD1# E1 H_D#1
18 DMI_ITX_MRX_N0
DMI_ITX_MRX_N0 AA31 DMIRXN0 CFG0 G16 CFG0
H_A#5 E9 F4 H_D#2 DMI_ITX_MRX_N1 AB35 H13 MCH_CLKSEL1
HA5# HD2# 18 DMI_ITX_MRX_N1 DMIRXN1 CFG1 MCH_CLKSEL1 13
H_A#6 B7 H7 H_D#3 DMI_ITX_MRX_N2 AC31 G14 MCH_CLKSEL0
HA6# HD3# 18 DMI_ITX_MRX_N2 DMIRXN2 CFG2 MCH_CLKSEL0 13
H_A#7 A10 E2 H_D#4 DMI_ITX_MRX_N3 AD35 F16
HA7# HD4# 18 DMI_ITX_MRX_N3 DMIRXN3 CFG3
H_A#8 F9 F1 H_D#5 F15
D HA8# HD5# CFG4 D
H_A#9 D8 E3 H_D#6 DMI_ITX_MRX_P0 Y31 G15 CFG5 +1.05VS
HA9# HD6# 18 DMI_ITX_MRX_P0 DMIRXP0 CFG5
H_A#10 B10 D3 H_D#7 DMI_ITX_MRX_P1 AA35 E16 CFG6
HA10# HD7# 18 DMI_ITX_MRX_P1 DMIRXP1 CFG6
H_A#11 E10 K7 H_D#8 DMI_ITX_MRX_P2 AB31 D17 CFG7 CFG0 R363 1 2 10K_0402_5%
HA11# HD8# 18 DMI_ITX_MRX_P2 DMIRXP2 CFG7
H_A#12 G10 F2 H_D#9 DMI_ITX_MRX_P3 AC35 J16
HA12# HD9# 18 DMI_ITX_MRX_P3 DMIRXP3 CFG8
H_A#13 D9 J7 H_D#10 D15 CFG9
H_A#14 HA13# HD10# H_D#11 DMI_MTX_IRX_N0 CFG9
E11 HA14# HD11# J8 18 DMI_MTX_IRX_N0 AA33 DMITXN0 CFG10 E15
H_A#15 F10 H6 H_D#12 DMI_MTX_IRX_N1 AB37 D14 CFG5 R364 1 2 @ 1K_0402_5%
18 DMI_MTX_IRX_N1

DMI
H_A#16 HA15# HD12# H_D#13 DMI_MTX_IRX_N2 DMITXN1 CFG11 CFG12
G11 HA16# HD13# F3 18 DMI_MTX_IRX_N2 AC33 DMITXN2 CFG12 E14
H_A#17 G13 K8 H_D#14 DMI_MTX_IRX_N3 AD37 H12 CFG13 CFG6 R362 1 2 1K_0402_5%
HA17# HD14# 18 DMI_MTX_IRX_N3 DMITXN3 CFG13
H_A#18 C10 H5 H_D#15 C14
H_A#19 HA18# HD15# H_D#16 DMI_MTX_IRX_P0 CFG14 CFG7 R360 1 2 @ 1K_0402_5%

CFG/RSVD
C11 HA19# HD16# H1 18 DMI_MTX_IRX_P0 Y33 DMITXP0 CFG15 H15
H_A#20 D11 H2 H_D#17 DMI_MTX_IRX_P1 AA37 J15 CFG16
HA20# HD17# 18 DMI_MTX_IRX_P1 DMITXP1 CFG16
H_A#21 C12 K5 H_D#18 DMI_MTX_IRX_P2 AB33 H14 CFG9 R359 1 2 @ 1K_0402_5%
HA21# HD18# 18 DMI_MTX_IRX_P2 DMITXP2 CFG17
H_A#22 B13 K6 H_D#19 DMI_MTX_IRX_P3 AC37 G22 CFG18
HA22# HD19# 18 DMI_MTX_IRX_P3 DMITXP3 CFG18
H_A#23 A12 J4 H_D#20 G23 CFG19 CFG12 R361 1 2 @ 1K_0402_5%
H_A#24 HA23# HD20# H_D#21 CFG19
F12 HA24# HD21# G3 CFG20 D23
H_A#25 G12 H3 H_D#22 AM33 G25 CFG13 R369 1 2 @ 1K_0402_5%
HA25# HD22# 11 DDRA_CLK0 SM_CK0 RSVD21
H_A#26 E12 J1 H_D#23 AL1 G24
HA26# HD23# 11 DDRA_CLK1 SM_CK1 RSVD22
H_A#27 C13 L5 H_D#24 AE11 J17 CFG16 R358 1 2 @ 1K_0402_5%
H_A#28 HA27# HD24# H_D#25 SM_CK2 RSVD23
B11 HA28# HD25# K4 12 DDRB_CLK0 AJ34 SM_CK3 RSVD24 A31
H_A#29 D13 J5 H_D#26 AF6 A30
HA29# HD26# 12 DDRB_CLK1 SM_CK4 RSVD25
H_A#30 A13 P7 H_D#27 AC10 D26 CFG[17:3]: internal pull-up
H_A#31 HA30# HD27# H_D#28 SM_CK5 RSVD26
F13 HA31# HD28# L7 RSVD27 D25
J3 H_D#29 AN33
HD29# 11 DDRA_CLK0# SM_CK0# +2.5VS

DDR MUXING
A11 P5 H_D#30 AK1
HOST

HPCREQ# HD30# 11 DDRA_CLK1# SM_CK1#


H_REQ#0 A7 L3 H_D#31 AE10
H_REQ#1 HREQ#0 HD31# H_D#32 SM_CK2# CFG18 R355 1
D7 HREQ#1 HD32# U7 12 DDRB_CLK0# AJ33 SM_CK3# 2 @ 1K_0402_5%
H_REQ#2 B8 V6 H_D#33 AF5
HREQ#2 HD33# 12 DDRB_CLK1# SM_CK4#
H_REQ#3 C7 R6 H_D#34 AD10 CFG19 R345 1 2 @ 1K_0402_5%
H_REQ#4 HREQ#3 HD34# H_D#35 SM_CK5#
A8 HREQ#4 HD35# R5
B9 P3 H_D#36 AP21 CFG[19:18]: internal pull-down
C 4 H_ADSTB#0 HADSTB#0 HD36# 11 DDRA_CKE0 SM_CKE0 C
E13 T8 H_D#37 AM21
4 H_ADSTB#1 HADSTB#1 HD37# 11 DDRA_CKE1 SM_CKE1
R7 H_D#38 AH21
HD38# 12 DDRB_CKE0 SM_CKE2
AB1 R8 H_D#39 AK21
13 CLK_MCH_BCLK# HCLKN HD39# 12 DDRB_CKE1 SM_CKE3
AB2 U8 H_D#40 J23
13 CLK_MCH_BCLK HCLKP HD40# BM_BUSY# PM_BMBUSY# 18
R4 H_D#41 AN16 J21 EXT_TS#0
HD41# 11 DDRA_SCS#0 SM_CS0# EXT_TS0#
G4 T4 H_D#42 AM14 H22 EXT_TS#1
4 H_DSTBN#0 HDSTBN#0 HD42# 11 DDRA_SCS#1 SM_CS1# EXT_TS1#
K1 T5 H_D#43 AH15 F5 H_THERMTRIP#
4 H_DSTBN#1 HDSTBN#1 HD43# 12 DDRB_SCS#0 SM_CS2# THRMTRIP# H_THERMTRIP# 4,17
R3 R1 H_D#44 AG16 AD30
4 H_DSTBN#2 HDSTBN#2 HD44# 12 DDRB_SCS#1 SM_CS3# PWROK VGATE 13,18,40
V3 T3 H_D#45 AE29

CLK PM
4 H_DSTBN#3 HDSTBN#3 HD45# RSTIN# PLT_RST# 15,16,18,23,29
G5 V8 H_D#46 R351 1 2@ 40.2_0402_1%10mils M_OCDCOMP0 AF22
4 H_DSTBP#0 HDSTBP#0 HD46# H_D#47 R365 1 M_OCDCOMP1 SM_OCDCOMP0
4 H_DSTBP#1 K2 HDSTBP#1 HD47# U6 2@ 40.2_0402_1%10mils AF16 SM_OCDCOMP1
R2 W6 H_D#48 AP14 A24 CLK_DREF_96M#
4 H_DSTBP#2 HDSTBP#2 HD48# 11 DDRA_ODT0 SM_ODT0 DREF_CLKN CLK_DREF_96M# 13
W4 U3 H_D#49 AL15 A23 CLK_DREF_96M
4 H_DSTBP#3 HDSTBP#3 HD49# 11 DDRA_ODT1 SM_ODT1 DREF_CLKP CLK_DREF_96M 13
H8 V5 H_D#50 AM11 D37 CLK_DREF_SSC
4 H_DINV#0 HDINV#0 HD50# 12 DDRB_ODT0 SM_ODT2 DREF_SSCLKP CLK_DREF_SSC 13
K3 W8 H_D#51 AN10 C37 CLK_DREF_SSC#
4 H_DINV#1 HDINV#1 HD51# 12 DDRB_ODT1 SM_ODT3 DREF_SSCLKN CLK_DREF_SSC# 13
T7 W7 H_D#52
4 H_DINV#2 HDINV#2 HD52# H_D#53 R366 1 M_RCOMPN
4 H_DINV#3 U5 HDINV#3 HD53# U2 +1.8V 2 80.6_0402_1%10mils AK10 SMRCOMPN
U1 H_D#54 R368 1 2 80.6_0402_1%10mils M_RCOMPP AK11 AP37 +2.5VS
HD54# H_D#55 SMVREF0 SMRCOMPP NC1
HD55# Y5 AF37 SMVREF0 NC2 AN37
H10 Y2 H_D#56 SMVREF1 AD1 AP36 EXT_TS#0 R357 1 2 10K_0402_5%
4 H_CPURST# HCPURST# HD56# H_D#57 M_XSLEW SMVREF1 NC3
HD57# V4 AE27 SMXSLEWIN NC4 AP2
F8 Y7 H_D#58 10mils AE28 AP1 EXT_TS#1 R350 1 2 10K_0402_5%
4 H_ADS# HADS# HD58# H_D#59 M_YSLEW SMXSLEWOUT NC5
4 H_TRDY# B5 HTRDY# HD59# W1 AF9 SMYSLEWIN NC6 AN1
G6 W3 H_D#60 10mils AF10 B1
4 H_DPW R# HDPWR# HD60# SMYSLEWOUT NC7
F7 Y3 H_D#61 A2
4 H_D RDY# HDRDY# HD61# H_D#62 NC8
4 H_DEFER# E6 HDEFER# HD62# Y6
+1.8V NC9 B37 Refer to sheet 6 for FSB
H_D#63

NC
F6 HEDRDY# HD63# W2
+1.05VS NC10 A36 CFG[2:0] frequency select
4 H_HITM# D6 HHITM# NC11 A37
D4 J11 H_VREF Low = DMI x 2
4 H_HIT# HHIT# HVREF

1
B3 C1 H_XRCOMP R41 2 1 24.9_0402_1% (10mil:20mil) CFG5 High = DMI x 4
B
4
4
H_LOCK#
H_BR0# E7
HLOCK#
HBREQ0#
HXRCOMP
HXSCOMP C2 H_XSCOMP
H_YRCOMP
R3801
R45 2
2 54.9_0402_1%
24.9_0402_1%
R30 ALVISO_BGA1257 GM@ * B
A5 T1 1 Low = DDR-II
4
4
H_BNR#
H_BPRI# D5
HBNR#
HBPRI#
HYRCOMP
HYSCOMP L1 H_YSCOMP
H_XSWING
R3791 2 54.9_0402_1% 1K_0402_1% CFG6 High = DDR-I *
C6 D1

2
4 H_DBSY# CPU_SLP# HDBSY# HXSWING H_YSW ING 0.1U_0402_16V4Z SMVREF0
G8 HCPUSLP# HYSWING P1 Low = DT/Transportable CPU
H_RS#0 A4 15mils CFG7 High = Mobile CPU
HRS0#
*

1
H_RS#1 C5 1 1
H_RS#2 HRS1# R33 C46
B4 HRS2# CFG9 Low = Reverse Lane
C47 High = Normal Operation
GM@ ALVISO_BGA1257
1K_0402_1%
2 2
0.1U_0402_16V4Z *
00 = Reserved
H_XRCOMP & H_YRCOMP Trace / Space = 10 / 20 mil 2 CFG[13:12] 01 = XOR Mode Enabled
10 = All Z Mode Enabled
R371 1 2 CPU_SLP# 11 = Normal Operation (Default)
4,17 H_CPUSLP#
0_0402_5% +1.8V *
CFG16
(FSB Dynamic Low = Disabled
1

+1.05VS +1.05VS +1.05VS


High = Enabled
R44 ODT) *
1

1K_0402_1% CFG18
R367 R40 R46 Low = 1.05V (Default)
*
2

100_0603_1% 221_0603_1% 221_0603_1% 0.1U_0402_16V4Z SMVREF1 (VCC Select) High = 1.5V


15mils
1

(5mil:15mil) (12mil:10mil) 1 1 CFG19


2

R47 C162 Low = 1.05V (Default)


H_VREF H_XSWING H_YSW ING (12mil:10mil) 1K_0402_1%
C155
0.1U_0402_16V4Z
(VTT Select) High = 1.2V *
1

2 2
1 1 1
2

C468 R370 C152 R43 C154


R42
0.1U_0402_16V4Z 200_0603_1% 0.1U_0402_16V4Z 100_0603_1% 0.1U_0402_16V4Z 100_0603_1%
2 2 2
A A
2

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2005/08/22 Deciphered Date 2008/08/22 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Alviso HOST(1/5)
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number R ev
1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
HTW00 M/B LA-2871
Date: Saturday, August 20, 2005 Sheet 6 of 41
5 4 3 2 1
5 4 3 2 1

DDRA_SDQ[0..63] DDRB_SDQ[0..63]
11 DDRA_SDQ[0..63] 12 DDRB_SDQ[0..63]
DDRA_SDM[0..7] DDRB_SDM[0..7]
11 DDRA_SDM[0..7] 12 DDRB_SDM[0..7]

DDRB_SMA[0..13]
12 DDRB_SMA[0..13]
DDRA_SMA[0..13]
11 DDRA_SMA[0..13]

D D

U5C U5D
AK15 AG35 DDRA_SDQ0 AJ15 AE31 DDRB_SDQ0
11 DDRA_SBS0# SA_BS0# SADQ0 12 DDRB_SBS0# SB_BS0# SBDQ0
AK16 AH35 DDRA_SDQ1 AG17 AE32 DDRB_SDQ1
11 DDRA_SBS1# SA_BS1# SADQ1 12 DDRB_SBS1# SB_BS1# SBDQ1
AL21 AL35 DDRA_SDQ2 AG21 AG32 DDRB_SDQ2
11 DDRA_SBS2# SA_BS2# SADQ2 12 DDRB_SBS2# SB_BS2# SBDQ2
AL37 DDRA_SDQ3 AG36 DDRB_SDQ3
DDRA_SDM0 SADQ3 DDRA_SDQ4 DDRB_SDM0 SBDQ3 DDRB_SDQ4
AJ37 SA_DM0 SADQ4 AH36 AF32 SB_DM0 SBDQ4 AE34
DDRA_SDM1 AP35 AJ35 DDRA_SDQ5 DDRB_SDM1 AK34 AE33 DDRB_SDQ5
DDRA_SDM2 SA_DM1 SADQ5 DDRA_SDQ6 DDRB_SDM2 SB_DM1 SBDQ5 DDRB_SDQ6
AL29 SA_DM2 SADQ6 AK37 AK27 SB_DM2 SBDQ6 AF31
DDRA_SDM3 AP24 AL34 DDRA_SDQ7 DDRB_SDM3 AK24 AF30 DDRB_SDQ7
DDRA_SDM4 SA_DM3 SADQ7 DDRA_SDQ8 DDRB_SDM4 SB_DM3 SBDQ7 DDRB_SDQ8
AP9 SA_DM4 SADQ8 AM36 AJ10 SB_DM4 SBDQ8 AH33
DDRA_SDM5 AP4 AN35 DDRA_SDQ9 DDRB_SDM5 AK5 AH32 DDRB_SDQ9
DDRA_SDM6 SA_DM5 SADQ9 DDRA_SDQ10 DDRB_SDM6 SB_DM5 SBDQ9 DDRB_SDQ10
AJ2 SA_DM6 SADQ10 AP32 AE7 SB_DM6 SBDQ10 AK31
DDRA_SDM7 AD3 AM31 DDRA_SDQ11 DDRB_SDM7 AB7 AG30 DDRB_SDQ11
SA_DM7 SADQ11 DDRA_SDQ12 SB_DM7 SBDQ11 DDRB_SDQ12
SADQ12 AM34 SBDQ12 AG34
DDRA_SDQS0 AK36 AM35 DDRA_SDQ13 DDRB_SDQS0 AF34 AG33 DDRB_SDQ13
11 DDRA_SDQS0 DDRA_SDQS1 SA_DQS0 SADQ13 DDRA_SDQ14 12 DDRB_SDQS0 DDRB_SDQS1 SB_DQS0 SBDQ13 DDRB_SDQ14
11 DDRA_SDQS1 AP33 SA_DQS1 SADQ14 AL32 12 DDRB_SDQS1 AK32 SB_DQS1 SBDQ14 AH31
DDRA_SDQS2 AN29 AM32 DDRA_SDQ15 DDRB_SDQS2 AJ28 AJ31 DDRB_SDQ15
11 DDRA_SDQS2 DDRA_SDQS3 SA_DQS2 SADQ15 DDRA_SDQ16 12 DDRB_SDQS2 DDRB_SDQS3 SB_DQS2 SBDQ15 DDRB_SDQ16
11 DDRA_SDQS3 AP23 SA_DQS3 SADQ16 AN31 12 DDRB_SDQS3 AK23 SB_DQS3 SBDQ16 AK30
DDRA_SDQS4 AM8 AP31 DDRA_SDQ17 DDRB_SDQS4 AM10 AJ30 DDRB_SDQ17
11 DDRA_SDQS4 DDRA_SDQS5 SA_DQS4 SADQ17 DDRA_SDQ18 12 DDRB_SDQS4 DDRB_SDQS5 SB_DQS4 SBDQ17 DDRB_SDQ18
11 DDRA_SDQS5 AM4 SA_DQS5 SADQ18 AN28 12 DDRB_SDQS5 AH6 SB_DQS5 SBDQ18 AH29
DDRA_SDQS6 AJ1 AP28 DDRA_SDQ19 DDRB_SDQS6 AF8 AH28 DDRB_SDQ19
11 DDRA_SDQS6 DDRA_SDQS7 SA_DQS6 SADQ19 DDRA_SDQ20 12 DDRB_SDQS6 DDRB_SDQS7 SB_DQS6 SBDQ19 DDRB_SDQ20
11 DDRA_SDQS7 AE5 SA_DQS7 SADQ20 AL30 12 DDRB_SDQS7 AB4 SB_DQS7 SBDQ20 AK29
AM30 DDRA_SDQ21 AH30 DDRB_SDQ21
DDRA_SDQS0# SADQ21 DDRA_SDQ22 DDRB_SDQS0# SBDQ21 DDRB_SDQ22
11 DDRA_SDQS0# AK35 SA_DQS0# SADQ22 AM28 12 DDRB_SDQS0# AF35 SB_DQS0# SBDQ22 AH27
DDRA_SDQS1# AP34 AL28 DDRA_SDQ23 DDRB_SDQS1# AK33 AG28 DDRB_SDQ23

DDR SYSTEM MEMORY B


11 DDRA_SDQS1# DDRA_SDQS2# SA_DQS1# SADQ23 DDRA_SDQ24 12 DDRB_SDQS1# DDRB_SDQS2# SB_DQS1# SBDQ23 DDRB_SDQ24
AN30 AP27 AK28 AF24
DDR MEMORY SYSTEM A

11 DDRA_SDQS2# DDRA_SDQS3# SA_DQS2# SADQ24 DDRA_SDQ25 12 DDRB_SDQS2# DDRB_SDQS3# SB_DQS2# SBDQ24 DDRB_SDQ25
11 DDRA_SDQS3# AN23 SA_DQS3# SADQ25 AM27 12 DDRB_SDQS3# AJ23 SB_DQS3# SBDQ25 AG23
DDRA_SDQS4# AN8 AM23 DDRA_SDQ26 DDRB_SDQS4# AL10 AJ22 DDRB_SDQ26
C 11 DDRA_SDQS4# DDRA_SDQS5# SA_DQS4# SADQ26 DDRA_SDQ27 12 DDRB_SDQS4# DDRB_SDQS5# SB_DQS4# SBDQ26 DDRB_SDQ27 C
11 DDRA_SDQS5# AM5 SA_DQS5# SADQ27 AM22 12 DDRB_SDQS5# AH7 SB_DQS5# SBDQ27 AK22
DDRA_SDQS6# AH1 AL23 DDRA_SDQ28 DDRB_SDQS6# AF7 AH24 DDRB_SDQ28
11 DDRA_SDQS6# DDRA_SDQS7# SA_DQS6# SADQ28 DDRA_SDQ29 12 DDRB_SDQS6# DDRB_SDQS7# SB_DQS6# SBDQ28 DDRB_SDQ29
11 DDRA_SDQS7# AE4 SA_DQS7# SADQ29 AM24 12 DDRB_SDQS7# AB5 SB_DQS7# SBDQ29 AH23
AN22 DDRA_SDQ30 AG22 DDRB_SDQ30
DDRA_SMA0 SADQ30 DDRA_SDQ31 DDRB_SMA0 SBDQ30 DDRB_SDQ31
AL17 SA_MA0 SADQ31 AP22 AH17 SB_MA0 SBDQ31 AJ21
DDRA_SMA1 AP17 AM9 DDRA_SDQ32 DDRB_SMA1 AK17 AG10 DDRB_SDQ32
DDRA_SMA2 SA_MA1 SADQ32 DDRA_SDQ33 DDRB_SMA2 SB_MA1 SBDQ32 DDRB_SDQ33
AP18 SA_MA2 SADQ33 AL9 AH18 SB_MA2 SBDQ33 AG9
DDRA_SMA3 AM17 AL6 DDRA_SDQ34 DDRB_SMA3 AJ18 AG8 DDRB_SDQ34
DDRA_SMA4 SA_MA3 SADQ34 DDRA_SDQ35 DDRB_SMA4 SB_MA3 SBDQ34 DDRB_SDQ35
AN18 SA_MA4 SADQ35 AP7 AK18 SB_MA4 SBDQ35 AH8
DDRA_SMA5 AM18 AP11 DDRA_SDQ36 DDRB_SMA5 AJ19 AH11 DDRB_SDQ36
DDRA_SMA6 SA_MA5 SADQ36 DDRA_SDQ37 DDRB_SMA6 SB_MA5 SBDQ36 DDRB_SDQ37
AL19 SA_MA6 SADQ37 AP10 AK19 SB_MA6 SBDQ37 AH10
DDRA_SMA7 AP20 AL7 DDRA_SDQ38 DDRB_SMA7 AH19 AJ9 DDRB_SDQ38
DDRA_SMA8 SA_MA7 SADQ38 DDRA_SDQ39 DDRB_SMA8 SB_MA7 SBDQ38 DDRB_SDQ39
AM19 SA_MA8 SADQ39 AM7 AJ20 SB_MA8 SBDQ39 AK9
DDRA_SMA9 AL20 AN5 DDRA_SDQ40 DDRB_SMA9 AH20 AJ7 DDRB_SDQ40
DDRA_SMA10 SA_MA9 SADQ40 DDRA_SDQ41 DDRB_SMA10 SB_MA9 SBDQ40 DDRB_SDQ41
AM16 SA_MA10 SADQ41 AN6 AJ16 SB_MA10 SBDQ41 AK6
DDRA_SMA11 AN20 AN3 DDRA_SDQ42 DDRB_SMA11 AG18 AJ4 DDRB_SDQ42
DDRA_SMA12 SA_MA11 SADQ42 DDRA_SDQ43 DDRB_SMA12 SB_MA11 SBDQ42 DDRB_SDQ43
AM20 SA_MA12 SADQ43 AP3 AG20 SB_MA12 SBDQ43 AH5
DDRA_SMA13 AM15 AP6 DDRA_SDQ44 DDRB_SMA13 AG15 AK8 DDRB_SDQ44
SA_MA13 SADQ44 DDRA_SDQ45 SB_MA13 SBDQ44 DDRB_SDQ45
SADQ45 AM6 SBDQ45 AJ8
AN15 AL4 DDRA_SDQ46 AH14 AJ5 DDRB_SDQ46
11 DDRA_SCAS# SA_CAS# SADQ46 12 DDRB_SCAS# SB_CAS# SBDQ46
AP16 AM3 DDRA_SDQ47 AK14 AK4 DDRB_SDQ47
11 DDRA_SRAS# SA_RAS# SADQ47 12 DDRB_SRAS# SB_RAS# SBDQ47
AF29 AK2 DDRA_SDQ48 AF15 AG5 DDRB_SDQ48
SA_RCVENIN# SADQ48 DDRA_SDQ49 SB_RCVENIN# SBDQ48 DDRB_SDQ49
AF28 SA_RCVENOUT# SADQ49 AK3 AF14 SB_RCVENOUT# SBDQ49 AG4
AP15 AG2 DDRA_SDQ50 AH16 AD8 DDRB_SDQ50
11 DDRA_SW E# SA_WE# SADQ50 12 DDRB_SW E# SB_WE# SBDQ50
AG1 DDRA_SDQ51 AD9 DDRB_SDQ51
SADQ51 DDRA_SDQ52 SBDQ51 DDRB_SDQ52
SADQ52 AL3 SBDQ52 AH4
AF28,AF29 should be routed to a via AM2 DDRA_SDQ53 AF14,AF15 should be routed to a via AG6 DDRB_SDQ53
SADQ53 DDRA_SDQ54 SBDQ53 DDRB_SDQ54
SADQ54 AH3 SBDQ54 AE8
AG3 DDRA_SDQ55 AD7 DDRB_SDQ55
SADQ55 DDRA_SDQ56 SBDQ55 DDRB_SDQ56
SADQ56 AF3 SBDQ56 AC5
AE3 DDRA_SDQ57 AB8 DDRB_SDQ57
B SADQ57 DDRA_SDQ58 SBDQ57 DDRB_SDQ58 B
SADQ58 AD6 SBDQ58 AB6
AC4 DDRA_SDQ59 AA8 DDRB_SDQ59
SADQ59 DDRA_SDQ60 SBDQ59 DDRB_SDQ60
SADQ60 AF2 SBDQ60 AC8
AF1 DDRA_SDQ61 AC7 DDRB_SDQ61
SADQ61 DDRA_SDQ62 SBDQ61 DDRB_SDQ62
SADQ62 AD4 SBDQ62 AA4
AD5 DDRA_SDQ63 AA5 DDRB_SDQ63
SADQ63 SBDQ63

GM@ ALVISO_BGA1257 GM@ ALVISO_BGA1257

A A

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2005/08/22 Deciphered Date 2008/08/22 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Alviso DDR(2/5)
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number R ev
1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
HTW00 M/B LA-2871
Date: Saturday, August 20, 2005 Sheet 7 of 41
5 4 3 2 1
5 4 3 2 1

U5G
+2.5VS R342 1 2 @ 3K_0402_1% H24 D36 PEG_COMP 1 2 +1.5VS
R341 1 SDVOCTRL_DATA EXP_COMPI
2 @ 3K_0402_1% H25 SDVOCTRL_CLK EXP_ICOMPO D34 10mils R343 24.9_0402_1%
AB29

MISC
13 CLK_MCH_3GPLL# GCLKN
AC29 E30 PCEI_GTX_C_MRX_N0
13 CLK_MCH_3GPLL GCLKP EXP_RXN0/SDVO_TVCLKIN#
F34 PCEI_GTX_C_MRX_N1
EXP_RXN1/SDVO_INT# PCEI_GTX_C_MRX_N2
EXP_RXN2/SDVO_FLDSTALL# G30
GMCH_TV_COMPS A15 H34 PCEI_GTX_C_MRX_N3
GMCH_TV_LUMA TVDAC_A EXP_RXN3 PCEI_GTX_C_MRX_N4 PCIE_MTX_C_GRX_N[0..15]
14 GMCH_TV_LUMA C16 TVDAC_B EXP_RXN4 J30 15 PCIE_MTX_C_GRX_N[0..15]
GMCH_TV_CRMA A17 K34 PCEI_GTX_C_MRX_N5
14 GMCH_TV_CRMA TVDAC_C EXP_RXN5 PCIE_MTX_C_GRX_P[0..15]
2
R356
1
4.99K_0402_1%
10mils TV_REFSET J18 TV_REFSET EXP_RXN6 L30 PCEI_GTX_C_MRX_N6
PCEI_GTX_C_MRX_N7
15 PCIE_MTX_C_GRX_P[0..15]
B15 TV_IRTNA EXP_RXN7 M34
B16 N30 PCEI_GTX_C_MRX_N8 PCEI_GTX_C_MRX_N[0..15]
D TV_IRTNB EXP_RXN8 15 PCEI_GTX_C_MRX_N[0..15] D
B17 P34 PCEI_GTX_C_MRX_N9

TV
TV_IRTNC EXP_RXN9 PCEI_GTX_C_MRX_N10 PCEI_GTX_C_MRX_P[0..15]
EXP_RXN10 R30 15 PCEI_GTX_C_MRX_P[0..15]
T34 PCEI_GTX_C_MRX_N11
EXP_RXN11 PCEI_GTX_C_MRX_N12
EXP_RXN12 U30
V34 PCEI_GTX_C_MRX_N13
EXP_RXN13 PCEI_GTX_C_MRX_N14
EXP_RXN14 W30
GMCH_CRT_CLK E24 Y34 PCEI_GTX_C_MRX_N15
14 GMCH_CRT_CLK DDCCLK EXP_RXN15
GMCH_CRT_DATA E23
14 GMCH_CRT_DATA DDCDATA
E21 D30 PCEI_GTX_C_MRX_P0
14 GMCH_CRT_B BLUE EXP_RXP0/SDVO_TVCLKIN
2 1 D21 E34 PCEI_GTX_C_MRX_P1
R333 150_0402_1% BLUE# EXP_RXP1/SDVO_INT PCEI_GTX_C_MRX_P2
14 GMCH_CRT_G C20 GREEN EXP_RXP2/SDVO_FLDSTALL F30
2 1 B20 G34 PCEI_GTX_C_MRX_P3
R329 150_0402_1% GREEN# EXP_RXP3 PCEI_GTX_C_MRX_P4
14 GMCH_CRT_R A19 RED EXP_RXP4 H30
2 1 B19 J34 PCEI_GTX_C_MRX_P5
R316 150_0402_1% RED# EXP_RXP5 PCEI_GTX_C_MRX_P6
H21 K30

VGA
14 GMCH_CRT_VSYNC VSYNC EXP_RXP6
G21 L34 PCEI_GTX_C_MRX_P7
14 GMCH_CRT_HSYNC HSYNC EXP_RXP7

PCI - EXPRESS GRAPHICS


1 2 REFSET J20 REFSET EXP_RXP8 M30 PCEI_GTX_C_MRX_P8
R353 255_0402_1% N34 PCEI_GTX_C_MRX_P9
EXP_RXP9 PCEI_GTX_C_MRX_P10
10mils EXP_RXP10 P30
PCEI_GTX_C_MRX_P11
EXP_RXP11 R34
T30 PCEI_GTX_C_MRX_P12
EXP_RXP12 PCEI_GTX_C_MRX_P13
EXP_RXP13 U34
V30 PCEI_GTX_C_MRX_P14
EXP_RXP14 PCEI_GTX_C_MRX_P15
EXP_RXP15 W34
+2.5VS E25
LBKLT_EN LBKLT_CTL PCIE_MTX_GRX_N0
F25 LBKLT_EN EXP_TXN0/SDVOB_RED# E32 C411 1 2 PM@ 0.1U_0402_16V4Z PCIE_MTX_C_GRX_N0
R346 1 2 4.7K_0402_5% GMCH_CRT_CLK LCTLA_CLK C23 F36 PCIE_MTX_GRX_N1 C55 1 2 PM@ 0.1U_0402_16V4Z PCIE_MTX_C_GRX_N1
LCTLB_DATA LCTLA_CLK EXP_TXN1/SDVOB_GREEN# PCIE_MTX_GRX_N2
C22 LCTLB_DATA EXP_TXN2/SDVOB_BLUE# G32 C415 1 2 PM@ 0.1U_0402_16V4Z PCIE_MTX_C_GRX_N2
R347 1 2 4.7K_0402_5% GMCH_CRT_DATA LDDC_CLK F23 H36 PCIE_MTX_GRX_N3 C57 1 2 PM@ 0.1U_0402_16V4Z PCIE_MTX_C_GRX_N3
LDDC_DATA LDDC_CLK EXP_TXN3/SDVOB_CLKN PCIE_MTX_GRX_N4
F22 LDDC_DATA EXP_TXN4/SDVOC_RED# J32 C419 1 2 PM@ 0.1U_0402_16V4Z PCIE_MTX_C_GRX_N4
R352 1 GM@ 2 2.2K_0402_5% LCTLB_DATA GM CH_ENVDD F26 K36 PCIE_MTX_GRX_N5 C60 1 2 PM@ 0.1U_0402_16V4Z PCIE_MTX_C_GRX_N5
C 15 GMCH_ENVDD LVDD_EN EXP_TXN5/SDVOC_GREEN# C
LIBG C33 L32 PCIE_MTX_GRX_N6 C425 1 2 PM@ 0.1U_0402_16V4Z PCIE_MTX_C_GRX_N6
R349 1 GM@ 2.2K_0402_5% LCTLA_CLK LIBG EXP_TXN6/SDVOC_BLUE# PCIE_MTX_GRX_N7 C64 PCIE_MTX_C_GRX_N7
2 C31 LVBG EXP_TXN7/SDVOC_CLKN M36 1 2 PM@ 0.1U_0402_16V4Z
F28 N32 PCIE_MTX_GRX_N8 C431 1 2 PM@ 0.1U_0402_16V4Z PCIE_MTX_C_GRX_N8
LVREFH EXP_TXN8 PCIE_MTX_GRX_N9 C77 PCIE_MTX_C_GRX_N9
Intel Recommand F27 LVREFL EXP_TXN9 P36 1 2 PM@ 0.1U_0402_16V4Z
R32 PCIE_MTX_GRX_N10 C438 1 2 PM@ 0.1U_0402_16V4Z PCIE_MTX_C_GRX_N10
R323 1 100K_0402_5% LBKLT_EN GMCH_TXCLK- EXP_TXN10 PCIE_MTX_GRX_N11 C88 PM@ 0.1U_0402_16V4Z PCIE_MTX_C_GRX_N11
2 15 GMCH_TXCLK- B30 LACLKN EXP_TXN11 T36 1 2
GMCH_TXCLK+ B29 U32 PCIE_MTX_GRX_N12 C442 1 2 PM@ 0.1U_0402_16V4Z PCIE_MTX_C_GRX_N12
15 GMCH_TXCLK+ LACLKP EXP_TXN12

LVDS
R35 1 2 1.5K_0402_1% LIBG C25 V36 PCIE_MTX_GRX_N13 C105 1 2 PM@ 0.1U_0402_16V4Z PCIE_MTX_C_GRX_N13
LBCLKN EXP_TXN13 PCIE_MTX_GRX_N14
C24 LBCLKP EXP_TXN14 W32 C457 1 2 PM@ 0.1U_0402_16V4Z PCIE_MTX_C_GRX_N14
R37 1 2 75_0402_1% GMCH_TV_COMPS Y36 PCIE_MTX_GRX_N15 C116 1 2 PM@ 0.1U_0402_16V4Z PCIE_MTX_C_GRX_N15
GMCH_TXOUT0- EXP_TXN15
15 GMCH_TXOUT0- B34 LADATAN0
R311 1 2 150_0402_1% GMCH_TV_LUMA GMCH_TXOUT1- B33
15 GMCH_TXOUT1- LADATAN1
GMCH_TXOUT2- B32 D32 PCIE_MTX_GRX_P0 C410 1 2 PM@ 0.1U_0402_16V4Z PCIE_MTX_C_GRX_P0
15 GMCH_TXOUT2- LADATAN2 EXP_TXP0/SDVOB_RED
R322 1 2 150_0402_1% GMCH_TV_CRMA E36 PCIE_MTX_GRX_P1 C53 1 2 PM@ 0.1U_0402_16V4Z PCIE_MTX_C_GRX_P1
EXP_TXP1/SDVOB_GREEN PCIE_MTX_GRX_P2
EXP_TXP2/SDVOB_BLUE F32 C414 1 2 PM@ 0.1U_0402_16V4Z PCIE_MTX_C_GRX_P2
GMCH_TXOUT0+ A34 G36 PCIE_MTX_GRX_P3 C56 1 2 PM@ 0.1U_0402_16V4Z PCIE_MTX_C_GRX_P3
15 GMCH_TXOUT0+ LADATAP0 EXP_TXP3/SDVOB_CLKP
GMCH_TXOUT1+ A33 H32 PCIE_MTX_GRX_P4 C418 1 2 PM@ 0.1U_0402_16V4Z PCIE_MTX_C_GRX_P4
15 GMCH_TXOUT1+ LADATAP1 EXP_TXP4/SDVOC_RED
GMCH_TXOUT2+ B31 J36 PCIE_MTX_GRX_P5 C58 1 2 PM@ 0.1U_0402_16V4Z PCIE_MTX_C_GRX_P5
15 GMCH_TXOUT2+ LADATAP2 EXP_TXP5/SDVOC_GREEN
K32 PCIE_MTX_GRX_P6 C422 1 2 PM@ 0.1U_0402_16V4Z PCIE_MTX_C_GRX_P6
EXP_TXP6/SDVOC_BLUE PCIE_MTX_GRX_P7 C62 PCIE_MTX_C_GRX_P7
EXP_TXP7/SDVOC_CLKP L36 1 2 PM@ 0.1U_0402_16V4Z
M32 PCIE_MTX_GRX_P8 C428 1 2 PM@ 0.1U_0402_16V4Z PCIE_MTX_C_GRX_P8
EXP_TXP8 PCIE_MTX_GRX_P9 C70 PCIE_MTX_C_GRX_P9
C29 LBDATAN0 EXP_TXP9 N36 1 2 PM@ 0.1U_0402_16V4Z
D28 P32 PCIE_MTX_GRX_P10 C436 1 2 PM@ 0.1U_0402_16V4Z PCIE_MTX_C_GRX_P10
LBDATAN1 EXP_TXP10 PCIE_MTX_GRX_P11 C83 PCIE_MTX_C_GRX_P11
C27 LBDATAN2 EXP_TXP11 R36 1 2 PM@ 0.1U_0402_16V4Z
T32 PCIE_MTX_GRX_P12 C439 1 2 PM@ 0.1U_0402_16V4Z PCIE_MTX_C_GRX_P12
EXP_TXP12 PCIE_MTX_GRX_P13 C97 PCIE_MTX_C_GRX_P13
EXP_TXP13 U36 1 2 PM@ 0.1U_0402_16V4Z
V32 PCIE_MTX_GRX_P14 C450 1 2 PM@ 0.1U_0402_16V4Z PCIE_MTX_C_GRX_P14
EXP_TXP14 PCIE_MTX_GRX_P15 C108 1 PCIE_MTX_C_GRX_P15
C28 LBDATAP0 EXP_TXP15 W36 2 PM@ 0.1U_0402_16V4Z
D27 LBDATAP1
C26 LBDATAP2
B B

ALVISO_BGA1257
GM@

+2.5VS +3VS +2.5VS


+3VS
1
2

R19 R18 R332


GM@ 4.7K_0402_5% GM@ 4.7K_0402_5% GM@ 2.2K_0402_5%
2

2
G

G
2

Q3
1

LDDC_CLK 3 1 GM CH_LCD_CLK 1 3 LBKLT_EN


GMCH_LCD_CLK 15 15,29 ENBKL
S

GM@ BSS138_SOT23
Q6
GM@ BSS138_SOT23
+2.5VS
+3VS
A A
2

R28 R24
GM@ 4.7K_0402_5% GM@ 4.7K_0402_5%
2
G

Q8
1

LDDC_DATA 3 1 GMCH_LCD_DATA GMCH_LCD_DATA 15 Security Classification Compal Secret Data Compal Electronics, Inc.
S

GM@ BSS138_SOT23 2005/08/22 2008/08/22 Title


Issued Date Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Alviso PCI-E(3/5)
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number R ev
1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
HTW00 M/B LA-2871
Date: Saturday, August 20, 2005 Sheet 8 of 41
5 4 3 2 1
5 4 3 2 1

+1.05VS
4000mA (10uF x3, 0.1uF x3)
U 5F C40
U5E 0.1U_0402_16V4Z C41 2.2U_0805_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z
+1.05VS K13 AM37 V1. 8_DDR_CAP1 2 1 0.1U_0402_16V4Z
VTT0 VCCSM0 V1. 8_DDR_CAP2
+1.05VS T29 VCC0 VCCA_TVDACA0 F17 +3VS_DAC J13 VTT1 VCCSM1 AH37 2 1 1 1 1 1 1 1
R29 E17 K12 AP29 V1. 8_DDR_CAP5 2 1 C166 C462 C476
VCC1 VCCA_TVDACA1 VTT2 VCCSM2 C63
N29 VCC2 VCCA_TVDACB0 D18 W11 VTT3 VCCSM3 AD28 +1.8V
M29 C18 120mA V11 AD27 0.1U_0402_16V4Z C165 C491 C472
VCC3 VCCA_TVDACB1 VTT4 VCCSM4 2 2 2 2 2 2
K29 VCC4 VCCA_TVDACC0 F18 U11 VTT5 VCCSM5 AC27
J29 E18 T11 AP26 22U_1206_16V4Z_V1
VCC5 VCCA_TVDACC1 VTT6 VCCSM6 2.2U_0805_16V4Z 0.1U_0402_16V4Z
V28 R11 AN26
D U28
T28
VCC6
VCC7
VCC8 POWER VCCA_TVBG
VSSA_TVBG
H18
G18
+1.05VS P11
N11
VTT7
VTT8
VTT9
POWER VCCSM7
VCCSM8
VCCSM9
AM26
AL26
D

R28 0.1U_0402_16V4Z M11 AK26


VCC9 VTT10 VCCSM10
P28 VCC10 VCCD_TVDAC D19 L11 VTT11 VCCSM11 AJ26
N28 VCC11 VCCDQ_TVDAC H17 24mA 1 1 K11 VTT12 VCCSM12 AH26
M28 VCC12 W10 VTT13 VCCSM13 AG26
+1.05VS C471 C483 +1.8V
L28 VCC13 VCCD_LVDS0 B26 +1.5VS V10 VTT14 VCCSM14 AF26 2200mA (10uF x2, 0.1uF x6)
K28 VCC14 VCCD_LVDS1 B25 U10 VTT15 VCCSM15 AE26
0.1U_0402_16V4Z 2 2 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z
J28 VCC15 VCCD_LVDS2 A25 60mA T10 VTT16 VCCSM16 AP25
H28 VCC16 R10 VTT17 VCCSM17 AN25 1
1 1 G28 A35 +2.5VS 0.1U_0402_16V4Z P10 AM25 1 1 1 1 1 1 1 1
VCC17 VCCA_LVDS VTT18 VCCSM18 + C452 C466 C437 C434
V27 VCC18 10mA N10 VTT19 VCCSM19 AL25
C435 C424 U27 B22 M10 AK25 C463
VCC19 VCCHV0 VTT20 VCCSM20 C461 C447 C433 C441
2 2
T27 VCC20 VCCHV1 B21 2mA K10 VTT21 VCCSM21 AJ25
2 2 2 2 2 2 2 2 2
R27 VCC21 VCCHV2 A21 J10 VTT22 VCCSM22 AH25
P27 VCC22 Y9 VTT23 VCCSM23 AG25
0.1U_0402_16V4Z N27 B28 W9 AF25 330U_D_2VM 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z
VCC23 VCCTX_LVDS0 VTT24 VCCSM24
M27 VCC24 VCCTX_LVDS1 A28 60mA U9 VTT25 VCCSM25 AE25
L27 VCC25 VCCTX_LVDS2 A27 R9 VTT26 VCCSM26 AE24
K27 VCC26 P9 VTT27 VCCSM27 AE23
J27 VCC27 VCCA_SM0 AF20 +1.5VS_DDRDLL N9 VTT28 VCCSM28 AE22
H27 VCC28 VCCA_SM1 AP19 M9 VTT29 VCCSM29 AE21
K26 AF19 L9 AE20 +2.5VS
VCC29 VCCA_SM2 VTT30 VCCSM30
H26 VCC30 VCCA_SM3 AF18 J9 VTT31 VCCSM31 AE19 VCCA_LVDS (Ball A35) VCCHV(Ball A21,B21,B22) VCCTX_LVDS(Ball A27,A28,B28)
K25 VCC31 N8 VTT32 VCCSM32 AE18
J25 VCC32 VCC3G0 AE37 +1.5VS_PEG M8 VTT33 VCCSM33 AE17
K24 VCC33 VCC3G1 W37 N7 VTT34 VCCSM34 AE16 1 1 1 1 1 1 1 1
K23 U37 M7 AE15 C52 C54 C663 C98 C59 C61 C440 C420
VCC34 VCC3G2 VTT35 VCCSM35
K22 VCC35 VCC3G3 R37 1000mA N6 VTT36 VCCSM36 AE14
K21 VCC36 VCC3G4 N37 M6 VTT37 VCCSM37 AP13
2 0.1U_0402_16V4Z 2 0.01U_0402_16V7K 2 4.7U_0805_10V4Z 2 0.1U_0402_16V4Z 2 4.7U_0805_10V4Z 2 2 2
W20 VCC37 VCC3G5 L37 A6 VTT38 VCCSM38 AN13
U20 VCC38 VCC3G6 J37 N5 VTT39 VCCSM39 AM13
C C148 1 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z C
T20 VCC39 M5 VTT40 VCCSM40 AL13
K20 0.47U_0603_16V4Z N4 AK13
VCC40 VTT41 VCCSM41
V19 VCC41 M4 VTT42 VCCSM42 AJ13 (0.1uF x1, 0.01uF x1) (10uF x1, 0.1uF x1) (4.7uF x1, 0.1uF x1)
U19 VCC42 VCCA_3GPLL0 Y29 +1.5VS_3GPLL N3 VTT43 VCCSM43 AH13
2
K19 VCC43 VCCA_3GPLL1 Y28 M3 VTT44 VCCSM44 AG13
W18 VCC44 VCCA_3GPLL2 Y27 N2 VTT45 VCCSM45 AF13
V18 VCC45 M2 VTT46 VCCSM46 AE13 VCCA_CRTDAC(Ball F19,E19)
T18 VCC46 B2 VTT47 VCCSM47 AP12
+2.5VS_CRTDAC +2.5VS
K18 VCC47 VCCA_3GBG F37 0.15mA +2.5VS_3GBG V1 VTT48 VCCSM48 AN12 VCC_SYNC(Ball H20)

0.47U_0603_16V4Z
K17 G37 N1 AM12 R488
VCC48 VSSA_3GBG VTT49 VCCSM49
1 M1 VTT50 VCCSM50 AL12 2 1
+1.5VS AC1 H20 C150 G1 AK12
VCCD_HMPLL1 VCC_SYNC VTT51 VCCSM51 1_0603_5%
AC2 VCCD_HMPLL2 VCCSM52 AJ12 1 1 1 1
+1.5VS_DPLLA +1.5VS_DPLLA B23 F19 70mA +2.5VS_CRTDAC AH12 C103 C109 C664 C445
VCCA_DPLLA VCCA_CRTDAC0 2 VCCSM53

0.22U_0402_10V4Z
+1.5VS_DPLLB +1.5VS_DPLLB C35 E19 AG12
+1.5VS_HPLL VCCA_DPLLB VCCA_CRTDAC1 VCCSM54
+1.5VS_HPLL AA1 VCCA_HPLL VSSA_CRTDAC G19 1 VCCSM55 AF12
+1.5VS_MPLL 4.7U_0805_10V4Z 2 2 4.7U_0805_10V4Z 2 0.1U_0402_16V4Z 2 0.022U_0402_16V7K
+1.5VS_MPLL AA2 VCCA_MPLL VCCSM56 AE12
VCCSM57 AD11
C151 AC11
2 VCCSM58
20mils ALVISO_BGA1257 0.22U_0402_10V4Z AB11
VCCSM59 C475
1 VCCSM60 AB10 (10uF x1, 0.1uF x1) (0.1uF x1, 0.022uF x1)
GM@ AB9 0.1U_0402_16V4Z C161
VCCSM61
VCCSM62 AP8 V1. 8_DDR_CAP6 2 1 0.1U_0402_16V4Z
C153
VCCSM63 AM1 V1. 8_DDR_CAP4 2 1
2
VCCSM64 AE1 V1. 8_DDR_CAP3 2 1
C160
0.1U_0402_16V4Z
ALVISO_BGA1257 +1.5VS
+1.5VS
VCCD_TVDAC (Ball D19) VCCDQ_TVDAC (Ball H17)
+2.5VS_3GBG 0.1U_0402_16V4Z 0.1U_0402_16V4Z
GM@ VCCD_LVDS(Ball A25,B25,B26) 0.1U_0402_16V4Z 0.1U_0402_16V4Z
(0.1uF x1)
B B
1 2 +2.5VS 1 1 1 1
R338 0_0603_5% C65 +1.5VS_PEG R31 1 1 1 1 1 1
C75 C456 C76 + (220uF x1, 10uF x2) 0_0805_5% C78 C74 C449 C429 C432 C427
1
4.7U_0805_10V4Z 1 2 +1.5VS
C408 2 2 2
2 150U_D2_6.3VM 1
0.1U_0402_16V4Z 1 1 1 4.7U_0805_10V4Z 2 2 2 2 2 2
2 0.1U_0402_16V4Z C44 C43 C42 + C39
0.1U_0402_16V4Z 0.022U_0402_16V7K 0.022U_0402_16V7K
2 2 2 2 470U_D2_2.5VM (10uF x1, 0.1uF x1) (0.1uF x1, 0.022uF x1) (0.1uF x1, 0.022uF x1)
22U_1206_16V4Z_V1 4.7U_0805_10V4Z
+1.5VS_DPLLA L5 +1.5VS_DPLLB L4
0_0603_5% 0_0603_5% +1.5VS_DDRDLL R354
60mA 60mA
1 2 +1.5VS 1 2 +1.5VS 0_0603_5%
Change to 0 ohm Change to 0 ohm 1 2 +1.5VS
1 1 1 1
C93 C89 C49 C51 +1.05VS
1 1 950mA(0.47uF x2, 0.22uF x2)
C443 C444
2.2U_0805_16V4Z 2.2U_0805_16V4Z
2 22U_1206_16V4Z_V1 2 0.1U_0402_16V4Z 2 22U_1206_16V4Z_V1 2 0.1U_0402_16V4Z
2 2 VCCA_TVDAC VCCA_TVBG
1 1 1 1
C489 C158 C159 C490 120mA +3VS_DAC (Ball H18)
22U_1206_16V4Z_V1 0.1U_0402_16V4Z CHB1608U301_0603
+3VS 1 2 22U_1206_16V4Z_V1 0.022U_0402_16V7K 0.022U_0402_16V7K
2 2 2 2 L26
1 1 1 1 1 1 1
2.2U_0805_16V4Z 2.2U_0805_16V4Z C465 C469 C453 C455 C454 C448
+1.5VS_HPLL L7 +1.5VS_MPLL L6 +
0_0603_5% 0_0603_5% +1.5VS_3GPLL R344 L21 C481 GM@ GM@
60mA 60mA 2 2 2 2 2 2
A 1 2 +1.5VS 1 2 +1.5VS 0.5_0603_1% 0_0603_5% GM@ A
2 150U_D2_6.3VM
Change to 0 ohm Change to 0 ohm 1 2 +3GPLL 1 2 +1.5VS
1 1 1 1 4.7U_0805_10V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z
C164 C157 C163 C156 1 1 Change to 0 ohm
C423 For TV-Out Wave Issue (0.1uF x1, 0.022uF x1) (0.1uF x1, 0.022uF x1)
C421
2 22U_1206_16V4Z_V1 2 0.1U_0402_16V4Z 2 22U_1206_16V4Z_V1 2 0.1U_0402_16V4Z 0.1U_0402_16V4Z
2 2
Security Classification Compal Secret Data Compal Electronics, Inc.
10U_1206_16V4Z 2005/08/22 2008/08/22 Title
Issued Date Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Alviso POWER(4/5)
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number R ev
1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
HTW00 M/B LA-2871
Date: Saturday, August 20, 2005 Sheet 9 of 41
5 4 3 2 1
5 4 3 2 1

U 5H
U5I U5J
+1.05VS L12 VTT_NCTF17 VCCSM_NCTF31 AB12 +1.8V
M12 VTT_NCTF16 VCCSM_NCTF30 AC12 Y1 VSS271 AL24 VSS267
N12 VTT_NCTF15 VCCSM_NCTF29 AD12 D2 VSS270 VSSALVDS B36 AN24 VSS266 VSS67 AC32
P12 VTT_NCTF14 VCCSM_NCTF28 AB13 G2 VSS269 A26 VSS265 VSS66 AD32
R12 VTT_NCTF13 VCCSM_NCTF27 AC13 J2 VSS268 VSS195 AA11 E26 VSS264 VSS65 AJ32
T12 VTT_NCTF12 VCCSM_NCTF26 AD13 L2 VSS260 VSS194 AF11 G26 VSS263 VSS64 AN32
U12 VTT_NCTF11 VCCSM_NCTF25 AC14 P2 VSS259 VSS193 AG11 J26 VSS262 VSS63 D33
V12 VTT_NCTF10 VCCSM_NCTF24 AD14 T2 VSS258 VSS192 AJ11 B27 VSS261 VSS62 E33
D W12 VTT_NCTF9 VCCSM_NCTF23 AC15 V2 VSS257 VSS191 AL11 E27 VSS129 VSS61 F33 D
L13 VTT_NCTF8 VCCSM_NCTF22 AD15 AD2 VSS256 VSS190 AN11 G27 VSS128 VSS60 G33
M13 VTT_NCTF7 VCCSM_NCTF21 AC16 AE2 VSS255 VSS189 B12 W27 VSS127 VSS59 H33
N13
P13
R13
T13
U13
VTT_NCTF6
VTT_NCTF5
VTT_NCTF4
VTT_NCTF3
VCCSM_NCTF20
VCCSM_NCTF19
VCCSM_NCTF18
VCCSM_NCTF17
AD16
AC17
AD17
AC18
AD18
AH2
AL2
AN2
A3
C3
VSS254
VSS253
VSS252
VSS251
VSS
VSS188
VSS187
VSS186
VSS185
D12
J12
A14
B14
F14
AA27
AB27
AF27
AG27
AJ27
VSS126
VSS125
VSS124
VSS123
VSS VSS58
VSS57
VSS56
VSS55
J33
K33
L33
M33
N33
VTT_NCTF2 VCCSM_NCTF16 VSS250 VSS184 VSS122 VSS54
V13 VTT_NCTF1 VCCSM_NCTF15 AC19 AA3 VSS249 VSS183 J14 AL27 VSS121 VSS53 P33
W13 VTT_NCTF0 VCCSM_NCTF14 AD19 AB3 VSS248 VSS182 K14 AN27 VSS120 VSS52 R33
VCCSM_NCTF13 AC20 AC3 VSS247 VSS181 AG14 E28 VSS119 VSS51 T33
VCCSM_NCTF12 AD20 AJ3 VSS246 VSS180 AJ14 W28 VSS118 VSS50 U33
Y12 VSS_NCTF68 VCCSM_NCTF11 AC21 C4 VSS245 VSS179 AL14 AA28 VSS117 VSS49 V33
AA12 VSS_NCTF67 VCCSM_NCTF10 AD21 H4 VSS244 VSS178 AN14 AB28 VSS116 VSS48 W33
Y13 VSS_NCTF66 VCCSM_NCTF9 AC22 L4 VSS243 VSS177 C15 AC28 VSS115 VSS47 AD33
AA13 VSS_NCTF65 VCCSM_NCTF8 AD22 P4 VSS242 VSS176 K15 A29 VSS114 VSS46 AF33
L14 VSS_NCTF64 VCCSM_NCTF7 AC23 U4 VSS241 VSS175 A16 D29 VSS113 VSS45 AL33
M14 VSS_NCTF63 VCCSM_NCTF6 AD23 Y4 VSS240 VSS174 D16 E29 VSS112 VSS44 C34
N14 VSS_NCTF62 VCCSM_NCTF5 AC24 AF4 VSS239 VSS173 H16 F29 VSS111 VSS43 AA34
P14 VSS_NCTF61 VCCSM_NCTF4 AD24 AN4 VSS238 VSS172 K16 G29 VSS110 VSS42 AB34
R14 VSS_NCTF60 VCCSM_NCTF3 AC25 E5 VSS237 VSS171 AL16 H29 VSS109 VSS41 AC34
T14 VSS_NCTF59 VCCSM_NCTF2 AD25 W5 VSS236 VSS170 C17 L29 VSS108 VSS40 AD34
U14 VSS_NCTF58 VCCSM_NCTF1 AC26 AL5 VSS235 VSS169 G17 P29 VSS107 VSS39 AH34
V14 VSS_NCTF57 VCCSM_NCTF0 AD26 AP5 VSS234 VSS168 AF17 U29 VSS106 VSS38 AN34
W14 VSS_NCTF56 B6 VSS233 VSS167 AJ17 V29 VSS105 VSS37 B35
Y14 VSS_NCTF55 VCC_NCTF78 L17 +1.05VS J6 VSS232 VSS166 AN17 W29 VSS104 VSS36 D35
AA14 VSS_NCTF54 VCC_NCTF77 M17 L6 VSS231 VSS165 A18 AA29 VSS103 VSS35 E35
AB14 VSS_NCTF53 VCC_NCTF76 N17 P6 VSS230 VSS164 B18 AD29 VSS102 VSS34 F35
L15 VSS_NCTF52 VCC_NCTF75 P17 T6 VSS229 VSS163 U18 AG29 VSS101 VSS33 G35
M15 T17 AA6 AL18 AJ29 H35
NCTF

VSS_NCTF51 VCC_NCTF74 VSS228 VSS162 VSS100 VSS32


N15 VSS_NCTF50 VCC_NCTF73 U17 AC6 VSS227 VSS161 C19 AM29 VSS99 VSS31 J35
P15 VSS_NCTF49 VCC_NCTF72 V17 AE6 VSS226 VSS160 H19 C30 VSS98 VSS30 K35
C C
R15 VSS_NCTF48 VCC_NCTF71 W17 AJ6 VSS225 VSS159 J19 Y30 VSS97 VSS29 L35
T15 VSS_NCTF47 VCC_NCTF70 L18 G7 VSS224 VSS158 T19 AA30 VSS96 VSS28 M35
U15 VSS_NCTF46 VCC_NCTF69 M18 V7 VSS223 VSS157 W19 AB30 VSS95 VSS27 N35
V15 VSS_NCTF45 VCC_NCTF68 N18 AA7 VSS222 VSS156 AG19 AC30 VSS94 VSS26 P35
W15 VSS_NCTF44 VCC_NCTF67 P18 AG7 VSS221 VSS155 AN19 AE30 VSS93 VSS25 R35
Y15 VSS_NCTF43 VCC_NCTF66 R18 AK7 VSS220 VSS154 A20 AP30 VSS92 VSS24 T35
AA15 VSS_NCTF42 VCC_NCTF65 Y18 AN7 VSS219 VSS153 D20 D31 VSS91 VSS23 U35
AB15 VSS_NCTF41 VCC_NCTF64 L19 C8 VSS218 VSS152 E20 E31 VSS90 VSS22 V35
L16 VSS_NCTF40 VCC_NCTF63 M19 E8 VSS217 VSS151 F20 F31 VSS89 VSS21 W35
M16 VSS_NCTF39 VCC_NCTF62 N19 L8 VSS216 VSS150 G20 G31 VSS88 VSS20 Y35
N16 VSS_NCTF38 VCC_NCTF61 P19 P8 VSS215 VSS149 V20 H31 VSS87 VSS19 AE35
P16 VSS_NCTF37 VCC_NCTF60 R19 Y8 VSS214 VSS148 AK20 J31 VSS86 VSS18 C36
R16 VSS_NCTF36 VCC_NCTF59 Y19 AL8 VSS213 VSS147 C21 K31 VSS85 VSS17 AA36
T16 VSS_NCTF35 VCC_NCTF58 L20 A9 VSS212 VSS146 F21 L31 VSS84 VSS16 AB36
U16 VSS_NCTF34 VCC_NCTF57 M20 H9 VSS211 VSS145 AF21 M31 VSS83 VSS15 AC36
V16 VSS_NCTF33 VCC_NCTF56 N20 K9 VSS210 VSS144 AN21 N31 VSS82 VSS14 AD36
W16 VSS_NCTF32 VCC_NCTF55 P20 T9 VSS209 VSS143 A22 P31 VSS81 VSS13 AE36
Y16 VSS_NCTF31 VCC_NCTF54 R20 V9 VSS208 VSS142 D22 R31 VSS80 VSS12 AF36
AA16 VSS_NCTF30 VCC_NCTF53 Y20 AA9 VSS207 VSS141 E22 T31 VSS79 VSS11 AJ36
AB16 VSS_NCTF29 VCC_NCTF52 L21 AC9 VSS206 VSS140 J22 U31 VSS78 VSS10 AL36
R17 VSS_NCTF28 VCC_NCTF51 M21 AE9 VSS205 VSS139 AH22 V31 VSS77 VSS9 AN36
Y17 VSS_NCTF27 VCC_NCTF50 N21 AH9 VSS204 VSS138 AL22 W31 VSS76 VSS8 E37
AA17 VSS_NCTF26 VCC_NCTF49 P21 AN9 VSS203 VSS137 H23 AD31 VSS75 VSS7 H37
AB17 VSS_NCTF25 VCC_NCTF48 T21 D10 VSS202 VSS136 AF23 AG31 VSS74 VSS6 K37
AA18 VSS_NCTF24 VCC_NCTF47 U21 L10 VSS201 VSS135 B24 AL31 VSS73 VSS5 M37
AB18 VSS_NCTF23 VCC_NCTF46 V21 Y10 VSS200 VSS134 D24 A32 VSS72 VSS4 P37
AA19 VSS_NCTF22 VCC_NCTF45 W21 AA10 VSS199 VSS133 F24 C32 VSS71 VSS3 T37
AB19 VSS_NCTF21 VCC_NCTF44 L22 F11 VSS198 VSS132 J24 Y32 VSS70 VSS2 V37
AA20 VSS_NCTF20 VCC_NCTF43 M22 H11 VSS197 VSS131 AG24 AA32 VSS69 VSS1 Y37
AB20 VSS_NCTF19 VCC_NCTF42 N22 Y11 VSS196 VSS130 AJ24 AB32 VSS68 VSS0 AG37
R21 VSS_NCTF18 VCC_NCTF41 P22
B Y21 R22 B
VSS_NCTF17 VCC_NCTF40
AA21 VSS_NCTF16 VCC_NCTF39 T22
AB21 U22 ALVISO_BGA1257 ALVISO_BGA1257
VSS_NCTF15 VCC_NCTF38
Y22 VSS_NCTF14 VCC_NCTF37 V22
AA22 VSS_NCTF13 VCC_NCTF36 W22 GM@ GM@
AB22 VSS_NCTF12 VCC_NCTF35 L23
Y23 VSS_NCTF11 VCC_NCTF34 M23
AA23 VSS_NCTF10 VCC_NCTF33 N23
AB23 VSS_NCTF9 VCC_NCTF32 P23
Y24 VSS_NCTF8 VCC_NCTF31 R23
AA24 VSS_NCTF7 VCC_NCTF30 T23
AB24 VSS_NCTF6 VCC_NCTF29 U23
Y25 VSS_NCTF5 VCC_NCTF28 V23
AA25 VSS_NCTF4 VCC_NCTF27 W23
AB25 VSS_NCTF3 VCC_NCTF26 L24
Y26 VSS_NCTF2 VCC_NCTF25 M24
AA26 VSS_NCTF1 VCC_NCTF24 N24
AB26 VSS_NCTF0 VCC_NCTF23 P24
VCC_NCTF22 R24
+1.05VS V25 VCC_NCTF10 VCC_NCTF21 T24
W25 VCC_NCTF9 VCC_NCTF20 U24
L26 VCC_NCTF8 VCC_NCTF19 V24
M26 VCC_NCTF7 VCC_NCTF18 W24
N26 VCC_NCTF6 VCC_NCTF17 L25
P26 VCC_NCTF5 VCC_NCTF16 M25
R26 VCC_NCTF4 VCC_NCTF15 N25
T26 VCC_NCTF3 VCC_NCTF14 P25
U26 VCC_NCTF2 VCC_NCTF13 R25
V26 VCC_NCTF1 VCC_NCTF12 T25
W26 VCC_NCTF0 VCC_NCTF11 U25

A A
ALVISO_BGA1257

GM@

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2005/08/22 Deciphered Date 2008/08/22 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Alviso POWER(5/5)
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number R ev
1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
HTW00 M/B LA-2871
Date: Saturday, August 20, 2005 Sheet 10 of 41
5 4 3 2 1
5 4 3 2 1

+1.8V +1.8V

+1.8V
Layout note : Place one 0.1u cap close to every DDR-SODIMM pin
JP16
one 2.2u cap close to every 2 0.1u cap
+DIMM_VREF 1 VREF VSS 2
3 4 DDRA_SDQ4 +1.8V
DDRA_SDQ0 VSS DQ4 DDRA_SDQ5
5 DQ0 DQ5 6

1
DDRA_SDQ1 7 8 2.2U_0805_16V4Z 2.2U_0805_16V4Z 2.2U_0805_16V4Z 10U_0805_10V4Z
DQ1 VSS DDRA_SDM0 R23
9 VSS DM0 10
DDRA_SDQS0# 11 12 1K_0402_1% 1 1 1 1 1 1 1 1
7 DDRA_SDQS0# DDRA_SDQS0 DQS0# VSS DDRA_SDQ6 C82 C141 C79 C474 C84 C142 C73 C80
7 DDRA_SDQS0 13 DQS0 DQ6 14
15 16 DDRA_SDQ7

2
DDRA_SDQ2 VSS DQ7
17 DQ2 VSS 18 +DIMM_VREF
DDRA_SDQ3 DDRA_SDQ12 2 2 2 2 2 2 2 2
19 DQ3 DQ12 20

1
21 22 DDRA_SDQ13 1 1
DDRA_SDQ8 VSS DQ13 C30 C26 R20
D 23 DQ8 VSS 24 D
DDRA_SDQ9 25 26 DDRA_SDM1 1K_0402_1% 2.2U_0805_16V4Z 2.2U_0805_16V4Z 2.2U_0805_16V4Z 10U_0805_10V4Z
DQ9 DM1 0.1U_0402_16V4Z
27 VSS VSS 28
DDRA_SDQS1# 2 2
2.2U_0805_16V4Z +1.8V
29 30 DDRA_CLK0 6

2
7 DDRA_SDQS1# DDRA_SDQS1 DQS1# CK0
7 DDRA_SDQS1 31 DQS1 CK0# 32 DDRA_CLK0# 6
33 34 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z
DDRA_SDQ10 VSS VSS DDRA_SDQ14
35 DQ10 DQ14 36
DDRA_SDQ11 37 38 DDRA_SDQ15 1 1 1 1 1 1
DQ11 DQ15 C92 C102 C112 C119 C126 C135
39 VSS VSS 40

DDRA_SMA[0..13] 2 2 2 2 2 2
41 VSS VSS 42 7 DDRA_SMA[0..13]
DDRA_SDQ16 43 44 DDRA_SDQ20
DDRA_SDQ17 DQ16 DQ20 DDRA_SDQ21 DDRA_SDQ[0..63]
45 DQ17 DQ21 46 7 DDRA_SDQ[0..63]
47 48 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z
DDRA_SDQS2# VSS VSS DDRA_SDM[0..7]
7 DDRA_SDQS2# 49 DQS2# NC 50 7 DDRA_SDM[0..7]
DDRA_SDQS2 51 52 DDRA_SDM2 +1.8V
7 DDRA_SDQS2 DQS2 DM2 +0.9VS
53 VSS VSS 54
DDRA_SDQ18 55 56 DDRA_SDQ22 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z
DDRA_SDQ19 DQ18 DQ22 DDRA_SDQ23
57 DQ19 DQ23 58
59 VSS VSS 60 1 1 1 1 1 1
DDRA_SDQ24 61 62 DDRA_SDQ28 DDRA_SBS2# 1 4 C94 C99 C113 C120 C127 C133
DDRA_SDQ25 DQ24 DQ28 DDRA_SDQ29 DDRA_CKE0
63 DQ25 DQ29 64 2 3
65 66 RP27 56_0404_4P2R_5%
DDRA_SDM3 VSS VSS DDRA_SDQS3# 2 2 2 2 2 2
67 DM3 DQS3# 68 DDRA_SDQS3# 7
69 70 DDRA_SDQS3 DDRA_SMA9 1 4
NC DQS3 DDRA_SDQS3 7 DDRA_SMA12
71 VSS VSS 72 2 3
DDRA_SDQ26 73 74 DDRA_SDQ30 RP28 56_0404_4P2R_5% 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z
DDRA_SDQ27 DQ26 DQ30 DDRA_SDQ31
75 DQ27 DQ31 76
77 78 DDRA_SMA5 1 4
DDRA_CKE0 VSS VSS DDRA_CKE1 DDRA_SMA8
6 DDRA_CKE0 79 CKE0 NC/CKE1 80 DDRA_CKE1 6 2 3 Layout note :
81 82 RP29 56_0404_4P2R_5%
C VDD VDD C
83 NC NC/A15 84 Place one cap close to every 2 pull up resistors termination to
DDRA_SBS2# 85 86 DDRA_SMA1 1 4
7 DDRA_SBS2# BA2 NC/A14 DDRA_SMA3
+0.9VS
87 VDD VDD 88 2 3
DDRA_SMA12 89 90 DDRA_SMA11 RP30 56_0404_4P2R_5%
DDRA_SMA9 A12 A11 DDRA_SMA7
91 A9 A7 92
DDRA_SMA8 93 94 DDRA_SMA6 DDRA_SBS0# 1 4 +0.9VS
A8 A6 DDRA_SMA10
95 VDD VDD 96 2 3
DDRA_SMA5 97 98 DDRA_SMA4 RP31 56_0404_4P2R_5% 0.1U_0402_16V4Z 0.1U_0402_16V4Z
DDRA_SMA3 A5 A4 DDRA_SMA2
99 A3 A2 100
DDRA_SMA1 101 102 DDRA_SMA0 DDRA_SCS#0 1 4 1 1 1 1 1
A1 A0 DDRA_SW E# C87 C446 C451 C460 C467
103 VDD VDD 104 2 3
DDRA_SMA10 105 106 DDRA_SBS1# RP16 56_0404_4P2R_5%
A10/AP BA1 DDRA_SBS1# 7
DDRA_SBS0# 107 108 DDRA_SRAS#
7 DDRA_SBS0# BA0 RAS# DDRA_SRAS# 7 2 2 2 2 2
DDRA_SW E# 109 110 DDRA_SCS#0 DDRA_ODT1 1 4
7 DDRA_SW E# WE# S0# DDRA_SCS#0 6
111 112 DDRA_SRAS# 2 3
DDRA_SCAS# VDD VDD DDRA_ODT0 RP13 56_0404_4P2R_5%
7 DDRA_SCAS# 113 CAS# ODT0 114 DDRA_ODT0 6
DDRA_SCS#1 115 116 DDRA_SMA13 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z
6 DDRA_SCS#1 NC/S1# NC/A13
117 VDD VDD 118
DDRA_ODT1 119 120 +0.9VS
6 DDRA_ODT1 NC/ODT1 NC
121 122 DDRA_CKE1 1 4
DDRA_SDQ32 VSS VSS DDRA_SDQ36 DDRA_SMA11 0.1U_0402_16V4Z 0.1U_0402_16V4Z
123 DQ32 DQ36 124 2 3
DDRA_SDQ33 125 126 DDRA_SDQ37 RP1 56_0404_4P2R_5%
DQ33 DQ37
127 VSS VSS 128 1 1 1 1 1
DDRA_SDQS4# 129 130 DDRA_SDM4 DDRA_SMA7 1 4 C147 C111 C137 C459 C464
7 DDRA_SDQS4# DDRA_SDQS4 DQS4# DM4 DDRA_SMA6
7 DDRA_SDQS4 131 DQS4 VSS 132 2 3
133 134 DDRA_SDQ38 RP4 56_0404_4P2R_5%
DDRA_SDQ34 VSS DQ38 DDRA_SDQ39 2 2 2 2 2
135 DQ34 DQ39 136
DDRA_SDQ35 137 138 DDRA_SMA4 1 4
DQ35 VSS DDRA_SDQ44 DDRA_SMA2
139 VSS DQ44 140 2 3
DDRA_SDQ40 141 142 DDRA_SDQ45 RP7 56_0404_4P2R_5% 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z
DDRA_SDQ41 DQ40 DQ45
143 DQ41 VSS 144
B 145 146 DDRA_SDQS5# DDRA_SMA0 1 4 +0.9VS B
DDRA_SDM5 VSS DQS5# DDRA_SDQS5 DDRA_SDQS5# 7 DDRA_SBS1#
147 DM5 DQS5 148 DDRA_SDQS5 7 2 3
149 150 RP10 56_0404_4P2R_5% 0.1U_0402_16V4Z
DDRA_SDQ42 VSS VSS DDRA_SDQ46
151 DQ42 DQ46 152
DDRA_SDQ43 153 154 DDRA_SDQ47 DDRA_SCS#1 1 4 1 1 1
DQ43 DQ47 DDRA_SCAS# C100 C122 C129
155 VSS VSS 156 2 3
DDRA_SDQ48 157 158 DDRA_SDQ52 RP32 56_0404_4P2R_5%
DDRA_SDQ49 DQ48 DQ52 DDRA_SDQ53
159 DQ49 DQ53 160
DDRA_ODT0 2 2 2
161 VSS VSS 162 1 4
163 164 DDRA_SMA13 2 3
NC,TEST CK1 DDRA_CLK1 6
165 166 RP19 56_0404_4P2R_5%
VSS CK1# DDRA_CLK1# 6
DDRA_SDQS6# 167 168 0.1U_0402_16V4Z 0.1U_0402_16V4Z
7 DDRA_SDQS6# DDRA_SDQS6 DQS6# VSS DDRA_SDM6
7 DDRA_SDQS6 169 DQS6 DM6 170
171 VSS VSS 172 For EMI Request:
DDRA_SDQ50 173 174 DDRA_SDQ54
DDRA_SDQ51 DQ50 DQ54 DDRA_SDQ55
175 DQ51 DQ55 176 +1.8V 1 2 C655 +1.5VS
177 178 100P_0402_50V8J
DDRA_SDQ56 VSS VSS DDRA_SDQ60
179 DQ56 DQ60 180 1 2 C656
DDRA_SDQ57 181 182 DDRA_SDQ61 100P_0402_50V8J
DQ57 DQ61
183 VSS VSS 184 1 2 C657
DDRA_SDM7 185 186 DDRA_SDQS7# 100P_0402_50V8J
DM7 DQS7# DDRA_SDQS7 DDRA_SDQS7# 7
187 VSS DQS7 188 DDRA_SDQS7 7 1 2 C658
DDRA_SDQ58 189 190 100P_0402_50V8J
DDRA_SDQ59 DQ58 VSS DDRA_SDQ62
191 DQ59 DQ62 192
193 194 DDRA_SDQ63 +1.8V
D_CK_SDATA VSS DQ63
12,13 D_CK_SDATA 195 SDA VSS 196
D_CK_SCLK 197 198 1 2 100P_0402_50V8J
12,13 D_CK_SCLK SCL SAO
+3VS 199 200 R50 1 10K_0402_5%
2
VDDSPD SA1 R51 10K_0402_5% 1 1
C659 C660
PTI_A5652D-A0G16-P
A A
2 2

DIMM0 STD H:5.2mm (BOT) 100P_0402_50V8J

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2005/08/22 Deciphered Date 2008/08/22 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
DDRII-SODIMM SLOT0
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number R ev
1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
HTW00 M/B LA-2871
Date: Saturday, August 20, 2005 Sheet 11 of 41
5 4 3 2 1
A B C D E

+1.8V +1.8V

JP15 ***
1 2 +DIMM_VREF +1.8V
+DIMM_VREF VREF VSS
3 4 DDRB_SDQ4
DDRB_SDQ0 VSS DQ4 DDRB_SDQ5
5 DQ0 DQ5 6
DDRB_SDQ1 7 8 1 1
DQ1 VSS DDRB_SDM0
9 VSS DM0 10 1 1
DDRB_SDQS0# 11 12 C27 C31 C185+ C33 +
7 DDRB_SDQS0# DDRB_SDQS0 DQS0# VSS DDRB_SDQ6
7 DDRB_SDQS0 13 DQS0 DQ6 14
15 16 DDRB_SDQ7 2.2U_0805_16V4Z 150U_D2_6.3VM
DDRB_SDQ2 VSS DQ7 2 2
0.1U_0402_16V4Z 2 2
150U_D2_6.3VM
17 DQ2 VSS 18
DDRB_SDQ3 19 20 DDRB_SDQ12
DQ3 DQ12 DDRB_SDQ13
21 VSS DQ13 22
DDRB_SDQ8 23 24
1 DQ8 VSS 1
DDRB_SDQ9 25 26 DDRB_SDM1
DQ9 DM1
27 VSS VSS 28 Layout note : Place one 0.1u cap close to every DDR-SODIMM pin
DDRB_SDQS1# 29 30
7 DDRB_SDQS1# DDRB_SDQS1 DQS1# CK0 DDRB_CLK0 6 one 2.2u cap close to every 2 0.1u cap
7 DDRB_SDQS1 31 DQS1 CK0# 32 DDRB_CLK0# 6
33 34 +1.8V
DDRB_SDQ10 VSS VSS DDRB_SDQ14
35 DQ10 DQ14 36
DDRB_SDQ11 37 38 DDRB_SDQ15 2.2U_0805_16V4Z 2.2U_0805_16V4Z 2.2U_0805_16V4Z 10U_0805_10V4Z
DQ11 DQ15
39 VSS VSS 40
1 1 1 1 1 1 1 1
C81 C86 C85 C139 C140 C136 C71 C72
41 VSS VSS 42
DDRB_SDQ16 43 44 DDRB_SDQ20 DDRB_SMA[0..13]
DQ16 DQ20 7 DDRB_SMA[0..13] 2 2 2 2 2 2 2 2
DDRB_SDQ17 45 46 DDRB_SDQ21
DQ17 DQ21 DDRB_SDQ[0..63]
47 VSS VSS 48 7 DDRB_SDQ[0..63]
DDRB_SDQS2# 49 50
7 DDRB_SDQS2# DDRB_SDQS2 DQS2# NC DDRB_SDM2 DDRB_SDM[0..7] 2.2U_0805_16V4Z 2.2U_0805_16V4Z 2.2U_0805_16V4Z 10U_0805_10V4Z
7 DDRB_SDQS2 51 DQS2 DM2 52 7 DDRB_SDM[0..7]
53 VSS VSS 54
DDRB_SDQ18 55 56 DDRB_SDQ22 +1.8V
DDRB_SDQ19 DQ18 DQ22 DDRB_SDQ23
57 DQ19 DQ23 58
59 60 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z
DDRB_SDQ24 VSS VSS DDRB_SDQ28
61 DQ24 DQ28 62
DDRB_SDQ25 63 64 DDRB_SDQ29 1 1 1 1 1 1
DQ25 DQ29 C91 C101 C110 C118 C125 C131
65 VSS VSS 66
DDRB_SDM3 67 68 DDRB_SDQS3#
DM3 DQS3# DDRB_SDQS3 DDRB_SDQS3# 7
69 NC DQS3 70 DDRB_SDQS3 7 2 2 2 2 2 2
71 VSS VSS 72
DDRB_SDQ26 73 74 DDRB_SDQ30
DDRB_SDQ27 DQ26 DQ30 DDRB_SDQ31
75 DQ27 DQ31 76
77 78 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z
DDRB_CKE0 VSS VSS DDRB_CKE1
6 DDRB_CKE0 79 CKE0 NC/CKE1 80 DDRB_CKE1 6
81 82 +0.9VS +1.8V
2 VDD VDD 2
83 NC NC/A15 84
DDRB_SBS2# 85 86 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z
7 DDRB_SBS2# BA2 NC/A14
87 88 DDRB_SBS2# 1 4
DDRB_SMA12 VDD VDD DDRB_SMA11 DDRB_CKE0
89 A12 A11 90 2 3 1 1 1 1 1 1
DDRB_SMA9 91 92 DDRB_SMA7 RP2 56_0404_4P2R_5% C95 C106 C114 C121 C128 C132
DDRB_SMA8 A9 A7 DDRB_SMA6
93 A8 A6 94
95 96 DDRB_SMA9 1 4
DDRB_SMA5 VDD VDD DDRB_SMA4 DDRB_SMA12 2 2 2 2 2 2
97 A5 A4 98 2 3
DDRB_SMA3 99 100 DDRB_SMA2 RP5 56_0404_4P2R_5%
DDRB_SMA1 A3 A2 DDRB_SMA0
101 A1 A0 102
103 104 DDRB_SMA5 1 4 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z
DDRB_SMA10 VDD VDD DDRB_SBS1# DDRB_SMA8
105 A10/AP BA1 106 DDRB_SBS1# 7 2 3
DDRB_SBS0# 107 108 DDRB_SRAS# RP8 56_0404_4P2R_5%
7 DDRB_SBS0# BA0 RAS# DDRB_SRAS# 7
DDRB_SW E# 109 110 DDRB_SCS#0
7 DDRB_SW E# WE# S0# DDRB_SCS#0 6
111 112 DDRB_SMA1 1 4 Layout note :
DDRB_SCAS# VDD VDD DDRB_ODT0 DDRB_SMA3
7 DDRB_SCAS# 113 CAS# ODT0 114 DDRB_ODT0 6 2 3
DDRB_SCS#1 115 116 DDRB_SMA13 RP11 56_0404_4P2R_5% Place one cap close to every 2 pull up resistors termination to
6 DDRB_SCS#1 NC/S1# NC/A13
117 VDD VDD 118 +0.9VS
DDRB_ODT1 119 120 DDRB_SBS0# 1 4
6 DDRB_ODT1 NC/ODT1 NC +0.9VS
121 122 DDRB_SMA10 2 3
DDRB_SDQ32 VSS VSS DDRB_SDQ36 RP14 56_0404_4P2R_5%
123 DQ32 DQ36 124
DDRB_SDQ33 125 126 DDRB_SDQ37 0.1U_0402_16V4Z 0.1U_0402_16V4Z
DQ33 DQ37 DDRB_SCAS#
127 VSS VSS 128 1 4
DDRB_SDQS4# 129 130 DDRB_SDM4 DDRB_SW E# 2 3 1 1 1 1 1
7 DDRB_SDQS4# DDRB_SDQS4 DQS4# DM4 RP17 56_0404_4P2R_5% C107 C117 C124 C134 C143
7 DDRB_SDQS4 131 DQS4 VSS 132
133 134 DDRB_SDQ38
DDRB_SDQ34 VSS DQ38 DDRB_SDQ39 DDRB_ODT1
135 DQ34 DQ39 136 1 4
DDRB_SDQ35 DDRB_SCS#1 2 2 2 2 2
137 DQ35 VSS 138 2 3
139 140 DDRB_SDQ44 RP20 56_0404_4P2R_5%
DDRB_SDQ40 VSS DQ44 DDRB_SDQ45
141 DQ40 DQ45 142
DDRB_SDQ41 143 144 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z
3 DQ41 VSS DDRB_SDQS5# DDRB_CKE1 3
145 VSS DQS5# 146 DDRB_SDQS5# 7 1 4
DDRB_SDM5 147 148 DDRB_SDQS5 DDRB_SMA11 2 3 +0.9VS
DM5 DQS5 DDRB_SDQS5 7 RP3 56_0404_4P2R_5%
149 VSS VSS 150
DDRB_SDQ42 151 152 DDRB_SDQ46 0.1U_0402_16V4Z 0.1U_0402_16V4Z
DDRB_SDQ43 DQ42 DQ46 DDRB_SDQ47 DDRB_SMA7
153 DQ43 DQ47 154 1 4
155 156 DDRB_SMA6 2 3 1 1 1 1 1
DDRB_SDQ48 VSS VSS DDRB_SDQ52 RP6 56_0404_4P2R_5% C115 C123 C130 C138 C149
157 DQ48 DQ52 158
DDRB_SDQ49 159 160 DDRB_SDQ53
DQ49 DQ53 DDRB_SMA4
161 VSS VSS 162 1 4
DDRB_SMA2 2 2 2 2 2
163 NC,TEST CK1 164 DDRB_CLK1 6 2 3
165 166 RP9 56_0404_4P2R_5%
VSS CK1# DDRB_CLK1# 6
DDRB_SDQS6# 167 168
7 DDRB_SDQS6# DDRB_SDQS6 DQS6# VSS DDRB_SDM6 DDRB_SMA0 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z
7 DDRB_SDQS6 169 DQS6 DM6 170 1 4
171 172 DDRB_SBS1# 2 3 +0.9VS
DDRB_SDQ50 VSS VSS DDRB_SDQ54 RP12 56_0404_4P2R_5%
173 DQ50 DQ54 174
DDRB_SDQ51 175 176 DDRB_SDQ55 0.1U_0402_16V4Z
DQ51 DQ55 DDRB_SRAS#
177 VSS VSS 178 1 4
DDRB_SDQ56 179 180 DDRB_SDQ60 DDRB_SCS#0 2 3 1 1 1
DDRB_SDQ57 DQ56 DQ60 DDRB_SDQ61 RP15 56_0404_4P2R_5% C104 C90 C96
181 DQ57 DQ61 182
183 VSS VSS 184
DDRB_SDM7 185 186 DDRB_SDQS7# DDRB_ODT0 1 4
DM7 DQS7# DDRB_SDQS7 DDRB_SDQS7# 7 DDRB_SMA13 2 2 2
187 VSS DQS7 188 DDRB_SDQS7 7 2 3
DDRB_SDQ58 189 190 RP18 56_0404_4P2R_5%
DDRB_SDQ59 DQ58 VSS DDRB_SDQ62
191 DQ59 DQ62 192
193 194 DDRB_SDQ63 0.1U_0402_16V4Z 0.1U_0402_16V4Z
D_CK_SDATA VSS DQ63
11,13 D_CK_SDATA 195 SDA VSS 196
D_CK_SCLK 197 198 1 2
11,13 D_CK_SCLK SCL SAO
+3VS 199 200 R48 1 2 10K_0402_5% +3VS
VDDSPD SA1 R49 10K_0402_5%

P-TWO_A5692B-A0G16-P
4 4

DIMM1 STD H:9.2mm (BOT)


Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2005/08/22 Deciphered Date 2008/08/22 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
DDRII-SODIMM SLOT1
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number R ev
1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
HTW00 M/B LA-2871
Date: Saturday, August 20, 2005 Sheet 12 of 41
A B C D E
A B C D E F G H

L8
KC FBM-L11-201209-221LMAT_0805 40mil
+CLK_VDD1
Clock Generator
+CLK_VDD48 +CLK_VDDREF +3VS 1 2
FSC FSB FSA CPU SRC PCI 1
C240
1
C238
1 1 1 1 1 1
C235 C214 C223 C229 C220 C215
CLKSEL0 CLKSEL1 CLKSEL2 MHz MHz MHz 0.047U_0402_16V7K 2.2U_0805_16V4Z 0.047U_0402_16V7K 0.047U_0402_16V7K 0.047U_0402_16V7K 0.047U_0402_16V7K
2 2.2U_0805_16V4Z 2 0.047U_0402_16V7K 2 2 2 2 2 2
1 0 1 100 100 33.3
*
0 0 1 133 100 33.3
1 1
0 1 1 166 100 33.3 +CLK_VCCA 1 2 +CLK_VDD1
+CLK_VDD1 R103
U9
40mil 2.2_0402_5% L10 +CLK_VDD2
0 1 0 200 100 33.3 1 1
KC FBM-L11-201209-221LMAT_0805
+CLK_VDD2 40mil
21 VDDPCIEX_0 +3VS 1 2
28 37 C222 C225
VDDPCIEX_1 VDDA 2 2.2U_0805_16V4Z 2 0.047U_0402_16V7K
+3VS Table : ICS 954226AG 34 VDDPCIEX_2 1 1 1
GNDA 38
1 VDDPCI_0
7 C252 C246 C247
CLKSEL2 VDDPCI_1 PM_STP_PCI# 2 2.2U_0805_16V4Z 2 0.047U_0402_16V7K 2 0.047U_0402_16V7K
1 2 PCI/SRC_STOP# 55 PM_STP_PCI# 18
R137 10K_0402_5% +CLK_VDD1
54 PM_STP_CPU#
CPU_STOP# PM_STP_CPU# 18,40
1 2 CLK_PCI0
R143 10K_0402_5% 42 VDDCPU
Y3 1 2 +CLK_VDDREF 48 VDDREF
1 2 CLK_PCI2 14.318MHZ_16PF_DSX840GA R134 1_0402_5% 15mil
R150 10K_0402_5% C249 41 CLK_CPU1 R114 1 2 33_0402_5% CLK_MCH_BCLK
CPUCLKT1 CLK_MCH_BCLK 6
1 1 2 +CLK_VDD48 11 VDD48
30P_0402_50V8J R138 2.2_0402_5% 15mil 40 CLK_CPU1# R108 1 2 33_0402_5% CLK_MCH_BCLK#
CPUCLKC1 CLK_MCH_BCLK# 6
1 2 CLK_PCI1 CLK_MCH_BCLK 1 2
R144 10K_0402_5% C244 XTALIN 50 R113 49.9_0402_1%
30P_0402_50V8J X1 CLK_MCH_BCLK# 1 2
2

XTALOUT 49 44 CLK_CPU0 R128 1 2 33_0402_5% CLK_CPU_BCLK R107 49.9_0402_1%


X2 CPUCLKT0 CLK_CPU_BCLK 4
CLK_CPU_BCLK 1 2
CLK_ICH_48M R136 1 2 12_0402_5% 43 CLK_CPU0# R120 1 2 33_0402_5% CLK_CPU_BCLK# R127 49.9_0402_1%
18 CLK_ICH_48M CPUCLKC0 CLK_CPU_BCLK# 4
CLK_SD_48M5IN1@ R135 1 2 12_0402_5% CLKSEL2 12 CLK_CPU_BCLK# 1 2
23 CLK_SD_48M FS_A/USB_48MHz
CLK_14M_CODEC R147 2 1 33_0402_5% CLKSEL0 53 R119 49.9_0402_1%
27 CLK_14M_CODEC REF1/FSLC/TEST_SEL
CLK_14M_VGA_SS R149 2 1 33_0402_5%
2 15 CLK_14M_VGA_SS 2
PM@ CLKSEL1 16 36
FSLB/TEST_MODE CPUCLKT2_ITP/PCIEXT6

Without VGA_SS, use 33ohm 35 CLK_PCIE_CARD 1 2


CPUCLKC2_ITP/PCIEXC6 NEW CARD@ R80 49.9_0402_1%
CLK_PCI_LAN 1 2 CLK_PCI5 5 CLK_PCIE_CARD# 1 2
21 CLK_PCI_LAN PCICLK5
R153 33_0402_5% NEW CARD@ R68 49.9_0402_1%
CLK_PCI_MINI 1 2 CLK_PCI4 4 33 CLK_PCIE_SATA 1 2
26 CLK_PCI_MINI PCICLK4 PEREQ1#/PCIEXT5
R152 33_0402_5% R83 49.9_0402_1%
CLK_PCI_SIO 1 2 CLK_PCI3 3 32 R93 2 1 0_0402_5% CLK_PCIE_SATA# 1 2
32 CLK_PCI_SIO PCICLK3 PEREQ2#/PCIEXC5 PCIEC_CLKREQ# 24
R151 33_0402_5% NEW CARD@ R71 49.9_0402_1%
CLK_PCI_PCM 1 2 CLK_PCI2 56 CLK_MCH_3GPLL 1 2
23 CLK_PCI_PCM PCICLK2/REQ_SEL
R160 33_0402_5% 31 CLK_SRC5 R81 1 2 33_0402_5% CLK_PCIE_CARD R90 49.9_0402_1%
PCIEXT4 CLK_PCIE_CARD 24
CLK_PCI_LPC 1 2 CLK_PCI1 9 NEW CARD@ CLK_MCH_3GPLL# 1 2
29 CLK_PCI_LPC SELPCIEX_LCDCLK#/PCICLK_F1
R142 33_0402_5% 30 CLK_SRC5# R69 1 2 33_0402_5% CLK_PCIE_CARD# R77 49.9_0402_1%
PCIEXC4 CLK_PCIE_CARD# 24
NEW CARD@ CLK_PCIE_VGA 1 2
R102 PM@49.9_0402_1%
CLK_PCI_ICH 1 2 CLK_PCI0 8 26 CLK_SRC4 R82 1 2 33_0402_5% CLK_PCIE_SATA CLK_PCIE_VGA# 1 2
16 CLK_PCI_ICH ITP_EN/PCICLK_F0 SATACLKT CLK_PCIE_SATA 17
R139 33_0402_5% R100 PM@49.9_0402_1%
D_CK_SCLK 46 27 CLK_SRC4# R70 1 2 33_0402_5% CLK_PCIE_SATA# CLK_PCIE_ICH 1 2
11,12 D_CK_SCLK SCLK SATACLKC CLK_PCIE_SATA# 17
R112 49.9_0402_1%
CLK_PCIE_ICH# 1 2
D_CK_SDATA 47 24 CLK_SRC3 R89 1 2 33_0402_5% CLK_MCH_3GPLL R105 49.9_0402_1%
11,12 D_CK_SDATA SDATA PCIEXT3 CLK_MCH_3GPLL 8
CLK_DREF_SSC 1 2
25 CLK_SRC3# R76 1 2 33_0402_5% CLK_MCH_3GPLL# R116 49.9_0402_1%
PCIEXC3 CLK_MCH_3GPLL# 8
1 2 CLKIREF 39 IREF
CLK_DREF_SSC# 1 2
R106 475_0402_1% 15mil R110 49.9_0402_1%
+3VS 22 CLK_SRC2 R101 1 2 33_0402_5% CLK_PCIE_VGA CLK_DREF_96M 1 2
PCIEXT2 CLK_PCIE_VGA 15
R133 PM@ R130 49.9_0402_1%
4.7K_0402_5% 23 CLK_SRC2# R99 1 2 33_0402_5% CLK_PCIE_VGA# CLK_DREF_96M# 1 2
PCIEXC2 CLK_PCIE_VGA# 15
2

PM@ R122 49.9_0402_1%


G

1 2 +3VS
3 1 3 D_CK_SCLK 19 CLK_SRC1 R111 1 2 33_0402_5% CLK_PCIE_ICH 3
18,24 CK_SCLK PCIEXT1 CLK_PCIE_ICH 18
D

Q12 20 CLK_SRC1# R104 1 2 33_0402_5% CLK_PCIE_ICH#


PCIEXC1 CLK_PCIE_ICH# 18
2N7002_SOT23 13 GND_0
29 17 CLK_SRC0 R115 1 2 33_0402_5% CLK_DREF_SSC
GND_1 LCDCLK_SS/PCIEX0T CLK_DREF_SSC 6
+3VS 2 18 CLK_SRC0# R109 1 2 33_0402_5% CLK_DREF_SSC#
GND_2 LCDCLK_SS/PCIEX0C CLK_DREF_SSC# 6
R132
4.7K_0402_5% 45 GND_3
2

CLK_DOT R129 1 2 33_0402_5% CLK_DREF_96M


G

1 2 +3VS DOTT_96MHz 14 CLK_DREF_96M 6


51 15 CLK_DOT# R121 1 2 33_0402_5% CLK_DREF_96M#
GND_4 DOTC_96MHz CLK_DREF_96M# 6
1 3 D_CK_SDATA
18,24 CK_SDATA
6
D

Q11 GND_5
2N7002_SOT23 +3VS 1 2 VGATE 6,18,40
R140 10K_0402_5%

2
G
10 VTT_POWERGD# 1 3
+1.05VS +1.05VS VTT_PWRGD#/PD

S
52 CLK_REF 1 2 CLK_14M_SIO Q15
REF0 CLK_14M_SIO 32
R145 @ 33_0402_5% 2N7002_SOT23
2

R157 R124
@ 1K_0402_5% @ 1K_0402_5% ICS954226AGT_TSSOP56 1 2 CLK_ICH_14M
CLK_ICH_14M 18
R146 33_0402_5%
R148 R156 R123 R125
4.7K_0402_5% 8.2K_0402_5% 4.7K_0402_5% 0_0402_5% Without SIO, use 33ohm
1

CLKSEL0 1 2 1 2 CLKSEL1 1 2 1 2
MCH_CLKSEL0 6 MCH_CLKSEL1 6
1 2 2 1 CPU_BSEL0 5 1 2 2 1 CPU_BSEL1 5
4 R162 R161 R118 R117 4
@ 0_0402_5% 0_0402_5% @ 0_0402_5% 0_0402_5%

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2005/08/22 Deciphered Date 2008/08/22 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Clock Generator
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number R ev
1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
HTW00 M/B LA-2871
Date: Saturday, August 20, 2005 Sheet 13 of 41
A B C D E F G H
A B C D E

CRT Connector +5VS +R_CRT_VCC +CRT_VCC


D5 D22
@ DAN217_SC59 @ DAN217_SC59 W=40mils
D3 W=40mils

1
2 1 F1

RB411D_SOT23 POLYSW ITCH_1A


1
D4
@ DAN217_SC59 C388

3
0.1U_0402_16V4Z
2
1 +3VS 1

Pull down for impedance match JP13


6
11
R321 1 2 PM@ 0_0402_5% CRT_R 1 2 CRT_R_L 1
15 VGA_CRT_R
1 2 L3 7
8 GMCH_CRT_R
R320 GM@ 0_0402_5% FCM2012C-800_0805 12
R325 1 2 PM@ 0_0402_5% CRT_G 1 2 CRT_G_L 2
15 VGA_CRT_G
1 2 L17 8
8 GMCH_CRT_G
R324 GM@ 0_0402_5% FCM2012C-800_0805 13
R331 1 2 PM@ 0_0402_5% CRT_B 1 2 CRT_B_L 3
15 VGA_CRT_B
1 2 1 1 1 L1 1 1 1 DDC_MD2
+CRT_VCC 9
8 GMCH_CRT_B

1
R330 GM@ 0_0402_5% C14 C17 C16 FCM2012C-800_0805 C13 C391 C11 14
R6 R7 R5 4
8P_0402_50V8K 8P_0402_50V8K 8P_0402_50V8K 8P_0402_50V8K 1 10
150_0402_1% 150_0402_1% 150_0402_1% 2 2 2 2 2 2 C9 15
8P_0402_50V8K 8P_0402_50V8K 5

2
2 TYCO_1470801-1
1 2 CRT_HSYNC_L 100P_0402_50V8J
L16 FCM1608C-121T_0603
DSUB_12
1 2 CRT_VSYNC_L
+CRT_VCC L2 FCM1608C-121T_0603 1

1 2 2 1 1 1
C392 0.1U_0402_16V4Z R302 10K_0402_5% C10
C390 C12 2

5
1
2 10P_0402_50V8K 10P_0402_50V8K 68P_0402_50V8K DSUB_15 2
2 2

P
OE#
1 2 CRT_HSYNC 2 4 CRT_HSYNC_B 1
15 VGA_CRT_HSYNC A Y
R334 PM@ 0_0402_5%

G
1 2 U25 C8
8 GMCH_CRT_HSYNC
R335 GM@ 39_0402_5% SN74AHCT1G125GW_SOT353-5 68P_0402_50V8K

3
2
+CRT_VCC

1 2
C15 0.1U_0402_16V4Z

5
1
+CRT_VCC

P
OE#
1 2 CRT_VSYNC 2 4 CRT_VSYNC_B
15 VGA_CRT_VSYNC A Y
R326 PM@ 0_0402_5%

G
1 2 U1
8 GMCH_CRT_VSYNC
R327 GM@ 39_0402_5% SN74AHCT1G125GW_SOT353-5

1
1 2 R10 +3VS
PM@ 0_0402_5%
R301 1 2 R11 +2.5VS
4.7K_0402_5% R300 GM@ 0_0402_5%

2
D9 D8 R9

G
2 1
@ DAN217_SC59 @ DAN217_SC59 4.7K_0402_5% GM@ 0_0402_5% GMCH_CRT_DATA 8
1 DSUB_12 1 3 1 2 R13

1
PM@ 0_0402_5% VGA_DDC_DATA 15

S
Q31

2
BSS138_SOT23

G
DSUB_15 1 3 1 2 R12
VGA_DDC_CLK 15

2
3 PM@ 0_0402_5% 3

S
2

3
Q32 2 1 R8
L29 BSS138_SOT23 GM@ 0_0402_5% GMCH_CRT_CLK 8
+3VS
FCM1608C-121T_0603
1 2
1 2 C509 @22P_0402_50V8J
15 VGA_TV_LUMA

1
R314 PM@ 0_0402_5%
1 2 TV_LUMA 1 2
8 GMCH_TV_LUMA
R315 GM@ 0_0402_5% L28 FCM1608C-121T_0603
JP19
1 2 TV_CRMA 1 2 TV_GND 1
15 VGA_TV_CRMA 1
R317 PM@ 0_0402_5% L27 FCM1608C-121T_0603 2 5
2 TV-GND_2_1394-GND 23
1 2 TV_LUMA_L 3 6
8 GMCH_TV_CRMA 3
R318 GM@ 0_0402_5% 1 2 TV_CRMA_L 4 4
100P_0402_50V8J

100P_0402_50V8J

100P_0402_50V8J

100P_0402_50V8J

C506 @22P_0402_50V8J
1

1
150_0402_1%

150_0402_1%

1 1 ALLTO_C10877-104A1-L_4P
R52 R53 C503 C508 1 1
C507 C510
2 2
TV-OUT Conn.
2

2 2 1. Y ground
2. C ground
3. Y (luminance+sync)
Pull down for impedance match 4. C (crominance)

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2005/08/22 Deciphered Date 2008/08/22 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
CRT & TVout Connector
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number R ev
1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
HTW00 M/B LA-2871
Date: Saturday, August 20, 2005 Sheet 14 of 41
A B C D E
5 4 3 2 1

+5VALW +2.5VS +3VS +1.5VS +1.8VS

PCEI_GTX_C_MRX_N[0..15] 1 1 1 1 1 1 1 1
8 PCEI_GTX_C_MRX_N[0..15]
C50 C45 C32 C405 C404 C35 C416 C413
LCD POWER CIRCUIT 8 PCEI_GTX_C_MRX_P[0..15]
PCEI_GTX_C_MRX_P[0..15]

10U_0805_10V4Z

10U_0805_10V4Z

10U_0805_10V4Z

10U_0805_10V4Z

10U_0805_10V4Z

10U_0805_10V4Z

10U_0805_10V4Z

10U_0805_10V4Z
PCIE_MTX_C_GRX_N[0..15] 2 2 2 2 2 2 2 2
8 PCIE_MTX_C_GRX_N[0..15]
PCIE_MTX_C_GRX_P[0..15]
8 PCIE_MTX_C_GRX_P[0..15]
D D
PM@ PM@ PM@ PM@ PM@ PM@ PM@
PM@
+LCDVDD +5VALW

2
VGAPWR_B+
R308
GM@ 300_0402_5%
R310
GM@ +3VS
VGA BOARD Conn.
B+ 1 2
100K_0402_5% PM@ L35 FBM-L11-201209-121LMT_0805
W=60mils JP14

1 2

1
1 2 1 2

3
D 10K_0402_5%
S
Q33 PM@ L36 FBM-L11-201209-121LMT_0805
Q34 3 4
2 1 2 2 5 6
GM@ 2N7002_SOT23 G R309 GM@
GM@ DAC_BRIG 7 8 VG A_DDC_CLK
S
3
G
AOS 3401_SOT23 +LCDVDD DISPOFF# 9 10 VGA_DDC_DATA VGA_DDC_CLK 14
D
INVT_PWM 11 12 VGA_DDC_DATA 14
2 W=60mils

1
13 14

1
D

0.01U_0402_16V7K
VGA_TV_LUMA
15 16 VGA_TV_LUMA 14
GM CH_ENVDD 2 VGA_CRT_R
8 GMCH_ENVDD 14 VGA_CRT_R 17 18
G GM@ 1 1 VGA_TV_CRMA
19 20 VGA_TV_CRMA 14
2

1 C399
100K_0402_5%

Q4 S GM@ C395 C396 VGA_CRT_G


3
14 VGA_CRT_G 21 22
BSS138_SOT23 GM@ GM@ VGA_CRT_VSYNC
23 24 VGA_CRT_VSYNC 14
R312 4.7U_0805_10V4Z 0.1U_0402_16V4Z VGA_CRT_B VGA_CRT_HSYNC
2 2 14 VGA_CRT_B 25 26 VGA_CRT_HSYNC 14
SUSP#
27 28 SUSP# 24,25,28,29,31,33,39
GM@ +3VALW ENBKL ENBKL 8,29
1

29 30
31 32
+2.5VS 33 34 +1.5VS
35 36 R22
+1.8VS 37 38 1 2 PM@ 0_0402_5% EC_SMB_CK2 4,29
R27 1 2 PM@ 0_0402_5% EC_SMB_DA2 4,29
C 39 40 C
41 42
43 44 +3VS
45 46
47 48
49 50
51 52 +5VALW
53 54
55 56
57 58
59 60 CLK_14M_VGA_SS 13
18 PLTRST_VGA# R339 1 2 PM@ 0_0402_5% 61 62 CLK_PCIE_VGA 13
6,16,18,23,29 PLT_RST# R336 1 2 @ 0_0402_5%
63 64 CLK_PCIE_VGA# 13
PCEI_GTX_C_MRX_P0 65 66 PCIE_MTX_C_GRX_P0
PCEI_GTX_C_MRX_N0 67 68 PCIE_MTX_C_GRX_N0
69 70
PCEI_GTX_C_MRX_P1 71 72 PCIE_MTX_C_GRX_P1
PCEI_GTX_C_MRX_N1 73 74 PCIE_MTX_C_GRX_N1
75 76
PCEI_GTX_C_MRX_P2 77 78 PCIE_MTX_C_GRX_P2
PCEI_GTX_C_MRX_N2 79 80 PCIE_MTX_C_GRX_N2
81 82
PCEI_GTX_C_MRX_P3 83 84 PCIE_MTX_C_GRX_P3
PCEI_GTX_C_MRX_N3 85 86 PCIE_MTX_C_GRX_N3
87 88
PCEI_GTX_C_MRX_P4 89 90 PCIE_MTX_C_GRX_P4
PCEI_GTX_C_MRX_N4 91 92 PCIE_MTX_C_GRX_N4
93 94
+3VS PCEI_GTX_C_MRX_P5 95 96 PCIE_MTX_C_GRX_P5
PCEI_GTX_C_MRX_N5 97 98 PCIE_MTX_C_GRX_N5
99 100
101 102
1

B PCEI_GTX_C_MRX_P6 PCIE_MTX_C_GRX_P6 B
R305 PCEI_GTX_C_MRX_N6 103 104 PCIE_MTX_C_GRX_N6
105 106
4.7K_0402_5% PCEI_GTX_C_MRX_P7 107 108 PCIE_MTX_C_GRX_P7
D23 PCEI_GTX_C_MRX_N7 109 110 PCIE_MTX_C_GRX_N7
2

BKOFF# DISPOFF# 111 112


29 BKOFF# 1 2 @ RB751V_SOD323 113 114
PCEI_GTX_C_MRX_P8 PCIE_MTX_C_GRX_P8
R313 0_0402_5% PCEI_GTX_C_MRX_N8 115 116 PCIE_MTX_C_GRX_N8
1 2 117 118
PCEI_GTX_C_MRX_P9 119 120 PCIE_MTX_C_GRX_P9
PCEI_GTX_C_MRX_N9 121 122 PCIE_MTX_C_GRX_N9
Width: 40mils JP1 123 124
PCEI_GTX_C_MRX_P10 125 126 PCIE_MTX_C_GRX_P10
2 1 GMCH_TXCLK- PCEI_GTX_C_MRX_N10 127 128 PCIE_MTX_C_GRX_N10
AT LEAST 60 MIL 4 3 GMCH_TXCLK- 8 129 130
GMCH_TXCLK+
6 5 GMCH_TXCLK+ 8 131 132
+LCDVDD 2 1 R307+LCDVDD_LCD 8 7
PCEI_GTX_C_MRX_P11
133 134
PCIE_MTX_C_GRX_P11
GM@ FBMA-L11-321611-121LMA30T_1206 GMCH_TXOUT0- PCEI_GTX_C_MRX_N11 PCIE_MTX_C_GRX_N11
10 9 GMCH_TXOUT0- 8 135 136
+3VS 1 2 R306 +3VS_LCD GMCH_TXOUT0+
12 11 GMCH_TXOUT0+ 8 137 138
GM@ FBMA-L11-201209-121LMT 0805 PCEI_GTX_C_MRX_P12 PCIE_MTX_C_GRX_P12
GM CH_LCD_CLK 14 13 GMCH_TXOUT2- PCEI_GTX_C_MRX_N12 139 140 PCIE_MTX_C_GRX_N12
8 GMCH_LCD_CLK 16 15 GMCH_TXOUT2- 8 141 142
8 GMCH_LCD_DATA GMCH_LCD_DATA GMCH_TXOUT2+
18 17 GMCH_TXOUT2+ 8 143 144
29 DAC_BRIG DAC_BRIG PCEI_GTX_C_MRX_P13 PCIE_MTX_C_GRX_P13
INVT_PWM 20 19 GMCH_TXOUT1- PCEI_GTX_C_MRX_N13 145 146 PCIE_MTX_C_GRX_N13
29 INVT_PWM 22 21 GMCH_TXOUT1- 8 147 148
DISPOFF# GMCH_TXOUT1+
24 23 GMCH_TXOUT1+ 8 149 150
PCEI_GTX_C_MRX_P14 PCIE_MTX_C_GRX_P14
26 25 PCEI_GTX_C_MRX_N14 151 152 PCIE_MTX_C_GRX_N14
INVPW R_B+ 28 27 153 154
30 29 PCEI_GTX_C_MRX_P15 155 156 PCIE_MTX_C_GRX_P15
ACES_88242-3000 PCEI_GTX_C_MRX_N15 157 158 PCIE_MTX_C_GRX_N15
GM@ 159 160
PM@ ACES_88081-1600
A
INVPW R_B+ A

GM@ L18 KC FBM-L11-201209-221LMAT_0805


1 2 B+
1 2
+LCDVDD_LCD C394 1 2 1 1 GM@ L19 KC FBM-L11-201209-221LMAT_0805
0.1U_0402_16V4Z GM@ C398
0.1U_0603_25V7K GM@ C397 Security Classification Compal Secret Data Compal Electronics, Inc.
+3VS_LCD C393 1 2 68P_0402_50V8K 2005/08/22 2008/08/22 Title
2 2 Issued Date Deciphered Date
0.1U_0402_16V4Z GM@ GM@
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
VGA / LCD CONN.
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number R ev
1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
HTW00 M/B LA-2871
Date: Saturday, August 20, 2005 Sheet 15 of 41
5 4 3 2 1
A B C D

1 1

RP24
1 8 PCI_SERR#
+3VS
2 7 PCI_FRAME#
3 6 PCI_TRDY#
4 5 PCI_STOP# U10B
21,23,26 PCI_AD[0..31]
PCI_AD0 E2 L5 PCI_REQ#0 Internal Pull-up.
8.2K_0804_8P4R_5% PCI_AD1 AD[0] REQ[0]#
PCI_AD2
E5
C2
AD[1] PCI GNT[0]# C1
B5 PCI_REQ#1 Sample high destination is LPC.
AD[2] REQ[1]# PCI_REQ#1 26
PCI_AD3 F5 B6 PCI_GNT#1
AD[3] GNT[1]# PCI_GNT#1 26
PCI_AD4 F3 M5 PCI_REQ#2 PCI_GNT#5
AD[4] REQ[2]# PCI_REQ#2 23
RP25 PCI_AD5 E9 F1 PCI_GNT#2
AD[5] GNT[2]# PCI_GNT#2 23
1 8 PCI_PLOCK# PCI_AD6 F2 B8 PCI_REQ#3
+3VS AD[6] REQ[3]# PCI_REQ#3 21

1
2 7 PC I_IRDY# PCI_AD7 D6 C8 PCI_GNT#3
AD[7] GNT[3]# PCI_GNT#3 21
3 6 PCI_PERR# PCI_AD8 E6 F7 PCI_REQ#4 R425
PCI_DEVSEL# PCI_AD9 AD[8] REQ[4]#/GPI[40] @ 0_0402_5%
4 5 D3 AD[9] GNT[4]#/GPO[48] E7
PCI_AD10 A2 E8 PCI_REQ#5
8.2K_0804_8P4R_5% PCI_AD11 AD[10] REQ[5]#/GPI[1] PCI_GNT#5
D2 F6

2
2 PCI_AD12 AD[11] GNT[5]#/GPO[17] PCI_REQ#6 2
D5 AD[12] REQ[6]#/GPI[0] B7 2 1 BT_DET# 31
PCI_AD13 H3 D8 R428 BT@0_0402_5%
PCI_AD14 AD[13] GNT[6]#/GPO[16]
B4 AD[14]
RP23 PCI_AD15 J5 J6 PCI_CBE#0 PCI_CBE#0 21,23,26
PCI_PIRQD# PCI_AD16 AD[15] C/BE[0]# PCI_CBE#1
+3VS 1 8 K2 AD[16] C/BE[1]# H6 PCI_CBE#1 21,23,26
2 7 PCI_PIRQB# PCI_AD17 K5 G4 PCI_CBE#2
AD[17] C/BE[2]# PCI_CBE#2 21,23,26
3 6 PCI_PIRQC# PCI_AD18 D4 G2 PCI_CBE#3
AD[18] C/BE[3]# PCI_CBE#3 21,23,26
4 5 PCI_PIRQA# PCI_AD19 L6
PCI_AD20 AD[19] PC I_IRDY#
G3 AD[20] IRDY# A3 PC I_IRDY# 21,23,26
8.2K_0804_8P4R_5% PCI_AD21 H4 E1 PCI_PAR
PCI_AD22 AD[21] PAR PCI_RST# PCI_PAR 21,23,26
H2 AD[22] PCIRST# R2 PCI_RST# 21,23,24,26,29,32
PCI_AD23 H5 C3 PCI_DEVSEL#
RP35 PCI_AD24 AD[23] DEVSEL# PCI_PERR# PCI_DEVSEL# 21,23,26
B3 AD[24] PERR# E3 PCI_PERR# 21,23,26
1 8 PCI_REQ#4 PCI_AD25 M6 C5 PCI_PLOCK#
+3VS AD[25] PLOCK#
2 7 PCI_REQ#5 PCI_AD26 B2 G5 PCI_SERR#
AD[26] SERR# PCI_SERR# 21,23,26
3 6 PCI_PIRQE# PCI_AD27 K6 J1 PCI_STOP#
AD[27] STOP# PCI_STOP# 21,23,26
4 5 PCI_REQ#3 PCI_AD28 K3 J2 PCI_TRDY#
AD[28] TRDY# PCI_TRDY# 21,23,26
PCI_AD29 A5
8.2K_0804_8P4R_5% PCI_AD30 AD[29]
L1 AD[30]
PCI_AD31 K4 AD[31] PLT_RST#
PLTRST# R5 PLT_RST# 6,15,18,23,29
RP34 G6 CLK_ICH_PCI CLK_PCI_ICH
PCICLK CLK_PCI_ICH 13
1 8 PCI_PIRQG# PCI_FRAME# J3 P6
+3VS 21,23,26 PCI_FRAME# FRAME# PME#
2 7 PCI_PIRQF#

2
3 6 PCI_REQ#1 Interrupt I/F
4 5 PCI_REQ#6 PCI_PIRQA# N2 D9 PCI_PIRQE#
23 PCI_PIRQA# PIRQ[A]# PIRQ[E]#/GPI[2]
PCI_PIRQB# L2 C7 PCI_PIRQF# R423
23 PCI_PIRQB# PIRQ[B]# PIRQ[F]#/GPI[3] PCI_PIRQF# 21
8.2K_0804_8P4R_5% PCI_PIRQC# M1 C6 PCI_PIRQG# @ 10_0402_5%
23 PCI_PIRQC# PIRQ[C]# PIRQ[G]#GPI[4] PCI_PIRQG# 26
PCI_PIRQD# L3 M3 PCI_PIRQH#
23 PCI_PIRQD# PCI_PIRQH# 26

1
PIRQ[D]# PIRQ[H]#/GPI[5]

3 RP22 AC5
RESERVED 1
C589 3
SATA[1]RXN/RSVD[1] @ 10P_0402_50V8K
+3VS 1 8 AD5 SATA[1]RXP/RSVD[2]
2 7 PCI_REQ#0 AF4
PCI_REQ#2 SATA[1]TXN/RSVD[3] 2
3 6 AG4 SATA[1]TXP/RSVD[4]
4 5 PCI_PIRQH# AC9 SATA[3]RXN/RSVD[5]
AD9 SATA[3]RXP/RSVD[6]
8.2K_0804_8P4R_5% AF8 SATA[3]TXN/RSVD[7]
AG8 SATA[3]TXP/RSVD[8]
U3 TP[3]/RSVD[9]
ICH6_BGA609

ICH6-M
(R3:SA828010890)
(R1:SA8280108B0)

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2005/08/22 Deciphered Date 2008/08/22 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
ICH6(1/4)_PCI
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number R ev
1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. HTW00 M/B LA-2871
Date: Saturday, August 20, 2005 Sheet 16 of 41
A B C D
A B C D

Place near ICH6 side.


C251
18P_0402_50V8J
2 1 ICH_RTCX1
+RTCVCC
1 1

10M_0402_5%
Y2

1
3 NC OUT 4
1

R141
R395 32.768KHZ_12.5P_1TJS125DJ2A073 2 1
NC IN U10A
1M_0402_1% C241 +1.05VS

2
18P_0402_50V8J Y1 P2 LPC_AD0
2

RTCX1 LAD[0]/FWH[0] LPC_AD0 29,32

RTC
2 1 ICH_RTCX2 Y2 N3 LPC_AD1
RTCX2 LAD[1]/FWH[1] LPC_AD1 29,32
INTRUDER# N5 LPC_AD2
LAD[2]/FWH[2] LPC_AD2 29,32
1 2 ICH_RTCRST# AA2 N4 LPC_AD3 H_FERR# 1 2

LPC
+RTCVCC RTCRST# LAD[3]/FWH[3] LPC_AD3 29,32
R394 R91 56_0402_5%
20K_0402_5% INTRUDER# AA3 N6 H_DPRSLP# 1 2
INTVRMEN INTRUDER# LDRQ[0]# LPC_DRQ#1 R95 56_0402_5%
AA5 INTVRMEN LDRQ[1]#/GPI[41] P4 LPC_DRQ#1 32
+3VS
2 1 P3 LPC_FRAME#
LFRAME#/FWH[4] LPC_FRAME# 29,32
close to RAM door J1 JOPEN D12 EE_CS
1

@ B12 R74 1 2 10K_0402_5% +3VS


R401 EE_SHCLK EC_GA20
D11 EE_DOUT A20GATE AF22 EC_GA20 29
C556 F13 AF23 H_A20M#
EE_DIN A20M# H_A20M# 4
10K_0402_5% 1U_0402_6.3V4Z

LAN
R84 2 @ 0_0402_5% H_CPUSLP#

CPU
1 2 F12 AE27 1
2

LAN_CLK CPUSLP# H_CPUSLP# 4,6


B11 AE24 R96 1 2 0_0402_5% H_DPRSLP# H_DPRSLP# 4
PHDD_LED# LAN_RSTSYNC DPRSLP#/TP[4]
DPSLP#/TP[2] AD27 H_DPSLP# 4
E12 LANRXD[0]
E11 AF24 1 2 H_FERR# H_FERR# 4
LANRXD[1] FERR# R98 56_0402_5%
C13 LANRXD[2]
AG25 H_PW RGOOD H_PW RGOOD 4
CPUPWRGD/GPO[49] MAINPW ON 34,35,37
C12 LANTXD[0]
C11 AG26 H_IG NNE# H_IGNNE# 4 R73
LANTXD[1] IGNNE#

1
C603 R429 E13 AE22 @ 330_0402_5% C
2 @ 10P_0402_50V8K @ 10_0402_5% LANTXD[2] INIT3_3V# H_INIT# Q10 2
INIT# AF27 H_INIT# 4 +1.05VS 1 2 2
1 2 2 1 AG24 H_INTR H_INTR 4 R97 B @ 2SC2411K_SC59
INTR 10K_0402_5% E

3
AC97_BITCLK C10 1 2 +3VS
27 AC97_BITCLK ACZ_BIT_CLK

AC-97/AZALIA
27 AC97_SYNC AC97_SYNC_R B9 AD23 EC_KBRST#
ACZ_SYNC RCIN# EC_KBRST# 29
AC97_RST_R# A10 AF25 H_NMI H_NMI 4 +1.05VS 1 2 2 1 THRMTRIP#
27 AC97_RST# ACZ_RST# NMI
AG27 H_SMI# H_SMI# 4 R78 75_0402_1% R79
AC_SDIN0 SMI# 56_0402_5%
27 AC97_SDIN0 F11 ACZ_SDIN[0]
27 AC97_SDIN1 F10 AE26 H_STPCLK# H_STPCLK# 4
ACZ_SDIN[1] STPCLK# H_THERMTRIP#
B10 ACZ_SDIN[2] H_THERMTRIP# 4,6
AE23 THRMTRIP#
AC97_SDOUT_R THRMTRIP#
27 AC97_SDOUT C9 ACZ_SDO
AC16 IDE_DA0 IDE_DA0 20
PHDD_LED# DA[0] IDE_DA1
29 PHDD_LED# AC19 SATALED# DA[1] AB17 IDE_DA1 20
AC17 IDE_DA2 IDE_DA2 20
DA[2]

20 SATA_DTX_C_IRX_N0 SATA_DTX_C_IRX_N0 AE3 AD16 IDE_DCS1# IDE_DCS1# 20


SATA_DTX_C_IRX_P0 SATA[0]RXN DCS1# IDE_DCS3#
20 SATA_DTX_C_IRX_P0 AD3 SATA[0]RXP DCS3# AE17 IDE_DCS3# 20
C227 1 2 3900P_0402_50V7K SATA_ITX_DRX_N0 AG2
20 SATA_ITX_C_DRX_N0 C228 1 SATA_ITX_DRX_P0 SATA[0]TXN
20 SATA_ITX_C_DRX_P0 2 3900P_0402_50V7K AF2 SATA[0]TXP IDE_DD[0..15] 20
Place near ICH6 side AD14 IDE_DD0
DD[0]

SATA
R400 1 2 1K_0402_5% SATA2_RXN AD7 SATA[2]RXN DD[1] AF15 IDE_DD1

PIDE
R399 1 2 1K_0402_5% SATA2_RXP AC7 SATA[2]RXP DD[2] AF14 IDE_DD2
AF6 AD12 IDE_DD3
SATA[2]TXN DD[3] IDE_DD4
AG6 SATA[2]TXP DD[4] AE14
AC11 IDE_DD5
CLK_PCIE_SATA# AC2 DD[5] IDE_DD6
13 CLK_PCIE_SATA# SATA_CLKN DD[6] AD11
CLK_PCIE_SATA AC1 AB11 IDE_DD7
13 CLK_PCIE_SATA SATA_CLKP DD[7] IDE_DD8
DD[8] AE13
3 AG11 AF13 IDE_DD9 3
R92 SATARBIAS AF11 SATARBIAS# DD[9] IDE_DD10
1 2 24.9_0402_1% SATARBIAS DD[10] AB12
AB13 IDE_DD11
DD[11] IDE_DD12
DD[12] AC13
AE15 IDE_DD13
R72 ID E_DIORDY DD[13] IDE_DD14
+3VS 1 2 4.7K_0402_5% DD[14] AG15
ID E_DIORDY AF16 AD13 IDE_DD15
20 ID E_DIORDY IORDY DD[15]
IDE_IRQ AB16
20 IDE_IRQ IDEIRQ
R397 1 2 8.2K_0402_5% IDE_IRQ IDE_DDACK# AB15
20 IDE_DDACK# DDACK#
IDE_DIOW # AC14 AB14 IDE_DDREQ
20 IDE_DIOW # DIOW# DDREQ IDE_DDREQ 20
IDE_DIOR# AE16
20 IDE_DIOR# DIOR#

ICH6_BGA609

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2005/08/22 Deciphered Date 2008/08/22 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
ICH6(2/4)_CPU,AC97,IDE,LPC
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number R ev
1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
HTW00 M/B LA-2871
Date: Saturday, August 20, 2005 Sheet 17 of 41
A B C D
A B C D E F G H

+3VALW

1 2 ICH_SMLINK0
R403 10K_0402_5% U10C
1 2 ICH_SMLINK1 EC_SW I# T2 H25
R410 10K_0402_5% 29 EC_SW I# RI# PERn[1]
PERp[1] H24
1 2 CK_SCLK GPI26 AF17 G27
R404 2.2K_0402_5% GPI27 SATA[0]GP/GPI[26] PETn[1]
AE18 SATA[1]GP/GPI[29] PETp[1] G26
1 2 CK_SDATA GPI28 AF18
1 SATA[2]GP/GPI[30] 1
R396 2.2K_0402_5% GPI29 AG18 K25 PCIE_PTX_C_IRX_N2
SATA[3]GP/GPI[31] PERn[2] PCIE_PTX_C_IRX_N2 24
1 2 LINKALERT# K24 PCIE_PTX_C_IRX_P2
PERp[2] PCIE_PTX_C_IRX_P2 24
R405 10K_0402_5% CK_SCLK Y4 J27 PCIE_ITX_PRX_N2 1 2 PCIE_ITX_C_PRX_N2 PCIE_ITX_C_PRX_N2 24
13,24 CK_SCLK SMBCLK PETn[2]

PCI-EXPRESS
1 2 EC_LID_OUT# CK_SDATA W5 J26 PCIE_ITX_PRX_P2 C265 0.1U_0402_16V4Z 1 2 PCIE_ITX_C_PRX_P2 PCIE_ITX_C_PRX_P2 24
13,24 CK_SDATA SMBDATA PETp[2]
R417 @ 10K_0402_5% LINKALERT# Y5 C267 0.1U_0402_16V4Z
EC_SW I# ICH_SMLINK0 LINKALERT#
1 2 W4 SMLINK[0] PERn[3] M25

GPIO
R413 10K_0402_5% ICH_SMLINK1 U6 M24
PM_BATLOW# MCH_SYNC# SMLINK[1] PERp[3]
1 2 AG21 MCH_SYNC# PETn[3] L27
R407 8.2K_0402_5% SB_SPKR F8 L26
ICH_PCIE_W AKE# 27 SB_SPKR SPKR PETp[3]
1 2
R406 1K_0402_1% W3 P24
31 SUS_STAT# SUS_STAT#/LPCPD# PERn[4]
1 2 SYSRST# P23
R409 10K_0402_5% SYSRST# PERp[4] +3VALW
U2 SYS_RESET# PETn[4] N27
PETp[4] N26
6 PM_BMBUSY# AD19 BM_BUSY#/GPI[6]
+3VS T25 DMI_MTX_IRX_N0 RP33
DMI[0]RXN DMI_MTX_IRX_N0 6
ICH_G PI7 AE19 T24 DMI_MTX_IRX_P0 USB_OC#5 4 5
GPI[7] DMI[0]RXP DMI_MTX_IRX_P0 6
1 2 ICH_G PI7 R398 1 2 0_0402_5% 29 EC_SMI# R1 R27 DMI_ITX_MRX_N0 USB_OC#4 3 6
GPI[8] DMI[0]TXN DMI_ITX_MRX_N0 6
R87 10K_0402_5% R26 DMI_ITX_MRX_P0 USB_OC#6 2 7
DMI[0]TXP DMI_ITX_MRX_P0 6

DIRECT MEDIA INTERFACE


1 2 PM_CLKRUN# 1 2 @ W6 USB_OC#7 1 8
29,30,34 AC IN SMBALERT#/GPI[11]
R67 8.2K_0402_5% D10 RB751V_SOD323 V25 DMI_MTX_IRX_N1
DMI[1]RXN DMI_MTX_IRX_N1 6
1 2 ICH_VGATE +3VALW 2 1 EC_LID_OUT# M2 V24 DMI_MTX_IRX_P1 10K_0804_8P4R_5%
29 EC_LID_OUT# GPI[12] DMI[1]RXP DMI_MTX_IRX_P1 6
R85 10K_0402_5% 100K_0402_5% R408@ R6 U27 DMI_ITX_MRX_N1
29 EC_SCI# GPI[13] DMI[1]TXN DMI_ITX_MRX_N1 6
1 2 MCH_SYNC# U26 DMI_ITX_MRX_P1 RP26
DMI[1]TXP DMI_ITX_MRX_P1 6
R88 10K_0402_5% PM_STP_PCI# AC21 USB_OC#0 4 5
13 PM_STP_PCI# STP_PCI#/GPO[18]
1 2 SERIRQ Y25 DMI_MTX_IRX_N2 USB_OC#3 3 6
DMI[2]RXN DMI_MTX_IRX_N2 6
R392 10K_0402_5% AB21 Y24 DMI_MTX_IRX_P2 USB_OC#2 2 7
31 SB_INT_FLASH_SEL# GPO[19] DMI[2]RXP DMI_MTX_IRX_P2 6
W27 DMI_ITX_MRX_N2 USB_OC#1 1 8
DMI[2]TXN DMI_ITX_MRX_N2 6
AD22 W26 DMI_ITX_MRX_P2
13,40 PM_STP_CPU# STP_CPU#/GPO[20] DMI[2]TXP DMI_ITX_MRX_P2 6
10K_0804_8P4R_5%
AB24 DMI_MTX_IRX_N3
2 DMI[3]RXN DMI_MTX_IRX_N3 6 2
1 2 PW ROK AD20 AB23 DMI_MTX_IRX_P3
GPO[21] DMI[3]RXP DMI_MTX_IRX_P3 6
R393 10K_0402_5% AD21 AA27 DMI_ITX_MRX_N3
15 PLTRST_VGA# GPO[23] DMI[3]TXN DMI_ITX_MRX_N3 6
1 2 EC_RSMRST# AA26 DMI_ITX_MRX_P3
DMI[3]TXP DMI_ITX_MRX_P3 6
R402 10K_0402_5% 2 1 SATA_HDD_RST# R485 1 2@ 0_0402_5% V3
20 SATA_HDDRST# GPIO[24]
D38 @ RB751V_SOD323 AD25 CLK_PCIE_ICH#
DMI_CLKN CLK_PCIE_ICH# 13
RP21 +3VALW 1 2 P5 AC25 CLK_PCIE_ICH
20 IDE_ODDRST# GPIO[25] DMI_CLKP CLK_PCIE_ICH 13
4 5 GPI29 R486 @ 10K_0402_5% R3
24 EXP_CPPE# GPIO[27]
3 6 GPI28 31 EC_FLASH# T3
GPI27 PM_CLKRUN# GPIO[28]
2 7 21,26 PM_CLKRUN# AF19 CLKRUN#/GPIO[32] DMI_ZCOMP F24
1 8 GPI26 AF20 GPIO[33] DMI_IRCOMP R424 1
AC18 GPIO[34] DMI_IRCOMP F23 2 24.9_0402_1% +1.5VS
100_1206_8P4R_5%
24 ICH_PCIE_W AKE# ICH_PCIE_W AKE# U5 C23 USB_OC#4
WAKE# OC[4]#/GPI[9] USB_OC#5
OC[5]#/GPI[10] D23
1 2 PM_DPRSLPVR SERIRQ AB20 C25 USB_OC#6
R86 100K_0402_5% 23,29,32 SERIRQ SERIRQ OC[6]#/GPI[14] USB_OC#7
OC[7]#/GPI[15] C24
EC_THERM# AC20
29 EC_THERM# THRM# USB_OC#0
Intel new update OC[0]# C27
6,13,40 VGATE 2 1 ICH_VGATE AF21 VRMPWRGD OC[1]# B27 USB_OC#1
R75 0_0402_5% B26 USB_OC#2
CLK_14M_ICH OC[2]# USB_OC#3
E10 CLK14 OC[3]# C26

CLK_48M_ICH USB20_N0

CLOCK
A27 CLK48 USBP[0]N C21 USB20_N0 32
D21 USB20_P0
USBP[0]P USB20_P0 32
V6 SUSCLK USBP[1]N A20
USBP[1]P B20
SLP_S3# T4 D19 USB20_N2
29 PM_SLP_S3# SLP_S3# USBP[2]N USB20_N2 32
SLP_S4# T5 C19 USB20_P2
SLP_S4# USBP[2]P USB20_P2 32

USB
SLP_S5# T6 A18
EC_SYS_PW ROK R220 1 SLP_S5# USBP[3]N
29 EC_SYS_PW ROK 2 0_0402_5% USBP[3]P B18
SYS_PW ROK R218 1 2@ 0_0402_5% PW ROK AA1 E17 USB20_N4
32 SYS_PW ROK PWROK USBP[4]N USB20_N4 32

POWER MGT
3 D17 USB20_P4 3
USBP[4]P USB20_P4 32
PM_DPRSLPVR AE20 B16 USB20_N5
40 PM_DPRSLPVR DPRSLPVR/TP[1] USBP[5]N USB20_N5 31
A16 USB20_P5
USBP[5]P USB20_P5 31
PM_BATLOW# V2 C15 USB20_N6
BATLOW#/TP[0] USBP[6]N USB20_N6 24
D15 USB20_P6
USBP[6]P USB20_P6 24
PBTN_OUT# U1 A14
29 PBTN_OUT# PWRBTN# USBP[7]N
USBP[7]P B14
PLT_RST# V5
6,15,16,23,29 PLT_RST# LAN_RST# USBRBIAS
USBRBIAS# A22 1 2
EC_RSMRST# Y3 B22 R430 21.5_0402_1%
29 EC_RSMRST# RSMRST# USBRBIAS
ICH6_BGA609

+3VALW C612
0.1U_0402_16V4Z
1 2
RTC Battery
14

U12A +RTCPWR
1 SLP_S4#
P

CLK_48M_ICH CLK_14M_ICH A BATT1 45@


3
13 CLK_ICH_48M 13 CLK_ICH_14M 29 PM_SLP_S5# O
2 SLP_S5# - + C311
G

B
1

2 1 1 2
1

R426 SN74LVC08APW_TSSOP14 0.1U_0402_16V4Z

1
R431 @ 10_0402_5%
@ 10_0402_5% ML1220T13RE
2
2

BAS40-04_SOT23
1
D14
4 1 4
C597 +RTCVCC

2
C611 @ 10P_0402_50V8K
@ 10P_0402_50V8K 2
2

+CHGRTC

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2005/08/22 Deciphered Date 2008/08/22 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
ICH6(3/4)_USB,PM,LAN,GPIO
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number R ev
1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
HTW00 M/B LA-2871
Date: Saturday, August 20, 2005 Sheet 18 of 41
A B C D E F G H
5 4 3 2 1

+1.5VS
Near PIN F27(C155), +1.5VS C577
P27(C154), AB27(C157) U10E +RTCVCC 0.1U_0402_16V4Z U10D
1 2 E27 VSS[172] VSS[86] F4
+1.5VS AA22 VCC1_5[1] VCC1_5[98] F9 Y6 VSS[171] VSS[85] F22

220U_D2_4VM_R12

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z
1 AA23 U17 0.1U_0402_16V4Z C571 Y27 F19
VCC1_5[2] VCC1_5[97] 0.1U_0402_16V4Z VSS[170] VSS[84]
2 2 2 AA24 VCC1_5[3] VCC1_5[96] U16 Y26 VSS[169] VSS[83] F17

C255
+ AA25 U14 1 2 Y23 E25
VCC1_5[4] VCC1_5[95] 2 2 VSS[168] VSS[82]

C601

C563

C248
AB25 U12 C554 W7 E19
VCC1_5[5] VCC1_5[94] C581 VSS[167] VSS[81]
AB26 VCC1_5[6] VCC1_5[93] U11 W25 VSS[166] VSS[80] E18
2 1 1 1 0.1U_0402_16V4Z
D AB27 VCC1_5[7] VCC1_5[92] T17 W24 VSS[165] VSS[79] E15 D
F25 T11 C5551 1
1 2 W23 E14
VCC1_5[8] VCC1_5[91] VSS[164] VSS[78]
F26 VCC1_5[9] VCC1_5[90] P17 W1 VSS[163] VSS[77] D7
F27 P11 0.1U_0402_16V4Z C557 V4 D22
VCC1_5[10] VCC1_5[89] 0.1U_0402_16V4Z VSS[162] VSS[76]
G22 M17 V27 D20

CORE
VCC1_5[11] VCC1_5[88] VSS[161] VSS[75]
G23 VCC1_5[12] VCC1_5[87] M11 1 2 V26 VSS[160] VSS[74] D18
G24 VCC1_5[13] VCC1_5[86] L17 V23 VSS[159] VSS[73] D14
G25 L16 C590 U25 D13
+5VS +3VS VCC1_5[14] VCC1_5[85] 0.1U_0402_16V4Z VSS[158] VSS[72]
H21 VCC1_5[15] VCC1_5[84] L14 U24 VSS[157] VSS[71] D10
H22 VCC1_5[16] VCC1_5[83] L12 1 2 U23 VSS[156] VSS[70] D1
J21 VCC1_5[17] VCC1_5[82] L11 U15 VSS[155] VSS[69] C4
2

2 J22 VCC1_5[18] VCC1_5[81] AA21 C562 U13 VSS[154] VSS[68] C22


R433 D12 K21 AA20 0.1U_0402_16V4Z T7 C20
VCC1_5[19] VCC1_5[80] VSS[153] VSS[67]
K22 VCC1_5[20] VCC1_5[79] AA19 1 2 T27 VSS[152] VSS[66] C18

PCIE
10_0402_5% RB751V_SOD323 L21 T26 C14
VCC1_5[21] C599 VSS[151] VSS[65]
L22 T23 B25
1

VCC1_5[22] 0.1U_0402_16V4Z +3VS 0.1U_0402_16V4Z VSS[150] VSS[64]


M21 VCC1_5[23] VCC3_3[21] AA10 T16 VSS[149] VSS[63] B24
ICH_V5REF_RUN M22 AG19 1 2 T15 B23
VCC1_5[24] VCC3_3[20] VSS[148] VSS[62]
2 2 2 N21 VCC1_5[25] VCC3_3[19] AG16 T14 VSS[147] VSS[61] B21
N22 AG13 2 2 C582 T13 B19
C300 C559 VCC1_5[26] VCC3_3[18] 0.1U_0402_16V4Z VSS[146] VSS[60]
N23 VCC1_5[27] VCC3_3[17] AD17 T12 VSS[145] VSS[59] B15
1U_0603_10V4Z C301 0.1U_0402_16V4Z N24 AC15 C217 Near PIN 1 2 T1 B13
1 1 1 VCC1_5[28] VCC3_3[16] VSS[144] VSS[58]
N25 AA17 R4 AG7

IDE
0.1U_0402_16V4Z VCC1_5[29] VCC3_3[15] C2161 1 AG13, AG16 C565 VSS[143] VSS[57]
P21 VCC1_5[30] VCC3_3[14] AA15 R25 VSS[142] VSS[56] AG3
P25 AA14 0.1U_0402_16V4Z R24 AG22
VCC1_5[31] VCC3_3[13] VSS[141] VSS[55]
P26 VCC1_5[32] VCC3_3[12] AA12 1 2 R23 VSS[140] VSS[54] AG20
P27 0.1U_0402_16V4Z R17 AG17
VCC1_5[33] C578 VSS[139] VSS[53]
R21 VCC1_5[34] R16 VSS[138] VSS[52] AG14
R22 P1 +3VS 0.1U_0402_16V4Z R15 AG12
VCC1_5[35] VCC3_3[11] VSS[137] VSS[51]

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z
T21 VCC1_5[36] VCC3_3[10] M7 2 2 2 1 2 R14 VSS[136] VSS[50] AG1
T22 VCC1_5[37] VCC3_3[9] L7 R13 VSS[135] VSS[49] AF7

C596

C588

C584
U21 L4 C608 R12 AF3
C VCC1_5[38] VCC3_3[8] 0.01U_0402_16V7K VSS[134] VSS[48] C
U22 VCC1_5[39] VCC3_3[7] J7 R11 VSS[133] VSS[47] AF26
1 1 1
V21 VCC1_5[40] VCC3_3[6] H7 1 2 P22 VSS[132] VSS[46] AF12

GROUND
PCI
V22 VCC1_5[41] VCC3_3[5] H1 P16 VSS[131] VSS[45] AF10
W21 VCC1_5[42] VCC3_3[4] E4 Near PIN A25 P15 VSS[130] VSS[44] AF1
W22 VCC1_5[43] VCC3_3[3] B1 Near PIN P14 VSS[129] VSS[43] AE7
Y21 A6 C553 P13 AE6
VCC1_5[44] VCC3_3[2] A2-A6, D1-H1 0.01U_0402_16V7K VSS[128] VSS[42]
Y22 VCC1_5[45] P12 VSS[127] VSS[41] AE25
VCCSUS1_5[3] U7 +1.5VALW 1 2 N7 VSS[126] VSS[40] AE21
+1.5VS AA6 VCC1_5[46] VCCSUS1_5[2] R7 N17 VSS[125] VSS[39] AE2
AB4 VCC1_5[47] Near PIN AA19 N16 VSS[124] VSS[38] AE12

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z
AB5 VCC1_5[48] 2 2 2 N15 VSS[123] VSS[37] AE11

USB
2 AB6 VCC1_5[49] VCCSUS1_5[1] G19 N14 VSS[122] VSS[36] AE10

C564
C592

C570
AC4 VCC1_5[50] N13 VSS[121] VSS[35] AD6
Near PIN AG5 C219 AD4 G20 N12 AD24
0.1U_0402_16V4Z VCC1_5[51] VCC1_5[78] 1 1 1 VSS[120] VSS[34]
AE4 VCC1_5[52] VCC1_5[77] F20 N11 VSS[119] VSS[33] AD2
1
AE5 VCC1_5[53] VCC1_5[76] E24 N1 VSS[118] VSS[32] AD18

SATA
AF5 VCC1_5[54] VCC1_5[75] E23 M4 VSS[117] VSS[31] AD15

USB CORE
AG5 VCC1_5[55] VCC1_5[74] E22 M27 VSS[116] VSS[30] AD10
VCC1_5[73] E21 +3VALW M26 VSS[115] VSS[29] AD1
+1.5VS AA7 VCC1_5[56] VCC1_5[72] E20 M23 VSS[114] VSS[28] AC6
AA8 D27 C594 M16 AC3
VCC1_5[57] VCC1_5[71] 0.1U_0402_16V4Z VSS[113] VSS[27]
AA9 VCC1_5[58] VCC1_5[70] D26 M15 VSS[112] VSS[26] AC26
2 AB8 VCC1_5[59] VCC1_5[69] D25 1 2 M14 VSS[111] VSS[25] AC24
AC8 VCC1_5[60] VCC1_5[68] D24 +1.5VS M13 VSS[110] VSS[24] AC23
+5VALW +3VALW C218 C610
Near PIN AG9 AD8 VCC1_5[61] +2.5VS
M12 VSS[109] VSS[23] AC22
0.1U_0402_16V4Z AE8 G8 0.1U_0402_16V4Z L25 AC12
1 VCC1_5[62] VCC1_5[67] VSS[108] VSS[22]
AE9 VCC1_5[63] 1 2 L24 VSS[107] VSS[21] AC10
2

AF9 VCC1_5[64] VCC2_5[4] AB18 L23 VSS[106] VSS[20] AB9


R432 D13 AG9 PCI/IDE RBP P7 C561 L15 AB7
VCC1_5[65] VCC2_5[2] 0.1U_0402_16V4Z VSS[105] VSS[19]
L13 VSS[104] VSS[18] AB2

0.1U_0402_16V4Z
10_0402_5% RB751V_SOD323 ICH6_VCCPLL AC27 AA18 ICH_V5REF_RUN 2 1 2 K7 AB19
B VCCDMIPLL V5REF[2] VSS[103] VSS[17] B
E26 A8 K27 AB10
1

+3VS VCC3_3[1] V5REF[1] VSS[102] VSS[16]

C560
ICH_V5REF_SUS C609 K26 AB1
ICH_V5REF_SUS 0.1U_0402_16V4Z VSS[101] VSS[15]
2 2 +1.5VS AE1 VCCSATAPLL V5REF_SUS F21 K23 VSS[100] VSS[14] AA4
C299 1
2 +3VS AG10 VCC3_3[22] 1 2 K1 VSS[99] VSS[13] AA16
C593 Near PIN A25 +1.5VS J4 AA13
1U_0603_10V4Z 0.1U_0402_16V4Z VCCUSBPLL VSS[98] VSS[12]
1 1 E26, E27
A13 VCCLAN3_3/VCCSUS3_3[1] VCCSUS3_3[20] A24 +3VALW Near PIN A24 J25 VSS[97] VSS[11] AA11
C598 F14 J24 A9
+3VS VCCLAN3_3/VCCSUS3_3[2] VSS[96] VSS[10]
0.1U_0402_16V4Z 1 G13 AB3 +RTCVCC J23 A7
VCCLAN3_3/VCCSUS3_3[3] VCCRTC VSS[95] VSS[9]
G14 VCCLAN3_3/VCCSUS3_3[4] Near PIN AB18 H27 VSS[94] VSS[8] A4
VCCLAN1_5/VCCSUS1_5[2] G11 H26 VSS[93] VSS[7] A26
+3VALW A11 VCCSUS3_3[1] VCCLAN1_5/VCCSUS1_5[1] G10 +1.5VS H23 VSS[92] VSS[6] A23
U4 VCCSUS3_3[2] G9 VSS[91] VSS[5] A21
V1 VCCSUS3_3[3] V_CPU_IO[3] AG23 G7 VSS[90] VSS[4] A19
+3VS
V7 VCCSUS3_3[4] V_CPU_IO[2] AD26 +1.05VS G21 VSS[89] VSS[3] A15
W2 AB22 C606 G12 A12
VCCSUS3_3[5] V_CPU_IO[1] 0.1U_0402_16V4Z VSS[88] VSS[2]
Y7 VCCSUS3_3[6] G1 VSS[87] VSS[1] A1

0.1U_0402_16V4Z
VCCSUS3_3[19] G16 2 1 2
+3VALW A17 VCCSUS3_3[7] VCCSUS3_3[18] G15 Near PIN AG23
C552

change 0 ohm B17 F16 ICH6_BGA609


VCCSUS3_3[8] VCCSUS3_3[17]
0.1U_0402_16V4Z

0.1U_0402_16V4Z

2 2 C17 VCCSUS3_3[9] VCCSUS3_3[16] F15


L9 R131 1 C558
F18 VCCSUS3_3[10] VCCSUS3_3[15] E16
C605

C602

0_0603_5% 0.5_0603_1% G17 D16 0.1U_0402_16V4Z


ICH6_VCCDMIPLL1 ICH6_VCCPLL VCCSUS3_3[11] VCCSUS3_3[14]
+1.5VS 1 2 2 G18 VCCSUS3_3[12] VCCSUS3_3[13] C16 1 2
1 1

2 1 ICH6_BGA609 Near PIN AG10


Near PIN A17
C239
0.1U_0402_16V4Z 1 C242 2
0.01U_0402_16V7K
A A

Near PIN
AC27

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2005/08/22 Deciphered Date 2008/08/22 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
ICH6(4/4)_POWER&GND
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number R ev
1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
HTW00 M/B LA-2871
Date: Saturday, August 20, 2005 Sheet 19 of 41
5 4 3 2 1
5 4 3 2 1

+5VSHDD +3VSHDD
0.1U_0402_16V4Z 1U_0603_10V4Z
0.1U_0402_16V4Z 1U_0603_10V4Z
Reserve for SATA HDD RESET
1 1 1 1 1 1 1 1 1 1 Q44
C630 C633
C635 C618 C619 C620 C623 C627 @ AOS 3401_SOT23
C631 C634 10U_1206_16V4Z 10U_1206_16V4Z
2 2 2 2 2 2 2 2 2 2
+5VS 3 1 +5VSHDD
1000P_0402_50V7K 0.1U_0402_16V4Z 1000P_0402_50V7K 0.1U_0402_16V4Z

PJ15
Pleace near HD CONN

2
2 1
Pleace near HD CONN 2 1 +5VS

D
@ JUMP_43X118 D
R479
+5VALW 1 2
@ 240K_0402_5%
+3VS
S-ATA HDD Conn. C661 R480 @ 10K_0402_5%
1 2 2 1

1
JP23
@ 1U_0603_10V4Z R411
GND 1 10K_0402_5%
2 SATA_ITX_C_DRX_P0 @
A+ SATA_ITX_C_DRX_P0 17

1
SATA_ITX_C_DRX_N0 D
3

2
A- SATA_ITX_C_DRX_N0 17 2N7002_SOT23 SATA_HDDRST#
GND 4 2
SATA_DTX_IRX_N0 C230 2 Q45 SATA_HDDRST# 18
B- 5 1 3900P_0402_50V7K SATA_DTX_C_IRX_N0 17
G
6 SATA_DTX_IRX_P0 C234 2 1 3900P_0402_50V7K @ S

3
B+ SATA_DTX_C_IRX_P0 17
GND 7
Q47
@ AOS 3401_SOT23
VCC3.3 8 +3VSHDD
VCC3.3 9 +3VS 3 1 +3VSHDD
VCC3.3 10
GND 11
12 PJ16

2
GND
GND 13 2 2 1 1 +3VS
VCC5 14 +5VSHDD
15 @ JUMP_43X118
VCC5 R482
VCC5 16
GND 17 +5VALW 1 2
18 @ 240K_0402_5%
RESERVED
GND 19
20 C662 R483 @ 10K_0402_5%
C VCC12 C
VCC12 21 1 2 2 1
VCC12 22
@ 1U_0603_10V4Z

SUYIN_127043FB022G208ZR_22P_RV

1
D
2N7002_SOT23 SATA_HDDRST#
2
Q48 G
@ S

3
CDROM CONN
2 1 CD_AGND
C224 10U_0805_10V4Z JP21
INT_CD_L 1 2 INT_CD_R
27 INT_CD_L INT_CD_R 27
27 CD_AGND 3 4
5 6 IDE_DD8 1 2
18 IDE_ODDRST#
IDE_DD7 7 8 IDE_DD9 R94 @ 0_0603_5%
IDE_DD6 9 10 IDE_DD10
B IDE_DD5 11 12 IDE_DD11 B
IDE_DD4 13 14 IDE_DD12
IDE_DD3 15 16 IDE_DD13
IDE_DD2 17 18 IDE_DD14
IDE_DD1 19 20 IDE_DD15
IDE_DD0 21 22 IDE_DDREQ 17
23 24 IDE_DIOR# 17
17 IDE_DIOW # 25 26
17 ID E_DIORDY 27 28 IDE_DDACK# 17
17 IDE_IRQ 29 30
PDIAG# 100K_0402_5%
17 IDE_DA1 31 32 1 R389 2 +5VS
17 IDE_DA0 33 34 IDE_DA2 17
IDE_DCS1# 35 36 IDE_DCS3# Placea caps. near CDROM
17 IDE_DCS1# W=80mils IDE_DCS3# 17
+5VS 1 2 37 38 +5VS
R388 100K_0402_5% 39 40 CONN.
+5VS 41 42
43 44 +5VS
45 46
1 R387 2 SD_CSEL 47 48
470_0402_5% 49 50 1 2 +5VS
51 52 R386 @ 100K_0402_5% 1 1 1 1
OCTEK_CDR-50JD1 IDE_DD[ 0..15] C199 C189 C200
IDE_DD[0..15] 17 C198 1U_0603_10V4Z 10U_1206_16V4Z
1000P_0402_50V7K 2 2 2 2

0.1U_0402_16V4Z

A A

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2005/08/22 Deciphered Date 2008/08/22 Title
SATA/PATA-HDD, PATA ODD Connector
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number R ev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS HTW00 M/B LA-2871 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Saturday, August 20, 2005 Sheet 20 of 41
5 4 3 2 1
5 4 3 2 1

LAN RTL8100C(L)
U3 +3VALW
PCI_AD[0..31] PCI_AD0 104 108 LAN_EEDO U26
16,23,26 PCI_AD[0..31] AD0 EEDO
PCI_AD1 103 109 LAN_EEDI 1 2 LAN_EECS 1 8
AD1 AUX/EEDI +3VALW CS VCC
PCI_AD2 102 111 LAN_EECLK R319 LAN_EECLK 2 7 1
PCI_AD3 AD2 EESK LAN_EECS 3.6K_0402_5% LAN_EEDI SK NC
98 AD3 EECS 106 3 DI NC 6
PCI_AD4 97 LAN_EEDO 4 5 C403
PCI_AD5 AD4 ACTIVITY# DO GND 0.1U_0402_16V4Z
96 AD5 LED0 117
PCI_AD6 LINK10_100# AT93C46-10SI-2.7_SO8 2
95 AD6 LED1 115
PCI_AD7 93 114
PCI_AD8 AD7 LED2
D 90 AD8 NC/LED3 113 D
PCI_AD9 89
CLK_PCI_LAN PCI_AD10 AD9 LAN_TD+
87 AD10 TXD+/MDI0+ 1
PCI_AD11 86 2 LAN_TD-
AD11 TXD-/MDI0-
1

PCI_AD12 LAN_RD+ U2
@ PCI_AD13
85
83
AD12 RXIN+/MDI1+ 5
6 LAN_RD-
Place Close to Chip
R34 PCI_AD14 AD13 RXIN-/MDI1- R16 2 LAN_TD+ RJ45_TX+
82 AD14 1 49.9_0402_1% 1 TD+ TX+ 16
10_0402_5% PCI_AD15 79 14 C20 2 1 R17 2 1 49.9_0402_1% LAN_TD- 3 14 RJ45_TX-
PCI_AD16 AD15 NC/MDI2+ TD- TX- R304 1 RJ45_GND
59 15 2 15 2 75_0402_1%
2

PCI_AD17 AD16 NC/MDI2- 0.01U_0402_16V7K CT CT


1 58 AD17 NC/MDI3+ 18 4 NC NC 13
@ PCI_AD18 57 19 C19 2 1 0.1U_0402_16V4Z 5 12
C48 PCI_AD19 AD18 NC/MDI3- NC NC R303 1 RJ45_GND
55 AD19 7 CT CT 10 2 75_0402_1%
15P_0402_50V8J PCI_AD20 53 121 LAN_X1 R14 2 1 49.9_0402_1% LAN_RD+ 6 11 RJ45_RX+
2 PCI_AD21 AD20 X1 LAN_X2 C18 R15 2 LAN_RD- RD+ RX+ RJ45_RX-
50 AD21 X2 122 2 1 1 49.9_0402_1% 8 RD- RX- 9

PCI I/F
PCI_AD22 49 10mil
PCI_AD23 AD22 R25 1
47 AD23 LWAKE 105 2 1K_0402_5% +3VS 0.01U_0402_16V7K
PCI_AD24 LAN_ISOLATE# R26 1 2 15K_0402_5% 0.5u_TS6121C
PCI_AD25
43
42
AD24 ISOLATE# 23
127 LOAN_RTSET R328 1 2 5.6K_0603_1%
Place Close to Chip
PCI_AD26 AD25 RTSET
40 AD26 NC/SMBCLK 72 10mil
PCI_AD27 39 74
PCI_AD28 AD27 NC/SMBDATA
37 AD28
PCI_AD29 36 88
PCI_AD30 AD29 NC/M66EN
34 AD30
PCI_AD31 33 10
AD31 NC/AVDDH
NC/HV 120
PCI_CBE#0 92
16,23,26 PCI_CBE#0 C/BE#0
PCI_CBE#1 77 11
16,23,26 PCI_CBE#1 C/BE#1 NC/HSDAC+
PCI_CBE#2 60 123
16,23,26 PCI_CBE#2 C/BE#2 NC/HG
PCI_CBE#3 44 124
16,23,26 PCI_CBE#3 C/BE#3 NC/LG2
126 +LAN_DVDD Q2
PCI_AD17 NC/LV2 DTA114YKA_SOT23
1 2 LAN_IDSEL 46 JP11

E
IDSEL
R36 100_0402_5%
LAN I/F +3VALWP 3 1 1 2 10mil 12 Amber LED+

47K
C
76 +3VALW R4 C

C
16,23,26 PCI_PAR PAR
61 9 300_0402_5% 11
16,23,26 PCI_FRAME# FRAME# NC/VSS Amber LED-

10K
63 13 16

B
16,23,26 PC I_IRDY# IRDY# NC/VSS SHLD2
16,23,26 PCI_TRDY# 67 TRDY# 8 PR4-

3
68 E 15
16,23,26 PCI_DEVSEL#

2
DEVSEL# CTRL25 Q5 SHLD1
16,23,26 PCI_STOP# 69 STOP# NC/GND 22 2 7 PR4+
48 B 2SB1197K_SOT23 ACTIVITY#
NC/GND C RJ45_RX-
16,23,26 PCI_PERR# 70 62 40mil 6

1
PERR# NC/GND PR2-
16,23,26 PCI_SERR# 75 SERR# NC/GND 73 +2.5V_LAN
NC/GND 112 1 1 5 PR3-
16 PCI_REQ#3 30 REQ# NC/GND 118
29 C36 C37 4
16 PCI_GNT#3 GNT# PR3+
10U_0805_10V4Z 0.1U_0402_16V4Z
2 2 RJ45_RX+
16 PCI_PIRQF# 25 INTA# 3 PR2+
8 CTRL25
CTRL25 RJ45_TX-
26,29 ONBD_LAN_PME# 31 PME# 2 PR1-
RTT3/CRTL18 125 SHLD2 14
27 RJ45_TX+ 1
16,23,24,26,29,32 PCI_RST# RST# PR1+
VDD33 26 +3VALW SHLD1 13
CLK_PCI_LAN 28 41 10
13 CLK_PCI_LAN CLK VDD33 Green LED-
PM_CLKRUN# 65 56

E
18,26 PM_CLKRUN# CLKRUN# VDD33
VDD33 71 +3VALWP 3 1 1 2 10mil 9 Green LED+

47K
84 R3

C
VDD33

1
94 300_0402_5% TYCO_3-440470-4
VDD33

10K
107

B
VDD33 Q1 R2 R1
4 GND/VSS
17 DTA114YKA_SOT23 75_0402_1% 75_0402_1%

2
GND/VSS
128

2
GND/VSS +LAN_AVDDL LINK10_100#
AVDD33/AVDDL 3 1 2 +3VALW
7 40mil L20 0_0805_5%
AVDD33/AVDDL
21 GND/VSSPST AVDD33/AVDDL 20 1 1 1
B 38 16 C401 0.1U_0402_16V4Z C409 RJ45_GND 1 2 LANGND B
GND/VSSPST NC/AVDDL
51 GND/VSSPST 20mil 1 1
66 0.1U_0402_16V4Z C406 0.1U_0402_16V4Z C3
GND/VSSPST 2 2 2 1000P_1206_2KV7K C2 C1
Y1 81 32
LAN_X1 LAN_X2 GND/VSSPST VDD25/VDD18 4.7U_0805_10V4Z
91 GND/VSSPST VDD25/VDD18 54
2 2
101 GND/VSSPST VDD25/VDD18 78
119 99 +LAN_DVDD 1 2 +2.5V_LAN
25MHZ_20P_6X25000017 GND/VSSPST VDD25/VDD18 R29 0_0805_5% 0.1U_0402_16V4Z
1 1 40mil
Power

1 1 1
C22 C21 35 24 0.1U_0402_16V4Z Termination plane should be closed
27P_0402_50V8J 27P_0402_50V8J GND NC/VDD18 C68
52 GND NC/VDD18 45 to chassis ground and also depends
2 2 C412 C66 0.1U_0402_16V4Z
80 GND NC/VDD18 64
2 2 2 on safety concern
100 GND NC/VDD18 110
116 0.1U_0402_16V4Z
NC/VDD18
+3VALW
12 +2.5V_LAN_VDD 1 2 +2.5V_LAN
AVDD25/HSDAC- R32 0_0805_5% 0.1U_0402_16V4Z 0.1U_0402_16V4Z
20mil 1 1
RTL8100C_QFP128 1 1 1 1 1 1
C34 C38
0.1U_0402_16V4Z 10U_0805_10V4Z C417 C407 C402 C69 C67 C400
2 2 0.1U_0402_16V4Z
2 2 2 2 2 2
0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z

A A

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2005/08/22 Deciphered Date 2008/08/22 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
LAN RTL8100CL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number R ev
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
HTW00 M/B LA-2871
Date: Saturday, August 20, 2005 Sheet 21 of 41
5 4 3 2 1
A B C D E

+S1_VCC +3VS

1 1

S1_A[0..25]
25 S1_A[0..25]
For Cardbus TI7411 & TI6411

M10
M12
H10
H11
H12

D19
A11

K12

K19
J12
M7

M9
S1_D[0..15]

H8
H9

N7
A5

K8
J8
25 S1_D[0..15]
U28A

VCCA
VCCA

VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC

RSVD
RSVD
S1_D10 D1
S1_D9 A_CAD31/A_D10
C1 A_CAD30/A_D9
S1_D1 D3 N1
A_CAD29/A_D1 DATA DATA_CB 25
S1_D8 C2 L6
A_CAD28/A_D8 CLOCK CLOCK_CB 25
S1_D0 B1 N2
A_CAD27/A_D0 LATCH LATCH_CB 25
S1_A0 B4
S1_A1 A_CAD26/A_A0
A4 A_CAD25/A_A1
S1_A2 E6
S1_A3 A_CAD24/A_A2
B5 A_CAD23/A_A3
S1_A4 C6 B15 +3VS
S1_A5 A_CAD22/A_A4 RSVD 1U_0603_10V4Z
B6 A_CAD21/A_A5 RSVD A16
S1_A6 G9 B16 0.1U_0402_16V4Z 0.1U_0402_16V4Z
S1_A25 A_CAD20/A_A6 RSVD
C7 A_CAD19/A_A25 RSVD A17 1 1 1 2 2
S1_A7 B7 C16
S1_A24 A_CAD18/A_A7 RSVD C297 C275 C292 C285 C278
A7 A_CAD17/A_A24 RSVD D17
S1_A17 A10 C19
S1_IOW R# A_CAD16/A_A17 RSVD 2 2 2 1 1
25 S1_IOW R# E11 A_CAD15/A_IOWR# RSVD D18
S1_A9 G11 E17 0.1U_0402_16V4Z 0.1U_0402_16V4Z
S1_IORD# A_CAD14/A_A9 RSVD
25 S1_IORD# C11 A_CAD13/A_IORD# RSVD E19
S1_A11 B11 G15
S1_OE# A_CAD12/A_A11 RSVD +3VS
25 S1_OE# C12 A_CAD11/A_OE# RSVD F18
S1_CE2# B12 H14
25 S1_CE2# A_CAD10/A_CE2# RSVD
S1_A10 A12 H15 0.1U_0402_16V4Z 0.1U_0402_16V4Z
S1_D15 A_CAD9/A_A10 RSVD
E12 A_CAD8/A_D15 RSVD G17 1 1 1 1 1
2 S1_D7 C302 2
C13 A_CAD7/A_D7 RSVD K17
S1_D13 F12 L13 C277 C291 C281 C282
S1_D6 A_CAD6/A_D13 RSVD 10U_0805_10V4Z
A13 A_CAD5/A_D6 RSVD K18
S1_D12 2 2 2 2 2
C14 A_CAD4/A_D12 RSVD L15
S1_D5 E13 L17 0.1U_0402_16V4Z 0.1U_0402_16V4Z
S1_D11 A_CAD3/A_D5 RSVD
A14 A_CAD2/A_D11 RSVD L18
S1_D4 B14 L19
S1_D3 A_CAD1/A_D4 RSVD
E14 A_CAD0/A_D3 RSVD M17
M14

S1_REG# C5
PCI 7411 RSVD
RSVD M15
N19
+S1_VCC
25 S1_REG# A_CC/BE3#/A_REG# RSVD
S1_A12 F9 N18
S1_A8 A_CC/BE2#/A_A12 RSVD
B10 A_CC/BE1#/A_A8 RSVD N15 1 1 1 1
S1_CE1# G12 M13
25 S1_CE1# A_CC/BE0#/A_CE1# RSVD
P18 C613 C600 C595 C615
S1_A13 RSVD 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z
G10 A_CPAR/A_A13 RSVD P17 0.1U_0402_16V4Z
S1_A23 2 2 2 2
C8 A_CFRAME#/A_A23 RSVD P19
S1_A22 A8 F15
S1_A15 A_CTRDY#/A_A22 RSVD
B8 A_CIRDY#/A_A15 RSVD G18
S1_A20 A9 K14
S1_A21 A_CSTOP#/A_A20 RSVD
C9 A_CDEVSEL#/A_A21 RSVD M18
S1_A19 E10 K13
S1_A14 A_CBLOCK#/A_A19 RSVD
F10 A_CPERR#/A_A14 RSVD G19
S1_WAIT# B3 H17
25 S1_WAIT# A_CSERR#/A_WAIT# RSVD
S1_INPACK# E7 J13
25 S1_INPACK# A_CREQ#/A_INPACK# RSVD
S1_WE# B9 J17
25 S1_WE# A_CGNT#/A_WE# RSVD
S1_BVD1 B2 H19
25 S1_BVD1 A_CSTSCHG/A_BVD1(STSCHG/RI) RSVD
S1_WP C3 J19
25 S1_WP A_CCLKRUN#/A_WP(IOIS16) RSVD
S1_A16 2 1 A16_CLK E9 J18
R182 33_0402_5% A_CCLK/A_A16 RSVD
C4 A_CINT#/A_READY(IREQ) RSVD B18
S1_RDY# E18
25 S1_RDY# RSVD
3 S1_RST A6 J15 3
25 S1_RST A_CRST#/A_RESET RSVD
RSVD F14
S1_BVD2 A2 A18 4510_2 2 1
25 S1_BVD2 A_CAUDIO/A_BVD2(SPKR#) RSVD
H18 R415 1K_0402_5%
S1_CD1# RSVD (44+1)10@
25 S1_CD1# C15 A_CCD1#/A_CD1# RSVD B19
S1_CD2# E5 F17
25 S1_CD2# A_CCD2#/A_CD2# RSVD
S1_VS1 A3 C17
25 S1_VS1 A_CVS1/A_VS1# RSVD
S1_VS2 E8 N13 Reserve for TI PCI4510
25 S1_VS2 A_CVS2/A_VS2# RSVD
RSVD B17
S1_D14 B13 C18
S1_D2 A_CRSVD/A_D14 RSVD
D2 F19
S1_A18 C10
A_CRSVD/A_D2
A_CRSVD/A_A18
RSVD
RSVD
RSVD
N17
A15
PCI4510 =one Slot Cardbus + 1394
+3VS 2 1 E2 A_USB_EN# RSVD K15
R436 2 @ 10K_0402_5%
1 E1
R437 @ 10K_0402_5% B_USB_EN#
PCI1510 =one Slot Cardbus
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND

7411@ PCI7411GHK_PBGA288
PCI6411 =one Slot Cardbus + 5 in 1
G7
G8
G13
H13
J9
J10
J11
K9
K10
K11
L8
L9
L10
L11
L12
M8

PCI7411 =one Slot Cardbus + 5 in 1 + 1394

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2005/08/22 Deciphered Date 2008/08/22 Title
PCI7411-1 Slot0
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number R ev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom HTW00 M/B LA-2871 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Saturday, August 20, 2005 Sheet 22 of 41
A B C D E
A B C D E

+3VS
change 0 ohm
L30 +VDPLL_33 (44+1)10@
0_0603_5% C572 Place C854 near T18 and T19
1 2 0.01U_0402_16V7K 0.1U_0402_16V4Z 1 2 FILTER1

1 1 1 1 1 0.1U_0402_16V4Z
C569 7411@
C579 C580 C583 C575 C568
10U_0805_10V4Z
2 2 2 2 2
1 2 Place C755 near T17 and T18
0.01U_0402_16V7K 0.1U_0402_16V4Z 0.1U_0402_16V4Z
change 0 ohm +3VS
C624
+3VS +AVDD_7411 2 1
1 1
0_0603_5%
2 1 0.1U_0402_16V4Z 0.01U_0402_16V7K 1U_0603_10V4Z 0.1U_0402_16V4Z 0.01U_0402_16V7K 1U_0603_10V4Z
L31 1 1 1 1 2
1 1 1 1 1
C591 C286 C604 C276 C614 C617
C269 C274 C586 C587
2 2 2 2 1

W10
M19
R13
R14
V17

V19
T18
2 2 2 2 2

W3
H1
0.1U_0402_16V4Z 0.01U_0402_16V7K
0.1U_0402_16V4Z 0.01U_0402_16V7K 10U_0805_10V4Z U28B

AVDD
AVDD
AVDD

VDPLL_33
VDPLL_15

VR_PORT
VR_PORT

VCCP
VCCP
U2 PCI_AD31
AD31 PCI_AD30
AD30 V1
MC_PW R_CTRL_0 F1 V2 PCI_AD29
24 MC_PW R_CTRL_0 MC_PWR_CTRL_0 AD29 PCI_AD[0..31]
1 2 F2 U3 PCI_AD28 PCI_AD[0..31] 16,21,26
R440 @ 0_0402_5% MC_PWR_CTRL_1 AD28 PCI_AD27 +3VS
AD27 W2
SDCD# E3 V3 PCI_AD26
24 SDCD# SD_CD# AD26
MSCD# F5 U4 PCI_AD25
24 MSCD# MS_CD# AD25

1
SMCD# F6 V4 PCI_AD24
24 SMCD# SM_CD# AD24
V5 PCI_AD23 R451
R205 1 5IN1@ 2 33_0402_5% AD23 PCI_AD22 82_0402_5%
24 MSCLK_SDCLK AD22 U5
R204 1 5IN1@ 2 33_0402_5%G5 R6 PCI_AD21 5IN1@
24 SMELWP# MS_CLK/SD_CLK/SM_EL_WP# AD21
MSBS_SDCMD_SMWE2 F3 P6 PCI_AD20
24 MSBS_SDCMD_SMWE2

2 2
MSDATA3_SDDAT3_SMD3 H5 MS_BS/SD_CMD/SM_WE# AD20 PCI_AD19
24 MSDATA3_SDDAT3_SMD3 MS_DATA3/SD_DAT3/SM_D3 AD19 W6
MSDATA2_SDDAT2_SMD2 G3 V6 PCI_AD18 D19
24 MSDATA2_SDDAT2_SMD2 MS_DATA2/SD_DAT2/SM_D2 AD18
MSDATA1_SDDAT1_SMD1 G2 U6 PCI_AD17
24 MSDATA1_SDDATA1_SMD1 MS_DATA1/SD_DAT1/SM_D1 AD17
MSDATA0_SDDAT0_SMD0 G1 R7 PCI_AD16 5IN1@
24 MSDATA0_SDDAT0_SMD0 MS_SDIO(DATA0)/SD_DAT0/SM_D0 AD16
V9 PCI_AD15 HT-191NB_BLUE_0603
R191 5IN1@ AD15 PCI_AD14
U9
24 SMRE# 1 2 33_0402_5% J5
AD14
R9 PCI_AD13 5IN1 LED

1
SMALE SD_CLK/SM_RE#/SC_GPIO1 AD13 PCI_AD12
24 SMALE J3 N9
SD_CMD/SM_ALE/SC_GPIO2 AD12
Side View

V-PORT-0603-220 M-V05_0603
SMD4 H3 V10 PCI_AD11
2 24 SMD4 SD_DAT0/SM_D4/SC_GPIO6 AD11 2
SMD5 J6 U10 PCI_AD10
24 SMD5 SD_DAT1/SM_D5/SC_GPIO5 AD10
SMD6 J1 R10 PCI_AD9
24 SMD6 SD_DAT2/SM_D6/SC_GPIO4 AD9

2
SMD7 J2 N10 PCI_AD8 D34
24 SMD7 SD_DAT3/SM_D7/SC_GPIO3 AD8

1
SDW P_SMCE# PCI_AD7 Q17 D
24 SDW P_SMCE# H7 SD_WP/SM_CE# AD7 V11
U11 PCI_AD6 5IN1_LED 2
AD6 PCI_AD5 G
AD5 R11
SMCLE J7 W12 PCI_AD4 5IN1@ S
24 SMCLE

3
SMRB# SM_CLE/SC_GPIO0 AD4 PCI_AD3 2N7002_SOT23
24 SMRB# K1 V12

1
SM_R/B AD3 PCI_AD2
K2 SM_PHYS_WP#/SC_FCB AD2 U12
N11 PCI_AD1
AD1 PCI_AD0
AD0 W13
L2 RSVD
K5 @
RSVD
C625 K3 RSVD C/BE3# W4 PCI_CBE#3 16,21,26
R434 +3VS 2 1 K7 W7
RSVD C/BE2# PCI_CBE#2 16,21,26
2 1 2 1 CLK_SD_48M R189 10K_0402_5% L1 W9

@ 15P_0402_50V8J @ 10_0402_5%
L3
L5
RSVD
RSVD PCI7411 C/BE1#
C/BE0# W11
PCI_CBE#1
PCI_CBE#0
16,21,26
16,21,26
25 VCCD1# RSVD
PAR P9 PCI_PAR 16,21,26
1 2 P12 TEST0 FRAME# V7 PCI_FRAME# 16,21,26
R177 1K_0402_5% W17 R8
NC TRDY# PCI_TRDY# 16,21,26
Reserve for TI PCI4510 FILTER1 T19 U7
RSVD IRDY# PC I_IRDY# 16,21,26
1 2 STOP# W8 PCI_STOP# 16,21,26
1K_0402_5% R442(44+1)10@ N8
DEVSEL# PCI_DEVSEL# 16,21,26
CLK_SD_48M M1 W5 PCM_ID 2 1 PCI_AD20
13 CLK_SD_48M CLK_48 IDSEL R192 C293
V8 100_0402_5% R186
PERR# PCI_PERR# 16,21,26
R168 4.7K_0402_5%
EAL20 CONN 1 +3VS 1 2 R17 PHY_TEST_MA
SERR#
REQ#
U8
U1
PCI_SERR# 16,21,26
PCI_REQ#2 16
1
@
2 1
@
2
2

1394@ T2
GNT# PCI_GNT#2 16 10_0402_5% 15P_0402_50V8J
C257 1394@ 1394@
1U_0603_10V4Z 56.2_0603_1% 56.2_0603_1% R416 6.34K_0402_1% P5 CLK_PCI_PCM
2 PCICLK CLK_PCI_PCM 13
3 R163 R164 1 2 1394@ U18 R3 R438 2 1 0_0402_5% 3
R0 PCIRST# PCI_RST# 16,21,24,26,29,32
U19 T1 R439 2 1 @ 0_0402_5%
1

R1 GRST# PLT_RST# 6,15,16,18,29


JP20 U15 TPBIAS0 T3
TPA0+ TPBIAS0 RI_OUT#/PME#
4 4 V15 TPA0P
6 3 W15 TPA0- R2 1 2 +3VS
G 3 TPB0+ TPA0N SUSPEND# R435 4.7K_0402_5%
5 G 2 2 V14 TPB0P
1 W14 TPB0- L7 PCM_SPK#
1 TPB0N SPKROUT PCM_SPK# 27
2 1 U17 TPBIAS1
2

TYCO_1470383-2 1394@ 1 2 C262 1394@ 1U_0603_10V4Z V18 N3 7411_PIRQA#


TPA1P MFUNC0 PCI_PIRQA# 16

2
1394@ R174 1394@ 1K_0402_5% W18 M5 7411_PIRQB#
TPA1N MFUNC1 PCI_PIRQB# 16
56.2_0603_1% 56.2_0603_1% 1394@ 1 2 V16 P1 7411_PIRQC# R200
TPB1P MFUNC2 PCI_PIRQC# 16
R176 R173 R172 1394@ 1K_0402_5% W16 P2 33K_0603_1%
TPB1N MFUNC3 SERIRQ 18,29,32
+AVDD_7411 1 2 M11 P3 7411_PIRQD#
1

CPS MFUNC4 PCI_PIRQD# 16


2 1 R169 1394@ 1K_0402_5% P15 N5 5IN1_LED
TV-GND_2_1394-GND 14 5IN1_LED 24

1
R170 1394@ 4.7K_0402_5% CNA MFUNC5
R19 XO MFUNC6 R1 2 1
1 R18 R444 @ 10K_0402_5%
XI
2

PJ17 R12 PC0(TEST1) SCL M3 1 2


1394@ 1394@ U13 M2 1 R201 2 300_0402_5% 2 1 +3VS
5.11K_0603_1% PC1(TEST2) SDA
VSSPLL
VSSPLL

2 1 C279 V13 R202 300_0402_5% R445 10K_0402_5%


2 1 PC2(TEST3)
AGND
AGND
AGND

R175 220P_0402_50V7K 2
VR_EN# H2
@ JUMP_43X39 18P_0402_50V8J C574
1

PJ18
2

1394@ 7411@ PCI7411GHK_PBGA288


N12
U14
U16

P14
T17

2 1 X1
2 1

2
24.576MHz_16P_3XG-24576-43E1 1
@ JUMP_43X39 1394@ R441 C621
1

1K_0402_5% 0.1U_0402_16V4Z
18P_0402_50V8J C573
2

1
1394@

4 4

PCI1510 & PCI6411 UNMOUNT THOSE PARTS


Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2005/08/22 Deciphered Date 2008/08/22 Title
PCI7411-2 PCI/5in1/1394Conn
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number R ev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom HTW00 M/B LA-2871 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Monday, August 22, 2005 Sheet 23 of 41
A B C D E
5 4 3 2 1

+VCC_5IN1 +3VS +3VS +3VS


+VCC_5IN1 +VCC_5IN1
JP9
41 XD-VCC SD-VCC 15
MS-VCC 9
MSDATA0_SDDAT0_SMD0 33
1 23 MSDATA0_SDDAT0_SMD0 XD-D0

2
MSDATA1_SDDAT1_SMD1 34 4 IN 1 CONN 16 MSCLK_SDCLK
23 MSDATA1_SDDATA1_SMD1 XD-D1 SD_CLK MSCLK_SDCLK 23
R263 R227 R243 R254 MSDATA2_SDDAT2_SMD2 35 19 MSDATA0_SDDAT0_SMD0
23 MSDATA2_SDDAT2_SMD2 XD-D2 SD-DAT0
2.2K_0402_5% 10K_0402_5% 10K_0402_5% 10K_0402_5% MSDATA3_SDDAT3_SMD3 36 20 MSDATA1_SDDAT1_SMD1
23 MSDATA3_SDDAT3_SMD3 XD-D3 SD-DAT1
5IN1@ @ @ @ SMD4 37 11 MSDATA2_SDDAT2_SMD2
23 SMD4 XD-D4 SD-DAT2
SMD5 38 12 MSDATA3_SDDAT3_SMD3
2

1
23 SMD5 XD-D5 SD-DAT3
SDCD# SMD6 39 13 MSBS_SDCMD_SMWE2
23 SMD6 XD-D6 SD-CMD
SMD7 40 21 SDCD#
23 SMD7 XD-D7 SD-CD-SW SDCD# 23
MSCD# 22
D SD-CD-COM D
MSBS_SDCMD_SMWE2 30 43 SDW P_SMCE# 1 R253 2 +VCC_5IN1
23 MSBS_SDCMD_SMWE2 XD-WE SD-WP-SW
SMCD# SMELWP# 31 44 5IN1@ 2.2K_0402_5%
23 SMELWP# XD-WP SD-WP-COM
SMALE 29
23 SMALE XD-ALE
SMRB# SMCD# 23 8 MSCLK_SDCLK
23 SMCD# XD-CD MS-SCLK
SMRB# 25 4 MSDATA0_SDDAT0_SMD0
23 SMRB# XD-R/B MS-DATA0
SMRE# 26 3 MSDATA1_SDDAT1_SMD1
23 SMRE# XD-RE MS-DATA1
SDW P_SMCE# 27 5 MSDATA2_SDDAT2_SMD2
23 SDW P_SMCE# XD-CE MS-DATA2
SMCLE 28 7 MSDATA3_SDDAT3_SMD3
23 SMCLE XD-CLE MS-DATA3
6 MSCD#
MS-INS MSCD# 23
32 2 MSBS_SDCMD_SMWE2
XD-GND MS-BS
24 XD-GND SD-GND 14
18 N.C. SD-GND 17
42 N.C. MS-GND 1
MS-GND 10
45 SHIELD GND
46 SHIELD GND
5IN1@ TAITW _R012-210-LR

C C

+3VS
SD/XD/MS/SM PWR SWITCH

2
+VCC_5IN1
R215 +VCC_5IN1
10K_0402_5%
5IN1@ U15
1 8

1
GND OUT

1
2 IN OUT 7
5IN1@ 3 6 0.1U_0402_16V4Z R216
MC_PW R_CTRL_1 IN OUT
23 MC_PW R_CTRL_0 1 R214 2 4 EN# FLG 5 1 1 470_0402_5%
C305 4.7U_0805_10V4Z 5IN1@

1
D

1U_0603_10V4Z
0_0603_5% 1 G528_SO8 5IN1@ 1U_0603_10V4Z 5IN1@

1 2
2 C303 5IN1@ C295 2 1 SMCD#
23 5IN1_LED 2 2 D
G 5IN1@ 5IN1@ R228 @ 0_0402_5%
2

Q16 S C315 2 2 1 MC_PW R_CTRL_0

3
R209 2N7002_SOT23 2 G R221 5IN1@ 0_0402_5%
10K_0402_5% S Q19

3
5IN1@ 2N7002_SOT23
@ 5IN1@
1

B B

New Card Connector +3VS +3VALW +1.5VS

JP8
16 1 CLK_PCIE_CARD 13 10U_0805_10V4Z 10U_0805_10V4Z 10U_0805_10V4Z
13,18 CK_SCLK 16 1
17 2 CLK_PCIE_CARD# 13 NEW CARD@ NEW CARD@ NEW CARD@
13,18 CK_SDATA 17 2
18 18 3 3
+1.5VS 19 19 4 4 USB20_P6 18
20 20 5 5 USB20_N6 18 1 1 1 1 1 1
+3VALW 21 6 C326 C328 C325 C324 C321 C320
21 6
22 22 7 7 PCIE_ITX_C_PRX_P2 18
+3VS 23 8 PCIE_ITX_C_PRX_N2 18 0.1U_0402_16V4Z
23 8 NEW CARD@ 2 2 2 2 2 2
24 24 9 9
25 25 10 10 PCIE_PTX_C_IRX_N2 18
26 26 11 11 PCIE_PTX_C_IRX_P2 18
27 12 0.1U_0402_16V4Z 0.1U_0402_16V4Z
16,21,23,26,29,32 PCI_RST# 27 12
18 ICH_PCIE_W AKE# 28 13 SYSON 29,30,38 NEW CARD@ NEW CARD@
28 13
18 EXP_CPPE# 29 29 14 14 SUSP# 15,25,28,29,31,33,39 60milsImax = 1.35A
A 13 PCIEC_CLKREQ# 30 30 15 15 A

NEW CARD@ 40mil Imax = 0.275A


SUYIN_200135FA030S200ZU

40mil Imax = 0.75A


Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2005/08/22 Deciphered Date 2008/08/22 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
5in1 Socket&NewCard/B Conn
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number R ev
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
HTW00 M/B LA-2871
Date: Saturday, August 20, 2005 Sheet 24 of 41
5 4 3 2 1
5 4 3 2 1

CardBus Socket
JP7
GND 1
GND 35
2 S1_D3
DATA3 S1_CD1#
CD1# 36 S1_CD1# 22
3 S1_D4
DATA4 S1_D11
DATA11 37
4 S1_D5
DATA5 S1_D12
DATA12 38
5 S1_D6
D DATA6 D
39 S1_D13
DATA13 S1_D7
DATA7 6
S1_D14
Power Switch for PCMCIA DATA14 40
7 S1_CE1#
CE1# S1_D15 S1_CE1# 22
DATA15 41
S1_A10
Power Switch for PCMCIA (PCI7411 & PCI6411 only) ADD10 8
42 S1_CE2#
CE2# S1_OE# S1_CE2# 22
OE# 9 S1_OE# 22
43 S1_VS1
VS1# S1_A11 S1_VS1 22 S1_A[0..25]
ADD11 10 S1_A[0..25] 22
U11 44 S1_IORD#
IORD# S1_A9 S1_IORD# 22 S1_D[0..15]
ADD9 11 S1_D[0..15] 22
VPPD1 3 20 45 S1_IOW R#
22 DATA_CB DATA 12V IOWR# S1_IOW R# 22
VCCD0# 4 7 12 S1_A8
22 CLOCK_CB CLOCK 12V +3VS ADD8
VPPD0 5 46 S1_A17
22 LATCH_CB LATCH ADD17
12 7464@ 13 S1_A13
15,24,28,29,31,33,39 SUSP# RESET# ADD13
15 14 2 1 C308 0.1U_0402_16V4Z 47 S1_A18
OC# NC3 R225 @ 0_1206_5% 7464@ ADD18 S1_A14
+3VS 2 1 21 SHDN# 3.3V 13 ADD14 14
1

R185 R210 10K_0402_5% C307 4.7U_0805_10V4Z 48 S1_A19


47K_0402_5% 7464@ +5VS ADD19 S1_WE#
20mil WE# 15 S1_WE# 22
7464@ +S1_VPP 8 24 2 1 49 S1_A20
AVPP NC4 R195 @ 0_1206_5% 7464@ ADD20 S1_RDY#
19 NC0 5V 2 READY 16 S1_RDY# 22
1 1 C288 0.1U_0402_16V4Z 50 S1_A21
2

+S1_VCC 5V 7464@ ADD21


VCC 17 +S1_VCC
C287 7464@ 9 11 C284 4.7U_0805_10V4Z 51
AVCC GND VCC
10 AVCC VPP 18 +S1_VPP
2 1U_0603_10V4Z 2 1 40mil 52
VPP
0.01U_0402_16V7K

17 23 19 S1_A16
C290 NC1 NC5 ADD16 S1_A22
18 NC2 NC6 22 ADD22 53
7464@ 7464@ 16 20 S1_A15
1 C294 10U_0805_10V4Z2 NC7 ADD15 S1_A23
NC8 6 ADD23 54
C S1_A12 C
ADD12 21
55 S1_A24
TPS2220ADBR_SSOP24 ADD24 S1_A7
ADD7 22
7464@ 56 S1_A25
ADD25 S1_A6
ADD6 23
57 S1_VS2
VS2# S1_A5 S1_VS2 22
ADD5 24
58 S1_RST
RESET S1_A4 S1_RST 22
ADD4 25
59 S1_WAIT#
WAIT# S1_A3 S1_WAIT# 22
ADD3 26
60 S1_INPACK#
INPACK# S1_A2 S1_INPACK# 22
ADD2 27
61 S1_REG#
REG# S1_A1 S1_REG# 22
ADD1 28
62 S1_BVD2
BVD2 S1_A0 S1_BVD2 22
ADD0 29
63 S1_BVD1
BVD1 S1_D0 S1_BVD1 22
DATA0 30
64 S1_D8
DATA8 S1_D1
DATA1 31
69 65 S1_D9
GND DATA9 S1_D2
Power Switch for PCMCIA (PCI1510 & PCI4510 only) 70 GND DATA2 32
66 S1_D10
DATA10 S1_WP
WP 33 S1_WP 22
67 S1_CD2#
U8 +S1_VCC CD2# S1_CD2# 22
1 2 15PWS@ GND 34
13 40mil C260 0.1U_0402_16V4Z 68
VCC 15PWS@ GND
VCC 12
9 11 C259 0.1U_0402_16V4Z SANTA_130606-1_LT
12V VCC
1 2 15PWS@
B C264 10U_0805_10V4Z B
+S1_VPP 1 2 15PWS@
20mil C258 0.01U_0402_16V7K
+5VS 10 1 2 15PWS@
15PWS@ VPP C263 1U_0603_10V4Z
0.1U_0402_16V4Z C237 5 Close to
5V +S1_VCC
6
4.7U_0805_10V4Z C236 5V CardBus Conn.
15PWS@ 1 VCCD0#
VCCD0
VCCD1 2 VCCD1# 23 1 1 1
15 VPPD0 C273
+3VS VPPD0 VPPD1 C271 C272
VPPD1 14
15PWS@ 10U_0805_10V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z
0.1U_0402_16V4Z C253 2 2 2
3 3.3V
4 3.3V OC 8
SHDN

4.7U_0805_10V4Z C243
GND

15PWS@
2

R159 TPS2211AIDBR_SSOP16
7

16

10K_0402_5% 15PWS@ 15PWS@ +S1_VPP


1

1 2

0.01U_0402_16V7K
C280
4.7U_0805_10V4Z
2 C283 1

A A

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2005/08/22 Deciphered Date 2008/08/22 Title
Cardbus Socket
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number R ev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom HTW00 M/B LA-2871 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Saturday, August 20, 2005 Sheet 25 of 41
5 4 3 2 1
A B C D E

+3VALW
+5VS +3VS +3VS

0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z

1 1 1 1 1 1 1 1 1 1 1 1
C637 C639 C632 C628 C626 C607 C616 C585 C576 C638 C636 C567
KS@ KS@ KS@ KS@ KS@ KS@ KS@ KS@ KS@ KS@ KS@ KS@
2 2 2 2 2 2 2 2 2 2 2 2
1 1
1000P_0402_50V7K 10U_0805_10V4Z 1000P_0402_50V7K 4.7U_0805_10V4Z 1000P_0402_50V7K 4.7U_0805_10V4Z
1000P_0402_50V7K 4.7U_0805_10V4Z

PCI_AD[0..31]
PCI_AD[0..31] 16,21,23

+3VALW

SN74LVC08APW_TSSOP14 JP24
14

U12C
9 TIP 1 2 RING
P

29 W L_OFF# A 1 2
O 8 KEY KEY
29,30,31 KILL_SW# 10 B 3 4
G

3 4
5 5 6 6
7 8
7

7 8
9 9 10 10
D31
11 11 12 12
KS@ 1 2 13 14
RB751V_SOD323 13 14
15 15 16 16
16 PCI_PIRQH# 17 17 18 18 W=40mils +5VS
+3VS W=40mils 19 19 20 20 PCI_PIRQG# 16
21 21 22 22
23 23 24 24 W=40mils +3VALW
CLK_PCI_MINI 25 26
2 13 CLK_PCI_MINI 25 26 PCI_RST# 16,21,23,24,29,32 2
27 27 28 28 W=40mils +3VS
PCI_REQ#1 29 30 PCI_GNT#1
16 PCI_REQ#1 29 30 PCI_GNT#1 16
31 32 R418 @ 0_0402_5%
PCI_AD31 31 32
33 33 34 34 1 2 MINI_PME# 21,29
PCI_AD29 35 36 R419 1 2
35 36 W LAN_BT_CLK 31
37 38 PCI_AD30 KS@ 0_0402_5%
PCI_AD27 37 38
39 39 40 40

2
KS@ 0_0402_5% PCI_AD25 41 42 PCI_AD28
41 42 PCI_AD26
31 W LAN_BT_DATA 2 1 R422 43 43 44 44 R420
45 46 PCI_AD24 @ 100K_0402_5%
16,21,23 PCI_CBE#3 45 46
PCI_AD23 47 48 MINI_IDSEL 1 2 R427 PCI_AD18
47 48
2

49 50 KS@ 100_0402_5%

1
R421 PCI_AD21 49 50 PCI_AD22
51 52
@ 100K_0402_5% PCI_AD19 53
55
51
53
52
54 54
56
PCI_AD20 Port 80 Debug Card Connector
55 56 PCI_PAR 16,21,23
PCI_AD17 57 58 PCI_AD18
1

PCI_CBE#2 57 58 PCI_AD16
59 60
16,21,23 PCI_CBE#2
16,21,23 PC I_IRDY#
PC I_IRDY# 61
59
61
60
62 62 **
63 64 PCI_FRAME# JP26
63 64 PCI_FRAME# 16,21,23
65 66 PCI_TRDY# PCI_CBE#0 20
18,21 PM_CLKRUN# 65 66 PCI_TRDY# 16,21,23 20
PCI_SERR# 67 68 PCI_STOP# PCI_AD6 19
16,21,23 PCI_SERR# 67 68 PCI_STOP# 16,21,23 19
69 70 PCI_AD4 18
PCI_PERR# 69 70 PCI_DEVSEL# PCI_AD2 18
16,21,23 PCI_PERR# 71 71 72 72 PCI_DEVSEL# 16,21,23 17 17
PCI_CBE#1 73 74 PCI_AD0 16
16,21,23 PCI_CBE#1 PCI_AD14 73 74 PCI_AD15 PCI_AD1 16
75 75 76 76 15 15
77 78 PCI_AD13 PCI_AD3 14
PCI_AD12 77 78 PCI_AD11 PCI_AD5 14
79 79 80 80 13 13
PCI_AD10 81 82 PCI_AD7 12
81 82 PCI_AD9 PCI_AD8 12
83 83 84 84 11 11
PCI_AD8 85 86 PCI_CBE#0 PCI_CBE#1 10
PCI_AD7 85 86 PCI_CBE#0 16,21,23 PCI_CBE#2 10
87 87 88 88 9 9
3 89 90 PCI_AD6 PCI_CBE#3 8 3
PCI_AD5 89 90 PCI_AD4 R470@ 0_0402_5% 8
91 91 92 92 7 7
93 94 PCI_AD2 CLK_PCI_MINI 1 2 6
PCI_AD3 93 94 PCI_AD0 6
95 95 96 96 +5VS 5 5
W=40mils 97 98 PCI_RST# 4
+5VS 97 98 4
PCI_AD1 99 100 PCI_FRAME# 3
99 100 PCI_TRDY# 3
101 101 102 102 2 2
103 104 PCI_AD9 1
103 104 1
105 105 106 106
107 108 @ ACES_85201-2005
107 108
109 109 110 110
111 111 112 112
113 113 114 114
115 116
117
119
115
117
116
118 118
120
Place under MiniPCI Socket
119 120
W=30mils 121 121 122 122 W=40mils
+5VS 123 123 124 124 +3VALW
125 125 126 126

KS@ FOX_AS0A226-S2T

CLK_PCI_MINI

4 4
1

R414

@ 10_0402_5%
2

1
C566
Security Classification Compal Secret Data Compal Electronics, Inc.
@ 10P_0402_50V8K Title
2 Issued Date Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Mini PCI Slot
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number R ev
1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. HTW00 M/B LA-2871
Date: Saturday, August 20, 2005 Sheet 26 of 41
A B C D E
A B C D E F G H

+AVDD_AC97 +3VS

AC97 Codec +VDDA 1


L13
2
CHB2012U170_0805
1 1
INT_CD_L 2 1 CD_L 1 1
20 INT_CD_L
R258 20K_0402_5% C343 C336
INT_CD_R2 1 C D_R 0.1U_0402_16V4Z 10U_0805_10V4Z C330 C329
20 INT_CD_R 2 2 10U_0805_10V4Z
R268 20K_0402_5% 0.1U_0402_16V4Z
CD_GNA 2 2
2 1
20 CD_AGND R262 20K_0402_5%

25

38
2

9
R246 R261 R257 R267 1 2

6.8K_0402_5%

6.8K_0402_5%
C353 @ 1000P_0402_50V7K

6.8K_0402_5%

AVDD1

AVDD2

DVDD1

DVDD2
1 1
0_0402_5% 1 2
C354 @ 1000P_0402_50V7K

2
1

1 2 14 35 LINEL 1 2 AMP_LEFT
C642 0.1U_0402_16V4Z AUX_L LINE_OUT_L C360 1U_0402_6.3V4Z AMP_LEFT 28
1 2 15 36 LINER 1 2 AMP_RIGHT
C643 0.1U_0402_16V4Z AUX_R LINE_OUT_R C355 1U_0402_6.3V4Z AMP_RIGHT 28
SPK_ID: HIGH: Harman/Kardom 29 SPK_SEL 16 JD2 MONO_OUT/VREFOUT3 37
NBA_PLUG
Low: No Brand 28 NBA_PLUG
1 2 17 39
C331 1U_0402_6.3V4Z JD1 HP_OUT_L
bypass EQ when NBA_PLUG = High 1 2 23 41 C327 @ 47P_0402_50V8J
C346 0.1U_0402_16V4Z LINE_IN_L HP_OUT_R
2 1
1 2 24 LINE_IN_R
C347 0.1U_0402_16V4Z 6 1 2 AC97_BITCLK
BIT_CLK AC97_BITCLK 17
CD_L 2 1 C D_LIN 18 R244 33_0402_5%
C333 1U_0402_6.3V4Z CD_L
SDATA_IN 8 1 2 AC97_SDIN0 17
C D_R 2 1 CD _RIN 20 R249 33_0402_5% C361 4.7U_0805_10V4Z
C337 1U_0402_6.3V4Z CD_R
XTL_IN 2 CLK_14M_CODEC 13 +AUD_VREF 1 2
CD_GNA 2 1 CD_GNA1 19
C334 1U_0402_6.3V4Z CD_GND
1 2
M IC 2 1 C_MIC 21
28 MIC MIC1
C340 1U_0402_6.3V4Z C368 0.1U_0402_16V4Z
22 MIC2 XTL_OUT 3

2 1 13 PHONE AFILT1 29 1 2
C332 1U_0402_6.3V4Z C350 1000P_0402_50V7K
M ONO_IN 12 30 1 2
PC_BEEP AFILT2 C351 1000P_0402_50V7K
28 +VREFOUT 1 2
VREFOUT +AUD_VREF
AC97_RST# 1 2 11 R282 0_0603_5%
2 17 AC97_RST# RESET# 2
R247 33_0402_5% 27
AC97_SYNC 1 VREF
17 AC97_SYNC 2 10 SYNC
R248 33_0402_5% 32
AC97_SDOUT 1 DCVOL
17 AC97_SDOUT 2 5 SDATA_OUT

1U_0402_6.3V4Z

0.1U_0402_16V4Z

1U_0402_6.3V4Z
0.01U_0402_16V7K
R245 33_0402_5%
45 SDA NC 31 1 1 1 1
46 33 C352 C359 C349 C348
XTLSEL VREFOUT2

1U_0402_6.3V4Z
VAUX 34

1
47 43 R281 1
29 EAPD SPDIFI/EAPD DISABLE# 2 2 2 2

0_0402_5%
SCK 44
1

48 @
R252 SPDIFO C358
NC 40
0_0402_5% 2
Ra 4 26

2
DVSS1 AVSS1 AG ND
7 DVSS2 AVSS2 42
2

U17 ALC250-VD_LQFP48
DGND AGND 1
R255
2
10K_0402_5%
+3VS
Place these components
UnPoped:Clock source from X'tal
Poped: Clock source from Clock Gen
close to Codec

MDC Connector
3 +AVDD_AC97 3
1

System Sound R275


10K_0402_5%
2

+3V_MDC 1 2
R443 0_0805_5% +3VALW
1 1 2
1

C363 R285 C356 C629


1 2 1 2 R279 10U_0805_10V4Z C622
29 BEEP# JP25
10K_0402_5% TYCO_1-1775149-2~D 10U_0805_10V4Z
1U_0402_6.3V4Z 560_0402_5% 2 2 1
1 2 0.1U_0402_16V4Z
2

C357 AC97_SDOUT R447 1 GND1 RES0


2 33_0402_5% 3 IAC_SDATA_OUT RES1 4
MONO_IN_O 2 1 M ONO_IN 5 6
AC97_SYNC R446 2 GND2 3.3V
1 33_0402_5% 7 IAC_SYNC GND3 8
1U_0402_6.3V4Z R213 2 1 33_0402_5% 9 10
17 AC97_SDIN1 IAC_SDATA_IN GND4
AC97_RST# R448 1 2 33_0402_5% 11 12 1 2 AC97_BITCLK
IAC_RESET# IAC_BITCLK
2

R287 R449 33_0402_5%


1

C366 C Q29 R286


1 2 1 2 MO NO_IN_I 2

GND
GND
GND
GND
GND
GND
23 PCM_SPK#
2.2K_0402_5%

B
2SC2411K_SC59

2 1U_0402_6.3V4Z 560_0402_5% E
3

13
14
15
16
17
18
C365
0.01U_0402_16V7K
1 Connector for MDC Rev1.5

4 C362 R283 4
18 SB_SPKR 1 2 1 2

1U_0402_6.3V4Z 560_0402_5%
1

R278 D20
10K_0402_5% RB751V_SOD323
Security Classification Compal Secret Data Compal Electronics, Inc.
2

Issued Date 2005/08/22 Deciphered Date 2008/08/22 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AC97 Codec_ALC250&MDC
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number R ev
1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
Custom
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. HTW00 M/B LA-2871
Date: Saturday, August 20, 2005 Sheet 27 of 41
A B C D E F G H
A B C D E

MICROPHONE
IN JACK
+AUD_VREF 1 2 JP28
R464 2.2K_0402_5% 5
1 2
R465 @ 2.2K_0402_5% 4
Audio AMP L14
KC FBM-L11-201209-221LMAT_0805 +AUD_VREF_J 3
1 2 6
M IC 1 2 MIC-1 2
+5VAMP 27 MIC
+5VS +5VAMP L34 FBM-11-160808-700T_0603 1 1 2 1
L15 R484 0_0603_5%
KC FBM-L11-201209-221LMAT_0805 4.7U_0805_10V4Z 0.1U_0402_16V4Z FOX_JA6033L-5S3-TR
1 1 2 C653 1
1

220P_0402_50V7K 2
W=80Mil 1
C372
1 1 1 W=80Mil
R288 22U_1206_16V4Z_V1 C344 C341 C342
@ 10K_0402_5% 1U_0603_10V4Z
2 2 2 2 +5VAMP
2

VOLMAX
0.1U_0402_16V4Z HEADPHONE
1

2
C379 OUT JACK
R292 R297
0_0402_5% 2 1 100K_0402_5% JP29
+5VAMP R296 5
47K_0402_5%
2

1
NBA_PLUG 2 1 4
U19
10 1 AMP_MUTE 29 INTSPK_R1 1 2 L32 1 2 3
VDD MUTE SHUTDOW N#
15 2 2 R290 1 C649 150U_D2_6.3VM FBM-11-160808-700T_0603 6

+
VDD SHUTDOWN# +5VAMP
100K_0402_5% INTSPK_L1 1 2 L33 1 2 2
9 INTSPK_L2 C650 150U_D2_6.3VM FBM-11-160808-700T_0603 1

+
LOUT-

1
VOL_AMP D
2 1 7 VOLUME 1 1
C371 0.1U_0402_16V4Z 16 INTSPK_R2 Q30 2 EC_EAPD 29 FOX_JA6033L-5S3-TR
VOLMAX ROUT- G C377 C378
8 VOLMAX
11 INTSPK_L1 S 2N7002_SOT23 330P_0402_50V7K 330P_0402_50V7K

3
NBA_PLUG LOUT+ 2 2
27 NBA_PLUG 13 SE/BTL#
14 INTSPK_R1
AMP_LEFT AMP_LIN AMP_LIN ROUT+
27 AMP_LEFT 1 2 6 LIN-
C374 1U_0603_10V4Z AMP_RIN 3
AMP_RIGHT AMP_RIN RIN-
27 AMP_RIGHT 1 2 GND 5
C373 1U_0603_10V4Z 4 12
BYPASS GND
1
C367
APA2068KAI-TRL_SOP16 Speaker Connector change 0 ohm
2 2.2U_0805_16V4Z 2
2 JP2
INTSPK_R1 L22 1 2 0_0603_5% SPK_R1
INTSPK_R2 L23 0_0603_5% SPK_R2 1
1 2 2
INTSPK_L1 L24 1 2 0_0603_5% SPK_L1
INTSPK_L2 L25 0_0603_5% SPK_L2 3
1 2 4
ACES_85204-0400

2
D24
D25 @ @ SM05_SOT23
SM05_SOT23

1
Variable Resistor
Regulator for CODEC

1 2 R459 +5VAMP
Reserve for noise. 3.9K_0603_1%
3 3
2
+5VALW
Adjustable Output +VDDA C652

4
U21 @ 0.1U_0402_16V4Z
+VDDA 1 0.01W _10KC_EVUTWZB19C14
4 VIN VOUT 5
VR1
4.7U_0805_10V4Z

0.1U_0402_16V4Z

4.7U_0805_10V4Z

2 DELAY SENSE or ADJ 6


R284 VOL_AMP 2 5
0.1U_0402_16V4Z

7 1 69.8K_0603_1%
C375 C376 ERROR CNOISE
8 3 +5VAMP
1

SD GND

3
SI9182DH-AD_MSOP8
VR

2
1

R461 R462
R280 100K_0402_5% 2 1
C369

24K _0402_1%
3.3K_0603_5%
15,24,25,29,31,33,39 SUSP#

1
D
C370

2
2 Q41
G 2N7002_SOT23 R463
S 6.19K_0603_1%

3
1
D
NBA_PLUG 2
Moat Bridge

1
G
S

3
Q40
1 2 2N7002_SOT23
R473 0_0805_5%
1 2
R474 0_0805_5%
4 1 2 4
R250 0_0805_5%
1 2
R293 0_0805_5%

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2005/08/22 Deciphered Date 2008/08/22 Title
AMP/VR/Audio Jack
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number R ev
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
HTW00 M/B LA-2871
Date: Monday, August 22, 2005 Sheet 28 of 41
A B C D E
A B C D E

+3VALW +EC_RTCVCC
+EC_AVCC
0.1U_0402_16V4Z 1000P_0402_50V7K 0.1U_0402_16V4Z 1 2
+3VALW
1 1 1 1 1 1 2 R234 0_0402_5%
+3VALW For EC Tools(Place under Door)

ECAGND
JP27
C304 C256 C270 C298 C313 C312 C319 1
1 +5VALW
1U_0603_10V4Z 2 E51_RXD
2 2 2 2 2 2 1 2 E51_TXD
3 3
4

123
136
157
166

161

159
4.7U_0805_10V4Z 0.1U_0402_16V4Z 4.7U_0805_10V4Z 4

16
34
45

95

96
U14 @ ACES_85205-0400
15

VCC
VCC
VCC
VCC
VCC
VCC
VCC

VCCA

AGND

VCCBAT

BATGND
L11 17,32 LPC_AD0 LAD0
1 2 14 49 KSO0
+3VALW +EC_AVCC 17,32 LPC_AD1 LAD1 GPOK0/KSO0
FBM-L11-160808-800LMT_0603 2 1 13 50 KSO1
17,32 LPC_AD2 LAD2 GPOK1/KSO1
10 51 KSO2
1 C268 17,32 LPC_AD3 LAD3 GPOK2/KSO2 +3VALW 1
C266 KSO3
0.1U_0402_16V4Z
17,32 LPC_FRAME#
LRST#
9 LFRAME# LPC Interface GPOK3/KSO3 52
KSO4
165 LRST#/GPIO2C GPOK4/KSO4 53
1 2

ENE-KB910-B4
CLK_PCI_LPC 18 56 KSO5 KSO[0..15]
L12 13 CLK_PCI_LPC LCLK GPOK5/KSO5 KSO[0..15] 30
1 2 ECAGND 7 57 KSO6 KBA5 1 2
18,23,32 SERIRQ SERIRQ GPOK6/KSO6 KSI[0..7]
FBM-L11-160808-800LMT_0603 1000P_0402_50V7K 25 58 KSO7 KSI[0..7] 30 R224 1K_0402_5%
CLKRUN#/GPIO0C * GPOK7/KSO7 KSO8 KBA4
24 LPCPD#/GPIO0B * GPOK8/KSO8 59 1 2
60 KSO9 ADB[0..7] R223 1K_0402_5%
GPOK9/KSO9 ADB[0..7] 31
FREAD# 150 61 KSO10 KBA1 1 2
+5VS 31 FREAD# RD# GPOK10/KSO10 KBA[0..19]
FW R# KSO11 R222 1K_0402_5%

Internal Keyboard
31 FW R# 151 WR# GPOK11/KSO11 64 KBA[0..19] 31
CLK_PCI_LPC FSEL# 173 65 KSO12
31 FSEL# MEMCS# GPOK12/KSO12
1 2 PSCLK1 SELIO# 152 IOCS# GPOK13/KSO13 66 KSO13
R184 10K_0402_5% ADB0 138 67 KSO14
D0 GPOK14/KSO14
1
1 2 PSDATA1 ADB1 139 D1 GPOK15/KSO15 68 KSO15
R183 10K_0402_5% R190 ADB2 140 153
D2 GPOK16/KSO16
1 2 TP_DATA ADB3 141 D3 GPOK17/KSO17 154 KSO17 30
R193 10K_0402_5% @ 10_0402_5% ADB4 144 D4
1 2 TP_CLK ADB5 145 71 KSI0
2

D5 GPIK0/KSI0

X-BUS Interface
R194 10K_0402_5% 1 ADB6 146 72 KSI1
D6 GPIK1/KSI1
1 2 PSDATA2 C296 ADB7 147 D7 GPIK2/KSI2 73 KSI2
R187 10K_0402_5% KBA0 124 74 KSI3
A0 GPIK3/KSI3
1 2 PSCLK2 @ 10P_0402_50V8K KBA1 125 A1/XIOP_TP GPIK4/KSI4 77 KSI4
R188 10K_0402_5% 2 KBA2 KSI5
126 A2 GPIK5/KSI5 78
KBA3 127 79 KSI6
KBA4 A3 GPIK6/KSI6 KSI7
128 A4/DMRP_TP GPIK7/KSI7 80
KBA5 131
KBA6 A5/EMWB_TP
132 A6 GPOW0/PWM0 32 INVT_PWM 15
R237 1 2 0_0402_5% LRST# KBA7 133 33
16,21,23,24,26,32 PCI_RST# A7 GPOW1/PWM1 BEEP# 27
KBA8 143 36
A8 FAN2PWM/GPOW2/PWM2 PW R_SUSP_LED 30
R238 1 2 @ 0_0402_5% KBA9 142 37
6,15,16,18,23 PLT_RST# A9 ACOFF 36
KBA10 135 A10 Pulse Width GPOW3/PWM3
GPOW4/PWM4 38 USB_EN# 32
KBA11 134 39
2 A11 GPOW5/PWM5 EC_ON 30 2
KBA12 130 40
A12 GPOW6/PWM6 EC_LID_OUT# 18 R178
KBA13 129 43 EC_EAPD 28 10K_0402_5%
+3VALW KBA14 A13 FAN1PWM/GPOW7/PWM7
121 A14 2 1 +3VALW
KBA15 120 2
A15 GPWU0 ON/OFFBTN# 30
1 2 IE_BTN# KBA16 113 26 A CIN_D 2 1
A16 GPWU1 AC IN 18,30,34
R181 10K_0402_5% KBA17 112 29 RB751V_SOD323 D11
A17 GPWU2 KILL_SW# 26,30,31
1 2 FSEL# KBA18 104 30
A18 GPWU3 PM_SLP_S3# 18
R211 10K_0402_5% KBA19 103 Wake Up Pin 44
30 IE_BTN# A19 GPWU4 PM_SLP_S5# 18
1 2 MODE# IE_BTN# 108 76
R198 10K_0402_5% R179 2 EC_TINIT# A20/GPIO23 GPWU5 PCI_PME#
+3VALW 1 10K_0402_5% 105 E51CS#/GPIO20/ISPEN TIN1/GPWU6 172 PCI_PME# 21,26
1 2 FREAD# 176 W W /JPN#
R232 10K_0402_5% PSCLK1 TIN2/FANFB2/GPWU7
110 PSCLK1 BATT_TEMPA 35
1 2 EC_SMI# PSDATA1 111 81 1 2 ECAGND
R158 10K_0402_5% PSCLK2 PSDAT1 GPIAD0/AD0 SKU_ID C254 0.01U_0402_16V7K ADP_IR R167
114 PSCLK2 GPIAD1/AD1 82 SKU_ID 30 1 2 ADP_I 36
SELIO# PSDATA2
1
R233
2
10K_0402_5% TP_CLK
115 PSDAT2PS2 Interface GPIAD2/AD2 83 BATT_OVP 36 10K_0402_5%
31 TP_CLK 116 PSCLK3 GPIAD3/AD3 84
1 2 ON/OFFBTN# 31 TP_DATA
TP_DATA 117 PSDAT3 Analog To Digital GPIAD4/AD4 87 ALI/MH# 35,36 1
R208 100K_0402_5% 88 MB_ID
EC_SMB_CK1 GPIAD5/AD5 AD_BID0 C261
31,35 EC_SMB_CK1 163 SCL1 GPIAD6/AD6 89
EC_SMB_DA1 164 90 ADP_IR 0.22U_0402_10V4Z
31,35 EC_SMB_DA1 SDA1 GPIAD7/AD7 2
+5VALWP EC_SMB_CK2 169 SMBus
4,15 EC_SMB_CK2 SCL2
4,15 EC_SMB_DA2 EC_SMB_DA2 170 99
SDA2 GPODA0/DA0 DAC_BRIG 15
1 2 EC_SMB_DA2 100 BT_PWR
GPODA1/DA1 BT_PWR 31
R219 10K_0402_5% 8 101
GPIO04 GPODA2/DA2 IR EF 36
1 2 EC_SMB_CK2 20 102
18 EC_SCI# GPIO07 GPODA3/DA3 EN_DFAN1 4
R230 10K_0402_5% BT_RST# 21 Digital To Analog 1
31 BT_RST# GPIO08 GPODA4/DA4
1 2 EC_SMB_CK1 BT_WAKE_UP 22 42
31 BT_WAKE_UP GPIO09 GPODA5/DA5
R235 10K_0402_5% ENBKL 27 47
EC_SMB_DA1 8,15 ENBKL GPIO0D GPODA6/DA6
1 2 15 BKOFF# 28 GPIO0E GPODA7/DA7 174
R236 10K_0402_5% 48
36 FSTCHG GPIO10
EC_SMI# 62 85
3
18 EC_SMI# GPIO13 *GPIO18/XIO8CS# POW ER_LED# 30 3
18 EC_SYS_PW ROK 63 GPIO14 86 W L_BT_LED# 30
69 *GPIO19/XIO9CS# 91
26 W L_OFF# GPIO15 *GPIO1A/XIOACS# HDD_LED# 30
70 GPIO 92 BATT_CHG_LOW_LED# 30
+3VALW 18 EC_SW I#
30 S4_LATCH 75
GPIO16
GPIO17 Expanded I/O **GPIO1C/XIOCCS#
GPIO1B/XIOBCS#
93 BATT_FULL_LED# 30
+3VALW

30 S4_DATA 109 GPIO24 94 1 2 EAPD 27


1 2 LID_SW # LID_SW # 118 *GPIO1D/XIODCS# 97 R171 0_0402_5%
30 LID_SW # GPIO25 *GPIO1E/XIOECS#
R199 20K_0402_5% MODE# 119 98
30 MODE# GPIO26 * GPIO1F/XIOFCS#

1
1 2 SUSP# 148
R475 100K_0402_5% 24,30,38 SYSON GPIO27 R471
15,24,25,28,31,33,39 SUSP# 149 GPIO28 GPIO2E/TOUT1/FANFB1 171 FANSPEED1 4
1 2 SYSON 155 12 1K_0402_5% 1 2 R203 0_0402_5%
40 VR_ON GPIO29 DPLL_TP/GPIO06/FANFB3
R476 100K_0402_5% 156 FANTEST_TP/GPIO05/FAN3PWM 11 @ 1K_0402_5% 1 2 R207 @ +3VALW
28 AMP_MUTE GPIO2A
BT_DETACH 162
31 BT_DETACH SPK_SEL 27

2
GPIO2B
18 PBTN_OUT# 168 GPIO2D 175 EC_THERM# 18
Timer PinTOUT2/GPIO2F

1
S4_CHECK
PADS_LED# 55 3 R217
30 PADS_LED# FnLock#/GPIO12* E51IT0/GPIO00 EC_RSMRST# 18
CAPS_LED# 54 4 S4_CHECK 100K_0402_5%
30 CAPS_LED# CapLock#/GPIO011* E51IT1/GPIO01 S4_CHECK 30
NUM_LED# 23 106 E51_RXD
30 NUM_LED# NumLock#/GPIO0A * E51RXD/GPIO21/ISPCLK
R180 PHDD_LED# 41 107 E51_TXD
17 PHDD_LED#

2
EC_RST# ScrollLock#/GPIO0F * E51TXD/GPIO22/ISPDAT
+3VALW 1 2 19 ECRST# MISC
47K_0402_5% 5 158 CRY1
17 EC_GA20 GA20/GPIO02 XCLKI
2 1 6 160 CRY2 R226 2 1
17 EC_KBRST# KBRST#/GPIO03 XCLKO 21,26 MINI_PME#
C289 31 @ 20M_0603_5%
GND
GND
GND
GND
GND
GND

ECSCI#

10P_0402_50V8K
0.1U_0402_16V4Z 1 R231 2
0_0402_5% 21,26 ONBD_LAN_PME#
1 1

10P_0402_50V8K
KB910Q B4_LQFP176 C318 C317
17
35
46
122
137
167

1
+3VALW
Y4 PCI_PME#

OUT

IN
MB_ID 2 2
MB_ID: High: PM 2 1
R477 PM@10K_0402_5%
LOW : GM 1 2

NC

NC
R478 GM@ 0_0402_5%
4 SKU_ID 2 1 4
R154 100K_0402_5%

2
2 1 32.768KHZ_12.5P_1TJS125DJ2A073
R155 @ 0_0402_5%
AD_BID0: Board ID AD_BID0 2 1
R165 10K_0402_5%
1
Ra 2
R166 0_0402_5%
* Rb Security Classification Compal Secret Data Compal Electronics, Inc.
WW/JPN#: No-Pop: WW Model Issued Date 2005/08/22 Deciphered Date 2008/08/22 Title
(EC Internal Pull-Up) W W /JPN# 1 2 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
EC KB910(LPC)
Pop: JPN Model R487 @ 0_0402_5% AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number R ev
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
HTW00 M/B LA-2871
Date: Saturday, August 20, 2005 Sheet 29 of 41
A B C D E
5 4 3 2 1

ON/OFF BUTTON
for debug only
Lid SW Kill SWITCH
RTCVREF BTN TOP D7
R294 2 ON/OFFBTN# SW3 KS@
ON/OFFBTN# 29
1 2 1 2 1 2 1 2 +3VALW 1 3 1 3 ON/O FF 1 3
R298 0_0402_5% R299 47K_0402_5% 0_0402_5% R295 100K_0402_5% 51_ON# 3
3 51_ON# 34
U23 2 4 2 4 2 R460
A3212EEH_MLP6 D21 DAN202U_SC70 2
+3VALW 1 2
2 LID_SW # @ SW2 @ SW1 100K_0402_5%
LID_SW # 29

6
5

6
5
5 1 LID1 1 KILL_SW#
VDD OUTPUT 1 KILL_SW# 26,29,31

1
3 S4_LID_SW# SMT1-05_4P SMT1-05_4P 1
D D
D6 3 +3VALW
0.1U_0402_16V4Z

10P_0402_50V8K
1 4 2 1 @ DAN202U_SC70 RLZ20A_LL34 1BS003-1211L_3P 1
C381 NC NC C380 Q9 C146 2
GND

1
D 2 0.01U_0402_16V7K D36

2
2 @ DAN217_SC59
2 2 29 EC_ON G
3

2
S 2N7002_SOT23

3
R38
10K_0402_5%

1
WL&BT LED
D37 KS@
+3VALW 1 2 2 1 W L_BT_LED# 29
R467 KS@ 300_0402_5% HT-191UD_AMBER_0603

POWER/ON(Green Pin2,1) +3VALW

Suspend (Amber Pin3,4) LED SYSON

3
Q27

2
D39 47K 2N7002_SOT23

G
PW R_SUSPLED1# 2 1
HT-191UD_AMBER_0603 2 1 3 PW R_SUSP_LED 2 2
10K PW R_SUSP_LED 29 MODE# 29 IE_BTN# 29
D40 MODEBTN# 1 IEBTN# 1

S
PW R_LED_0# 2 1 3 51_ON# 3 51_ON#
HT-191NB_BLUE_0603 1 2
Q28 R276 @ 0_0402_5% D28 D29
DTA114YKA_SOT23 DAN202U_SC70 DAN202U_SC70

1
R274 1 2 120_0402_5% PW R_SUSPLED#
C BATTERY CHG(Green Pin2,1) R273 1 2 120_0402_5% PW R_SUSPLED1# KSO17 C486 1 2@ 220P_0402_50V7K
C

BATTERY LOW(Amber Pin3,4) LED +5VALW


SW/LED Connector ON/O FF C485 1 2@ 220P_0402_50V7K
JP3
SYSON PW R_LED_1# PW R_LED_1# C488 1 2@ 220P_0402_50V7K
1

3
D41 PW R_SUSPLED#
2

2
R265 1 200_0402_5% BATT_CHG_LOW_LED# 47K Q23 SKU_ID PW R_SUSPLED# C487 1 2@ 220P_0402_50V7K

G
+5VALW 2 2 1 BATT_CHG_LOW_LED# 29 3 SKU_ID 29
HT-191UD_AMBER_0603 2N7002_SOT23 KSO17
D42 PW R_LED# 4 ON/O FF KSO17 29 IEBTN# C482 1
2 1 3 POW ER_LED# 29 5 2@ 220P_0402_50V7K
R266 1 200_0402_5%
2 2 1 BATT_FULL_LED# BATT_FULL_LED# 29
10K IEBTN#

S
+5VALW 6
HT-191NB_BLUE_0603 MODEBTN# MODEBTN# C479 1 2@ 220P_0402_50V7K
R2561 7 EC_PLAYBTN#
2 8 KSI0 29
Q24 @ 0_0402_5% EC_STOPBTN# EC_REVBTN# C470 1 2@ 220P_0402_50V7K
HDD LED 1
DTA114YKA_SOT23
R269 1 200_0402_5%
9
10
EC_FRDBTN# KSI1
KSI3
29
29
D18 2 PW R_LED_0# EC_REVBTN# EC_FRDBTN# C473 1 2@ 220P_0402_50V7K
PW R_LED_1# 11 KSI2 29
+5VS 1 2 2 1 HDD_LED# 29 1 2 12
R270 200_0402_5% HT-191NB_BLUE_0603 R260 300_0402_5% EC_PLAYBTN# C478 1 2@ 220P_0402_50V7K
ACES_85201-1205
AC IN LED EC_STOPBTN# C477 1 2@ 220P_0402_50V7K
D15
D

+5VALW 1 2 2 1 1 3
R272 200_0402_5% HT-191NB_BLUE_0603 Q22
2N7002_SOT23
For EMI Request
G
2

A CIN 18,29,34

Battery mode Hibernation


RTCVREF KEYBOARD CONN.
(Reserved) RTCVREF
RTCVREF
JP5 KSI[0..7]
KSI[0..7] 29
B 1 2 S4_CHECK NUM_LED# B
S4_CHECK 29 1 NUM_LED# 29 KSO[0..15]
R472@ 0_0402_5% PADS_LED#
2 PADS_LED# 29 KSO[0..15] 29
@ 680K_0402_5% C645 @ 0.1U_0402_16V4Z CAPS_LED#
3 CAPS_LED# 29
1

1 2 4 2 1 +3VS
1

D35 ON/O FF KSO15 R385 300_0402_5%


R458 R457 R454 @1N4148_SOD80 5 KSO14
6 KSO10
1 7
5

@ 100K_0402_5% @ 100K_0402_5% U20 KSO11 2 1PADS_LED# NUM_LED# 1 2


2

8
1

D Q38 C640 KSO8 100P_0402_50V8J C514 C513 100P_0402_50V8J


P
2

9
220P_0402_50V7K

1 2 2 4 1 2 2 KSO9 2 1 KSO14 CAPS_LED# 1 2


A Y R277 G 2 10 KSO13 100P_0402_50V8J C529 C528 100P_0402_50V8J
G

11
1

D
2N7002_SOT23

C648@ 1U_0603_10V4Z @ 10K_0402_5% S D32 KSI7 2 1 KSO11 KSO15 1 2


3

S4_LID_SW# Q42 @ NC7SZ14M5X_SOT23-5 @ PSOT24C_SOT23 12 KSO3 100P_0402_50V8J C530 C517 100P_0402_50V8J


2
3

13 KSO7
G @ 2N7002_SOT23
14 2 1 KSO9 KSO10 1 2
S KSO12 100P_0402_50V8J C531 C515 100P_0402_50V8J
3

15 KSI4 KSI7 KSO8


16 2 1 1 2
1

D KSI6 100P_0402_50V8J C532 C516 100P_0402_50V8J


SYSON 17 KSI5
24,29,38 SYSON 2 @
18 2 1 KSO7 KSO13 1 2
G @ KSO6 100P_0402_50V8J C533 C518 100P_0402_50V8J
Q37 19 KSO5 KSI4 KSO3
S 2 1 1 2
3

@ 2N7002_SOT23 20 KSI3 100P_0402_50V8J C534 C519 100P_0402_50V8J


21 KSI0 KSI5 KSO12
22 2 1 1 2
RTCVREF 1 2 1 2 KSO0 100P_0402_50V8J C542 C520 100P_0402_50V8J
23 KSO1
R455 @ C647 1U_0603_10V4Z
24 2 1 KSO5 KSI6 1 2
@ 10K_0402_5% KSI1 100P_0402_50V8J C537 C545 100P_0402_50V8J
RTCVREF 25 KSI2 KSI0 KSO6
26 2 1 1 2
R456 U29 @ 0.1U_0402_16V4Z KSO2 100P_0402_50V8J C538 C546 100P_0402_50V8J
27 KSO4
1 2 1 CD1# VCC 14 1 2 28 2 1 KSO1 KSI3 1 2
10K_0402_5% 2 13 C646 2 1 +3VS 100P_0402_50V8J C539 C547 100P_0402_50V8J
D1 CD2# 29 KSI2 KSO0
29 S4_LATCH 3 CP1 D2 12 1 R450 2 30
R391 300_0402_5% 2 1 1 2
RTCVREF 1 2 4 11 @ 0_0402_5% 100P_0402_50V8J C540 C548 100P_0402_50V8J
SD1# CP2 31
A R453 1 5 Q1 SD2# 10 32 2 1 KSO4 KSI1 1 2 A
@ 10K_0402_5% C644 6 09 100P_0402_50V8J C541 C543 100P_0402_50V8J
Q1# Q2 33 KSO2
7 GND Q2# 08 34 1 2 +3VS 1 2
@ 1U_0805_25V4Z R390 300_0402_5% C544 100P_0402_50V8J
2 @ 74LCX74MTC_TSSOP14 ACES_88170-3400
220P_0402_50V7K

+3VALW 1 2 1
For EMI Request
R452 Q39 @
Security Classification Compal Secret Data Compal Electronics, Inc.
1

10K_0402_5% D33 @ D C641


2 1 D_SET_S4 2 2005/08/22 2008/08/22 Title
29 S4_DATA 2 Issued Date Deciphered Date
G
@ RB751V_SOD323 2N7002_SOT23 S S4R/LID/KS/KB/LED/SW-B Conn
3

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number R ev
1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
HTW00 M/B LA-2871
Date: Monday, August 22, 2005 Sheet 30 of 41
5 4 3 2 1
5 4 3 2 1

TP CONN.
+5VS

JP4
5
BlueTooth Interface
TP_DATA 4 C167
29 TP_DATA 3
TP_CLK 0.1U_0402_16V4Z
29 TP_CLK 2 +5VS +3VS
1 +3VALW
MARU_00-6210-305-340-800_5P

14
D D
R126 C233 U12B
100K_0402_5% 0.1U_0402_16V4Z 26,29,30 KILL_SW# 4

P
BT@ BT@ A BT_RESET#
O 6 1 2

3
S
29 BT_RST# 5 R197 @0_0402_5%

1
B

G
+5VS
G
2
Q13

7
JP31 D BT@AO3413_SOT23 SN74LVC08APW_TSSOP14

1
1
Q14 C232
TP_DATA 4 BT@DTC124EK_SC59
TP_CLK 3 0.1U_0402_16V4Z
2 +BT_VCC 1 2
BT@ R196 BT@0_0402_5%
1
29 BT_PWR 2
@ ACES_87151-0405

3
BT@
MARU_00-6210-320-340-800_20P
Module ID
Indication for polarity of reset 20
Reset input High Active --> Low , BT_DET# 19
16 BT_DET# 18
Reset input Low Active --> Open
17
16
15
BT_RESET# 14
BT_WAKE_UP 13
29 BT_WAKE_UP 12
C 11 C
10
9
29 BT_DETACH 8
26 W LAN_BT_CLK 7
New Connection 6
USB20_P5
between 18 USB20_P5 5
USB20_N5
18 USB20_N5 4
WLAN&BT Module 26 W LAN_BT_DATA 3
2
+BT_VCC 1
(MAX=200mA) JP6
C226 C221
BT@ BT@ (Top Contact)
10U_1206_16V4Z 0.1U_0402_16V4Z
Bluetooth Connector

KBA[0..19]
29 KBA[0..19] +3VALW
ADB[0..7]
29 ADB[0..7]

1MBU30Flash ROM 1MB ROM Socket

1
+3VALW
R481
20K_0402_5%
KBA0 21 31
KBA1 A0 VCC0 JP30
20 30 1

2
KBA2 A1 VCC1 KBA16 KBA17
19 A2 1 2
B KBA3 18 C651 KBA15 B
KBA4 A3 ADB0 KBA14 3 4
17 A4 D0 25 0.1U_0402_16V4Z 5 6

1
KBA5 ADB1 2 KBA13 KBA19 D
16 A5 D1 26 7 8 2N7002_SOT23
KBA6 15 27 ADB2 KBA12 KBA10 2
A6 D2 9 10 Q46 SB_INT_FLASH_SEL# 18
KBA7 14 28 ADB3 KBA11 ADB7 G
KBA8 A7 D3 ADB4 KBA9 11 12 ADB6
8 32 S

3
KBA9 A8 D4 ADB5 KBA8 13 14 ADB5
7 A9 D5 33 15 16
KBA10 ADB6 FWE# ADB4

14
36 A10 D6 34 17 18
KBA11 ADB7 RESET# U13C

14
6 A11 D7 35 19 20 +3VALW
KBA12 5 INT_FLASH_EN# U12D

P
KBA13 A12 INT_FLASH_SEL 21 22
4 12 6 5

P
KBA14 A13 RESET# KBA18 23 24 ADB3 INT_FLASH_SEL 11 A O I
3 A14 RP# 10 1 2 +3VALW 25 26 O

G
KBA15 2 11 R466 100K_0402_5% KBA7 ADB2 13 @ SN74LVC14APWLE_TSSOP14
A15 NC 27 28

G
KBA16 KBA6 ADB1 SN74LVC08APW_TSSOP14 B
1 12

7
KBA17 A16 READY/BUSY# KBA5 29 30 ADB0
40 29

7
KBA18 A17 NC0 KBA4 31 32 FREAD#
13 A18 NC1 38 33 34 SUS_STAT# 18
KBA19 37 KBA3
A19 KBA2 35 36 FSEL#
INT_FSEL# KBA1 37 38 KBA0
22 CE# 39 40
FREAD# 24 23
29 FREAD# FWE# OE# GND0 @ SUYIN_80065AR-040G2T
9 WE# GND1 39

+3VALW
SST39VF080-70_TSOP40 +3VALW

20K_0402_5%
1
+3VALW
R468
14

SUSP# 15,24,25,28,29,33,39
U31A

2
+3VALW +3VALW Q43

G
14
1 FSEL# 29
P

INT_FSEL# A U31B 2N7002_SOT23


3

2
O INT_FLASH_EN#
2 4 1 3

P
G

B A EC_FLASH# 18
1

FWE# 6

S
A A
O
1 2 C364 R291 SN74LVC32APWLE_TSSOP14 2 1 R469 5
7

G
0.1U_0402_16V4Z 100K_0402_5% 100K_0402_5% B
2 1 C654 SN74LVC32APWLE_TSSOP14

7
U22 FW R# 29
2

8 1 0.1U_0402_16V4Z
VCC A0
7 WP A1 2
6 3
29,35 EC_SMB_CK1
29,35 EC_SMB_DA1 5
SCL
SDA
A2
GND 4
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2005/08/22 Deciphered Date 2008/08/22 Title
AT24C16N-10SI-2.7_SO8
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
1MB BIOS/ TP Conn/ BT Conn
1 R289 2 AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number R ev
100K_0402_5% 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
HTW00 M/B LA-2871
Date: Monday, August 22, 2005 Sheet 31 of 41
5 4 3 2 1
+USB_VCCA +USB_VCCC

1.4A 1.4A
U24 U7
1 GND OUT 8 1 GND OUT 8
+5VALW 2 IN OUT 7 +5VALW 2 IN OUT 7
3 IN OUT 6 3 IN OUT 6
USB_EN# 4 5 USB_EN# 4 5
29 USB_EN# EN# FLG EN# FLG
1 1
C389 G528_SO8 C231 G528_SO8

4.7U_0805_10V4Z 4.7U_0805_10V4Z
2 2

Close to JP29
Close to JP16

USB CONN. 3
USB CONN. 1 USB CONN. 2 +USB_VCCC
W=40mils
+USB_VCCA +USB_VCCA
W=40mils W=40mils
1
1 1
1 1 C551 + C549 C550
1 1 1 1 150U_D2_6.3VM
C384 + C382 C387 C383 C386 + C385 0.1U_0402_16V4Z 1000P_0402_50V7K
150U_D2_6.3VM 2 2 2
+3VALW +3VALW
0.1U_0402_16V4Z 1000P_0402_50V7K 1000P_0402_50V7K 0.1U_0402_16V4Z 150U_D2_6.3VM
2 2 2 2 2 2 JP22

14

14
1 VBUS S_GND 5
JP12 2 U13D U31C
18 USB20_N4 D- PJ19
1 5 3 9

P
VCC VCC 18 USB20_P4 D+ A
18 USB20_N0 2 D0- D1- 6 USB20_N2 18 4 GND S_GND 6 2 2 1 1 9 I O 8 O 8

2
18 USB20_P0 3 D0+ D1+ 7 USB20_P2 18 1 C245 1 C250 10

G
B

G
10P_0402_50V8K

10P_0402_50V8K
4 8 D30 TYCO_3-1470859-1 @ JUMP_43X39 @
VSS VSS
3

2
C5
1 1 C6 1 C4 1 C7 @ SM05_SOT23 SN74LVC32APWLE_TSSOP14

7
10P_0402_50V8K

10P_0402_50V8K

10P_0402_50V8K

10P_0402_50V8K
D1 10 9 D2 @ @
@ SM05_SOT23 G2 G1 @ SM05_SOT23 2 2 SN74LVC14APWLE_TSSOP14
12 G4 G3 11
@ @ @ @

1
2 2 TYCO_1470748-1 2 2
+3VALW
1

14
U31D
12

P
A
O 11
13
Power OK Circuit B

G
H1 H4 H16 H27 H22
H_S315D118 H_S315D118 H_S315D118 H_S315D118 H_S315D118 SN74LVC32APWLE_TSSOP14

7
+3VS
@ @ @ @ @
+3VALW +3VALW
1

1 C314
H6 H5 H17 H23 H26 R206 1 2
H_S315D118 H_S315D118 H_S315D197 H_S315D118 H_S315D118 330K_0402_5% @

14

14
@ U13A U13B 0.1U_0402_16V4Z
@ @ @ @ @

P
2

1 2 3 4
1

I O I O SYS_PW ROK 18

G
@ @
@
1 7
LPC Debug Port

7
C306 SN74LVC14APWLE_TSSOP14
1U_0603_10V4Z
H2 H25 H8 H11 2 +5VS +3VS
H_C138D138N H_O276X177D276X177N H_C315D157 H_C315D118 SN74LVC14APWLE_TSSOP14 CLK_PCI_SIO

2
@ @ @ @
JP10 R239
1

1 @ 22_0402_5%
H28 H29 H30 1
2 2
H_C315D118 H_S315D118 H_S315D118 3

1
H19 H12 H10 H7 3
4 4 1
@ @ @ H_C59D59N H_C79D79N H_C315D157 H_C177D177N 5 C323
5 CLK_14M_SIO
6
1

6 CLK_14M_SIO 13
@ @ @ @ 7 LPC_AD0 @ 10P_0402_50V8K
7 LPC_AD0 17,29 2
8 LPC_AD1
1

8 LPC_AD1 17,29
9 LPC_AD2
9 LPC_AD2 17,29
H13 H20 H14 H21 H15 H18 H24 10 LPC_AD3
10 LPC_AD3 17,29
H_C256D177 H_C256D177 H_C256D177 H_C256D177 H_TC157BC236D157 H_TC157BC236D157 H_TC157BC236D157 H31 H9 11 LPC_FRAME#
11 LPC_FRAME# 17,29
H_C79D79N H_TS315BC236D157 12 LPC_DRQ1#
@ @ @ @ @ @ @ 12 PCI_RST# LPC_DRQ#1 17
13 13 PCI_RST# 16,21,23,24,26,29
@ @ 14 1 2
1

14 R241 @ 0_0402_5% CLK_PCI_SIO


15
1

15 CLK_PCI_SIO 13
16 SERIRQ
16 SERIRQ 18,23,29
17 17
H32 H33 H34 18
H_O177X157D177X157N H_O118X197D118X197N H_C256D118 18
19
19
20 20 close to MINIPCI Conn.
F D4 F D6 F D5 F D2 F D3 F D1 C F2 C F4 CF11 @ @ @
1 1 1 @ ACES_85201-2005
1

@ @ @ @ @ @ @ @ @
1

CF10 C F9 CF12 C F5
1 1 1 1
Security Classification Compal Secret Data Compal Electronics, Inc.
@ @ @ @ 2005/08/22 2008/08/22 Title
Issued Date Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Screw Hole/USB/LPC Conn
C F7 C F6 C F8 C F3 C F1 AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number R ev
1.0
@
1
@
1
@
1
@
1
@
1 DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
HTW00 M/B LA-2871
Date: Saturday, August 20, 2005 Sheet 32 of 41
A B C D E

+3VALW to +3VS Transfer +5VALW to +5VS Transfer


+3VALW +3VS
+5VALW +5VS
1 1
U16
+12VALW 8 1 U18
D S +12VALW
10U_0805_10V4Z

0.1U_0402_16V4Z

10U_0805_10V4Z
7 D S 2 8 D S 1

10U_0805_10V4Z

0.1U_0402_16V4Z

10U_0805_10V4Z
1 6 D S 3 7 D S 2
1

5 D G 4 1 1 1 6 D S 3

1
R212 C322 5 4 1 1
100K_0402_5% AO4422_SO8 C310 C316 R229 R259 C338 D G C345 R271
2 470_0805_5% 100K_0402_5% AO4422_SO8 C339 470_0805_5%
2 2 2
@
2

2 2

2
1
RU NON D

1
D
2 SUSP 5VS_ON

0.01U_0402_16V7K
G Q25 2 SUSP
1

D 1
S Q20 @ 1 2N7002_SOT23 G

1
SUSP Q18 C309 2N7002_SOT23 D C335
2 S

3
G 2N7002_SOT23 0.1U_0402_16V7K SUSP 2 Q21
2

S G 2N7002_SOT23
3

S 2

3
+1.5VALW to +1.5VS Transfer
2 2
+5VALW

+1.5VALW +1.5VS

1
U4 R264
8 1 100K_0402_5%
D S
22U_1206_16V4Z_V1

0.1U_0402_16V4Z

7 D S 2
6 3 1 1

2
D S
10U_0805_10V4Z

10U_0805_10V4Z

10U_0805_10V4Z

5 4 C28 C25 R21


D G 470_0805_5%
1 1 1 AO4422_SO8 @ SUSP
2 2 39 SUSP
C29 C24 C23

1
D
1

2 2 2 D
15,24,25,28,29,31,39 SUSP# 2
2 SUSP G 2N7002_SOT23
RU NON G @ 2N7002_SOT23 S Q26

3
S Q7
3

+1.8V to +1.8VS Transfer

3 +1.8V +1.8VS 3

U27 PM@
8 D S 1
10U_0805_10V4Z

7 D S 2
0.1U_0402_16V4Z

10U_0805_10V4Z

1 6 D S 3
5 D G 4 1 1
C458 PM@ PM@ R348
PM@ AO4422_SO8 C430 C426 470_0805_5%
2
@
2 2
RU NON
1

D
2 SUSP
G Q35
S @ 2N7002_SOT23
3

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2005/08/22 Deciphered Date 2008/08/22 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
DC/DC Interface
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number R ev
1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. HTW00 M/B LA-2871
Date: Saturday, August 20, 2005 Sheet 33 of 41
A B C D E
A B C D

VS
PR1
V IN V IN 1M_0402_1%
PL1 1 2
PF1 FBM-L18-453215-900LMA90T_1812
DC301000F00

1
DC_IN_S1 1 2 DC_IN_S2 1 2

1
VS PR2
PJP1 7A_24VDC_429007.WRML PR3 5.6K_0402_5% PR4
1 84.5K_0402_1% 1K_0402_1%
+
1 2

2
AC IN 18,29,30

1
2 PR5

2
+

8
PC1 PC2 PC3 PC4 22K_0402_1% PU1A
3 1000P_0402_50V7K 100P_0402_50V8J 1000P_0402_50V7K 100P_0402_50V8J 1 2 3

P
2

2
- + PACIN
1
O 1 PACIN 36,37 1

- 4 2 -

G
1
1

1
@ SINGA_2DW -0005-B03 PR6 LM393M_SO8

4
PC5 20K_0402_1% PC6 PR7
1000P_0402_50V7K 0.1U_0402_16V7K PD1 10K_0402_1%

2
RLZ4.3B_LL34

2
2
PR8
1 RTCVREF Vin Detector
10K_0402_1%
V IN 3.3V
High 18.384 17.901 17.430

2
PD2
Low 17.728 17.257 16.976
1N4148_SOD80

PD3

1
1N4148_SOD80
BATT+ 2 1

1
PR9 PR155
68_1206_5% 68_1206_5%
PQ1 1 2
PR11 TP0610K-T1-E3_SOT23 PR10

2
200_0603_5% 1K_1206_5%
CHGRTCP 1 2 N1 3 1 VS
PD4
1N4148_SOD80
1

2 1 N3 1 2
VIN B+
1

1
2
PC8 PR12 2

PR13 PC7 0.1U_0603_25V7K 1K_1206_5%


100K_0402_1% 0.22U_1206_25V7K
2

2
2

30 51_ON# 1 2 1 2
PR14 PR15
22K_0402_1% 1K_1206_5%

RTCVREF
1

PR17 PR18
PR16 100K_0402_1% 2.2M_0402_5%

1
PU2 200_0603_5% 1 2 2 1
PR20 PR21 G920AT24U_SOT89 VL PR19
560_0603_5% 560_0603_5% 3.3V 499K_0402_1%
2

1 2 1 2 3 2 N2
+CHGRTC OUT IN PU1B

2
1

8
PD6 LM393M_SO8
1

GND PD5 2 5

P
PC10 PC9 RLZ16B_LL34 17,35,37 MAINPWON 1 7
+
10U_0805_10V4Z 1 1U_0805_25V4Z O
3 6 2 1 VL
36 ACON
2

G
-

1
2

1
RB715F_SOT323 PR22 PR23

4
1

1
34K_0402_1% 499K_0402_1% PC11

1
PC12 PR25 1000P_0402_50V7K

2
1000P_0402_50V7K PC13 PR24 191K_0402_1%

2
1000P_0402_50V7K 66.5K_0402_1%

2
3 3

PJ1 PJ2 PR26

1
D 47K_0402_1%
+3VALWP 2 2 1 1 +3VALW +1.8VP 2 2 1 1 +1.8V
2 2 1 PACIN
@ JUMP_43X118 @ JUMP_43X118 PQ2 G
(5A,200mils ,Via NO.= 10) (6A,240mils ,Via NO.= 12) 2N7002-7-F_SOT23-3
Precharge detector S

3
PJ3
PJ4 15.97V/14.84V FOR

1
+5VALWP 2 2 1 1 +5VALW
@ JUMP_43X118
+2.5VSP 2 2 1 1 +2.5VS ADAPTOR PQ3
DTC115EUA_SC70
(5A,200mils ,Via NO.= 10) @ JUMP_43X39
PJ5 (0.35A,40mils ,Via NO.=2) 2 +5VALWP

+12VALWP 2 2 1 1 +12VALW
PJ6
@ JUMP_43X39 +0.9VSP 2 1 +0.9VS

3
2 1
(120mA,40mils ,Via NO.= 2) @ JUMP_43X118
(2A,80mils ,Via NO.= 4)

PJ7 PJ8
+1.05VSP 2 2 1 1 +1.05VS 2 2 1 1
+1.5VALWP +1.5VALW
@JUMP_43X118 @ JUMP_43X118
(5A,200mils ,Via NO.= 10) (4.5A,180mils ,Via NO.= 9)
4 4

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2005/08/22 Deciphered Date 2008/08/22 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
DCIN & DETECTOR
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number R ev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Saturday, August 20, 2005 Sheet 34 of 41
A B C D
A B C D

PH1 under CPU botten side :


CPU thermal protection at 84 degree C
Recovery at 45 degree C

VL VS VL

2
VMB
PF2 PL2 PR27

1
1 1

PJP2 12A_65VDC_451012 FBM-L18-453215-900LMA90T_1812 47K_0402_1%


1 BATT_S1 1 2 1 2 PH1 PC14
BATT+ BATT+ MAINPW ON 17,34,37
PR28 100K_0603_1%_TH11-4H104FT 0.1U_0603_25V7K PR29

1
1K_0402_1% 47K_0402_1%

1
2 ALI/NIMH# 1 2 1 2

2
ID AB/I PR31
B/I 3 1 2 +3VALWP

8
4 TS_A PR30 13.7K_0402_1%
TS EC_SMDA 47K_0402_1% PC15 PC16 PU3A
5 1 2 3

P
SMD +

1
6 EC_SMCA 1000P_0402_50V7K 0.01U_0402_25V7Z 1 2 1 2 PQ4

2
SMC PR32 TM_REF1 O DTC115EUA_SC70
GND 7 2 -

G
1K_0402_1% PD7
SUYIN_250005MR007G132ZR LM393M_SO8 1SS355_SOD323

4
2

3
2

0.22U_0805_16V7K
PR33 PR34

22K_0402_1%
100_0402_5% 100_0402_5%

1
PC17
1

PR35

1000P_0402_50V7K
1

ALI/MH# 29,36
2 1

2
VL

PC18
PR37 PR36

2
6.49K_0402_1% 100K_0402_1%

2
2 1 +3VALWP

1
1

PR38
PR39 100K_0402_1%
1K_0402_1%

2
2

2 2

PH2 near main Battery CONN :


BATT_TEMPA 29
BAT. thermal protection at 79 degree C
EC_SMB_DA1 29,31 Recovery at 45 degree C
EC_SMB_CK1 29,31

VL VL

2
PR40
PH2 47K_0402_1%
100K_0603_1%_TH11-4H104FT PR41
47K_0402_1%

1
1 2

PR42

8
10.7K_0402_1% PU3B
1 2 5

P
+
O 7 2 1
TM_REF1 6 -

G
1
3 3

PD8

1
LM393M_SO8 1SS355_SOD323

4
PC19 PR43
0.22U_0805_16V7K 22K_0402_1%

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2005/08/22 Deciphered Date 2008/08/22 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
BATTERY CONN / OTP
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number R ev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Saturday, August 20, 2005 Sheet 35 of 41
A B C D
A B C D

Iadp=0~3.7A B+ PQ5
P2 P3 AO4407_SO8
PQ6 PQ7 1 8
PR44 2 7
AO4407_SO8 AO4407_SO8 0.02_2512_1% PL11 3 6
8 1 1 8 2 1 FBM-L18-453215-900LMA90T_1812 5
V IN
7 2 2 7 1 2 B++
6 3 3 6

4
5 5

1
PC20 PC21 PC22

4
4.7U_1206_25V6K 4.7U_1206_25V6K 4.7U_1206_25V6K

2
1
1 1

PR45
1

3
200K_0402_1% PR47
PR46 47K_0402_1%

2
47K

1
47K_0402_1% 1 2 V IN
2 PC23 PU4
47K

2
0.1U_0603_25V7K 1 24
2

2
29 ADP_I -INC2 +INC2

3
2
1
PR48
PQ9 10K_0402_1%
PQ8 2 1 2 23 AO4407_SO8
OUTC2 GND
1

DTA144EUA_SC70 PR49 PC24 4 ACO FF#


1

1
100K_0402_1% 0.022U_0402_16V7K
3 22 CS 1 2
+INE2 CS

1
2

1
4 -INE2 VCC(o) 21 1 2

1
PQ10 PR50 PR52

5
6
7
8
1
DTC115EUA_SC70 PC26 23.7K_0402_1% 10K_0402_1% PC25 2 ACOFF 29
1

D 0.1U_0402_16V7K PR51 0.1U_0603_25V7K DH_CHG


1 2 1 2 5 20
3

PQ12 PR53 10K_0402_1% FB2 OUT PQ11


2

2
G 2N7002-7-F_SOT23-3 150K_0402_1% PC27 DTC115EUA_SC70

2
S 4700P_0402_25V7K 6 19 1 2 LX_CHG
3

3
PR54 VREF VH PC28
2

1
PC29 1K_0402_1% 0.1U_0603_25V7K
0.1U_0402_16V7K 1 2 1 2 7 18 1 2
ACO FF#1 FB1 VCC PC31
2
CC=0.6~3A
2
PC30 0.1U_0603_25V7K
PD9 1000P_0402_50V7K 8 17 1 2
1SS355_SOD323 -INE1 RT PR55 CV=12.6V(6 CELLS LI-ION)
68K_0402_5%
CV=16.8V(8 CELLS LI-ION)
1

2 D PL3 2

29 IR EF 1 2 9 +INE1 -INE3 16
PACIN 1 2 2 PQ13 PR56 PR59 PR60 16UH_D104C-919AS-160M_3.7A_20%
34,37 PACIN
PR57 G 2N7002-7-F_SOT23-3 162K_0402_1% 10K_0402_1% 47K_0402_1% 1 2 1 2 BATT+
3K_0402_1% S 2 1 10 15 1 2 1 2
3

1 OUTC1 FB3 PR58

1
PC32 0.02_2512_1%

1
ACON PR61 PC33 11 14 ACON 1500P_0402_50V7K
34 ACON OUTD CTL

1
100K_0402_1% 0.1U_0402_16V7K PC36
2

PD10 PC34 4.7U_1206_25V6K


2

12 13 EC31QS04 4.7U_1206_25V6K

2
-INC1 +INC1 PC35
IREF=1.31*Icharge

2
4.7U_1206_25V6K
MB3387PFV-ERE1_SSOP24~N
IREF=0.6V~3.144V
ISE_CHG+
+3VALWP
CS
4.2V
1

2 1 2 1
1

PR64
47K_0402_1% PQ14 PR62 PQ38 PR63
DTC115EUA_SC70 150K_0603_0.1% 2N7002-7-F_SOT23-3 300K_0603_0.1%
2

D
2 3 1 2 1
1

PR65
300K_0603_0.1%

G
2
3

VL 1 2
3
29 FSTCHG 2 3

PR154 1
PQ15 100K_0402_1%
DTC115EUA_SC70
3

2
29,35 ALI/MH# BATT Type ALI/MH# Charge Current IREF
VMB PQ39
DTC115EUA_SC70
OVP voltage : LI 8 CELL 0V 3A 3.144V
3
1

4S2P : 18V--> BATT_OVP= 2V


3S2P : 13.5V--> BATT_OVP= 1.5V PR66
340K_0402_1% 6 CELL 3.3V 3A 3.144V
(BAT_OVP=0.1111 *VMB)
1 2

+12VALWP

PR67
499K_0402_1%
2
8

PU5A
LM358A_SO8 3
P

+
1 0
29 BATT_OVP 2
G

-
4
1

PR68
1

2.2K_0402_5%
1

4
PC37 4

PR69 0.01U_0402_25V7Z
2

105K_0402_1%
2
2

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2005/08/22 Deciphered Date 2008/08/22 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
CHARGER
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number R ev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Saturday, August 20, 2005 Sheet 36 of 41
A B C D
5 4 3 2 1

PC38
4.7U_1210_25V6K
N4 1 2

1
2
PC40 PC39 PD11
PL12 B+++ 0.1U_0603_25V7K 470P_0805_100V7K EC11FS2_SOD106

1
FBM-L18-453215-900LMA90T_1812 1 2 BST_3V BST_5V

2
1 2 SNB 2 1 FLYBACK
D B+ D
PR70

2
22_1206_5% PT1

8
7
6
5
1

PC41 1 PC42

D
D
D
D

2
4.7U_1206_25V6K 4.7U_1206_25V6K PQ16 PC43
SI4800DY-T1-E3_SO8 PD12 0.1U_0603_25V7K 10UH_SDT-1403P-100-120GP_4.5A
2

VS DAP202U_SOT323 1 2

3
G
S
S
S
PR71
0_0603_5% B+++

1
2
3
4

2
DH_3V-2 2 1

1
VL
LX_3V PD13

5
6
7
8
1SS355_SOD323 +12VALWP

8
7
6
5
PQ17

D
D
D
D
1

1
SI4800DY-T1-E3_SO8

D
D
D
D

1
PQ18 PC44 PC45

1
SI4810DY-T1-E3_SO8 PC46 4.7U_1206_25V6K 4.7U_1206_25V6K

G
1

S
S
S
4.7U_0805_6.3V6K

2
G

1
S
S
S
PC47 PR72

4
3
2
1
0.1U_0603_25V7K PC48 PC122 1.27K_0402_1%
1
2
3
4

2
1

1U_0805_25V4Z 1U_0805_25V4Z

2
DH_3V-1
1

DL_3V
PL4 PC49 PR74

5
6
7
8

1
10U_LF919AS-100M-P3_4.5A_20% 47P_0402_50V8J 0_0603_5%
2

2 1 DH_5V-1 2 1 DH_5V-2 PC50

D
D
D
D
PR73 47P_0402_50V8J
2

2
1.87K_0402_1% PQ19

22

21
2

1
PU6 SI4810DY-T1-E3_SO8

1
S
S
S
PR75 PC51 25 4

V+

VL
3.74K_0402_1% 0.47U_0603_16V7K BST3 12OUT PR76
5
2

4
3
2
1
VDD
2

27 18 2M_0402_1%
C DH3 BST5 C
16
1

PR77 DH5 LX_5V


2 1 26 17

2
1M_0402_1% PR78 LX3 LX5 DL_5V
24 DL3 DL5 19
+3VALWP 0_0402_5% 20
1

PGND
CSH5 14
PR79 ISE_3V+ 1 13 ISE_5V+
ISE_3V- CSH3 CSL5
2 1.24K_0402_1%
1 2 CSL3 FB5 12

1
3 FB3 SEQ 15

1
1 2 10 9 +2.5VREF PR81
34,36 PACIN SKIP# REF
2

PR80 23 6 PC52 576_0402_1%


SHDN# SYNC
1

1
1 PR82 10K_0402_1% 11 0.47U_0603_16V7K

2
RESET#
1

3.32K_0402_1% PC54 7 PC55

2
PC53 + 100P_0402_50V8J TIME/ON5 4.7U_0805_6.3V6K
2

2
150U_D2E_6.3VM_R18 PD14 28

GND
1

RUN/ON3 +5VALWP
SKUL30-02AT_SMA
2 VSE_3V PR83
2

1
47K_0402_1% MAX1902EAI+T_SSOP28

1
VS 1 2 PC56
2

1
1000P_0402_50V7K PR84 PC57 1
2

10.2K_0402_1% 100P_0402_50V8J

2
PR85 + PD15

2
1

10K_0402_1% VSE_5V PC58 SKUL30-02AT_SMA


POK 38
PC59 150U_D2E_6.3VM_R18
1

2
1
@ 0.047U_0603_25V7M 2
2

PR86
10K_0402_1%
2 1 VL
PR87

2
220K_0402_5%

B B
MAINPW ON 17,34,35
1

PC60
0.47U_0603_16V7K
2

A A

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2005/08/22 Deciphered Date 2008/08/22 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
3V / 5V / 12V
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number R ev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Saturday, August 20, 2005 Sheet 37 of 41
5 4 3 2 1
A B C D

PL13
FBM-L18-453215-900LMA90T_1812
1 2 B+

1
1

1
PC61 PC62 PR88

1
4.7U_1206_25V6K 4.7U_1206_25V6K 0_1206_5%
PC63 PC64

2
4.7U_1206_25V6K 4.7U_1206_25V6K

2
1
+5VALWP 1

2
PC65

1
4.7U_0805_6.3V6K PC66 PR89 PC67
0.1U_0603_25V7K 2.2_0603_5% 2.2U_0805_10V6K

2
PD16

1
DAP202U_SOT323

3
8
7
6
5
PQ20 BST_1.5V-1

D
D
D
D
+1.8V SI4800DY-T1-E3_SO8

BST_1.8V-1
PC68 PC69

14

28
G
S
S
S
+1.8VP 0.01U_0402_25V7Z PU7 0.01U_0402_25V7Z

5
6
7
8
PL5 2 1 12 SOFT1 17 2 1

VIN

VCC
1
2
3
4
1.8U_D104C-919AS-1R8N_9.5A_30% DH_1.8V-2 SOFT2

D
D
D
D
1 2 LX_1.8V PC70 PC71 PQ21
0.1U_0402_16V7K 0.1U_0402_16V7K SI4800DY-T1-E3_SO8

2
1 2 1 1 2BST_1.8V-2 6 23 BST_1.5V-2
1 2 2 1
BOOT1 BOOT2
+1.5V

G
S
S
S
PR90 PR91
+ PC72 PR156 3_0603_5% 3_0603_5%

4
3
2
1
8
7
6
5
220U_6.3V_M_R13 4.7_1206_5%
1 2 DH_1.8V-1 5 24 DH_1.5V-1 1 2 DH_1.5V-2 PL6 +1.5VALWP

D
D
D
D
1
2 PR92 UGATE1 UGATE2 PR93 1.8U_D104C-919AS-1R8N_9.5A_30%
1

PQ22 0_0603_5% 4 25 0_0603_5% LX_1.5V 1 2


PHASE1 PHASE2
1

PR94 PC73 SI4810DY-T1-E3_SO8

2
S
S
S
10K_0402_1% 0.01U_0402_25V7Z PC123 PR96 PR97

5
6
7
8
2
680P_0603_50V8J 1.87K_0402_1% 1.54K_0402_1% PR157 2
2

1
2
3
4
2

1 2 ISE_1.8V 7 22 ISE_1.5V 1 2 4.7_1206_5% 1

D
D
D
D
2

ISEN1 ISEN2

1
PR95 PQ23
0_0402_5% DL_1.8V 2 27 SI4810DY-T1-E3_SO8 PR98 + PC74

21
LGATE1 LGATE2

1
0_0402_5% PC75 PR99 220U_6.3V_M_R13

G
S
S
S
PC124 0.01U_0402_25V7Z 6.81K_0402_1%
1

680P_0603_50V8J 2

4
3
2
1

2
3 PGND1 PGND2 26
DL_1.5V

9 VOUT1 VOUT2 20
VSE_1.8V 10 19 VSE_1.5V
VSEN1 VSEN2
1 2 8 EN1 EN2 21 1 2
24,29,30 SYSON PR100 15 16 PR101 POK 37
0_0402_5% PG1 PG2/REF 0_0402_5%

GND

DDR
11 OCSET1 OCSET2 18
1

1
2

1
PR103 ISL6227CAZ-T_SSOP28 PR102 PR104

13
1

1
10K_0402_1% PR105 PC76 @ 0_0402_5% 10K_0402_1%
@ 0_0402_5% @ 0.1U_0402_16V7K PR107 PR106 PC77
100K_0402_1% 100K_0402_1% @ 0.1U_0402_16V7K
2

2
1

2
2

3 3

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2005/08/22 Deciphered Date 2008/08/22 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
1.8V / 1.5V
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number R ev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Saturday, August 20, 2005 Sheet 38 of 41
A B C D
5 4 3 2 1

PR108
10_0603_5% PJ12
1 2 2 2 1 1 +5VALWP

2
@ JUMP_43X118

1
PC78 PD17

1
1U_0603_6.3V6M 1N4148_SOD80
PC79 PC80

2
2

1
PC81 22U_1206_6.3V6M 22U_1206_6.3V6M

2
PR109 470P_0402_50V8J

5
6
7
8
6.49K_0402_1% BST_1.05V

5
PU8

D
D
D
D
PQ24

VCC
1
D D

1
SI4800DY-T1-E3_SO8
1 PC82
BOOT

G
S
S
S
7 0.1U_0402_16V7K

2
OCSET

4
3
2
1
PR110

1
100K_0402_1% D DH_1.05V PL7
UGATE 2
VL 1 2 2 PQ25 1.8U_D104C-919AS-1R8N_9.5A_30%
G 2N7002-7-F_SOT23-3 6 2 1 +1.05VSP
FB
S

3
8 LX_1.05V
PHASE

5
6
7
8
PR111 1

1
47K_0402_1% D

D
D
D
D
1 2 2 PQ27 PQ26 + PC83
15,24,25,28,29,31,33 SUSP# G 2N7002-7-F_SOT23-3 3 4 SI4810DY-T1-E3_SO8 220U_6.3V_M_R13
GND LGATE
S
3

G
1

S
S
S
2
PC84 APW 7057RKC-TRL_SO8

4
3
2
1
0.1U_0402_16V7K
2

DL_1.05V
PR112
2.26K_0402_1%
VSE_1.05V 1 2

2
PC85
PR113 1 2
7.15K_0402_1%
0.1U_0402_16V7K
1

C C

+1.8V

1
PJ13

1
@ JUMP_43X118

2
2
PU9
1 VIN VCNTL 6 +3VALWP
PJ14 PU10 +2.5VSP 2 5
GND NC

1
+3VS 2 2 1 1 2 VIN VO 3

1
PC86 3 7 PC87
VREF NC
2

B @ JUMP_43X39 1 4 10U_1206_6.3V7K PR114 1U_0603_6.3V6M B

2
EN ADJ
2

PC88 PC90 1K_0402_1% 4 8


4.7U_0805_6.3V6K PR199 10U_1206_6.3V7K VOUT NC
5 7
1

GND GND 22K_0402_1% 9


1

2
TP
6 8
2

GND GND APL5331KAC-TRL_SO8~N


G965-18ADJP1UF_SO8
1

1
+3VS 1 2 PR115 +0.9VSP

1
PR117 PR200 0_0402_5% D PR116
10K_0402_1% 20K_0402_1% 1 2 2 1K_0402_1% PC89

1
33 SUSP G 0.1U_0402_16V7K

2
1

1
S PQ28 PC91
2

2
PC94 PC92 2N7002-7-F_SOT23-3 10U_1206_6.3V7K

2
0.1U_0402_16V7K @ 0.1U_0402_16V7K
2

A A

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2005/08/22 Deciphered Date 2008/08/22 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
2.5V / 0.9V / 1.05V
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number R ev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Saturday, August 20, 2005 Sheet 39 of 41
5 4 3 2 1
CPU_B+
+5VS
PL8
FBM-L18-453215-900LMA90T_1812
1 2 B+

4.7U_1206_25V6K

4.7U_1206_25V6K
1

1
PD18 +
PR121 EP10QY03 PC100

PC102

PC103
10_0603_5% 2 1 @ 220U_25V_M

2
2

2
2

5
6
7
8
PC105

0.01U_0402_25V7Z
PC104 2.2U_0603_6.3V6K

0.22U_0603_16V7K
1U_0603_6.3V6M

PC106
PU12

BST_CPU1-2

PC107
4 PQ30

DH_CPU1-2
2
V CC 10 30 IRF7821_SO8
VCC VDD

2
5 CPU_VID0 24 D0 V+ 36

3
2
1
23 26 BST_CPU1-1 2 PR124 1
5 CPU_VID1 D1 BSTM 3_0603_5% +CPU_CORE
22 28 DH_CPU1-1 2 PR126 1 PL9 PR128
5 CPU_VID2 D2 DHM 0_0603_5% 0.56UH_ETQP4LR56W FC_21A_20% 0.001_2512_5%
21 27 LX_CPU1 1 2 1 2
5 CPU_VID3 D3 LXM

5
6
7
8
20 29 DL_CPU1
5 CPU_VID4 D4 DLM

2
19 31 PR131 CPU VCC SENSE
5 CPU_VID5 D5 PGND 4.7_1206_5%

1
25 37 ISE_CPU1+ PR132
6,13,18 VGATE VROK CMP 909_0402_1% PR133
4

2 1

1
4 38 ISE_CPU1- 499_0402_1%
S0 CMN

1000P_0402_50V7K
PQ31

2
PR136 V CC 5 17 O AIN+ IRF7832_SO8 PC108 PR134

2
0_0402_5% S1 OAIN+ 680P_0603_50V8J PC110 499_0402_1%

3
2
1

PC109
1 2 PR137 6 16 O AIN- 1 2 PR135
29 VR_ON

1
30.1K_0402_1% SHDN OAIN- 3K_0402_1%
2 1 1 15 VSE_CPU 0.47U_0603_16V7K

1
TIME FB
PR139 1 2 12 14 1 2 1 2
200K_0402_1% PC111 CCV CCI PC112 470P_0402_50V8J PR138 @
1 2 270P_0402_50V7K 2 35 BST_CPU2-1 909_0402_1%
TON BSTS
PR141 1 2 8 33 DH_CPU2-1
68.1K_0402_1% REF DHS
1 PR140 2
1 2 PC113 9 34 LX_CPU2 3K_0402_1%
0.22U_0603_16V7K ILIM LXS
+5VS
VSE_CPU 1 2 7 32 DL_CPU2 1 2 1 2
PR142 OFS DLS
10.7K_0402_1%

100P_0402_50V8J

100K_0402_1% 3 40 ISE_CPU2+ PC114 PR143


SUS CSP
2

1 2 2200P_0402_50V7K 0_0402_5%
PR144

PC115

18 39 ISE_CPU2-
SKIP CSN

3_0603_5%
2
1

2
D CPU_B+
27P_0402_50V8J
RHU002N06_SOT323

11 13 PD19
GND GNDS
1

PR145
13,18 PM_STP_CPU# 2 EP10QY03
1

PC116

G 2 41
PQ32 G TP
S
3

4.7U_1206_25V6K

4.7U_1206_25V6K
RHU002N06_SOT323 S
3

5
6
7
8
PQ33

1
BST_CPU2-2
PR146 MAX1532AETL+T_TQFN40

PC117

PC118
0_0402_5%

2
0.22U_0603_16V7K
18 PM_DPRSLPVR 1 2

1
2 1DH_CPU2-2
4

PC119
+5VS 1 2 PR147

2
0_0603_5% PQ34
PR148 IRF7821_SO8

3
2
1
2

20K_0402_1% PL10
2

PR149 0.56UH_ETQP4LR56W FC_21A_20%


PR150 10K_0402_1% 1 2
100K_0402_1%
1 1

5
6
7
8

1
1

D PR151
2 PQ36 4.7_1206_5% PR152
G RHU002N06_SOT323 909_0402_1%
S
3

2 1

2
1

C 4
2 PQ37
5 PSI# B HMBT2222A_SOT23 PQ35 PC120 1 2
E IRF7832_SO8 680P_0603_50V8J
3

1
PC121

3
2
1
0.47U_0603_16V7K

1 2

PR153
909_0402_1%

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2005/08/22 Deciphered Date 2008/08/22 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
CPU_CORE
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number R ev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Saturday, August 20, 2005 Sheet 40 of 41
POWER PIR LIST
page Reason for change Modify list
36,37, For EMI request to reduce the power board band Add bead PL11,PL12,PL13(SM010020720), add snubber 4.7ohm(SD001470B80)PR131,PR151 and 680P(SE024681J80)PC108,PC120 on CPU CORE
DVT 38,40
Add booster resistor 3ohm(SD013300B80) PR90,PR91 on 1.8V/1.5V and PR124,PR145 on CPU CORE
47 Reduce the high frequency noise Change PC38 to 4.7U_1210(SE065475K80)
34 Add design margine Add 68ohm(SD011680A80) PR155 and change PR9 to 68ohm

39 Change +2.5VSP enable signal for HW request Change +2.5VSP enable signal to +3VS
PVT
40 For EMI request to reduce CPU power board band Change PQ30,PQ34 to IRF7821(SB578210010); PQ31,PQ35 to IRF7832(SB578320010)
40 For cost down del PC100 and PR122,PR123,PR125,PR127,PR129,PR130

HW PIR LIST
HTW00 LA-2871 SCHEMATIC CHANGE LIST
REVISION CHANGE: 0.1 TO 0.2

NO DATE PAGE MODIFICATION LIST PURPOSE


-----------------------------------------------------------------------------------------------------
1 5/30 P29 ADD PULL DOWN 100K_0402_5% R475 ON SUSP# TO PREVENT SUSP# FLOATING
2 5/30 P29 ADD PULL DOWN 100K_0402_5% R476 ON SYSON TO PREVENT SYSON FLOATING
3 6/14 P17 CHANGE C241,C251 FROM 18PF TO 15PF FINE TUNE RTC TIMING
4 7/01 P30 CHANGE LED TYPE FROM SIDE VIEW TO TOP VIEW UPDATE LED LIBRARY
5 7/01 P30 CHANGE KB CONNECTOR EMI CAPS TO MOUNT FOR EMI REQUEST
6 7/01 P27 ADD SPK_SEL CONNECTION BETWEEN EC AND CODEC FOR CODEC EQ SELECTION FOR SPEAKER
7 7/01 P29 ADD MB_ID R477,R478 ON PIN88 FOR EC MB IDENTIFY
8 7/01 P17 CHANGE SATA DC COUPLING CAPS CAPACITANCE TO 3.9nf TO MEET INTEL CRB RECOMMAND VALUE
9 7/01 P30 CHANGE LED RESISTOR R265, R266, R270, R272, RESISTANCE TO INCREASE LED BRIGHTNESS
10 7/01 P20 ADD SATA HDD POWER CONTROL CIRCUIT TO RESERVE BACKUP SOLUTION FOR SATA HDD RESET
11 7/01 P28 ADD R484 FOR MIC JACK GROUND PIN CLEAN TO IMPROVE MIC SOUND QUALITY
12 7/01 P28 CHANGE U21 LDO POWER SOURCE FROM +5VALW TO +5VS FOR POWER TRACE LAYOUT IMPROVE

HTW00 LA-2871 SCHEMATIC CHANGE LIST


REVISION CHANGE: 0.2 TO 0.3

NO DATE PAGE MODIFICATION LIST PURPOSE


-----------------------------------------------------------------------------------------------------
1 8/6 P28 CHANGE U21 PIN 4 FROM +5VS TO +5VALW TO PREVENT NOISE FROM HDD SPIN UP
2 8/6 P15 CHANGE R306, R307 FROM RES TO BEAD FOR EMI REQUEST
3 8/6 P21 CHANGE U2 FROM H-50P (H=2mm) TO TS6121C (H=4mm) FOR COST POINT OF VIEW
4 8/6 P23 CHANGE D19 LED COLOR FROM GREEN TO BLUE CUSTOMER SPEC CHANGE
5 8/6 P09 ADD R488 0_0603 BETWEEN +2.5VS_CRTDAC TO +2.5VS TO IMPROVE CRT VIDEO QUALITY
6 8/6 P29 ADD PULL HIGH RES R487 ON PIN176 FOR WW/JPN# SELECT TO CONTROL M/B CONFIURATION
7 8/6 P30 CHANGE D15,D18,D40,D42 LED COLOR FROM GREEN TO BLUE CUSTOMER SPEC CHANGE

HTW00 LA-2871 SCHEMATIC CHANGE LIST


REVISION CHANGE: 0.3 TO 1.0

NO DATE PAGE MODIFICATION LIST PURPOSE


-----------------------------------------------------------------------------------------------------
1 8/22 P20 CHANGE C661,C662,Q44,Q45,Q47,Q48,R411,R479,R480,R482 REMOVE SATA-HDD POWER RESET FUNCTION
,R483 FROM MOUNT TO RESERVE FOR SW REQUEST
P18 CHANGE D38,R485 FROM MOUNT TO RESERVE
2 8/22 P28 CHANGE R459 RESISTANCE FROM 4.53K TO 3.9K TO REDUCE HEAD PHONE GAIN SETTING
CHANGE R463 RESISTANCE FROM 4.22K TO 6.19K
CHANGE R462 RESISTANCE FROM 4.87K TO 3.3K
3 8/22 P31 CHANGE JP4 AND JP6 VENDOR FROM ACES TO MANUNIX FOR CUSTOMER'S REQUEST
4 8/22 P31 RESERVE JP31 FOR TEST ABILITY

PROPRIETARY NOTE
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2005/08/22 Deciphered Date 2008/08/22 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PIR
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number R ev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Monday, August 22, 2005 Sheet 41 of 41

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