'SPRUGNGB-May 2017 ‘Submit Documentation Feedback Copyright ©2011, Texas neuen IncorporatesPreface .. 1 I} TEXAS INSTRUMENTS Contents Overview 1.1 Introduction .. 1.2 Block Diagram 1.3 ARM Subsystem 2 ARM Subsystem 2.1 Introduction .. . 22 Operating States/Modes save 25 23 Processor Status Registers .... . 25: 24 Exceptions and Exception Vectors. . 26 25 The 16-BIS/32-BIS Concept . 27 26 — 16-BISIS2-BIS Advantages 27 27 Co-Processor 15 (CP'5) . 28 2.7.1 Addresses in an ARM926EJ-S System .... a . . 28 2.7.2 Memory Management Unit 28 2.7.8 Caches and Write Butter . 29 3 System Interconnect 3.1 Introduction .. 3.2 System Interconnect Block Diagram . 4 System Memory 4.1 Introduction 42 ARM Memories .. . 4.3. On-Chip RAM Memory 36 4.4 External Memories . 38 4.5 Internal Peripherals sae 36 46 Peripherals .. = : — a 2 36 5 Memory Protection Unit (MPU) 37 5.1 Introduction .. evetnvnttneenese a . . 38 5.1.1 Purpose of the MPU 38 51.2 Features 5.1.3 Block Diagram .. 5.1.4 MPU Default Configuration .. 52 Architecture . 52.1. Privilege Levels 5.22 Memory Protection Ranges 523. Pemission Structures 5.24. Protection Check 52.5 MPU Hegisior Protection . 5.2.6 Invalid Accesses and Exceptions 527 Reset Considerations 5.2.8 Interrupt Support .. 5.2.9. Emulation Considerations 53 MPU Registers 5.3.1. Revision Identification Register (REVID) SPRUGNOB—May 2017 Contents 8 ‘Submit Documentation Feedback Copyright © 2011, Texas neuen IncorporatesTexas INSTRUMENTS www t.com 5.3.2 Configuration Register (CONFIG) 46 5.33. Inlerrupt Raw Status'Set Register (|RAWSTAT) + 47 5.3.4 Interrupt Enable StatusiClear Register IENSTAT) oe 48 5.35. Interrupt Enable Set Register (|ENSET) .... . 49 5.36 Intorupt Enable Clear Register (IENCLR) : 49 53.7 Fixed Range Start Address Register (FXD_MPSAR) + 50 538 Fixed Range End Address Register (FXD_MPEAR) + 50 5.3.9 Fixed Range Memary Protection Page Altibutes Register (FXD_MPPA) . 5 5.8.10 Programmable Range n Start Address Registers (PROG MPSAR) .vcsenscnee . 52 53.11 Programmable Range n End Address Registers (PROG MPEAR) 53 5.3.12 Programmable Range n Memory Protection Page Atibutes Register (PROGn MPPA) + 54 5.3.13 Fault Address Register (FLTADDRR) 5 5.3.14 Fault Status Reyister (FLTSTAT) + 56 5.3.15 Fault Clear Register (FLTCLA) . 87 Device Clocking 59 61 Oveniew .. 60 62 Frequency Fiexbiliy 1 62 6.3 Peripheral Clocking 63 63.1 USB Clocking + 63 6.32 DDR2mDDR Memory Controller Clocking . 65 63.3 EMIFA Giocking + 67 6.3.4 EMAC Clocking . : 68 6.3.5 _UPP Clocking 70 6.3.6 McASP Clocking .. 71 6.3.7 VO Domains ... : 72 Phase-Locked Loop Controller (PLLC) ..... 73 7.1 Introduction 74 72 PLL Controllers .. : : — : : : 74 7.2.1. Device Clock Generation Ul 7.2.2 Steps for Programming the PLLs .. 77 7:3 PLLC Registers .. woo 79 7.3.1 PLLCO Revision denilcaion Register (REVID) - 80 7.32 PLLC1 Revision Identification Register (REVID) . 81 7.3.3 Reset Type Status Register (RSTYPE) . 81 7.3.4 PLLCO Reset Control Register (RSCTRL) .. 82 7.3.5 PLLCO Control Register (PLLCTL) 83 7.3.6 PLLC1 Control Register (PLLCTL) . 84 7.3.7 PLLCO OBSCLK Select Register (OCSEL) woos 85 7.38 PLLC OBSCLK Select Register (OCSEL) . 86 7.3.9 PLL Multiplier Control Register (PLLM) . 87 7.3.10 PLLCO Pre-Divider Control Register (PREDIV) . 87 7.3.11. PLLCO Divider 1 Register (PLLDIV1) .. . 88 7.3.12 PLLC1 Divider 1 Register (PLLDIV1) - 88 7.3.13 PLLCO Divider 2 Register (PLLDIV2) .. 89 7.3.14 PLLC1 Divider 2 Register (PLLDIV2) 89 7.3.15 PLLCO Divider 3 Register (PLLDIVS) .. 90 7.3.16 PLLC Divider 3 Register (PLLDIV3) 90 7.3.17 PLLCO Divider 4 Register (PLLDIV4) .. 91 7.3.18 PLLCO Divider 5 Register (PLLDIVS) 1 7.3.19 PLLCO Divider 6 Register (PLLDIV6) .. 92 7.3.20 PLLCO Divider 7 Register (PLLDIV7) ose 92 7.3.21 LLCO Oscilator Divider 1 Register (OSCDIV) . 93 7.3.22 PLLC1 Oscillator Divider 1 Register (OSCDIV) .. . 93 Contents ‘SPRUGMOB-May 2017 ‘Submit Documentation Feedback ‘Copyright © 201, Texas insruments Incorporated‘Texas INSTRUMENTS: ewt.com 7.3.23. PLL Post-Divider Control Register (POSTOIV) 94 7.324 PLL Controller Command Register (PLLCMD) . 94 7.8.25. PLL Controller Status Register (PLLSTAT) soe 95 7.8.26 LLCO Clock Align Control Register (ALNCTL) . 96 7.827 PLLC! Clock Align Control Register (ALNCTL) . 97 7.828 PLLCO PLLDIV Ratio Change Status Register (OCHANGE) - 98 7.329 PLLC1 PLLDIV Ratio Change Status Register (DCHANGE) . 99 7.3.30 PLLCO Clock Enable Control Register (CKEN) 100 7331 PLLC! Clock Enable Control Register (KEN) 100 7.3.32 PLLOO Clack Status Register (CKSTAT) 101 7.833 PLLC! Clock Status Register (CKSTAT) «... 102 7.334 PLLOO SYSCLK Status Register (SYSTAT) 103 7.335 PLLCI SYSCLK Status Register (SYSTAT) . 104 7.3.96 Emulation Performance Counter 0 Register (EMUCNTO) . 105 7.337 Emulation Performance Counter 1 Register (EMUCNT!) .. 105 8 Power and Sleep Controller (PSC) . 107 8.1 Introduction .. 108 82 Power Domain and Module Topology 108 82.1 Power Domain States 110 822 Module States mt 83 Exeouting State Transitions 113 83.1 Power Domain State Transitions ..... cesntnneenneeneese eeseeneenee 113 83.2 Module State Transitions 113 84 _IcePick Emulation Support in the PSC... 114 85 PSC Interrupts ... 114 85.1. Interrupt Events 114 8.5.2. Interrupt Registers 115 85.3. Interrupt Handling 116 86 PSC Registers 417 86.1 Revision Identification Register (REVID) 118 8.62 Interrupt Evaluation Register (INTEVAL} «1... — 1 118 8.63. PSCO Module Error Pending Register 0 (modules 0-15) (MERRPRO) 119 8.6.4 PSC1 Module Error Pending Register 0 (modules 0-31) (MERRPRO) .-..-essesseenee 119 8.6.5 PSCO Module Error Clear Register 0 {modules 0-15) (MERRCRO) 120 8.6.6 PSC1 Module Error Clear Register 0 (modules 0-31) (MERRCRO) 120 8.6.7 Power Error Pending Register (PERRPR) 121 8.6.8 Power Error Clear Register (PERRCA) 12 8.6.9 Power Domain Transition Command Register (PTCMD) . 122 8.6.10 Power Domain Transition Status Register (PTSTAT) .. 123 8.6.11 Power Domain 0 Status Register (PDSTATO) : : — 1. 124 8.6.12 Power Domain 1 Status Register (PDSTAT1) 125 86.13 Power Domain 0 Control Register (PDCTLO} 128 8.6.14 Powor Domain 1 Control Register (PDCTL!) 127 8.6.15 Power Domain 0 Configuration Register (PDCFGO) 128 8.6.16 Power Domain 1 Configuration Register (POCFG1) 129 86.17 Module Status n Register (MDSTATn) 190 8.6.18 PSCO Module Control n Register (modules 0-15) (MDCTLm Ist 86.19 PSC1 Module Control n Register (modules 0-31) (MDCTLn) 192 9 Power Management 133 9.1 Introduction .. 134 9.2 Power Consumption Overview 134 93 PSC and PLLC Overview 134 94 Features ... - 135 SPRUGNOB—May 2017 Contos 8 ‘Submit Documentation Feedback ‘Copyright © 201, Texas insruments Incorporated