`timescale 1 ns/ 1 ps

// Infers BRAM Memory::: Both WR and RD operations are synchronous

module memory #(parameter WIDTH = 8, DEPTH=16)(
input wire clk_i ,

// wr port
input wire wr_en ,
input wire [$clog2(DEPTH)-1:0] wr_addr ,
input wire [WIDTH-1:0] wr_data ,

// rd port
input wire [$clog2(DEPTH)-1:0] rd_addr ,
output reg [WIDTH-1: 0] rd_data
);

reg [WIDTH-1:0] mem [0:DEPTH-1];

always @(posedge clk_i) begin

if (wr_en) begin
mem [wr_addr] <= wr_data;
end
rd_data <= mem[rd_addr];
end

endmodule