IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 55, NO.
2, FEBRUARY 2020
A CMOS 76–81-GHz 2-TX 3-RX FMCW Radar
Transceiver Based on Mixed-Mode PLL
Chirp Generator
Taikun Ma , Wei Deng , Senior Member, IEEE, Zipeng Chen , Jianxi Wu , Wei Zheng, Shufu Wang,
Nan Qi , Member, IEEE, Yibo Liu , and Baoyong Chi , Senior Member, IEEE
Abstract— A fully integrated 76–81-GHz frequency-modulated,
continuous-wave (FMCW) radar transceiver (TRX) in a 65-nm
CMOS is presented. Two transmitters (TXs) and three receivers
(RXs) are integrated for multiple-input multiple-output (MIMO)
processing. A 38.5-GHz mixed-mode phase-locked loop (PLL)
with reconfigurable loop bandwidth and a frequency doubling
scheme are employed to generate the reconfigurable FMCW
chirp waveforms. The coarse-to-fine-segmented current DAC is
utilized to support sawtooth FMCW chirps with fast frequency
ramping-down capability, and the delay lock loop (DLL)-based
delay time calibration is used to improve the linearity of the
embedded 2-D Vernier time-to-digital converter (TDC). Pas-
sive voltage-mode down-conversion is utilized to improve the
RX linearity against TX leakage and short-range interference.
A bottom-switching Gilbert-type modulator in the TX is proposed
to realize the bi-phase modulation, and the magnetically coupled
resonator technique is used to effectively expand the link band-
width. The measurement results show that the FMCW TRX could
generate reconfigurable chirps with the bandwidth from 250 MHz
to 4 GHz and the period from 30 µs to 10 ms. The root-mean-
square (rms) frequency error is 110 kHz for a sawtooth chirp
with 4-GHz bandwidth and 300-µs period. The TX maximum
output power is 13.4 dBm and is adjustable within 3 dB by
reconfiguring its low dropout regulator (LDO) voltage. The RX
achieves a 15.3-dB noise figure at 600-kHz IF and a −8.5-dBm RF
input-referred P1dB. The overall power consumption is 921 mW,
with two TXs and three RXs powered ON. Based on the proposed
TRX chip, prototype hardware and a data process algorithm are
developed. Real-time experimental results show that the distance
and the angular resolution of the MIMO radar achieved are 5 cm
and 9◦ , respectively.
Index Terms— CMOS, frequency-modulated continuous wave
(FMCW), millimeter-wave (mm-wave) radar, multiple-input
multiple-output (MIMO), phase-locked loop (PLL), transceiver
(TRX).
Manuscript received April 26, 2019; revised July 26, 2019 and
September 27, 2019; accepted October 18, 2019. Date of publication
November 8, 2019; date of current version January 28, 2020. This article
was approved by Associate Editor Kenichi Okada. (Corresponding author:
Baoyong Chi.)
T. Ma, W. Deng, Z. Chen, J. Wu, and B. Chi are with the Institute
of Microelectronics, Tsinghua University, Beijing 100084, China (e-mail:
chibylxc@tsinghua.edu.cn).
W. Zheng and S. Wang are with Radarchip Technology Company, Ltd.,
Beijing 100085, China.
N. Qi is with the Institute of Semiconductors, Chinese Academy of Sciences,
Beijing 100084, China.
Y. Liu is with the Institute of Microelectronics, Tsinghua University,
Beijing 100084, China, and also with the School of Electrical and Information
Engineering, Tianjin University, Tianjin 300072, China.
Color versions of one or more of the figures in this article are available
online at http://ieeexplore.ieee.org.
Digital Object Identifier 10.1109/JSSC.2019.2950184
0018-9200 © 2019 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission.
See http://www.ieee.org/publications_standards/publications/rights/index.html for more information.
Authorized licensed use limited to: KINGS COLLEGE LONDON. Downloaded on June 21,2022 at 05:33:45 UTC from IEEE Xplore. Restrictions apply.
233
I. I NTRODUCTION
I N RECENT years, automotive technique has been devel-
oped rapidly. More and more corporations have been testing
their systems in real-driving environments. Even some compa-
nies have begun to equip their cars with the automotive system.
High-performance and high-reliability visual systems play an
important role in developing a credible automotive system.
At present, sensors commonly used for automatic driving
are the laser radar, camera, ultrasound, and millimeter radar
[1], [2]. Among them, the millimeter-wave (mm-wave) radar
in 77 GHz, mostly based on frequency-modulated continuous
waves (FMCW), has drawn the most attention because of
its compact size and robustness over weather, temperature,
and light conditions [3]–[6]. Up until now, radars in CMOS
technology have become hotspots due to their high integration
and low cost. A number of works on the CMOS FMCW
radar have been established [7]–[12]. However, there are
still considerable shortcomings in current works, including
their single function, insufficient performance, and poor anti-
interference ability.
In a real complex traffic scenario, a single radar is
insufficient to ensure the security. Therefore, an advanced
driver assistance or automotive system requires multiple
radars with different functions. As shown in Fig. 1, these
radars are generally classified into three categories based
on the detectable distance as the long-range radar (LRR),
medium-range radar (MRR), and short-range radar (SRR).
Multi-mode radars supporting all the functions mentioned
above are preferred, because all the automotive sensors can
be developed without installing radar solutions for each
application [13]. They reduce the cost of the whole system
while introducing challenges to radar design.
To develop a multi-mode FMCW radar, a reconfigurable
chirp waveform is needed to support various functions. Frac-
tional N-phase-locked loops (PLLs) are utilized to generate
FMCW chirps in [4], [5], [10], and [14]. However, the loop
bandwidth is not able to change flexibly. Lou et al. [15] and
Wu et al. [16] used an all-digital PLL in the chirp generator,
contributing a flexible loop bandwidth configurability and a
higher frequency sweep linearity. In [17], a mixed-mode PLL
is used, which inherits the advantages of a digital PLL and
avoids digitally-controlled oscillators (DCOs) with compli-
cated calibration.
234
Fig. 1. Radar applications in advanced driver assistance.
Angular resolution is necessary for multi-function radars,
especially for short- and medium-range applications. Radars
with multiple channels are proposed [6], [13], [14], [18] with
limited angular resolution due to the small number of antennas,
since the angular resolution is inversely proportional to the
antenna aperture. To further improve the angular resolution
without consuming too much area, multiple-input multiple-
output (MIMO) technology is employed [1], [5], [19]–[21].
For an MIMO radar with m transmitters (TXs) and n receivers
(RXs), m×n virtual channels can be achieved. The key point of
MIMO technology is to let each TX transmit independent sig-
nals. This target can be achieved by time division multiplexing,
so that different TXs transmit signals, in turn [19], [20]. This
method can be implemented easily without adding any circuit.
However, it will lead to a multiplexed measurement time and
reduce the response speed of the system. Another method is
to generate TX signals by frequency division multiplexing.
Generating orthogonal signals is a feasible method, but it
makes the circuit more complicated [21]. Binary phase shift
keying (BPSK) is much simpler by adding a binary phase
modulator to TX channels [1], [5].
The problem of TX-leakage and short-range interference
deserves much concern since they may saturate the RF front
end and deteriorate the RX sensitivity. Efforts have been
made in [22]–[25] to directly cancel the TX leakage that
was produced by the chip itself like the lossy substrate,
even-order harmonics, and antenna mismatch. However,
they are incapable of dealing with short-range interferences.
In [26], an artificial on-chip target is utilized to cancel the
short-range leakage at the cost of increasing the complexity of
the circuit and signal analysis. Reference [27] illustrates that
a fast-modulation ramp helps solving the problem in SRR.
However, it will result in a too-high IF frequency in LRR
which introduces challenges in the analog baseband design.
To solve this problem, RXs with strong resistance against TX-
leakage and close-target interference have to be implemented.
This article presents a highly integrated, 76–81-GHz, 2-TX,
3-RX, FMCW, MIMO radar transceiver (TRX). To integrate
multiple functions in one radar, a mixed-mode PLL with a
flexible loop bandwidth configuration is utilized to generate
the FMCW chirp. The presented PLL supports sawtooth
Authorized licensed use limited to: KINGS COLLEGE LONDON. Downloaded on June 21,2022 at 05:33:45 UTC from IEEE Xplore. Restrictions apply.
IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 55, NO. 2, FEBRUARY 2020
FMCW chirps with fast frequency ramping-down capability
by utilizing the coarse-to-fine-segmented current DAC and
achieves a better root-mean-square (rms) frequency error and
a wider chirp bandwidth by using a 2-D Vernier time-to-digital
converter (TDC) with the delay-locked loop (DLL)-based
delay time calibration and the tail filtering voltage-controlled
oscillator (VCO) with the splitted-varactor technique. Two
TXs and three RXs are implemented for MIMO. The TRX
can also be cascaded to form a radar with a multiplied
number of TX and RX channels. The TX that supports bi-
phase modulation and ON/ OFF keying is proposed for MIMO
application with the bottom-switching Gilbert-type modulator
and a fast power-ON/down capability. Moreover, to improve
the TX leakage resilience, a high-linearity RX with the pas-
sive voltage-mode down-conversion is employed in the chip.
A low-noise, IF baseband amplifier with embedded high-pass
filtering is proposed to reduce the noise contribution of the
analog baseband to the RX. A demo system is also developed
by embedded wafer-level balls (eWLB) package technique and
patch antenna array fabrication on a Rogers RO3003 PCB to
test the radar system performance in a real environment.
This article is an extension of [28], wherein the chip and
some of the results are briefly introduced. The remaining
of this article is organized as follows. Section II presents
the fundamental principle of an FMCW MIMO radar and
estimates the link budget. Section III describes the system
architecture of the radar TRX and the details about circuit
implementation. The on-chip measurement of the TRX is
discussed in Section IV. The prototype hardware is introduced
in Section V and the measurement based on hardware is also
illustrated. Section VI shows the conclusion of this work.
II. R ADAR P RINCIPLE AND S YSTEM B UDGET
A. FMCW Principle
The principle of the FMCW radar is discussed in detail
here [14]. The radar transmits a continuous wave, whose
frequency changes linearly with time, and receives the echo
reflected by the target. By calculating the frequency difference,
the delay between the transmitted wave and the reflected wave
can be known to determine the position of the target. For a
moving target, the Doppler frequency will be included in the
frequency difference, so that the system can get the relative
speed of the target. For triangular waves, the relationship
between the beat frequency and the target distance and speed
is shown as follows:
2BWC 2 fC
f b1, 2 = ± ·R+ · v = ±α · R + β · v. (1)
c · TC c
Here, f b1,2 is a pair of beat frequencies of the rising and
falling segments. BWc is the bandwidth of the chirp and Tc is
the duration of the chirp. f c is the carrier frequency, which is
at about 77 GHz.
However, in the environment with multiple moving targets,
2N (N > 1) beat frequencies have to be generated, and the
system cannot correctly match the frequency pair of each
target, thus causing the ghost target problem. An effective
MA et al.: CMOS 76–81-GHz 2-TX 3-RX FMCW RADAR TRX 235

TABLE I
R ADAR S PECIFICS

Fig. 2. FMCW principle of a sawtooth wave.

solution is to use multiple chirps with different slopes. Never-

theless, this method also has limitations: it requires complex
algorithms to distinguish real targets from ghost targets. B. System Budget
Sawtooth wave is utilized to avoid the generation of ghost The detailed system specifications of LRR, MRR, and SRR
targets in principle. The waveform of ideal sawtooth chirps is are discussed in [2]. Based on that, to satisfy the application
the Sawtooth wave, which is utilized to avoid the generation requirements of the multi-mode radar, the performance indi-
of ghost targets, in principle. The principle is shown in Fig. 2. cators of the radar in this work are shown in Table I, and the
f r is the frequency difference between the transmitted signal circuit specifications are calculated as follows.
and the received echo signal and f d is the Doppler frequency. First, the input power is estimated. The relationship between
The transmitted signal can be expressed as follows: the received signal power and the target position is given by
   
B the well-known radar function
ST (t) = ST (ts , n) = cos 2π f c + · ts · ts + ϕ0 (2)
2T
σ G T G R λ2
t = ts + nT, 0 ≤ ts < T. (3) PR = · PT . (8)
(4π)3 L ATM R 4
Here, B and T are the bandwidth and the period of one
sawtooth chirp, respectively. ts is the time from the start of Here, σ is the target radar cross section, which can be assumed
the (n + 1)th chirp, and is defined as in (3). Then, the received as 10 m2 for a passenger car, according to the research in [29].
signal is derived as follows: G T and G R are the antenna gain of the TX and the RX,
    respectively. For highly integrated radar systems, microstrip
B
SR (ts , n) = cos 2π f c + · (ts − τ ) · (ts − τ ) + ϕ0 . antennas are usually used, whose typical gain is about 10 dBi
2T [1], [21]. λ is the wavelength of the signal and is 3.9 mm
(4) at 77 GHz. L ATM is the signal attenuation in the atmosphere,
Here, τ is the transmission delay of the electromagnetic (EM) which is around 0.5 dB/km at 77 GHz [14]. R in (7) is the
wave in air. For a moving object with a velocity of v, τ can distance between the target and the radar. PR and PT are
be defined as (5). Then, the simplified IF signal is derived as powers of transmitting and receiving signals, respectively.
below after mixing the transmitted signal with the received Assuming a PT of 10 dBm, the PR is −9 to −128 dBm
signal, and it is filtered by a low-pass filter (LPF) for a target with a distance of 0.15–150 m. Obviously,
to prevent the radar from being interfered by TX-leakage
2(R + vt) 2(R + vts + vT n)
τ = = (5) and short-range targets when working in a multi-target
c    c  environment, the out-of-band input-referred P1dB (IP1dB) of
B 2R 2 f c vT 2 fc R
Sb (ts , n) = cos 2π · ts + ·n+ . the RX must be higher than the power of TX-leakage and
T c c c short-range targets’ echo signals. Medra et al. [30] points out
(6) that the coupling between the TX/RX package and antennas
Before digital processing, the signal is sampled by an ADC at the mm-wave frequency band is the dominant leakage
whose sample rate is assumed as f s . Then, the sample index source. The 3-D EM simulations with HFSS show that the
m can be defined as m = ts · fs , and (6) can be written as TX–RX leakage due to the package and on-PCB antennas
follows: (discussed later) at 77 GHz is −22.5 dB. Hung et al. [31]
    claims a −25-dB TX–RX leakage for a 77-GHz radar, which
B 2R 1 2 f c vT 2 fc R
Sb (m, n) = cos 2π ·m+ ·n+ . is similar to our simulation results. In this work, a −20-dB
T c fs c c TX–RX leakage is assumed with a few-dB design margin,
(7) resulting in a −10-dBm TX–RX leakage signal. The IP1dB
Finally, the distance and the velocity of the object can be of the RX should be higher than this leakage signal power as
derived from the obtained 2-D beat frequency by 2-D-fast well as the short-range interference echo power of −9 dBm,
Fourier transform (FFT). The formula is shown in Fig. 2. resulting in the RX IP1dB requirement of −9 dBm.

Authorized licensed use limited to: KINGS COLLEGE LONDON. Downloaded on June 21,2022 at 05:33:45 UTC from IEEE Xplore. Restrictions apply.
236
Then, the noise figure (NF) of the RX is calculated accord-
ing to the receiving signal power. For one receiving channel,
the output SNR of the radar is shown as follows:
SNRsingle = 174 − NF + Sin,min − 10 lg RBW
where NF is the noise figure of the RX, Sin,min is the minimum
receiving signal power, and RBW is the resolution of FFT,
which are utilized to get beat frequencies. The RBW is deter-
mined by the FFT sampling frequency and the data length.
The data length is limited by the system frame per second
(FPS) and the data processing speed. For an FPS of 20 Hz,
the data length of 10 ms is reasonable, resulting in a 100-Hz
RBW.
For an MIMO radar with M-transmitting channels and
N-receiving channels, the output SNR will increase by
10lgMN dB
SNRarray = SNRsingle + 10 lg M N.
According to [32], the SNR needs to be larger than
15.3 dB with 99% detection probability and 10−8 false alarm
ratio (FAR). Thus, the NF is derived to be not less than
18.7 dB.
The performance of the waveform generator is critical to
implement a multi-mode radar. To satisfy the system res-
olution in Table I, the FMCW chirp (sawtooth) bandwidth
and duration must be carefully designed. The relationships
between the distance, the velocity resolution, and the chirp
waveform are shown in Fig. 2. Since the required R is
0.05 m, the maximum bandwidth of the chirp needs to be
wider than 3 GHz. As v is 0.5 m/s, the data length per
frame nT needs to be larger than 3.9 ms.
The PLL phase noise and nonlinearity of the on-chip
FMCW chirp generator also have significant influence on the
radar performance. The phase noise would be converted into
the baseband noise after the down-conversion and contributes
to the deterioration of SNR. Following [33, eqs. (5) and (56)],
the phase variance at the IF output can be given by
 ∞   
2 Dϕ 4π f L R
σϕ,out = Sϕ,out ( f )d f = 1 − exp −
0 π fL c tion T should be less than 32.5 μs:
(11)
where f L is the PLL bandwidth, R is the target distance, and
Dϕ is the phase diffusivity. Dϕ is derived as follows [34]:
Dϕ = 2π 2 Sϕ,VCO ( f )( f )2
where Sϕ,VCO ( f ) is the PLL phase noise at a specific
frequency offset f in the region of the phase noise spectrum
with −20 dB per decade. According to [33, eq. (41)], the PLL’s
phase noise contribution to the SNR is
1 2
= 2σϕ,out . (13)
SNR P N
As mentioned before, the required SNR of the radar system
is determined by the detection probability and the FAR [32].
In practical applications, the detection probability can be
increased by repeated measurements, thus reducing the SNR
requirement of the system. By setting the PLL bandwidth
and the target distance to 300 kHz and 150 m, respectively,
Authorized licensed use limited to: KINGS COLLEGE LONDON. Downloaded on June 21,2022 at 05:33:45 UTC from IEEE Xplore. Restrictions apply.
IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 55, NO. 2, FEBRUARY 2020
the SNR requirement is relaxed to 11 dB for 20 repeating
measurements, 99% detection probability, and 10−8 FAR.
According to (11)–(13), the phase noise at 1 MHz offset should
be less than −86.5 dBc/Hz. In this setting, the influence of the
(9)
phase noise on the SNR is much greater than the RX noise.
The nonlinearity of the FMCW chirp would influence
the radar distance resolution. Following [2, eq. (10)] and
[35, eq. (5)], the nonlinearity of the FMCW chirp is defined
as follows:
δf
Lin = (14)
BW
where BW is the bandwidth of the FMCW chirp and δ f is
the frequency error. After taking the chirp nonlinearity into
account, the distance resolution is given by
c 2
R = + (Lin · R)2 . (15)
(10) 2BW
For 4-GHz BW and 150-m detection distance, the nonlinearity
ratio Lin should be less than 0.02% to obtain 0.05-m distance
resolution.
The angular resolution ϕ of the radar is determined by
the half-power beamwidth of the antenna pattern, which can
be written as [32]
λ
ϕ = 0.88 (16)
Darray
where D array is the aperture of the antenna array. To offer
an angular resolution of 5◦ , the aperture of the antenna array
should be larger than 54 mm. For an MIMO system, the virtual
aperture is
Darray = NTX · NRX · d. (17)
NTX and NRX are the number of TX and RX channels,
respectively. d is the spacing between antennas. With a spacing
of λ/2, 1.95 mm, the number of MIMO virtual receiving
channels should be larger than 20.
To meet the requirement of a maximum velocity of 30 m/s,
which is derived in the following, the minimum chirp dura-
λ
v max = . (18)
4T
(12) III. C IRCUIT I MPLEMENTATION
A. System Architecture
Fig. 3 illustrates the architecture of the proposed
76–81-GHz, FMCW radar TRX. The system consists of two
TXs and three RXs for MIMO operation. A mixed-mode,
PLL chirp generator around 38.5 GHz is integrated, which
is distributed in the local oscillator (LO) network to multiple
branches. The LO network includes five frequency doublers
dedicated for each TX/RX channel, as well as a pair of input–
output LO buffers for multiple chip cascading. In the chirp
generator, a programmable waveform controller is utilized to
generate a triangular or sawtooth waveform control code. Each
RX consists of a low-noise amplifier (LNA), a mixer, an IF
baseband amplifier, and a programmable analog baseband,
MA et al.: CMOS 76–81-GHz 2-TX 3-RX FMCW RADAR TRX
Fig. 3. System block diagram of the presented FMCW TRX.
and each TX contains a power amplifier (PA) with a bi-
phase modulation stage. The bi-phase modulation stage could
provide 0◦ or 180◦ phase-shifting to support the BPSK mod-
ulation for MIMO operation.
In the RX design, the linearity requirement is first consid-
ered due to strong TX-leakage and near-target interferences
introduced by a car’s bumper. To realize a high-linearity RX
front-end, a single-stage low-gain LNA and a voltage-mode
passive mixer are employed. An IF baseband amplifier with
the high-pass filtering characteristics is utilized to eliminate
the leakage-induced dc-offsets. Due to the degraded noise-
suppression capability of the low-gain LNA, a low-noise
design is involved in the mixer and IF baseband amplifier.
In the simulation, the intermediate frequency amplifier (IFA)
contributes 2.9 dB to the RX total NF.
For the MIMO application, two TXs and three RXs are
integrated in this work. In each TX, a bottom-switching
PA that can be turned ON and OFF quickly is proposed to
realize bi-phase modulation and ON/ OFF keying. To generate
the FMCW chirp, a mixed-mode PLL with flexible loop
bandwidth configuration is utilized in this work. Compared to
all-digital PLLs, the mixed-mode PLL avoids the complicated
DCO design by replacing the DCO with a VCO and a current
DAC followed by an integrator.
B. High-Linearity RX
Fig. 4 shows the schematic of the RX RF front-end, includ-
ing a one-stage LNA and a passive mixer. The LNA adopts the
single-stage common-source topology for a large output swing
at low supply voltage. A pair of cross-coupled capacitors
(C1 , C2 ) is used to neutralize the transistor gate–drain parasitic
capacitance [36] to improve the reverse isolation. In the
LNA input matching network, a transformer and a digitally
controlled artificial dielectric (DiCAD) T-line [37] are utilized
to realize single-to-differential conversion, as well as the
matching frequency tuning. Compared to the MIM switched-
capacitor array, the DiCAD introduces less loss to the network.
The mutual coupling between the primary coil and the second
coil of the transformer complicates the design of the DiCAD.
Authorized licensed use limited to: KINGS COLLEGE LONDON. Downloaded on June 21,2022 at 05:33:45 UTC from IEEE Xplore. Restrictions apply.
237
Fig. 4. Schematic of the RX RF front end.
Fig. 5. Schematic of the IF baseband.
In this work, the DiCAD is carefully optimized to finely tune
the operation frequency while introducing small loss.
A double-balanced passive voltage-mode mixer is adopted
in the front end due to the following advantages. First, the pas-
sive mixer has high linearity, which is important to resist
the TX leakage. Second, no static current flows through the
passive mixer, which contributes less flicker noise and saves
power. The high-LO amplitude requirements of the passive
mixer are satisfied by utilizing the presented LO distribution
network, as discussed later.
Fig. 5 shows the scheme of the IF baseband, including
an IF baseband amplifier with embedded high-pass filtering
characteristics, three programmable gain amplifier (PGA)
stages, two high-pass filters (HPFs), two LPFs, and an output
buffer. In the IF baseband amplifier, the resistor (RF ) and the
coupling capacitor (CC ) form the first HPF, which eliminates
the dc-offsets introduced by TX leakage. To address the poor
noise-suppression of the LNA, a low-noise design must be
involved in the IF baseband amplifier. By employing the
current reuse technique and inserting RF into the feedback,
this amplifier is self-biased, and the noise contribution from
RF as well as the transistors is minimized. The simulation
shows that the NF of this amplifier is only 15 dB.
The PGA has three stages with a reconfigurable total
gain from 0 to 52.6 dB. The second R/C HPF stage helps
cancel the dc offsets from the IFA and the first PGA stage.
Its bandwidth is reconfigurable from 200 to 500 kHz to
smooth the receiving signal’s power between the near-target
echo and the far-target echo, reducing a received signal power
238
Fig. 6. Schematic of the PA.
Fig. 7. (a) Simplified schematic of MCRs. (b) Simulated Z21 with a fixed Q
of 5 and a variable k from 0.1 to 0.5.
range. The LPF bandwidth is also reconfigurable from 1.5 to
3 MHz, depending on the chirp configuration. By using a
2-GHz/1-ms chirp, the target with the maximum distance
of 150 m will introduce 2-MHz IF echo after the down-
conversion. The low-pass corner frequency of each LPF stage
is set to 3 MHz in that case to filter out the interferences.
C. TX With Bi-Phase Modulation
The three-stage PA is illustrated in Fig. 6, in which the first
stage is used as a bi-phase modulator, and the second and
third stages are common-source amplifiers with neutralization
capacitors.
A Gilbert double-balanced mixer circuit is used to realize
the bi-phase modulation in this work. In the conventional
mixer implementation, the signals are injected into the bot-
tom common-source transistors (M1a,b), and the top cascode
transistors (M2a–d ) act as the switches. However, the heavy
parasitic capacitance of M2a–d makes it difficult to realize
wideband impedance matching, while the turn-on resistance
increases the loss of the matching network. In the proposed
bottom-switching structure, the transistors M1a,b are used as
the tail switches that switch ON the bi-phase modulation.
LO signals are injected into the top cascode transistors M2a–d ,
which work as amplifying transistors. Larger-size tail transis-
tors can be used to obtain higher conductance without loading
the output node, thereby reducing the loss without degrading
the matching bandwidth.
To achieve a wideband performance, magnetically coupled
resonators (MCRs) [38] are used to realize the interstage and
output stage impedance matching. The simplified schematic
of MCRs is shown in Fig. 7. An MCR forms a fourth-order
network, and by controlling the resistor, quality factor Q, and
resonant frequencies at both primary and secondary coils as
Authorized licensed use limited to: KINGS COLLEGE LONDON. Downloaded on June 21,2022 at 05:33:45 UTC from IEEE Xplore. Restrictions apply.
IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 55, NO. 2, FEBRUARY 2020
Fig. 8. Transient simulation results of (a) ON/ OFF keying and (b) BPSK.
Fig. 9. Scheme of the mixed-mode PLL chirp generator and LO distributions.
well as the coupling coefficient between them, a wideband
response with an acceptable ripple could be achieved.
The PA output power can be adjusted from 10.3 to 13.4 dBm
by reconfiguring its low dropout regulator (LDO) voltage.
A power detector is used to monitor the output power of
the PA [39]. Two TXs can be turned ON and OFF rapidly to
support the dual-channel, time-division operation. According
to the simulation results shown in Fig. 8, the TX achieves a
switching time of less than 30 ns for ON/ OFF keying and less
than 130 ps for BPSK.
D. LO Generation and Mixed-Mode PLL
Fig. 9 depicts the building blocks in the LO generation
and distribution, including a waveform controller, a PLL,
and an LO network. The mixed-mode PLL is adopted to
generate LO signals [40], because its loop bandwidth can be
flexibly programed on-chip, which is useful to configure the
FMCW chirp slope. Compared to all-digital PLLs, the mixed-
mode PLL replaces the high-frequency resolution DCO-based
solution with a simple VCO and a DAC [41].
In the chirp generator, the waveform controller gener-
ates a triangular or sawtooth waveform control code with a
reconfigurable bandwidth and slope. In the mixed-mode PLL,
an LC VCO works around 38.5 GHz, whose output is divided
by 32 and then sent to a digital phase detector (DPD). The
DPD consists of a fine TDC and a coarse counter, detecting
the phase error between the divided clock and the external
reference clock. A digital differentiator (1 − z −1 ) converts
the phase error into the frequency and adds to the waveform
control code. It travels through the digital loop filter (DLF) and
the current DAC before being integrated to a voltage signal,
which controls the frequency of the VCO.
MA et al.: CMOS 76–81-GHz 2-TX 3-RX FMCW RADAR TRX
Fig. 10. Conceptual block diagram of the 2-D Vernier TDC and the
calibration loop.
In the DPD, a TDC is used to detect the period of the
divided clock. However, the mismatch between the rising and
falling times in the TDC degrades its performance. To address
this issue, a dual-rising edge DPD including a wide range
2-D Vernier TDC is employed. This TDC includes two delay
chains. The time resolution of the TDC, , is the delay
time difference between the delay units in two delay chains.
To retain the monotonicity of the TDC, the delay time of
each delay unit in two chains should be designed carefully.
Fig. 10 shows one example, where the delay times of each
delay unit in two chains are set to τx = 6 and τ y = 5 ,
respectively.
The delay units in two chains may cause the delay time
mismatch. A DLL [42] is utilized to calibrate the delay
time mismatch. During the calibration, the delay unit in the
X-chain is first configured as a reference. Then, the delay
time difference between the 5th stage output in the X-chain
and the 6th stage output in the Y-chain is estimated and
feedbacked to control the delay units in the Y-chain. When the
calibration is settled, the delay time difference would be zero.
Then, 5τx = 6τ y = 30 , which eliminates the delay time
mismatch between the delay units in two chains. The TDC
finally achieves 2.3-ns detection range and 10-ps resolution.
Compared with the conventional works, an integrator is
inserted between the DAC and the VCO to relax the resolution
requirement on the DAC. During the FMCW signal generation,
the DAC output represents only the slope of the FMCW
waveform and is constant in the ideal FMCW waveform case,
which significantly reduces the required resolution on the
DAC and lowers down its design complexity. The schematic
of the cascaded DAC, integrator and anti-aliasing filter, and
VCO is shown in Fig. 11. Considering the loop dynamics
in the fast down-segment of the sawtooth chirp, a coarse-to-
fine segmented current DAC is employed in this work. The
7-bit fine DAC with the LSB current of 10 μA is used for
ordinary FMCW chirp generation, supporting a chirp slope
from 10 kHz/25 ns to 4 GHz/0.1 ms. The 4-bit coarse DAC
Authorized licensed use limited to: KINGS COLLEGE LONDON. Downloaded on June 21,2022 at 05:33:45 UTC from IEEE Xplore. Restrictions apply.
239
Fig. 11. Schematic of the current steering DAC, integrator and anti-aliasing
filter, and VCO.
with the LSB current of 1.28 mA mainly works in the fast
down-segment of the sawtooth chirp, which provides fast loop
dynamics. It is also helpful when a chirp slope larger than
4 GHz/0.1 ms is needed.
The VCO uses the cross-coupled LC VCO topology.
By using the split varactors with different dc biases, the VCO
achieves a wider linear tuning range. The tail filtering tech-
nique is adopted to improve its phase noise performance. The
VCO oscillates at 38.5 GHz. A 2-bit switched-capacitor array
provides four discrete tuning curves, and each tuning curve
provides a tuning range of more than 2.0 GHz. With the
frequency doubling scheme, this work could support a wide
chirp bandwidth up to 4.0 GHz.
At the presented frequency, doubling LOs are distributed
into five branches and then doubled to 77 GHz to drive
two TXs and three RXs. Extra buffers are inserted to ensure
enough LO amplitude to drive the passive mixer in the RX and
the PA in the TX. Compared with the conventional solution
of doubling the LO first and then distributing the 77-GHz
LOs, this work minimizes the 77-GHz routing, which would
introduce high loss and need extra buffers to compensate the
loss. Although more frequency doublers are needed, the power
consumption is still reduced, since the 77-GHz LO buffer is
much power-hungry than the frequency doubler.
The PLL bandwidth is configurable based on the chirp
configuration, where the PLL settling time and the integrated
phase noise are the major considerations. To obtain a linear
FMCW chirp, the PLL settling time is limited by the time
step t of the digital waveform generator and the period of
the chirp [11]. The PLL settling time should be much longer
than t. Otherwise, a step-like chirp wave, rather than the
desired straight line waveform, would be generated, which
produces a square-wave modulated IF frequency (instead of a
monotone) after the RX down-conversion and deteriorates the
range resolution of the radar. In this work, t is 25 ns. So,
the loop bandwidth should be much less than 1/ t = 40 MHz.
Moreover, a wide loop bandwidth would increase the inte-
grated phase noise contribution to the frequency error.
On the other hand, the loop bandwidth should not be too
narrow, otherwise the high-order harmonics of the chirp will
240
Fig. 12. Chip photograph (2 = doubler, WC = waveform controller).
Fig. 13. Power consumption breakdown of the TRX.
be filtered out and a sinusoidal chirp, rather than a triangle or a
sawtooth chirp, will be generated. The PLL bandwidth should
pass enough high-order harmonics of the chirp.
The PLL bandwidth should be specially designed to support
the sawtooth FMCW chirp since a short chirp-down time is
desired. Here, a much wider loop bandwidth is configured
during the chirp-down segment to accelerate the PLL settling.
IV. O N -C HIP M EASUREMENT
The proposed 76–81-GHz, 2TX, 3RX, FMCW radar TRX
is implemented in 65-nm CMOS technology. As depicted
in Fig. 12, the entire chip area is 7.29 mm2 , including all bond-
ing pads. The power consumption of the chip is 921 mW, with
all the channels powered on. The power breakdown is shown
in Fig. 13. An on-chip measurement with an unpackaged chip
is completed and the setup is shown in Fig. 14. The RF GSG
pads of LNA and PA are probed on a probe-station. Other pads
of dc, digital control, IF, and 1-GHz FMCW chirp output are
wire-bonded to PCB. An MCU is used to control the radar
through SPI.
The VCO performance is measured at a 1-GHz divided LO
signal. During the test, the waveform controller is powered
OFF and fixed LO signals are generated. The measured VCO
band achieves a 4.8-GHz frequency tuning range, from 37.2 to
42.0 GHz. The measured PLL phase noise curve is illustrated
in Fig. 15. During the measurement, the waveform generator
output is set to a default dc value and the PLL works in
the fixed-frequency mode. The measured phase noise from
the 39.2-GHz carrier is −93.4 dBc/Hz at 1-MHz offset.
Considering 6-dB degradation after the frequency doubling,
Authorized licensed use limited to: KINGS COLLEGE LONDON. Downloaded on June 21,2022 at 05:33:45 UTC from IEEE Xplore. Restrictions apply.
IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 55, NO. 2, FEBRUARY 2020
Fig. 14. Setup of on-chip experiment.
Fig. 15. Measured phase noise of the PLL locked at a 39.2-GHz, fixed
frequency point.
the phase noise from the 78.4-GHz carrier is −87.4 dBc/Hz at
1-MHz offset. Spurs in the phase noise plot are mainly caused
by the DAC’s sampling clock leakage, limited TDC resolution,
and TDC non-linearity [43]. Theoretically, spurs would intro-
duce the intermodulation signals, which may appear as ghost
targets. This problem can be ignored in this work since the
spurs are too weak (maximum spur which would fall into the
desired IF band, 200 kHz to 3 MHz, is −60 dBc at 200 kHz)
to introduce detectable ghost signals.
FMCW chirps are also measured at the divided-by-32 LO
test output, which is sampled by a Keysight MSO9254a
Mixed Signal Oscilloscope and demodulated with the
Keysight 89601B software suite (the average operation among
four periods is enabled). The results are multiplied by 64 to get
the demodulated 77-GHz, FMCW frequency–time waveform
and the rms frequency error. In the measurement, the PLL
bandwidth is set to 100 and 800 kHz in the chirp-up segment
and chirp-down segment/flat segment, respectively. The
results are shown in Fig. 16. According to the measurements,
a maximum 4-GHz chirp bandwidth is achieved which leads
to a distance resolution of 3.75 cm. The 5-μs chirp-down time
MA et al.: CMOS 76–81-GHz 2-TX 3-RX FMCW RADAR TRX
Fig. 16. Demodulated FMCW chirps and frequency error without turning
points under different configurations. (a) 300-μs chirp-up time and 4-GHz
bandwidth. (b) 100-μs chirp-up time and 4-GHz bandwidth. (c) 30-μs chirp-
up time and 4-GHz bandwidth. (d) 1-ms chirp-up time and 1-GHz bandwidth.
(e) 30-μs chirp-up time and 300-MHz bandwidth.
and 5-μs flat segment time are set for all the configurations.
In Fig. 16(a), the FMCW chirp is generated with a 4-GHz
bandwidth and a 300-μs chirp-up time, which is preferred
for short-range applications since the distance is inversely
proportional to the slope of the chirp. The rms frequency
error of this configuration is calculated as 110 kHz (0.003%)
without turning points. Waveforms with a larger slope can
also be produced by the waveform controller. As shown
in Fig. 16(b) and (c), the chirp-up time can be as short as
100 and 30 μs with a bandwidth of 4 GHz, respectively. The
rms frequency errors are measured as 205 kHz (0.005%) and
Authorized licensed use limited to: KINGS COLLEGE LONDON. Downloaded on June 21,2022 at 05:33:45 UTC from IEEE Xplore. Restrictions apply.
241
Fig. 17. Measured RX minimum conversion gain and NF at 600-kHz IF.
4.62 MHz (0.11%). Fig. 16(d) illustrates the measurement
of a small slope chirp, whose bandwidth, chirp-up time,
and rms error are 1 GHz, 1 ms, and 55 kHz (0.006%),
respectively, which will be chosen for long-distance targets.
A fast FMCW chirp with a 30-μs duration and a 300-MHz
bandwidth, which can be used to detect high-speed targets
with velocities up to 30 m/s, is measured, and the result
is shown in Fig. 16(e); the rms error is 505 kHz (0.17%).
However, in Fig. 16(c) and (e) with 30-μs chirp-up time,
nonlinearity can be observed from the frequency error curve.
The main reason is that the 100-kHz loop bandwidth is a little
narrow for such fast chirps. With these chirps, the radar can
also be used to detect targets, but the performance including
the distance accuracy and resolution will be weakened.
The conversion gain of the RX is measured with the setup
shown in Fig. 14. A Keysight E8247C Signal Generator is
used to generate the RF signal, which is then multiplied to
around 77 GHz by an AV12412 mm-wave source module.
The signal is supplied to the RX through a GSG pad by
an on-chip probe. The IF output signal is measured at the
baseband output port using a signal analyzer. The measured
conversion gain is programmable from 26.2 to 78.8 dB. The
minimum RX gain and the corresponding NF are measured
by fixing a 600-kHz IF and sweeping the RF frequency from
76 to 81 GHz. As shown in Fig. 17, the NF is 15.3 dB at
78 GHz. The front-end gain (about 5 dB) and the central
frequency of the RX are somewhat lower than the simulated
results, mainly due to inaccurate modeling of transistors and
passive components in the LNA. It should be noted that the
RX NF at a low IF is degraded a lot by 1/ f noise from the
analog baseband due to low-RF front-end gain.
The linearity of the RX is also verified. Since the
TX-leakage and short-range interference are eliminated by an
HPF in IF, it is the linearity of the front end that really needs to
be concerned. The out-of-band input 1 dB compression point
at 10-MHz IF is measured to indicate the front-end linearity
(shown in Fig. 18), which achieves −8.5 dBm that satisfied
the system requirement of at least −9 dBm, which is slightly
higher than the simulated result, partly due to the lower RF
front-end conversion gain.
242
Fig. 18. Measured IP1dB of the RX front end.
Fig. 19. Measured PA output power versus the operation frequency.
The output power of the PA is measured by a power sensor
and a Keysight 4418A EPM series single-channel power
meter. As illustrated in Fig. 19, the saturated output power
(PSAT ) of PA can be reconfigured by changing the supply
voltage. With 1.3-V VDD , the PA achieves a PSAT of 13.4 dBm
and a −1-dB bandwidth of over 5 GHz from 76 to 81 GHz.
As the current consumption of one TX channel is 119 mA,
the PAE is calculated as 13.5%. To detect the short-range
object, the output power of the PA can be reduced by up to
3 dB by reducing the supply voltage to 1.0 V to improve the
resistance against TX-leakage and short-range interference.
The performances of the proposed FMCW radar TRX are
summarized and compared to similar works in Table II. It can
be seen that this work achieves the widest FMCW chirp
bandwidth of 4 GHz among CMOS works, which ensures the
highest distance resolution and covers the working bandwidth
of both LRR and SRR. The chirp generator in this work is
able to generate the steepest FMCW chirp with 133 MHz/μs
(4 GHz/30 μs) chirp slope. The TX output power of the
presented chip is higher than all the previous works imple-
mented in CMOS and is smaller only than [13] which is
implemented in 0.13-μm SiGe. The RX NF is better than [5]
and comparable with [4]. The NFs in [10] and [12]–[14]
Authorized licensed use limited to: KINGS COLLEGE LONDON. Downloaded on June 21,2022 at 05:33:45 UTC from IEEE Xplore. Restrictions apply.
IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 55, NO. 2, FEBRUARY 2020
Fig. 20. Photograph of the RF board including TX/RX antenna arrays and
cascaded packaged chips.
are better than this work. However, reference [13] is a SiGe
implementation, and references [10], [12], and [14] may have
a high-RX RF gain, which significantly degrades the linearity.
V. P ROTOTYPE H ARDWARE AND M EASUREMENT
Based on the proposed FMCW MIMO radar TRX, the pro-
totype hardware is developed with packaged chips and antenna
arrays on PCB. Several real-scene experiments are carried
out with the TDM-based MIMO to verify the performance of
the radar. First of all, a calibration is completed to eliminate
the amplitude, frequency, and delay offsets between differ-
ent transmitting and receiving channels. Then, the field of
view (FOV) of the system is estimated with a corner reflector.
After that, the distance and angular resolutions are measured
with two corner reflectors. A multi-target performance of the
radar is also evaluated by using numerous flagpoles in an open
square. Finally, the radar is tested with real cars in a parking
space.
A. Prototype Hardware
The presented prototype hardware contains packaged TRX
chips, antenna arrays, radar controller, data controller, and
data processer. As shown in Fig. 20, the MIMO radar has
two chips working in a cascaded master–slave mode to realize
more virtual antennas.
Each chip is packaged with embedded wafer level BGA
(eWLB) technique. It has a redistribution layer (RDL) to
reorganize the location of pads, increase the spacing between
solder balls, and relax the requirement for the PCB technology.
To utilize the eWLB package on 77-GHz radar RF ports,
the transition loss and the impedance match are addressed by
EM simulations in HFSS.
A nonuniform, excited, series-fed microstrip patch antenna
array [44]–[46] is utilized in this work. The antenna array is
designed on an RO3003 PCB with a thickness of 127 μm, a εr
of 3, and a tanδ of 0.0013. According to the simulation results,
a 11.2-dB antenna gain and a −20-dB sidelobe level (SLL) are
achieved. For the antenna array, the relationship between the
angle of the target and the phase difference among RXs is
MA et al.: CMOS 76–81-GHz 2-TX 3-RX FMCW RADAR TRX 243

TABLE II
C OMPARISON

given as follows: chain, the receiving signals of both channels are

   
λ · ϕ B
sin θ = (19) SR1 (t) = cos 2π f c + · t · t + ϕ0 (20)
2πd 2T
   
where θ is the angle of the target, φ is the phase difference B
SR2 (t) = cos 2π f c + · (t + t) · (t + t) + ϕ0 .
among RXs, and d is the spacing between antennas. To obtain 2T
±55◦ FOV, the spacing is designed as d = λ/[2πsin(55◦)] = (21)
2.2 mm.
Besides the packaged chips and antenna arrays, an MCU Then, the frequency offset fOS and the phase offset ϕOS are
is employed to control the TRX. Three off-chip, 11-bit ADCs B
are used to collect IF signals from the six receiving channels. f OS = · t (22)
T
An FPGA is utilized to convert the parallel data from three ϕOS = fc · t. (23)
ADCs to serial data. Then, a USB 3.0 chip is utilized to send
the data to the host computer for radar signal processing. The calibration setup is shown in Fig. 21 and a corner
reflector is used as a reference target. The edge length of the
corner reflector is 14 cm. During the calibration, the target
B. Calibration and One-Target Measurement is placed at an angle of 0◦ and distances of 3, 3.5, 4, and
Due to the asymmetry of the paths on the package and the 4.5 m. At each distance, 50 repeated tests are carried out.
PCB, the transmission times of signals on each transmitting Fig. 22(a) shows the obtained frequency and phase offsets
and receiving channel are different, resulting in amplitude, among different channels with the corner reflector at the
frequency, and phase offsets at IF after down-conversion. Thus, distance of 3 m, where the 11-point clouds in Fig. 22(a)
a calibration is required to be accomplished before any other indicate the test data for 11 MIMO virtual channels with
experiments. When a delay difference t exists on the signal the first channel as the reference. Due to the periodicity of

Authorized licensed use limited to: KINGS COLLEGE LONDON. Downloaded on June 21,2022 at 05:33:45 UTC from IEEE Xplore. Restrictions apply.
244 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 55, NO. 2, FEBRUARY 2020

Fig. 23. Measured angle pattern of the single corner reflector after calibration.

Fig. 21. Measurement scenario with one corner reflector.

Fig. 24. Measured result of radar’s FOV.

Fig. 22. Frequency and phase offsets among different channels. (a) 50 tests
with the corner reflector at the distance of 3 m. (b) Test with the corner the sidelobe and improve the angular resolution, radar super-
reflector at the distance of 3, 3.5, 4, and 4.5 m (average over 50 tests at each resolution algorithms based on Capon and MUSIC are utilized.
distance). As illustrated in Fig. 18, the SLL is lower than −30 dB and
the main lobe width is greatly reduced.
the phase and the limitation of the FFT frequency resolution,
the delay difference t cannot be calculated accurately by the C. FOV Measurement
measured frequency or phase offsets. So, both the frequency
To test the FOV of the MIMO radar, a corner reflector is
and phase offsets have to be measured. Fig. 22(b) illustrates
placed at a distance of 5 m and an angle of about −50◦.
the obtained average frequency and phase offsets over 50 tests
The measured result is shown in Fig. 24; the central point
among different channels with the corner reflector at different
of the main lobe is −53◦, which represents the actual tar-
distances. In practical applications, the average frequency
get. However, the result suffers from an ambiguity problem.
and the phase offset among multiple tests are used for off-
In the angle pattern, the width of the beam is broadened and
line calibration. The measurement shows that the standard
the power leaks to the neglect angle. Using the BeamScan
deviations of the frequency and phase offsets for each channel
algorithm, it is almost impossible to distinguish whether the
after multiple tests at different distances are less than 0.31 kHz
target is in the positive or negative direction. The performances
and 0.08 rad, respectively, which demonstrates the robustness
of Capon and MUSIC are much better due to their narrow
of the utilized offline calibration. Then, the frequency and
main lobe width. However, the noise bottom of the spectrum
phase offset compensation are realized in the digital baseband
is raised, resulting in the decrease of SNR. Fortunately, this
before radar signal processing. With the calibration, even
problem can be overcome by employing a constant false alarm
the frequency and phase offsets among chips from different
rate (CFAR) algorithm, since there is nearly no side lobes in
process corners can be compensated. Then, the cascaded
the spectrum.
multichip system is able to function normally.
The measured result of the single corner reflector with
calibration is shown in Fig. 23, in which the power has D. Distance and Angular Resolution Measurement
been normalized to the peak value. By using the normal FFT With Two Targets
(BeamScan) algorithm, the −10 dB width of the main lobe Two corner reflectors are used to evaluate the distance
is 11. There are side lobes in the spectrum due to the rectangle and angular resolution of the radar. As shown in Fig. 25,
window in sampling and the SLL is −13 dB. To compress the two corner reflectors are placed in front of the radar with

Authorized licensed use limited to: KINGS COLLEGE LONDON. Downloaded on June 21,2022 at 05:33:45 UTC from IEEE Xplore. Restrictions apply.
MA et al.: CMOS 76–81-GHz 2-TX 3-RX FMCW RADAR TRX 245

Fig. 27. Measured angle pattern with two corner reflectors and a minimum
variance (capon) beam former-based algorithm.
Fig. 25. Measurement scenario of distance and angle resolution with two
corner reflectors.

Fig. 26. Measured distance pattern with two corner reflectors by using a
sawtooth wave with 4-GHz bandwidth and 200-μs period.
Fig. 28. Measurement scenario of radar’s multi-target performance.

a distance of about 5 m. One of the two corner reflectors is

stationary. By changing the location of the other one, the dis-
tance and the angle between the two targets can be fine-tuned.
In the measurement, the FMCW chirp bandwidth and duration
are configured as 4 GHz and 200 μs, respectively, for a higher
distance resolution. With this configuration, the theoretically
calculated distance resolution is 3.75 cm. The measured result
is shown in Fig. 26. The locations of the two objects are
4.97 and 5.02 m. The two beams can be clearly identified
and distinguished from each other.
The measured angle pattern is shown in Fig. 27. The angle
of the two corner reflectors is −3◦ and 6◦ , respectively. The
statement can be drawn that the angle resolution of the MIMO
radar is smaller than 9◦ . Compared with single target mea-
surement, the SLL in this scenario increased obviously. Using
the BeamScan algorithm, the sidebands of two targets with
the same distance overlap each, producing beams in the angle
pattern that may be recognized as real objects by mistake.
Using the Capon and MUSIC algorithms, the main lobe widths Fig. 29. Measured 2-D normalized power distribution of a multi-target
scenario.
are narrower and the side lobes are nearly eliminated.
the scenario shown in Fig. 28. In this test, four flagpoles are
E. Multi-Target Performance used as targets. The flagpoles are made of aluminum and has
To further evaluate the performance of the radar in a a diameter of about 20 cm. These flagpoles are arranged in a
multiple target environment, the measurement is completed in straight line with a spacing of 2 m. Taking the radar as the

Authorized licensed use limited to: KINGS COLLEGE LONDON. Downloaded on June 21,2022 at 05:33:45 UTC from IEEE Xplore. Restrictions apply.
246
Fig. 30. Measurement scenario in a parking space with several cars in front
of the radar.
Fig. 31. Measured 2-D normalized power distribution of a parking environ-
ment with several cars.
coordinate origin, the coordinates of the four flagpoles in the
polar coordinate system are (−33◦, 5.3 m), (−13◦, 6.0 m),
(4◦ , 7.1 m), and (15◦, 8.9 m). The Capon-based algorithm
is employed in data processing. The measured 2-D power
distribution is shown in Fig. 29. The power has already been
normalized to the maximum value. It is clear that there are
four maximum points at the location of the poles, forming a
straight line. Behind the poles, a tree is also detected and its
location is circled in the picture. The power of the tree is lower
than the poles, due to smaller RCS. In the scenario, there is a
row of bicycles at the edge. Since the bikes have a large RCS,
they are recognized by high power. It should be noticed that
the angle of the bikes is 50◦ , which is close to the FOV.
F. Real Scene Experiment in a Parking Space
The prototype radar is tested in a parking place and several
cars are used as targets. As shown in Fig. 30, there are three
cars in front of the radar. The cars are parked side-by-side with
a distance of about 6 m. The measured power distribution
pattern is illustrated in Fig. 31. The measured signal power
Authorized licensed use limited to: KINGS COLLEGE LONDON. Downloaded on June 21,2022 at 05:33:45 UTC from IEEE Xplore. Restrictions apply.
IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 55, NO. 2, FEBRUARY 2020
is also normalized to the maximum value. Unlike the corner
reflectors and flagpoles, cars have a larger volume and RCS
also varies with different parts. So, a car is represented as a
group of points on the radar map. In the pattern, three peak
groups are located at the positions of the cars and are circled.
It is clear that the heads and tails of the cars have a stronger
reflection than other parts.
VI. C ONCLUSION
In this work, a 76–81-GHz, 2TX, 3RX, FMCW radar TRX
based on a mixed-mode PLL chirp generator in a 65-nm
CMOS is presented, enabling multi-chip cascading operation
for MIMO processing. A mixed-mode PLL is utilized to
generate the FMCW chirp signal. A high-linearity LNA
and a passive mixer are employed to resist the TX leakage.
A bottom-switching PA is proposed for bi-phase modulation.
The measurement results show a 4-GHz FMCW bandwidth,
133-MHz/μs maximum chirp slope, 13.4-dBm PA output
power, and −8.5-dBm RX input P1dB, at the cost of 921-mW
power consumption, in total.
Based on the proposed radar TRX, cascading prototype
hardware is developed with two chips, forming a 12-channel
MIMO radar with 2 TXs and 6 RXs. The calibration is
completed to compensate the amplitude and delay offsets
among different channels. A simple, 2-D FFT algorithm as
well as a minimum variance super-resolution algorithm are
implemented to get the radar power distribution map. The
measured range and angle resolution achieve 5 cm and 9◦ with
4 GHz/200-μs chirp configuration, respectively. The measured
FOV of the system is from −53◦ to 53◦. Experiments in real
scenarios are accomplished to evaluate the radar performance.
The corner reflectors, trees, bicycles, and cars are successfully
detected.
R EFERENCES
[1] R. Feger, C. Pfeffer, and A. Stelzer, “A frequency-division MIMO
FMCW radar system based on delta–sigma modulated transmitters,”
IEEE Trans. Microw. Theory Techn., vol. 62, no. 12, pp. 3572–3581,
Dec. 2014.
[2] J. Hatch, A. Topak, R. Schnabel, T. Zwick, R. Weigel, and
C. Waldschmidt, “Millimeter-wave technology for automotive radar
sensors in the 77 GHz frequency band,” IEEE Trans. Microw. Theory
Techn., vol. 60, no. 3, pp. 845–860, Mar. 2012.
[3] J. Park, H. Ryu, K.-W. Ha, J.-G. Kim, and D. Baek, “76–81–GHz
CMOS transmitter with a phase-locked-loop-based multichirp modulator
for automotive radar,” IEEE Trans. Microw. Theory Techn., vol. 63, no. 4,
pp. 1399–1408, Apr. 2015.
[4] T.-N. Luo, C.-H. E. Wu, and Y.-J. E. Chen, “A 77-GHz CMOS auto-
motive radar transceiver with anti-interference function,” IEEE Trans.
Circuits Syst. I, Reg. Papers, vol. 60, no. 12, pp. 3247–3255, Dec. 2013.
[5] B. P. Ginsburg et al., “A Multimode 76-to-81 GHz Automotive Radar
Transceiver with Autonomous Monitoring,” in IEEE Int. Solid-State
Circuits Conf. (ISSCC) Dig. Tech. Papers, San Francisco, CA USA,
Feb. 2018, pp. 158–160.
[6] M. Dudek, I. Nasr, G. Bozsik, M. Hamouda, D. Kissinger, and
G. Fischer, “System analysis of a phased-array radar applying adaptive
beam-control for future automotive safety applications,” IEEE Trans.
Veh. Technol., vol. 64, no. 1, pp. 34–47, Jan. 2015.
[7] J.-H. Song, C. Cui, S.-K. Kim, B.-S. Kim, and S. Nam, “A low-phase-
noise 77-GHz FMCW radar transmitter with a 12.8-GHz PLL and a ×6
frequency multiplier,” IEEE Microw. Wireless Compon. Lett., vol. 26,
no. 7, pp. 540–542, Jul. 2016.
[8] W. L. Chan and J. R. Long, “A 60-GHz Band 2×2 phased-array
transmitter in 65-nm CMOS,” IEEE J. Solid-State Circuits, vol. 45,
no. 12, pp. 2682–2695, Dec. 2010.
MA et al.: CMOS 76–81-GHz 2-TX 3-RX FMCW RADAR TRX
[9] S. Jameson and E. Socher, “A packaged 86–98 GHz CMOS transmitter
for FMCW radar applications with 30 dBm of EIRP,” in IEEE MTT-S
Int. Microw. Symp. Dig., Phoenix, AZ, USA, May 2015, pp. 1–4.
[10] J. Lee, Y.-A. Li, M.-H. Hung, and S.-J. Huang, “A fully-integrated
77-GHz FMCW radar transceiver in 65-nm CMOS technology,” IEEE
J. Solid-State Circuits, vol. 45, no. 12, pp. 2746–2756, Dec. 2010.
[11] T. Mitomo, N. Ono, H. Hoshino, Y. Yoshihara, O. Watanabe, and I. Seto,
“A 77 GHz 90 nm CMOS transceiver for FMCW radar applications,”
IEEE J. Solid-State Circuits, vol. 45, no. 4, pp. 928–937, Apr. 2010.
[12] C. Cui, S.-K. Kim, R. Song, J.-H. Song, S. Nam, and B.-S. Kim,
“A 77-GHz FMCW radar system using on-chip waveguide feeders in
65-nm CMOS,” IEEE Trans. Microw. Theory Techn., vol. 63, no. 11,
pp. 3736–3746, Nov. 2015.
[13] T. Fujibayashi et al., “A 76- to 81-GHz multi-channel radar transceiver,”
IEEE J. Solid-State Circuits, vol. 52, no. 9, pp. 2226–2241, Sep. 2017.
[14] H. Jia et al., “A 77 GHz frequency doubling two-path phased-array
FMCW transceiver for automotive radar,” IEEE J. Solid-State Circuits,
vol. 51, no. 10, pp. 2299–2311, Oct. 2016.
[15] L. Lou et al., “A DDS-driven ADPLL chirp synthesizer with ramp-
interpolating linearization for FMCW radar application in 65 nm
CMOS,” in Proc. IEEE Int. Symp. Circuits Syst. (ISCAS), Florence, Italy,
May 2018, pp. 1–4.
[16] W. Wu, X. Bai, R. B. Staszewski, and J. R. Long, “A mm-wave FMCW
radar transmitter based on a multirate ADPLL,” in Proc. IEEE Radio
Freq. Integr. Circuits Symp. (RFIC), Seattle, WA, USA, Jun. 2013,
pp. 107–110.
[17] J. Lin, Z. Song, N. Qi, W. Rhee, Z. Wang, and B. Chi, “A 77-GHz mixed-
mode FMCW signal generator based on bang-bang phase detector,”
IEEE J. Solid-State Circuits, vol. 53, no. 10, pp. 2850–2863, Oct. 2018.
[18] S. Y. Kim and G. M. Rebeiz, “A low-power BiCMOS 4-element phased
array receiver for 76–84 GHz radars and communication systems,” IEEE
J. Solid-State Circuits, vol. 47, no. 2, pp. 359–367, Feb. 2012.
[19] R. Feger, C. Wagner, S. Schuster, S. Scheiblhofer, H. Jager, and
A. Stelzer, “A 77-GHz FMCW MIMO radar based on an SiGe single-
chip transceiver,” IEEE Trans. Microw. Theory Techn., vol. 57, no. 5,
pp. 1020–1035, May 2009.
[20] M. Jahn, R. Feger, C. Wagner, Z. Tong, and A. Stelzer, “A four-channel
94-GHz SiGe-based digital beamforming FMCW radar,” IEEE Trans.
Microw. Theory Techn., vol. 60, no. 3, pp. 861–869, Mar. 2012.
[21] C. Pfeffer, R. Feger, C. Wagner, and A. Stelzer, “FMCW MIMO radar
system for frequency-division multiple TX-beamforming,” IEEE Trans.
Microw. Theory Techn., vol. 61, no. 12, pp. 4262–4274, Dec. 2013.
[22] L. Calderin, S. Ramakrishnan, A. Puglielli, E. Alon, B. Nikolić, and
A. M. Niknejad, “Analysis and design of integrated active cancellation
transceiver for frequency division duplex systems,” IEEE J. Solid-State
Circuits, vol. 52, no. 8, pp. 2038–2054, Aug. 2017.
[23] T. Chi, J. S. Park, S. Li, and H. Wang, “A millimeter-wave polarization-
division-duplex transceiver front-end with an on-chip multifeed self-
interference-canceling antenna and an all-passive reconfigurable can-
celler,” IEEE J. Solid-State Circuits, vol. 53, no. 12, pp. 3628–3639,
Dec. 2018.
[24] G. Pyo, C.-Y. Kim, and S. Hong, “Single-antenna FMCW radar CMOS
transceiver IC,” IEEE Trans. Microw. Theory Techn., vol. 65, no. 3,
pp. 945–954, Mar. 2017.
[25] W.-G. Lim, S.-Y. Park, W.-I. Son, M.-Q. Lee, and J.-W. Yu, “RFID
reader front-end having robust Tx leakage canceller for load variation,”
IEEE Trans. Microw. Theory Techn., vol. 57, no. 5, pp. 1348–1355,
May 2009.
[26] A. Melzer, A. Onic, F. Starzer, and M. Huemer, “Short-range leakage
cancelation in FMCW radar transceivers using an artificial on-chip
target,” IEEE J. Sel. Topics Signal Process., vol. 9, no. 8, pp. 1650–1660,
Dec. 2015.
[27] S. Trotta et al., “An RCP packaged transceiver chipset for automotive
LRR and SRR systems in SiGe BiCMOS technology,” IEEE Trans.
Microw. Theory Techn., vol. 60, no. 3, pp. 778–794, Mar. 2012.
[28] T. Ma et al., “A CMOS 76-81 GHz 2TX 3RX FMCW radar transceiver
based on mixed-mode PLL chirp generator,” in Proc. IEEE Asian Solid-
State Circuits Conf. (A-SSCC), Tainan, Taiwan, Nov. 2018, pp. 83–86.
[29] H. Buddendick and T. F. Eibert, “Acceleration of ray-based radar cross
section predictions using monostatic-bistatic equivalence,” IEEE Trans.
Antennas Propag., vol. 58, no. 2, pp. 531–539, Feb. 2010.
[30] A. Medra et al., “An 80 GHz low-noise amplifier resilient to the TX
spillover in phase-modulated continuous-wave radars,” IEEE J. Solid-
State Circuits, vol. 51, no. 5, pp. 1141–1153, May 2016.
[31] C.-M. Hung et al., “Toward automotive surround-view radars,” in IEEE
Int. Solid-State Circuits Conf. (ISSCC) Dig. Tech. Papers, San Francisco,
CA, USA, Feb. 2019, pp. 162–164.
Authorized licensed use limited to: KINGS COLLEGE LONDON. Downloaded on June 21,2022 at 05:33:45 UTC from IEEE Xplore. Restrictions apply.
247
[32] M. I. Skolnik, Introduction to Radar Systems. New York, NY, USA:
McGraw-Hill, 2001.
[33] F. Herzel, S. Waldmann, and D. Kissinger, “Numerical jitter minimiza-
tion for PLL-based FMCW radar systems,” IEEE Trans. Circuits Syst. I,
Reg. Papers, vol. 66, no. 7, pp. 2478–2488, Jul. 2019.
[34] F. Herzel, D. Kissinger, and H. J. Ng, “Analysis of ranging precision in
an FMCW radar measurement using a phase-locked loop,” IEEE Trans.
Circuits Syst., I, Reg. Papers, vol. 65, no. 2, pp. 783–792, Feb. 2018.
[35] Y. Liu, D. Goshi, K. Mai, L. Bui, and Y. Shih, “Linearity study of DDS-
based W-band FMCW sensor,” in IEEE MTT-S Int. Microw. Symp. Dig.,
Boston, MA, USA, Jun. 2009, pp. 1697–1700.
[36] W. L. Chan and J. R. Long, “A 58–65 GHz neutralized CMOS power
amplifier with PAE above 10% at 1-V supply,” IEEE J. Solid-State
Circuits, vol. 45, no. 3, pp. 554–564, Mar. 2010.
[37] H. Jia, B. Chi, L. Kuang, and Z. Wang, “Simple and robust self-healing
technique for millimetre-wave amplifiers,” IET Circuits, Devices Syst.,
vol. 10, no. 1, pp. 37–43, Jan. 2016.
[38] H. Jia, C. C. Prawoto, B. Chi, Z. Wang, and C. P. Yue, “A full ka-
band power amplifier with 32.9% PAE and 15.3-dBm power in 65-nm
CMOS,” IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 65, no. 9,
pp. 2657–2668, Sep. 2018.
[39] S. Kawai, T. Mitomo, and S. Saigusa, “A 60 GHz CMOS rectifier with-
27.5 dBm sensitivity for mm-Wave power detection,” in Proc. IEEE
Asian Solid State Circuits Conf. (A-SSCC), Kobe, Japan, Nov. 2012,
pp. 281–284.
[40] J. Wu et al., “A 77-GHz mixed-mode FMCW generator based on
a vernier TDC with dual rising-edge fractional-phase detector,” in
Proc. IEEE Asian Solid-State Circuits Conf. (A-SSCC), Tainan, Taiwan,
Nov. 2018, pp. 79–82.
[41] H. Sakurai, Y. Kobayashi, T. Mitomo, O. Watanabe, and S. Otaka,
“A 1.5 GHz-modulation-range 10 ms-modulation-period 180 kHzrms -
frequency-error 26 MHz-reference mixed-mode FMCW synthesizer for
mm-wave radar application,” in IEEE Int. Solid-State Circuits Conf.
(ISSCC) Dig. Tech. Papers, San Francisco, CA, USA, Feb. 2011,
pp. 292–294.
[42] A. Liscidini, L. Vercesi, and R. Castello, “Time to digital converter based
on a 2-dimensions Vernier architecture,” in Proc. IEEE Custom Integr.
Circuits Conf., Rome, Italy, Sep. 2009, pp. 45–48.
[43] M. Zanuso, S. Levantino, C. Samori, and A. L. Lacaita, “A wideband
3.6 GHz digital  fractional-N PLL with phase interpolation divider
and digital spur cancellation,” IEEE J. Solid-State Circuits, vol. 46, no. 3,
pp. 627–638, Mar. 2011.
[44] T. Zalabsky, P. Bezousek, and D. Matousek, “Patch antenna array for
X-band FMCW sensor: An antenna system for detection of obstacles in
near vicinity of a helicopter,” in Proc. Conf. Microw. Techn. (COMITE),
Pardubice, Czech Republic, Apr. 2015, pp. 1–5.
[45] A. Kuriyama, H. Nagaishi, H. Kuroda, and K. Takano, “A high effi-
ciency antenna with horn and lens for 77 GHz automotive long range
radar,” in Proc. 46th Eur. Microw. Conf. (EuMC), London, U.K., 2016,
pp. 1525–1528.
[46] J. Xu, W. Hong, H. Zhang, G. Wang, Y. Yu, and Z. H. Jiang,
“An array antenna for both long- and medium-range 77 GHz automotive
radar applications,” IEEE Trans. Antennas Propag., vol. 65, no. 12,
pp. 7207–7216, Dec. 2017.
Taikun Ma received the B.S. degree in microelec-
tronics from Tsinghua University, Beijing, China,
in 2016, where he is currently pursuing the Ph.D.
degree with the Institute of Microelectronics.
His current research interests include millimeter-
wave circuits, frequency-modulated continuous-
wave (FMCW) radar, RF antenna, and multiple-input
multiple-output (MIMO) radar circuit and system.
248
Wei Deng (S’08–M’13–SM’17) received the B.S.
and M.S. degrees in electronic engineering from the
University of Electronic Science and Technology
of China (UESTC), Chengdu, China, in 2006 and
2009, respectively, and the Ph.D. degree in electronic
engineering from the Tokyo Institute of Technology,
Tokyo, Japan, in 2013.
From 2013 to 2014, he was a Post-Doctoral
Researcher with the Tokyo Institute of Technol-
ogy. From 2015 to 2019, he was with Apple Inc.,
Cupertino, CA, USA, working on radio frequency
(RF), millimeter-wave (mm-wave), and mixed-signal IC design for wireless
transceivers and Apple A-series processors. Since 2019, he has been a Faculty
Member with the Department of Microelectronics and Nanoelectronics, Insti-
tute of Microelectronics, Tsinghua University, Beijing, China. He has authored
or coauthored over 70 IEEE journal and conference articles. He holds four
issued U.S. patents. His research interests include RF, mm-wave, terahertz,
and mixed-signal integrated circuits and system for wireless communications,
radars, and imaging systems.
Dr. Deng was a recipient of several national and international awards,
including the China Youth Science and Technology Innovation Award,
the IEEE SSCS Predoctoral Achievement Award, the Chinese Government
Award for Outstanding Self-Financed (non-government sponsored) Students
Abroad, the Tejima Research Award, and the ASP-DAC Best Design Award.
He currently serves as a Technical Program Committee Member of the IEEE
Symposium on VLSI Circuits (VLSIC) and the IEEE European Solid-State
Circuits Conference (ESSCIRC).
Zipeng Chen received the B.S. degree in microelec-
tronics from Tsinghua University, Beijing, China,
in 2015, where he is currently pursuing the Ph.D.
degree with the Institute of Microelectronics.
His research interests focus on millimeter-
wave (mm-wave)/THz circuit, frequency-modulated
continuous-wave (FMCW) radar, phased array cir-
cuit and system, and wireless transceiver design.
Jianxi Wu received the B.S. degree in micro-
electronics from Nankai University, Tianjin, China,
in 2016, and the M.S. degree from the Institute
of Microelectronics, Tsinghua University, Beijing,
China, in 2019.
His current research interest is the circuit and
system design of transceiver for radar applications.
Wei Zheng received the B.S. and M.S. degrees from
the Harbin Institute of Technology, Harbin, China,
in 2006 and 2008, respectively.
He is currently with Radarchip Technology Com-
pany, Ltd., Beijing, China. His research interest is
the circuit and system design of frequency synthe-
sizer design for wireless transceivers.
Authorized licensed use limited to: KINGS COLLEGE LONDON. Downloaded on June 21,2022 at 05:33:45 UTC from IEEE Xplore. Restrictions apply.
IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 55, NO. 2, FEBRUARY 2020
Shufu Wang received the B.S. degree from the
North China University of Technology, Beijing,
China, in 1995, the M.S. degree from the Harbin
Institute of Technology, Harbin, China, in 1997, and
the Ph.D. degree from Harbin Engineering Univer-
sity, Harbin, in 2001.
He is currently with Radarchip Technology Com-
pany, Ltd., Beijing. His research interest includes the
wireless transceivers for millimeter-wave radars and
Internet of Things (IoT).
Nan Qi (M’13) received the B.S. degree from
the Beijing Institute of Technology, Beijing, China,
in 2005, and the M.S. and Ph.D. degrees in
microelectronics from Tsinghua University, Beijing,
in 2008 and 2013, respectively.
From 2013 to 2015, he was a Research Scholar
with the Department of Electrical Engineering and
Computer Science, Oregon State University, Cor-
vallis, OR, USA. From 2015 to 2017, he was a
Post-Doctoral Senior Circuit-Design Engineer with
the Hewlett-Packard Labs, Palo Alto, CA, USA.
In 2017, he joined the Institute of Semiconductors, Chinese Academy of
Sciences, Beijing, where he is currently a Full Professor of electronic circuits
and systems. His research interests include the design of integrated circuits
for high-speed wireline and wireless transceivers.
Yibo Liu received the B.S., M.S., and Ph.D. degrees
from Tianjin University, Tianjin, China, in 2012,
2014, and 2019, respectively. He is currently pur-
suing the Ph.D. degree with the Institute of Micro-
electronics, Tsinghua University, Beijing, China.
His research interests include CMOS millimeter-
wave and terahertz integrated circuits and transceiver
systems design for wireless communications.
Baoyong Chi (M’05–SM’18) received the B.S.
degree in microelectronics from Peking University,
Beijing, China, in 1998, and the Ph.D. degree from
Tsinghua University, Beijing, in 2003.
From 2006 to 2007, he was a Visiting Assistant
Professor with Stanford University, Stanford,
CA, USA. He is currently a Full Professor
and the Deputy Director with the Institute of
Microelectronics, Tsinghua University. He has
authored over 140 academic articles and two
books and holds more than 20 patents. His current
research interests include RF/millimeter-wave integrated circuit design,
analog integrated circuit design, and monolithic wireless transceiver chips
for radar and communication.
Dr. Chi has been a TPC Member of A-SSCC since 2005.