intel. ADVANCE INFORMATION 8XC196NT CHMOS MICROCONTROLLER WITH 1 MBYTE LINEAR ADDRESS SPACE 20 MHz Operation 1 Oscillator Fall Detection Circultry m High Performance CHMOS 16-BIt CPU ——m_High Speed Peripheral Transaction 1 Up to 32 Kbytes of On-Chip OTPROM Server (PTS) 1 Up to 1 Kbyte of On-chip Register RAM M70 Dadlcated 16-BIt High-Speed . Resistor Revie So sees RaM 10 High Speed Capture/Compare (EPA) register Architecture Duplex Synchronous Serial 1/0 m4 Channel/10-BIt A/D with Sample/Hold ™ port (ssi0y @ 37 Prioritized Interrupt Sources lm Two Flexible 16-Bit Timer/Counters m Up to Seven 6-Bit (86) 1/0 Ports @ Quadrature Counting inputs 1 Full Duplex Serial I/O Port fm Flexible 8-/16-Bit External Bus m Dedicated Baud Rate Generator {Programmable} ‘= Interprocessor Communication Slave @ Programmable Bus (HOLD/HLDA) Port © 1.4 us 16 x 16 Multiply 1 Selectable Sus Timing Modes for © 24 us 32/18 Divide Flexible External Memory Interfacing = 6ePine Device | Pins/Package | OTPROM na gede ‘eee vo | epa | ao BXCISBNT | 68P PLCC 32k 1K 512 1 Mbyta 56 10 4 | X= 7 OTPROM Device X= 0 ROMLESS The 8XC196NT 16-bit microcontroller is @ high performance member of the MCS® 96 microcontroller family. ‘The @XC196NT is an enhanced BXC1S6KR device with 1 Mbyte of linear address space, 1000 byies of ragister RAM, 512 bytes of intemal RAM, 20 MHz operation and an optional 32 Kbytes of OTPROM. Intel's ‘CHMOS IIE process provides a high performance processor along with law power consumption. Ten high-speed capture/compare modules are provided. As capture modulas event times with 200 ne resolu- ‘tion can be recorded ard generate interrupts. As compare modules events such as toggling of a port pin, slarting an A/D conversion, pulse width modulation, and software timers can be generated. Events can be bbased on the timer or up/down counter.8XC196NT reno cota 2re26T=1 Figure 1. 8XC196NT Block Diagram PROCESS INFORMATION All thermal impedance data is approximate for static air conditions at 1W of power dissipation. Values will This device is manufactured on P629.5,.2 CHMOS change depending on operation conditions and ap- lI-E process. Additional process and retiability infor- plication. See the Intel Packaging Hanabaok (order ‘mation is available in Intel's Components Quality number 240800) for a description of Intel's thermal and Reltability Handbook, Order Number 210997. impedance test methodology. Table 1. Thermal Characteristics Package type | A PLCC 36.5°CW 1Fciw Ae Bx C 186NT cms wernt ram Heres op Serna bile 1) Fectge Tye options peitiweree Tamgarstary ond Buratn Oo fvtare 005700 ueet wi Wiha Seder wrae7-2 EXAMPLE: NB7C1G6NT is 68-Lead PLOG OTPROM. For complete package dimensional dala, refer ta the intel Packaging Handbook (Order Number 240800). Figure 2, The 8KC186NT Family Nomenciature8XC196NT intl ° BXC196NT Memory Map ‘Address (Note 7) Description FFFFFFH FFAQOOH External Memory FFOFFFH Internal OTPROM or External Memory (Determined by EA Pin) FF2090H oe at FF2080H FF207FH Mommony (internal OTPROM or External Memory) FF2000H {Determned oy EXP) ree External Memory FEpsoon {Internal FAM (identically Mapped into 00400H-O0SFFH} FFO3FFH FFO100H ‘External Memory FFOOFFH Fronoont Reserved fer ICE Beta External Memory for future devices Sonos 964 Kbytes External Memory corre Internal OTPROM or External Memory (Note 1) '00207FH Reserved Memory (Internal GTPROM or External Memory) 002000H (Notes 1, 3, and 6) ‘001FFFH 5 . SOIEEOLE Memory Mapped Special Function Registers (SFR's) oreo Internal Special Function Registers (SFR's) (Note 5) eoosers Extemal Memory (QO0SFFH Interna! RAM 000400H (Address with Indirect or Indexed Modes) ‘S003FFH Upper Register File (Addeass with Indirect or Roogistor FAM soo100r Indexed Modes.or through Windows.) (Note 2) ‘0000FFH Lower Register File 000018H Flogiater RAM (Addross with Direct, Indiract, or Indexed ooooats CPU SFR's Modes.) (Notes 2, 4) NOTES: 1, Thes6 areas are mapped internal OTPROM if the REMAP bit (CCB22) is set and EA ~ SV. Otherwise they are extarnal memory. 2. Code executed in locations 00G00H to COSFFH will be forced extarnal. 8. Reserved memary locations must contain OF FH unless noted. 4, Reserved SFR bt location must be writen wath O, 5. Roter to 8XC1S6NT User's Guide and Quick Rateranes for SFR doseriptions.. 6. WARNING: The contents or functions of reserved mamory locations may change with tuiure revisions of the device. Therefore, a program that relies on one or more of thesé:locations may not function proparty 7. Tha 8XC196NT intorally uses 24 bit address, but only 20 address lines are bended out allowing 1 Mbyte extemal eddress space.‘ : : eysmoTH/Ps.7 Cf arefers ava/er2 12 arrece.s 93 ave/er.o 14 a5 P47 AS ap14/r4.6} 16 013/045) 17 soi2/eaa Ch 16 apni Pa SON9 so1w/ea.2}20 anaes, i}21 ape /P4.0 22 sup7/a07/°3.70]23 SuPb/a08 /#3.60] 24 SuPs/a0s/P3.50 25 supa fan 73.4 26 sup3/403/P3.3} 3.5 /SR ARH sip2/402/03.2 3 g 8 b ake, : BSE ao a e gee 5, 8h 8bs asferse Jeiveegs 32-1 68 67 6 65 64 BS 62 61, 68 PIN PLCC NB7C196NT TOP VIEW Lecktng Down on Component Side ‘of PC Bore 32.55 34.35 36 37 58 5940 4142 48 “8 tre gs 8XCT96NT birs.2/1101K 1 /PMO0E.3/40N7 0.6/PMODE.2/ACHE 45 apo.s/ewove.1/xcHs 0.4 /FUODE.O/RCHA. ree? 8 Figure 3, 68-Pin PLCC Package Diagram@XC196NT intel. PIN DESCRIPTIONS ‘Symbol Name and Function Voc Main supply voltage (+ 5V). Ves. Ves. ¥ss1 | Digital circuit ground (OV). There are multiple Vgg pins, all of which MUST be connected. Vrer Reference for the A/D corivarter (+ §V). Vner Is also the supply voltage to the analog portion of the A/D converter and the logic used to read Port 0, Must be: connected for A/D and Port 0 to function. Vee Programming voltage for the OTPFIOM parts. It shoud be + 12.S¥ for programming. {tis also the timing pin for the return from powerdown circuit. Conniact to Voc it powerdown not being used, ANGND Reference ground for the A/D converter. Must be held al nominally the same potential as Ves. XTAL Input of the oscillator inverter and the intemal clock generator. XTAL2 Output ot the oscillator inverter. «| P2.P/CLKOUT Output of the internal clock generator. The frequency is ¥¢ the oscillator frequency. thas @ 50% duty cycle. Also LSIO pin, RESET Reset input to and open-drain output from the chip. RESET has an internal pullup. PS.7/BUSWIDTH | Input for bus width selection. If CCA bit 1 is a one and CCR bit 2 is a.ane, this pin dyamically controls the Buswidth of the bus cycle in progress. If BUSWIDTH is low, an 8-bit cycle occurs, if BUSWIDTH is high, & 16-bit cycle occurs. ff CCR bit 1 i8" and CCR1 bit 2is '"1”. all bus cycles are B-bit, if GOR bit 1 is "1" and CCRT bit 2 is: “9”, all bus cycles are 16-bit. CCR bit 1 = “0” and CCRI bit 2 = "0" is illegal, Also an LSIO pin when not used as BUSWIDTH. NM ‘A positive transition causes a non maskable intertupt vector through memory location 208EH. ‘Output high during an external memory read indicates the read is an instrustion fetch, INST is valid throughout the bus cycle. INST is active only during external ‘memory fetches, during intemal OTPROM fatches INST is held low. Also LSI when not INST. SLPCS is the Slave Port Chip Selact. ER Input for memory select (External Access). EA equal to a high causes memory accesses to locations OFF 2000H through OFF 9FFFH to be directed to on-chip OTPROM. EA equal to a low causes accesses to these locations tobe directed to off-chip memory, EA = + 12.5V causes execution to begin in the Programming Mode. EA is latched at reset. Bus Hold Input requesting contro! of the bus. Bus Hold acknowledge output indicating ralease of the: bus Bus Request output activaled when the bus controller has a pending external memory cycle, ‘Address Latch Enable or Address Valid output, as selected by CCA. Both pin options provide a latch to demuitiplex the address from the address/data bus. When the pin.is ADV, it goes inactive (high) atthe end of the bus cycle. ADV can be used a8 @ chip select for external memory. ALE/ADV is active only during external mamary accesses, Also LSIO when not used as ALE. SLPADDA is the Stave Port Address Gontral Input and SLPALE is the Slave Port Address Latch Enable Input. Read signal output to extemal memory. RD is active only during extemal memory roads oF LSIO when not usod as AD) ScPRD a ra Slave Port load Contr Input PS.1/INST/SLPCS: PS.0/ALE/ADW/ SLPADDR/ ‘SLPALE Ps.3/AD/SLPRDintel. exc196NT PIN DESCRIPTIONS (Continued) ‘Symbol ‘Name and Function 5.2/W0R/WRL/SEP WR ‘Write and Writ Low output to extemal memory, as selected by the COR, WAL val gow everett we, wile WAL wil gow on fe exter ‘ites where an even bytes being writen. WA/ WAL i active curing exornal ‘memory wites. Also an LSIO pin when not used as W/ WA. isthe Slave Por Write Contra Input 5 5/BRE/WAR ‘Byte High Enable or Wito High output, as selected by the COR. BHE 0 selects the bank of memory thas connocted othe high bye of the data bus, ‘AO 0 selecs that bank of memory thats connected tothe lw byte. Thus | aaccessas toa 16-bit wide memory an be tothe low byte only (AD 0, | BBHE = 1, tothe high byte only (AO ~ 1, BHE ~0) or both bytes (AO=0, BHE =0). ifthe WAH function is solecio, the pin wil go iow i to bus cyto fe writing to an odd memory locaton. BHE/WRH is only valid dung 16-bit {external momory read/ wit cycles. Also an LSIO pin when not SHE/WRE, PS.6/READY Ready input o lengthen external memory cycles, or interfacing with slow oF 6 nat Cs in Capacitance (Any pinto Vs) 10 | oF | tea = tOMHe Fwy | Weak Putup Resistance 150% a | (otwe) Fast | Reset Puiu 65K vox [a ores: ‘VAIBO @iecton pe cat NST ard CLKOUT. NST and LKOUT wr exclu ho ot apg wo Big cout aD irc Pr, Pon, ot Pot Soro, sd EDOM encot SPUN 4) 2 Standard input prs cue XTAL1, ER, RESET, and Pot 1/2/5/6 and EPORT whan sein as inputs. 5. Allbdrecona/0 pine when conte as Outputs (Push Pull, 6 Types 17. Velating abe speccaons in reel may cause the device to ener est modes (P54 and P26). 8.780 ~ To Be Determined 8. Pulp peta ring ret rom powerdown corto, 10: Whon 0 suse at analog puts, reer 0 4/0 spoceatons. 100% lal is 101, 11, Forteneratres| ADVANCE INFORMATI 4273 482b175 0144893 40798XC196NT intel. ‘8XC196NT ADDITIONAL BUS TIMING MODES: ‘The 8XCI96NT dovico has 3 additional bus timing ‘modes for external memory interfacing. MODE : Mode 3is the standard tining mode. Use this mode for systems that emulate the EXCT96KR. bus tim- ings. MODE 0: Made 0 i the standard ting made, but 1 (mint ‘mum walt stat is always Ingerted in external bus oycies. wove} mm LI MODE 1: Mode 1 is the long R/W mode. This mode advances RD and WR signals by 1 Tose creating a 2 Tose FRO/WH low time. ALE Is also advanced by 0. Tose but ALE high tino remains 1 Tosc: MODE 2: Mode 2 isthe long F/W mode with Early Addross. ‘Med 2 i simia” to Mode 1 with respect AO, WR ‘and ALE signals. Additonaly, the address is output (nthe bus 0.5 Toso eater in the bus cycle. woot (13) wove} wove vwooe (3 Seo} wane) Figure 4 Detaled MODE 1,2, 8, Comparieon 42m 4g2bh75 Ob44ad2 543 ADVANCE INFORMATIONintel : axc196NT EXPLANATION F Ac syMB018 Condtone: signi Each symbol is two pais of letters profxed by “T” ft pape ee Silat Swedee aa Sew elem Tim, CBRE LAlevaby Ses cos teria eee eee 5a SEB came goer, Srmbos weet SNS tonger GNLNOUT ROSSB Wan Santa A REV zing SBeomen Sova eas” Oe BUS MODE 0 and 3—AC CHARACTERISTICS (Over Specified Operating Conditions) Test Conditions: Capacitance Load on All Pins = 100 pF, Riso and Fall Times = 10 ns, ‘The system must moot these specications to work with the AXCG19NT. Symbol __ Parameter Min Max Units Taw | Ades Vat to Ready Soup 2Tosc —75 | _rat) Tern Non READY Time Ne Upper Lit 8 Tews READY Hod aftr GLKOUT Low ° Toso ~ 30 st) Tavoy | Address Vat to BUSWIDTH Setup 295075 | _val-8 Tuc | _ALE Low to BUSWIDTH Setup [Tos = 60 [nate Tevax | _BUSWIOTHHoldater CLKOUTLow | 0 ne rn ‘Tose —55_| re Tauov | _ RD actvo to input Data Vas Tose ~ 30 a) Toy | CLKOUT owt Input Data Vaid Toso — 60 ry Tawoz | _End ot AB to input Data Foat Tose ns Truox | _DataHold ater AB High ° ne ores TeitMax is exceade, adtiona wa sats wil ore 2 Mtwat stsas ar use, a2 Tose n, where n= numberof wa sates. 8. mode Of selected, one wa site intr s ways added etal wa sals are rogue, add 2 Tos tothe spodteaton ADVANGE INFORMATIOL 4275 4826175 0144893 YET8XC196NT intel. BUS MODE 0 and 3—AC CHARACTERISTICS (Over Spociied Operating Conditions) Test Conditons: Capacitance Load on All Pins = 100 pF, Rise and Fall Times = 10 ns. ‘Tho 8XC186NT wit meet these specications ‘Symbot Parameter Min Max ‘nite Fiera Frequency on XTALY 40 2 (wa) Tose ZXTALI Period (1/FxtaL) 0 260 8 Taro | _XTAL1 High to CLKOUT High or Low +20 110 ne Toro ‘Glock Falure to Rosot Pulled Lowi) 4 0 Hs Toxcu__| _CLKOUT Period 2 Tose 18 Toc. | _CLKOUT High Period Tose 10 | Tosc +30 6 Toun | _CLXOUT Low to ALE/ABV High =10 +15) 8 Tics | _ALE/ADV tow to CLKOUT High =25 +18 8 Tuan AALE/ADV Cyete Time Tose nai) To ALE/ABV High Time Tosc-10 | Toso + 10 8 Taw | Address Valid to ALE Low Tose — 15 18 Tux ‘Address Hold Alte ALE/ABV Low Tose = 40 6 Tune AALE/ABV Low to FD Low | Tosc= 40 | ns Truc. FD Low to CLKOUT Low = +36 ne Tauan | RD Low Period Tose si) Tamu | AD High to ALE/AB High Tose Tose + 25 | na) Tria __| PB Low to Address Float __ +5 ne Tue | _ALE/ABV Low to WF Low Tose — 10 re Tou | _CLKOUT Low to WR Low =10 +25 8 Town | _Data Vaid botore WF High Tose = 23 rs Tonwn | _CLKOUT High to WR High 10 315 re Twowt | WA Low Period Tose 30 rst Twix | Data Hols after WA High Tose — 35. re Twain | _WAHigh to ALE/ADV High Tosc—10 | Tose +16 | ns@ Twuex | _ BRE, INST Hold ater WR High Tose 10 re Twrax | _AD8-15 Hold ater WF High Toso — 30 att) Tanex | _ BHE, INST Hold ater RO High Tose — 10 a Trax | _ADE—15 Hold ater FD High Tos — 30 nat) notes: ‘Tretng pelrmes at 0 MHz owovr, the dovic Is sac by design and wil tyicay operate below 1 Hr 2 Typ apectleatons, not qurartod. 4: Ateuming backosback bus cycles fob na om. 5: wat laser usd, a9 2 Tose X 0, whore n ~ ruber of wa sats. todo 0 (Y automatic wal stata ado) ‘operations oelectd, add 2 Toate specication «Yona ne tne for he aria" fal detect cel (OFD) to reac to a clock falure. The OF cc enabld by ‘Bgrammng ne UPROM locaton 076 wih he value 0004H.NT/NO customer GROM codes rad to equate location ‘ote to te value OCOEH sth onctatr fal tect (OFD)functon a deared il manufacturing ses oeabon 2018H {St ag 1 term wheter ov tf program he Sock Datect Enabe (COE) bt. Programming the COE Bt ‘rable ecletor al detecton. 4276 426175 OLY4ES4 326 ADVANCE INFORMATIONintel. axC196NT BUS MODE 0 and 3—8XC196NT SYSTEM BUS TIMING ‘Lockout ALE/ADW BUS READ ae, st —X en x a ‘tt mode 0 eperaton slated, ad 2 Tose tts tne ADVANCE INFORMATION aon MM 4826175 GL44855 252 Ml‘8XC196NT MODE 0 and 3—READY TIMINGS (ONE WAIT STATE) uncut “+t ee ae al ae =| om zs aE i sus atxo “)X__sor >) C== avs wee YX aX 7 ‘1 mode 0 selected, one walt stata is always edd additonal wat stats are roqured, add 2 Tosc these specie MODE 0 and 3—8XC196NT BUSWIDTH TIMINGS Fem venom —e a a (i Ca ‘tt mode 0 selected, edd 2 Togc to these specications 4270 ADVANCE INFORMATION ME 4826175 0144896 199intel. sxcreonr BUS MODE 1—AC CHARACTERISTICS (Over Spectiod Operating Conditions) ‘Test Conditions: Capacitance Load on All Pins = 100 pF, Riso and Fall Times = 10 ns ‘The system must meet these specications to work with the BXC196NT. [-_Symbot Parameter min Max Unit Taw ‘Address Valid to Ready Setup 2 Tose — 75 re Tw Non READY Time ‘No Upper Limit 8 Tox EADY Hold ater CLKOUT Low ° Tose ~ 90 a) Twav, ‘Adress Vali to BUSWIDTH Setup 2Tose 75 8 Tuev ‘ALE Low to BUSWIDTH Sot 15Tosc — 60 o Tousx ‘BUSWIDTH Hold after CLKOUT Low 2 6 Tavow ‘Adress Val to Input Data Vaid 3 Tose — 60 nel Truov "RD active 1 input Data Valid 2 Tose — #4 nat Tow (LKOUT Low to Input Data Vaid Tose ~ 60 oa Trvioz End of 5 to Input Data Float Tose 8 Taiox. ° 8 notes: i Mig exceode,asstona wal stats wil occ 2. wat stale ae std, add 2 Togo % hwhare n= mumbo of wat sttos ADVANCE INFORMATION 8 4eeb47S 0144897 O2S8XC196NT intel. BUS MODE 1—AC CHARACTERISTICS (Over Specited Operating Conditons) ‘Test Conditions: Capacttance Load on All Pins = 100 pF, Rise and Fall Times ~ 10 ns. ‘The BXC19ENT wit meet these specications Symbol Parameter min Max Unite Fira | Frequency on XTALY ao | Mia Toso | _XTALI Peto (1/Fra) 50 125 im Tino | _XTALT High to OLKOUT High or Low +20 = 8 Tous. | CLKOUT Period 2Tose 8 Toner |_CLKOUT High Period Tose 10 | Toso + 7 8 Toa | CLKOUTHIGH to ALE/ADW High | 05 Toss 18 | 05Toso +15 | ne Tout | GLKOUT LOW te ALE/ADV Low O5Tosc 25 | 05Toso +15 | ns Tuan | ALE/ADY Oyelo Time - ‘Tose ns) [ALE/ADV High Tie z Toso 20__| Toso + 10 8 ‘Atress Vai to ALE Low 05 Toso = 20 8 ‘Address Hold Ator ALE/ADVLow | 05 Tose ~ 25 8 [ALE/ADV Low to RD Low 5 Toso — 15 78 THD Low to GLKOUT Low Toso- 10 | Toso +30_| ne FO Low Pec 2Tosc ~ 20 rst) RO High to ALE/IDV High "05 7osc | O8Tosc +26 | ne) FRO Low to Adevoas Float ‘5 78 [ALE/ADV Low to WR Low 05 Toso 10 8 CLKOUT Low to WAL Low Toso= 16 | Toso | re Data Val before WF High Bose = 23 ne ‘CLKOUT High to WA High =10 +15 3 WF Low Paria 2 Tose — 15 - rf) Cia Hold ater WF Fgh “Trostoso = 12 5 (WA High to ALE/ADV High 05Tosc~10 | 05Tosc +15 | ns Twnax | SHE Hold atter WA High Toss ~ 15 1s TTwwax | _INST Hold ater WA High 05 Tose - 18 Te | ADE—15 Hold after WH High 05 Tose = 20 rs Tavgx | _BHE Hols ater FO High Toso - 82 8 Tx | INST Hol aftr FO High 05 Tose — 32 Triax | _AD8=15 Hol after FD High 05 Tose ~ 30 ro Notes: {Testing pated at 8.0 MH, however, the doves tac by design and wit yplcaly operate below Ha 2. Typical spocteatons, not quran, 5. Ascurng backosack bu cys 4 ett us ony 5: twat tte se wed, a2 Tose >, where n ~ rub of wat states. 4.200 ADVANCE INFORMATION 4B2bL75 OL44898 ThEintel. exct96nT MODE 1—8XC196NT SYSTEM BUS TIMING Tose XTALY cLockouT ALE/RDV wD betanu-t BUS READ »)) pe tory fe ts aus weere oxo Tw Tos, frete Tomax Tenax ADB - A015, -_— Tera vam eareswoe —_—{_ ADVANCE INFORMATION 281 4 mm 4826175 0244899 973 axcteont intel. MODE 1—8XC196NT READY TIMINGS (ONE WAIT STATE) mat cuxour ws nexo Xe) == SD us wane Cae Xe > MODE 1—8XC196NT BUSWIDTH TIMINGS even Jf 7>?_ 7s at fF wy bp suston =X) be ter —_] aus wie Came Xe) oe 4-282 ADVANCE INFORMATION Mm 4826375 OL44900 447 aintel : #xc196NT BUS MODE 2—AC CHARACTERISTICS (Over Spected Operating Conditions) Test Conditons: Capacitance Load on All Pins = 100 pF, Rise and Fall Times = 10 ns ‘The system must mest these specications to work with the BXC196NT. Symbol Parameter Min ‘Max ] Taw "Across Vaid to Ready Setup 25 Toso — 78 Twa Non READY Time ‘No Upper Limit ns Torx READY Hold after GLKOUT Low ° Tose — 30 att Tava ‘Address Vali to BUSWIDTH Setup 25 Toso ~ 75 3 Tusv [ALE Low to SUSWIOTH Setup 15 Tosc — 60 re Toox 'BUSWIDTH Hold after CLKOUT Low © re Taw, ‘Addie Valid to Input Data Val 38 Tosc 55 | _ne®) Taov [RD activ to input Data Valid 2Tosc — 44 net Tov ‘CLKOUT Low to Input Data Valid Toso — 60 ts TrHo2 End of AD to Input Data Float [05 Tose 8 Trwox. Data Hold ater FD High ° oa NOTES: Tei xs excoode,asetiona wa stats wl occu 2. wat sates ae ots, a2 Togo > hw were n= sun of wal states, : 4.203 ADVANCE INFORMATION 4@2b175 0144901 3668XC196NT BUS MODE 2—AC CHARACTERISTICS (Over Specified Operating Conditions) ‘Test Conditions: Capacitance Load on All Pins = 100 pF, Riso and Fall Times ~ 10 ns. ‘The 8XC1SENT will meet these specications ‘Symbat Parameter win Max Unita ["Fitar | Frequency on XTALY 80 20 Ma) Toso | XTAL! Period (Fra 0 25 8 Trion | XTALI Hight CLKOUT Highor Low +20 85 1 Tower | GLKOUT Period Bose 8 Touc. | GLKOUT High Period Tose — 10 Tose + 27 ns Town | CLXOUTHIGH te ALE/AGVHigh | O5Tosc- 15 | OSTosc +15 | ne Tout | GLKOUTLOWWWALE/ADViow | 05Tosc—25 | 05 Tosc +15 | ne Tuan | _ALE/ADV Oyete Time ‘Tose ae Tun. | ALE/ADW High Tne Tose 20 | Tosc+ 10 | ne Tani | Adress Vad to ALE Low Toso 15 8 Tuax | Addess Hols Aer ALE/ABV Low | 0.5 Tose 20 ns Tum. | _ALE/ABV Low to RD Low 25 Tose = 18 1 Truc | FD Low o GLKOUT Low Toso- 10 | Tose +90_| ne Trunn —| FD Low Pero 2 Tose ~ 20 90 Tenn | FD High to ALEVADV igh 05 Toso - 5 | O5Tose + 25 | ns) Tauaz | FB Low to Across Float +5 18 Tum, | ALE/ADV Low to WA Low 08 Tose — 10 ne Team | CLKOUT Low to WR Low Tose = 22 18 Town | Data Vali botor WF Hah Bose = 25 ne Tex | GLKOUT High o WR High =10 ne Twuwn | WF Low Period 2Tosc ~ 20 ns) Twiax | Data Hots ator High 05 Toso — 12 ns Twat | _WAHigh to ALE/ADV High 05 Tosc +10 | _na@ Twix | BRE Hols after WF High a Twix | INST Hold ater WA High Twanx | ADB-15 Hod ater WA High 05 Tose ~ 90 ~ ns TTavex | BRE Hoi ater A High Tose 18 Tx | INST Hold after FD High 5 Tose - 2 Trax | ADE- 15 Hold ater FD High 05 Tose ~ 90 ne) noves: 1 Tering pedomad a 8.0 Mie however, he dv sac by design and wl pial operat below 1 He. 4. loon bce tsbaik tue oye terme 5. wal ea uted, add 2 Tos xm where ~ be of watts 204 ADVANCE INFORMATION 4826175 OLY4ADe 212intel. sxcioent MODE 2—8XC196NT SYSTEM BUS TIMING XTALY ‘cLocKouT ALE/ADW =D BUS READ eee sus wate, Xmen Xen Tos Yo ‘BHE X ‘SE VALID x Eee Tete Tote wos-aois, — Xm XK re ADVANCE INFORMATION MB 4626375 0144903 159 a 205sxcreent intel. MODE 2—8XC196NT READY TIMINGS (ONE WAIT STATE) cxoor_f ws were Xess aX eee x MODE 2—8XC196NT BUSWIDTH TIMINGS eee eee i ea te fous wane Se a a ))), “8° wm yg2b375 O14N904 055 Ml AVANCE [UFORGIATION 9intel 7 eXC196NT BUS MODE 0, 1, 2, and 3—HOLD/ALDA TIMINGS (Over Spectted Operation Consitons) “Test Conditions: Capacitance Load on All Pine = 100 pF, Rise and Fall Times = 10 ns. (F symbor Parameter win Max | __Unite THvox FOLD Setup Time +65 st) Tou. | _CLKOUT Low to UDA Low = | +15 1 Tousat__| _CLKOUT Low to BREG Low = | +18 ns Tuaiaz__| HODALLow to Address Float +25 ns Tuaisz | FCDA Low to BFE, INST, FD, WA Weakly Driven +25 ne Touran | CLKOUT Low to RLDA High =| +18 18 Tousrn | CLKOUT Low to BREG High =25 | +25 ns Tuwnax | ICDA High to Address No Longer Float =15 ns Twansv | ACOA High to BRE, INST, RD, WA Vali =10 ns Nore: {To quararoo recognition at pet clock 8XC196NT HOLD/ALDA TIMINGS 700 SE sad \— BE, Nst, ——————* = = 7 Se Lz ac J\ east yon INFORMATION ye2bi75 OL44sOS Tel mm “77exci9eNt intel. AC CHARACTERISTICS—SLAVE PORT SLAVE PORT WAVEFORM—~(SLP » a7— er =D — ‘SLAVE PORT TIMING—{(SLPL. ‘Symbol Parameter win Max Unite Teavwn. ‘Ads Vali to WR Low 50) a Tennav [RD High to Adcross Vala 60 ns Torun RD Low Period Tose ns Town Whi Low Period Tose ns Tsauov [AD Low to Output Data Vaid % 18 Tsovwne Input Data Setup to WR High 2 6 Tewnox WR High to Data inva 30 ne Tsei0z RD High to Data Float 16 ns Fiso/Fat Tine = 10 ns. Capactive Pin Load = 100 pF. sed upon theese! estates and/or brah tots 2. Specicatons above are advanced Ifmaton an are subject fo change, te 4B2bb75 OLY4IOb bb ADVANCE INFORMATIONintel. 8xC196NT AC CHARACTERISTICS—SLAVE PORT (Continued) SLAVE PORT WAVEFORM{SLPL = 1) SLAVE PORT TIMING{SLPL = 1) Symmbot Parameter Min Unite Tee GS lowio ALE Low 20 8 Teme HD or WR High to OS High 6 anal) Toure ‘ALE Low to RD Low Tose ne Toru ‘RO Low Poriod Tose 8 Tswuwm | _WALow Period Tose ne Tea ‘Address Val to ALE Low 20 ns Touax [ALE Low to Address invalid 20 ns Ter Low to Output Data Vai I ns Tsowwit Input Oata Setup to WA High 2 ns Tswacx [WR High to Data invalid 20 ne [Tsano ‘AD High to Data Float 5 ns noes: {Test Condtons: Fog = 20 Mts, Toso = $0 8. Rise /Fall Time 10:8. Capac Pin Load = 100 pF. 2 These values are no tsted in ped, andar based upon thao estas as abeatory eet, 5 Specitontone above are advancadifmaton and aro subject fo change. 4209 ADVANCE INFORMATION 4826375 OL44902 aryexcieent intel. EXTERNAL CLOCK DRIVE ‘Symbo! Parameter Min ‘Max Unite VT, Oscilator Frequency 4 2 Me Teo Oscilator Period (Toso) Ey 250 8 Ton High Time (0.35 * Tose 0.85 Tose. 8 Tax Low Time (038 x Tose 0.85 Toso. a Te Riso Time 10 8 Those. Fall Time 10 im EXTERNAL CLOCK DRIVE WAVEFORMS sera comsrennros nay wurrown vo OEE one 5 eae cirevermenmametly| | iitammeatns neti sumerrenanenic| | Ramee area 4200 ADVANCE INFORMATION 4826175 0144908 730 |intel. WAVEFORM—SERIAL PORT—SHIFT REGISTER MODE eXC196NT SERIAL PORT WAVEFORMSHIFT REGISTER MODE (MODE 0) Twav bee}! fete = Py oat SKK KX EK KEK EK KK AC CHARACTERISTICS—SERIAL PORT-SHIFT REGISTER MODE ‘SERIAL PORT TIMING—SHIFT REGISTER MODE (MODE 0) Test Conditions: Ta = —40°C 0 + 125°C: Voc = SOV #10%%; Vs = 0.0V; Load Capacitance — oF ‘Symbol Parameter Min Max _ [Units Fixxa( | Serial Por lock Period (BAA = 8002H) Receive Only Tose 18 Fx.xe | Serial Port Cock Falling Edge to Rising Edge (BRA = 6002H)| «Toso — 50 |4Tosc + 80) ns rx. | Serial Port Clock Period (BAR = 8001H) Transmit Ory Tose ne FFa.an | SerialPort Cock Faling Edge to ising Edge (BRR = 8001H)| 2 Tosc ~ 50 |2 Toso + 50| ns Frovxn | Output Data Setup to Glock Fising Edge 3 Tose 18 MTiviax | Output Data Hod attr Clock Rising Foye 2 Toso — 60 ns Tevov |Next Output Data Vai after Clock Rising Edge 2 Tose + 60| ns Tovar _|Input Data Setup to lock Rising Edge Tose * 200 8 "ox | nput Data Hold after Clock ising Edge ° ne FTxno2t |Last Clock Rising to Output Float ‘STose_| ne Nove: {Parameters nt test. £2 The meenam baud fete register val for Receive is €002H, The minum bau ae register value for Tanaris 00H ADVANGE INFORMATION 4-291sxoteont intel. ‘A to D CHARACTERISTICS ‘The A/D converter is ratiometic, so absolute accuracy is dependant on the accuracy and stabty of Vrer: 10-BIT MODE A/D OPERATING CONDITIONS. ‘Symbol Description Min Max Unite Ta ‘Ambient Temperature ° +70 *c Yoo Digital Supply Volage 450 550 v Vac “Analog Supply Voltage 450 550 0) Tsaw ‘Samplo Time 10. as Toon (Conversion Tino 10 5 st) Fose (Osciator Frequency 40 2 MH Noes: 1 Ver must be within OV of Veo 2. The vue of AD_TIME i saleiod 1 moet these specications. 10-BIT MODE A/D CHARACTERISTICS (Using Above Operating Conditions)'® arameter Te Min Max Unites Resolution ie ad y ‘Absolute Evor 0 230 isBe Ful Seal Eror 0.25 208 LSBs Zoro Otset Error 0.25 405 S88 Now Linearity 10 #20 30 LSBs Diforontial Nov-Lineariy ~075 +075 LSBs ‘Chanaet-o-Channol Matching #01 ° 210 sas Repeatability £025 ° isBsi¥ “Temperature Costicents: Offset 0.008 Lsavct Full Scale 0.009 Lusso Diterential Non-Lineaiy 0.009, ee) Offisolation =o 5029) Feedthrough =e BA ‘Voc Power Supply Rejection =60 8002) Input Resistance 750 12k aa DC input Leakage 10 ° £30 HA Vottage an Analog Input Pin ANGNO—05 | Vacr +05 ve, “Samping Capacitor 30. PF "An “USB as used her ha a value of approxatly 5 av. nores: 1 These values are expected for most pats a 28°C, bat ae not tested or gutrantoed 2 DC to 100 Ke 3 Motipleser broek elore-rake is qurarioes 4 Resstarce fom doves pn ough internal MUX. to srl capac. 5. Applying votages beyond these spoctcatons wil derade the sceracy of aber chanals being converted. 8 Alconversonspetoomed mah proceesorin DLE mee, sa | ° 4826175 0144910 399 aintel. sxcisor &-BIT MODE A/D OPERATING CONDITIONS ‘Symbol Description Min Max Unite Tr “Ambient Temperature 0 +70 “c Voc Digital Supply Voltage 459 5.60 v Vaer ‘Analog Supply Voltage 450 5.50, 0) Team ‘Sample Time 40 nal) Toow (Conversion Time i 20 ust) Fosc ‘Oscitator Frequency 40 20 MHz Nores: “1 Ver must be within 0.5 of Voc 2. The vais of AD__TME i eosin to moet these specications. 8:BIT MODE A/D CHARACTERISTICS (Using Above Operating Conditions©) Parameter Tye) Min Max units" Resolution Ti aoe raat ‘Absolute Eror oe 210 S68 Full Scalo Error £05) LSBs Zoro Offset Error Uses Non-Lingarity ° 210. LSBs Diforortal Nor-Linearty =05) +05 LSBs ‘Channel-to-Channel Mateting ° 10) LSBs Repeatabiity £0.25 ° 1sBstt) “Temperature Coefficients: Offset 0.003 Ls8/ot Full Sale 0.003 tss/cw Difforontal Non-Linearity 0.003 ts8/ct) (Off lsolaton = 60) aia) Feedthrough =60 att) ‘Voc Power Supply Rejection 60 8012) Input Resistance 750 42K 0) (DC Input Leakage £10 ° #30 BA ‘Yoltage on Analog Input Pin ANGND—05 | Vrcr +05 ve ‘Sampling Capacitor 30 PF An "LSB" a uted ore ha & veloe of approximately § ow. NoTes: {These vas ae expected for most pars at 25°, but are not 2:06 100 Khe 5. Muitpowb broak-olore:maks is quarartoos, ‘4 Resetanee fom doves pn ough tral MUX, to sample capaci 5: Roping volage beyond nese speiscton wl dogeada fe acouacy of oer chemnts bang converted 6. Alconvorions petermod win processor TOLE mode ADVANCE INFORMATION 4826175 OL4N9)3 225 a8XxC196NT OTPROM SPECIFICATIONS ‘OPERATING CONDITIONS. ‘Symbol Description Min Mex | _Unite Ts “Ambient Temperature During Programming 20 0 “c Vos. ‘Supply Voltage During Programming 45 35 vo Vaer | _ Reference Supply Voltage During Programming 45 55 ve Vee Programming Voltage 1225 | 1275 | ve Ve EAPin Voltage 1225 | 1275 | ve Fose Oscilator Frequoney during Auto 60 80 Me _and Siave Mode Programming Fose ‘Oselator Frequency during 60 200 | WHE Fun-Time Programming ores: 1 Vor and Var shoud nominally boat he same voltage dng programing. 2. Vop and Ven must never excaed the maxim spectceio, athe deve tay bo damaged 8: og and ARCND shoud nomial be a ina sar potent OV. 4 Lead capactance ding Auto and Save Mode pograning ~ 150 oF ‘AC OTPROM PROGRAMMING CHARACTERISTICS (SLAVE MODE) Symbol | Parameter win Max Units Tam ‘Address Setup Time ° Toso Tux ‘Address Hold Tine 700 Tose Tove. Data Setup Time (oma Toso Tox Data Hold Time 400, 7 Toso Tu PALE Pulse With 50 Toso Tepe PROG Pulse with 50 Toso Tune. PALE High to PROG Low 220 Tose Tout PROG High tonast FALE Low | 220 Tose TPHOK Word Dump Hold Time 50 Toso Tow HOG High to next PROG Low 220 Tose TuHPL ‘PALE High to PROG Low 220, Tose Tey PROG Low to Word Dump Valid 50 Tosc Tea RESET High to First PALE Low 1100 Tose Teen. TFFIOG High to AINC Low ° Toso Tum TRING Pulse wiath 240 Tosa Tuva VER Hold after AING Low 50 Toss Tae. ZINC Low to PROG Low 170 Tose Town _| _ PROG High to PVER vali 220 Tose ores: {Furie programming is done wih Fosc = 60 MH 0 100 Mi. Vcc. Vpo, Vper ~ SV 05¥, To = 2510 £5C ena Vop = 125Y "0.50. Foc runcime programmeg ove ful operating ge, Sonat factory. 2h specication sor he word duo moae Fr programing pulses see Moded Guck Pulse Agosthm. 296 ADVE “ 4826175 O1449)2 1b) alintel bE exc196NT 0c OTPROM PROGRAMMING CHARACTERISTICS Symbol Parameter wwe [wax [Unt tee ‘Vos Prraneing Supply Curent 200 mA nore, Gamage OTPROM PROGRAMMING WAVEFORMS ‘SLAVE PROGRAMMING MODE DATA PROGRAM MODE WITH SINGLE PROGRAM PULSE Do hot apo} Ver unt Voc is sabe and wan epeccatons and the osclatar/clock has etabizad ox the device may be wm jot Tae ee an } —< rosearreomne Note: Peo must be high (1°) ‘SLAVE PROGRAMMING MODE IN WORD DUMP MODE WITH AUTO INCREMENT xe ve Nove: P30 rust below ('") eae -22 | Aomance sxronmarion: mm yg2b175 ovuusaa ors amt?8XC196NT ‘SLAVE PROGRAMMING MODE TIMING IN DATA PROGRAM MODE WITH REPEATED PROG PULSE ‘AND AUTO INCREMENT. == This data sheet (272267-004) applies to devices The following ao diteconces betwaen the 272267- ‘marked wih a"D" atthe end ofthe topside tracking ‘number. 8XC196NT Design Considerations 1. When operating in bus timing modes 1 or 2, the upper and lower acdress/data lines musi be latched. Even in &-bit bus made, the upper ad: ross lines must be latched. In modes 0 and 9, the upper address lines DO NOT NEED tb latched in S-bi bus wath moda, But in T6-bit bbuswicth modo the upper address lines neod to be latched, ‘8XC196NT ERRATA see Faxback +2344 1, ILLEGAL Opcade interrupt vocto. 2. Aborted Interrupt vector to lowost prio 8. PTS Request during interupt latency. DATA SHEET REVISION HISTORY “This datashect applies to devices marked wih @"O" atthe end of the topside racking number. The top- sido tracking number consists of nino charactors land the second line onthe top side ofthe device. Datasheets are changod as new device information becomes availabe. Very with your local Intl sales office that you have the latest version betore fa ing a design or ordering devices. (003 and 272067-004 datashects: 1. Changed all references of “OTPROM” 2. Added all the Slave Port pins to the package sagram and pin descriptions. 8, Added INTOUT pin to pin descriptions, 4, Changed ILit (input leakage current for Port 0) from #1 wAto 3 yA, 5. Romoved Tiuyy ftom AC characterises and wavatorm diagrams. Taos in Mode 0 and 3, changed from +4 ne min. toS ne mi, 7. Twisgx in Mode 0 and 3, changed trom Tose "50 min to Toso ~ 35 min 8. Clarfed the Roady waveform timings for Mode © and 3, by adding "+2 Togo" 8. Tuy in Made 1, changed rom Tose to Tose ~ 20 min, 410. Taya in Mode 1, changed from 0.5 Tose — 18 mma t0 05 Tos¢ ~ 20 min. 11, Tuuax in Mode 1, changed from 0.5 Toso ~ 20 min. 0.05 Tage ~ 25 min. 12, Tig in Modo 2, changed trom Tose to Toso ~ 20 min, 18. Taunt and Ty for the Serial Port timings. were changed fo rfloct the minimum bauarats {or recoWve and transmit modes. 14, Addod tha BXCIG6NT ERRATA section, "EPROM" to tomin, 10min 4206 AOVANCE 1nar ATION 42b475 OLYNSLH T3Y onal