Low-power Interface

12.2 Low-power clock control

The low-power clock control interface consists of the following signals:

• a signal from the peripheral indicating when its clocks can be enabled or disabled
• two handshake signals for the system clock controller to request exit or entry into
a low-power state.

The primary signal in the clock control interface is CACTIVE. The peripheral uses this
signal to indicate when it requires its clock to be enabled. The peripheral asserts
CACTIVE to indicate that it requires the clock, and the system clock controller must
enable the clock immediately. The peripheral deasserts CACTIVE to indicate that it
does not require the clock. The system clock controller can then determine whether to
enable or disable the peripheral clock.

A peripheral that can have its clock enabled or disabled at any time can drive
CACTIVE LOW permanently. A peripheral that must have its clock always enabled
must drive CACTIVE HIGH permanently.
This simple interface to the system clock controller is sufficient for some peripherals
with no power-down or power-up sequence.

For a more complex peripheral with a power-down or power-up sequence, entry into a
low-power state occurs only after a request from the system clock controller. The AXI
protocol provides a two-wire request/acknowledge handshake to support this request:

CSYSREQ To request that the peripheral enter a low-power state, the system clock
controller drives the CSYSREQ signal LOW. During normal operation,
CSYSREQ is HIGH.
CSYSACK The peripheral uses the CSYSACK signal to acknowledge both the
low-power state request and the exit from the low-power state.

Figure 12-1 shows the relationship between CSYSREQ and CSYSACK.

T1 T2 T3 T4

CSYSREQ

CSYSACK

Figure 12-1 CSYSREQ and CSYSACK handshake

ARM IHI 0022B Copyright © 2003, 2004 ARM Limited. All rights reserved. 12-3