Low-power Interface

12.2.4 Clock control sequence summary

Figure 12-4 shows the typical flow for entering and exiting a low-power state.

Normal
clocked
operation

System clock controller Low -pow er

drives CSYSREQ low to unclocked
request low -pow er entry operation

Peripheral or system
Peripheral denies or
clock controller initiates
accepts request
low -pow er exit
System clock
Deny A ccept Peripheral controller

System clock controller

Peripheral keeps Peripheral perf orms Peripheral drives
immediately enables
CACTIV E HIGH pow er-dow n CACTIV E HIGH
clocks

Peripheral drives System clock controller

Peripheral drives System clock controller
CSYSACK LOW to immediately enables
CACTIV E LOW drives CSYSREQ HIGH
acknow ledge request clocks

Peripheral drives
System clock controller System clock controller Peripheral drives
CSYSACK LOW to
samples CACTIV E drives CSYSREQ HIGH CACTIV E HIGH
acknow ledge request

Peripheral drives Peripheral drives

System clock controller System clock controller
CSYSACK HIGH to CSYSACK HIGH to
drives CSYSREQ HIGH samples CACTIV E
complete handshake complete handshake

Peripheral drives
System clock controller
CSYSACK HIGH to
disables clocks
complete handshake

Figure 12-4 Low-power clock control sequence

12-6 Copyright © 2003, 2004 ARM Limited. All rights reserved. ARM IHI 0022B