DFT Engineer Job Description

DFT engineer provides tool support to design team members implementing System-on-Chip
(SOC) designs (Synthesis, Static Timing, DFT, Place and Route tools).

DFT Engineer Duties & Responsibilities

To write an effective DFT engineer job description, begin by listing detailed duties,
responsibilities and expectations. We have included DFT engineer job description templates that
you can modify and use.

Sample responsibilities for this position include:

A. Design/verification for Clock/JTAG/Analog/DFT IP
B. Scan Insertion, ATPG, scan verification and pattern generation
C. Memory BIST insertion, validation and pattern generation
D. Analysis of Functional Design for Testability, including product functionality and access
through external connections, BIST and Board Level Diagnostics, control of significant
circuits, and isolation of functional blocks for testing
E. Create and maintain DFT timing constraints
F. SoC DFT architecture specification including test muxing and DfT RTL coding
G. IEEE1149.1 Boundary Scan design
H. Functional Pattern generation
I. Pattern debug on ATE
J. Design Verification for DFT

DFT Engineer Qualifications

Qualifications for a job description may include education, certification, and experience.
Education for DFT Engineer

Typically a job would require a certain level of education.

Employers hiring for the DFT engineer job most commonly would prefer for their future
employee to have a relevant degree such as Bachelor's and Master's Degree in Computer
Engineering, Computer Science, Electrical Engineering, Computer, Electronic Engineering,
Design, Engineering, Electronics, Communication, Architecture

Skills for DFT Engineer

Desired skills for DFT engineer include:
ATPG
Fault models
Fault simulation
On-chip scan compression
BIST
Synthesis
MBIST
DFT concepts
Equivalence check
JTAG
Desired experience for DFT engineer includes:
1. Expertise in DfT methodology like scan test, boundary-scan and test access mechanisms
2. Knowledge in RF/mixed-signal circuit design and test
3. Experience with pre-Si verification using SystemVerilog/OVM methodology gate level
simulations
4. Experience in gate level simulation
5. Must have a BS + 12 yrs Experience with the DFT integration of IP