50 MHz Digital Storage Oscilloscope PM3350/PM3352 Service Manual PHILIPSIMPORTANT: In correspondence concerning this instrument, please qunta the CYPE number and serfal timber ee given on the type plate. Note; The design of this instrument is subject to continuous develoment ind inprovenent, Consequently, this instrument may ineorporace 210° Changes in detail fram the informetion contained in this manval © ¥.¥, PHILIPS GLORILAMPENEABRIZKEN-EINDUOVEN-THE METHERLANDS~1987conrenrs Page SAFETY INSTRUCTIONS co ha tntrotvetion eseseesees 1a Selety precautions «+. Ls Cceotion and warning statenents s+ eer Ma Syabole seeceee us Tapaiced safety-protection ssssessecsesseeeneeeeneeeeees 12 Le General clauses sssesssersesseeees 2 cnanactEatstics a at Display « we 2d 22 Vertical deflection or Y anit csssssessesersesneesneses 29 aa Horizontal deflection or X arte. 2.9.1 Tia base evvevseeee 21312 xedeelection cress 2313 EXT depot vets ee 2 Triggering. : 2s Signal acquisition eves cog 2.6 Cannel A and Boe an 28 ee ae cee BD 210 enmeim aul calculation facilities .ee0s aur huto eeteiag ceevereeseees ceecseetsesesers 210 as cursors + preonrorce . a0 aaa Power supply « ce tl 2s Sundeiee ssseesessaeeeeeseseeeneenseten 222 26 Acnitiary inputs oF outputs. 27 Enviromental characteristics ... weer) 2.18 Sefecy 7 we msS. TWWTRONUCTION TO CIRCUIT DESCRIPTION AND BLOCK DIAGRAM DESCRIPTION 3-1 at Introduction to circuit description en Bull Ganeeal « ee ia 3IUL2 Exptanaeioa’Oi signal “bane setup 2 ean SIIL3 Location of electrical parte seeses se Daz 32 lock diagrams deseripeion « - as a.2.1 Introduction ere 353 3122 Attenuator unit’ Gonie" Ai) taa3 S123 Precenplefier unie and adaption nie (nie Az and Ai6)" 3-20, 31204 Tlnerbase nie (nit al) « pecs sua BINS erunie (amie A) eevee peers 58 Ryweretply woke poeerenoe stan Blair Plecy cizeates ana ead Alas 2 3128 ane civeuie (onic Al3) vesesvee tewerees 3023 31219 Signal processing ante Gande 13" and" Ai) WII 323) 3lallo Fofae and XA0AC eiveuite (onie ALS) veve-slsssscu seis 32h SIATI1 Méeroprocessor eysten Cooit Al2) «+ errr eeeraa sea rrexvaroR ONrT (a1) on oe Vertical attenvators cecneeees dal 42 External input cescsssesseesseesesseeeee seoneee Ae. PRE-AMPLIFTER UNIT (42) sat sa Vertical prevanplifice «2+. soesseesseeseensneee Sel se 1 trigger pre-mplitier eevee 52 3a eeecMflereel rors J XYL-AOLIFTER WET (43) ot oat Introduction vssesesseesees os 6.2 Pinal vereicsl (¥) amplifier ... rere C5 63 Final Norizoatal (X) anplifioe veveseeseseeereeese 1 64 Final blanking (2) aaplifiee and CRT esseeseeseessseeses 62 TIME-BASE OMET (44) rm ma Tigger amplifier ssessesssecssesssseeseeeseeseessssses Tob ne Tning eleeute .. ey Sweep generators csseeseeee 1 XDEFL amplifier and display nod 1s amplifier « 1 ‘ining diagram -10, (ERE CONTROL UNT (AS) Bt PowrR SUPPLY UNIT (46) ot out Input eirouit sssssees pemerccon 9.2 Converter circuit sesseeseeseeeees 93 Secondary output rectifiers evsevessee we 8 9.8 BT supply veeeeees 98 95 calibrator 1903 [FRONT UNIT (47-48) 10-1 10.1 Reyrmeteix cece se Toot 10.2 Front controls and indicator rer es Toot 10.3 0 aieptay ekreute cess . MeTHERBOARD wnET (ALO) ry options (Ai) ae cerv mir (a2) 1a Introduction 13.2 Nenory map 13.3 circuit deseription vers. 1 Signal nme Met coeeseeeee se eu uwrr (a19) el aad Organisation of the memory ssscsesseeseesses Met 2 Introduction to the sample exansporte ceceeesseee suet 14.3 Signal acquisition « com ved 1 Copying samples from acquisition memory to dleplay DEBDEY ceeetessvsseese ea 14.5 Displaying of trace and register «. tes 14.6 Wieroprocessor mmnipulation re wa Displaying of text and cursore roy1s. ms Clearing the display menory s+. ie we Clearing the acquisition manory sssseseeeceeerees Mes 1.10 Exo D307 ae 6 a cup select « wer 14.12 ote and plotter conteol esse see Mer Lad ining dfageen ceeeeeeeeeeeeee see Mes 1416 Signal name GE vere eeeeeeee oi) ‘ct vurr (als) 1 15.1 ‘Teigger conteol + 15.2 cop + Abe Timing 15.3 Average and interpolation eircutt se..s+es 15.4 Signal sane Lise. eee asd Ave vee OT (ALS) 16-1 16.1 Ane cineuie seesseeseeeteeteeeee a 16.2 Vertical DAC circuit esesseeseeee seesssaeeses 166 16.3 Horizontal DAC efreule a ce 163 les X 70S Suiteh ciroutt ses... cee 16.5 2 control «. o soessesseesvenssseees 163 66 Plot snd pealife eireuie ron 16.7 Signal name Let scseeeeeeeeeeee soarrton uxt (416) 1 at Vertical display mode switch 2 Reel tine mode amplifier ...+. 3 Digital wenory amplifier so... 1 Signal name Ler.2. 2 wast cop wrt (417) 18-1 wa Introduction «. vee Wet 18.2 oput buffer oe 1-2 1a pleco = 090206 se sseeee le 18 Signal mane Lat ceseseeees Peco mrt (A18) 1st reat ‘Ace (advanced customised ECL) seescsssees 19.2 clock drivers. 19.3 Mini CCD defaule circuits «04 sess 192 19.4 Pop output «+ coo 19.5 al name List. cou snesseseeee 1983 PERFORIANCE CHECK 20-1 20.1 General information +. 20-1 20.2 Preliminary settings «++ 20-2 20.3 Recommended tort equipaeat cesses : 2002 20.8 checking procedure 2003 20.4.1. Pover supply 20-3 2014.2. Vertical deflection oF ¥ 20-3 2014.3 Horizontal deflection or Hrexis 20-3 2014.4 Triggering vveereeens 20-2 2014S Gucsore wecceseee 204 2OLd.6 Auxiliary inpute and outputs sellessise 20-15 DISMANTLING THE INSTRUMENT ait aa General information s+s++ a2 Removing the top and bottom covers « as Access to parte for the checking and adjosting cecxtng AND aDsUSTING zed aa General information « : eon na Recommended test and calibration equipment .-2. 22,3, Survey of adjusting elorents 2246 224 checking and adjusting procedure vssessssseeeeees 22-10 aca a Veegeen loser ck eeererr re zo 22.412. Powe supply adjorenene | er Feat fata scat] tep iy (ea) cecmee eer ae BALtG Guin and EF-eq.vave teaponee WAT and A inpae 2.0% Bal 22.415 Gain Sed Urceg.vave veaponse enennel ACB) ser. maa 2ai4i6 Oftse channel AC) SITS IIIT Boot Bal) Selggering Inn ad 22.418 Thoe onan sweep speeds TINEIIIIIIII a5 Balk18. ip aqiuave response Dena 22allo piceh-asjustaect (OxaitA‘aode) 22 ans BELLI bieplay 5 Bs 2214118 Gade see offect channel ACB) fn CORRECTIVE MATITENANCE aed 23.1 Replacements sos renner ie 23141 Stemieed parte ccs eee as BS1102 Special parce WI at S313 Trane MINN Ba 23.114. Seaciecocnsitive.conponente SIN Ba BBLS. Handling HOS eevscen MOBS BBI1i6 Soldering and descideriag of aurface aounted devices 1.) 23-3 25:2 Removing the onits and anchénieal pects... 23-5 aa.2.1_ Aevonator nit (A) eceett 235 23212 Peesanplifier unit (aa) sai aaptation aie (Ala) 222000 23-5 B23 Rigcamplifler wale (A) nesscenessereersesesesss 235 231214 Tinesbese unit (A) 0 eeerreneries ast 2312's Ger control wit (45S soccco loos axe 231216 Power supply amie (46) 0000) seretedae 23.2.7 Front cave CAT) and too sale (a8) 1107 Bo BLED bieteaance nd ay oo: 28 2312's. PiSep unit (ala) abd'tntc&d nit’ (Aiv) Bo 2512110 Renowing the delay-line cable + TIN Bs BILL Raplaconent of CH + peeeeiey y zo 23.3. Soldering techoiques ssesecessss eS an 234 Tnstrment FepacklOg sssscsseseeee al 23,5 teouble shooting 212 23.5.1 Introduction erssscecussceoss aan 23.3.2 Trovblecshocting eckoigace 2aaz 21:53. Rywessg noutine seer 2 Eso aa tioleeeelee cores aa 23,55. Teosblecshooting the powr roppiy Bas BASLE. presbe Intersontect lone visrirysvevsiseneweiees Das 23.6 pe aes 23.6.1 Tleming tit si0 313 eins 255612. pocsb. Soapper = 5322 $38. 91942 feccerassi9 231613, Extension boare - 5322 216'51211 220 23.7 Racalibeation after repeit ccsesses + 23-20Ps a. SAFETY INSPECTION AND TEST AFTER REPATR AND MAINTENANCE 18 THE PRIMARY CIRCUIT 2a General sieeceives sees 24.2 Safety components. 14.3 hacking the protective earth connection +. 2.4 checking the insulation resistance v2... 24.5 chacking the leakage current sess 24.6 voltage tent «+ PARTS LIST 25.1 Nechanicel pacts ssssssssersseesesesesseseesseee 25.11 Mechanical parte indicated da 'Eigare 25.10 000021 25.112 Mechanical parts indicated in figure 25.2 + 25.113 Mechanical parte indicated in figure 25.3 | 25.2 vite 25.3 Cceblee and connectors os -+s 1 Flateables and eonnectare 2. pue.bi-conneetors (nale headers! 3 50° dhe cables end connectors «- 5 Miscellaneous sockets and connectors’ solo: 25.4 Electrical parte « 1 Capacitors 2 Renistors «0 3 Senivconductozs 4 Intograeed etecuieés ss. 5 5 Colle ves Meecetiancous 2-4 25-1 25-1 25-2 25-2 25-2 25-5 25-5 26 266 25-8 25-8 a7 25-19 25-40 25-47 a549 25-5010 List oF Ficuaes Page Piguce 2.1 Dimensions a2 Figure 3.1. Block diagram, anatog part 37, Figure 212 Block diagran, digital. pare 37 Figure 4.1 Table of attenvntor settings ot Figure 4.2 Attenuator uate pre.be a3 Figure 4.3. Chrcuit diagran of attenuator, ch.A as Figure 414 Circuit diagear of attenuator, eh. ra Figure 415 Ateenuaeor unit p.eabe oa Figure 616 Circuit diagean of atenuator, EXT ato Figure 5.1 of the vertical pee-aaplifier sa Figure 5.2. Prevenplitier unit pee.b- 53 Figure $13 Girovlt dlagrar of preamplifier, channel sviteh and delay Line driver 37 Figure 5.6 Ciseuit dlagran of pre-amplifier, ceigger sviteh 58 Figure 3:3 PrevanpLifier unit pee.b- S10 Figure 3:6 Circuit diagram of prevamplifier, logic controt saz Figuee 6.1 XYZ amplifier pred. ea Figure 6.2. Circuit diagean of V2 amplifier, final X and Y amplifiers 6-5 613 wre amplifier p.c.b. 6 614 Circuit diagram of X12 amplifier, 2 amplifier and cet circuit 6-8 Figure 7.1 A103 configuration 12 Figure 1.2 Simplified diagram of the tino-base swvep generator 74 Figure 72. Peee-ronning aweepreining diagram ad Figure 71h Tine-bare unit preabe 9 Figur: 7.5 Circuit diagram of cime-base, trigger mplitier rn Figure 7.6 Glrsuit dlagem of Eime-base, sweep cleeuit ané final Xeanplitier 712 Pigure 7.7 Tinesbaze unfe p.e.b. re Figure 1.8 Civsuie diagram of tine-base, X prevamplifier and Z eviteh 7-16 Figuee 8.1 Circuit diagean of CRT control Figure #12 kf control unit pie.b. Figure 9.1 Converter eiresit 92 Figure 9.2 Timing. dlegean converter cireuit oa Figure 9.3. HT oscillator 9-3 Figure 914 over supply unit puc.b. 9-5 Figure 9.3. cireuie dagean of power supply 98 Figure 10,1 cCiecuit diagram of front unit, key matrix 10-3 Figure 10.2 Front unit poe-bs 10-5 Figure 10.3 Circuit aiagres of front unit, front controle and probe indication 10-7 Figure 10.4 L6D unit peas 10-8 Figure 10.3 Circuit diagram of LoD unit to-lo Figure U1. Motherboard unit pie.be ntFigure Figure Figure Figure Figure Baure Bigure Hiroe Figure Figure Figure Hse Figure Figure Figure igure Figure Figure Here Figure Figure Figure Figure Figure Figure Figure Rese Figure Figure Higore Figure Hgure Figure 13.1 132 3 14 wa il res 14.5 146 1 1s 13 1610 reat wea wy 13a 15.2 133 1514 1555 is 1622 1633, 164 18:5 166 18:7 158 15:9 1610 at 3 a 18.1 18.3 18.4 1815 19.41 1922 1333, 194 95 1316 189 8 913 2c bur structure Drack generator Cireuie diagear of CU unit, pert 1 CPU nie pre abe Glreute deagrar of CPU unit, part 2 Organisation of the nenory Display cyele controlled by S08. Block disgran of signal scquieition Block dispran of copying samples from acquisition senory fo display mensry Block diagran of Erace/egister dizpley flow Block diagem of text/currors display flow Block dispran of the clear function Block diagrams of the clear fonction Chip select efeeuit Nieing diagean for 0314 Gireule diapran of DCL wait, acquisition menory Circuit dfagien of DCL unit, display memory ‘ining diageae of the trigger control for Tb = 5 us and PRE-TRIG = 8 Tsing dae ACL unde presds Circuit dlagran of ACL unit, part 1 Circuit diagram of ACL unit, part 2 oD and Ave tining aveforee on NSOL avefore om 2501 aveform on degliteh cfcuit Zeontrol. for PLOT or DT 2 control for 2 O8 Circuit dtagren of ADC DAC une, Y-DAc eircuit Circuit diagram of ADC DAC unit, X-DAC and ADC circuit AOC TAC unit prewb. Giecuit dtagrem SF ADC DAC unit, part 3 Circuit glogran of adaptation wnie, pare 1 Mapestion unit p.e-b. Circuit alagran Sf adaptation > part 2 Schematic diagran of a Peco circuit Seaple and transport sequence Ovepot signal Wink Cod unit p.c.be ‘ineute diagram of aint CCD unit Principle of the sample clock drivers dgelonve essary correction Circuit diagran of PZccD, ACE jeeit Stages of F460, clock rivers coD unit pee, Greate diagran of PccD, pact 3 Giresie Slagean of P2coD, CH circuitFigure Figure Figure Pipure Figure Figure Figure Figure Figure 20.1 aL aa nia at 2.2 23 a 235 2316 207 23.8 9 23110 3.1 333 25a SOPTSTART cond Access to all parte for checking and adjusting Adjusting elements Squarecaave rennonee DAC and Coxe adjustment Arcangenent of vorking area for S.M.D. excharge snd MOS device clanping Lips for Xvt-asplifier unit Power supply unit outside the instrument Measuring the front unit working condition Wessuring the digital unit in working condition Rynoving. the CRT Telnning tool Hie prerbs Snapper Inride view shoving the parte in the CRT conpartinent lew of the unite1a 1a 1 ey ‘SAFETY INSTRUCTIONS Read these pages carefully before installation and use of the “uergosverion ‘The following clauses contain Infornation, cautions api warninge which fost be followed to ensure tafe operation end to retaia eho instrument n'a anfe condition. Adjustment, maintenance and repair of the instrument shell be carried but only By qualified persomnel. SAFETY PRECAUTIONS For the correct and safe use of this instrument it both operating and servicing pertonnel follow generatlymeceepted| cafety procedures in addition to the safety precautions specified in this manual Specific wavning and caution atatenente, where they apoty, will be Found throughout the manual, lihere neceesary, the warning and caution statements ani/or symbols are snecked on the apparatus. (CAUTION AND WARNING STATEMENTS ‘CAUTION: is used to indicate correct operating or waiatentence procedures in order to prevent danags to or destruction of the equipment ov other property. WARNING: calls attention to 4 potential danger that rigulees correct procedures or praciter in order to prevent personal iniry swans Mish vottage > 1000 ¥ (eed) Read the operating Snateuetions 4 AN Protective earth cose) (grounding) terminal1s IMPAIRED SAPETY-PROTECTION nenever it is Likely that aafeey-proteceion has boon impaired, the Tnstrument mst be nado inoperative end be secured against any tmintended Spetetions The matter should then be referred to qualified technieians. Sefety protection is Likely to be inpaiced if, for exemple, the [nstrament fails co perform the intended nessurenents or shows visible damages CenERAL CLAUSES WARNING: The opening of covers or renoval of parts, except those fo vhich access can be gained by hand, is Likely to expose {ive perte and accessible terminals which can be dangerous wo lives ‘the instrument shall be disconnected from all voltage sources before Et as opened. ear in wind that capacitors inside the insrunent can hold their Charge even {f the instrument hee been separeted trom all voltage WARNING: Any interruption of the protective earth conductor inside Gr outeide the instrament, or disconnection of the Srotective earth terminal, is Likely to rake the ineteument Eoggerouss Incentional Interruption ie prosibives. Componente which are inportant for the aafeey of che instrument aay only be renewed by components obtained through your Local Philips Sreanieation, (See also tection 23). After repair and maintenance in the primary clecuit, safety inspection and ccatsy at mentioned in section 25 have co be pet formed.2 CHARACTERISTICS Peeformance Characteristics = Propertion expressed in numerical valves with stated tolerance sre guaranteed by PHILIPS Specified non-telerance numerical Yalule Indicate those that could be nominally expected fron the ten of a renge of identical instruments. = This specification is valid after the Lagteument has varsed up Tor 30 minutes (reference temperature 23°C). Jor definitions of terms, reference {2 ade to TEC Pub 3si-l safety characteriaticn = This apparatus hae been designed and tested in accordance with Sefety Class I requicemente of I8C Tublicstion 348, Safety Peguitenents for Electronic Moarsring Apparetee, UL 1246 end CSA S5ee and has Seen supplied in a safe condition. = Overati dimensions: ~ wiaen Including handle 387m Excluding Sandie 350 nm Including handle, axel. knobs + 518,5 am Excluding fret, knoba $ 443)5 am Including incl, knobs + 530,3 a= Excluding nol, knobe £ 455,3 am = tesgne Including feet 146,3 a Excluding feet 2 138)5 Brel, under cabinet 2 152)5 meHorizoneatly on bottom feet Vertically on rear feet £1 On the cafeyiag handle in two sloping positions, 1 bisplay, 2 Vertical deftection or Y axis 3 Horizontal deflection or X axis 5 Signal acquisition © Ghanmets A and B 2 Tiger "9 Memory 1 1 I Galeulation facilities 2 hata seeeing 5 Sundries 8 Safety aecuanacreRtsTies ADDITIONAL, TAFORATION + ot ‘Type No Gee) Screen type Scendecd Option + total acealere ‘en voltage Blumination + Display tine per chennel in shopped node tal displey Type to. Visible are + Deflection coute variable gaia control. eenge Exvor Limit Paralleted. by Max. impst Man, test volte ses (ome) + Bandwidth for 20 a¥ up to 10 v ease Day Sa and er pers p 14-372 40. 100 nm 3 & @ 7) 16k ue 9438130 25,4 88,8 nm 2 aV/div...10 v/div be o2, efor 1M ohm «/-28 20 pF 2/29 foo’ (set aces peak) Sov > 50 me > 35 Me 7 ne oF less @ x 10 div. A subdiv. (od) = 2 am visible in display. to 1, 2, 5 sequence. TE EN 8935/09 is used, deflec- tlon coeff, ie automatically calculated in display. Only in calibrated position. Measured at fj <1 Miz Measured at #2 <1 Mix Mex. duration 50 sec. Input 6 div. sine-wave. Input 6 div. sinewave. Ceteutated fron 950/f-3 68cuanacrenistics Poles aberration ringing and Duration of ringing Hole or bump Drop or tile Noise 20 a¥..10-V Lower - 3. g5 poine @ 25° Dynamic ange @ 10 mie 0 50 me Decoupling fac~ eo me 650 mie Rejection Ratio © 1 mie Visibte signal delay fata FS Variable jump sPEcrPrcATION < 0,7 ad (peak? < 0,7 4 (peak <0 8 > 26 atv. 38 iv, > feb aiv. 1: > 100 11> 100 > 15 ne q fic] 6 id < 0,6 iv. 2,5, 4 Tine Base mag- Expansion #10 Rot valid in X-doflection. nifier + eevor Limit 10 Minimum hold-off ime ia rele Kedeflection + deflection coefe. Via chansel Aor 2aVe.10 Waiv. 1, 2, 5 sequence, Via ExT. input 100 av/aiv. Vie channel Aor € 4/- 5% Vie BRT, input < 4/- SE * nandwideh De... 2 Miz DC coupled amplitude @ in put signal 6 div, Dae + Phase shife be-< 3° @ 100 He teween X and Yo aetlection Dynamic range > o> 12 div. @ 100 ane2.3.3 2 CHARACTERISTICS SPECIFICATION ADDITIONAL. THFORUATION EXT inpue Input impedance 1M ote #/= 22 £ <1 Me Paralleled ty. 20pP 4/2 pF 0 1 oe 400 v (dee + ave pean) Soo'v Max. duration 60 sc. “Lover 348 < 10 He AC coupled poise sRLGcERING teigsnode AUTO (auto free rn) single Trigger source (is); ExT, Line Trigger coupling Peaketo-peak (orp), Be, TL, ‘be INTERNAL Tr Trigger slope absence of trigger igre > Gor Stee dato free run starts 100 a8 (eyp.) acer no teig.pulee, Svicches autonaticelly to auto free tun if one of the dleplay chansele is grouded. Sn ‘multi-channel mode Calter pated) each channel is armed ‘fter seset; if sweep hat leeady started, weep it not finished. Line trigger source alas triggers om main frequency. Line teigger enplivude depends on Line input voltage Approx. 6 div. @ 210 VAC input voltage. prp coupling {2 00 rejected. Slope sign in 1c0 end + or ~ SE TWP in chosen.25 cuazacreatsrocs tivity SRTERRAL on 10 mse 230 Mie © 100 ye J een O10 Hite 50 me 100 we {L/P TTERNAL SSTONAL AcQUISTTION + sampling type 0,3 ws/aive. 50° a/aiv. + vax.Sample rate Real tine: + vertical Goltage) 4 forizontal (eine) Reroition 1p single-channel 05 na/aiv 50 s/aiv. 00,5 ws/aiv. 2 ne/aie. In dual cheanel 00,5 wo/atv Danaldive % Rocord Length SPECIFICATION < 0,5 div. <1 div £30 ae, < 50.07 £150 av 500 av < 0,7 div. Soto av Real vine 100 negesanptee/= 4096 sump. / sequisition 512 samp,/ 2048 samp! 512 sanp./ 10,2 x eime/atv. 2 ADDITIONAL. INFORMATION ‘rig. coupling 0c, Trig: coupling DC. ‘Trig: coupling 2C. ‘eig- coupling De. Telg coupling Dc. Sync. putes. Syne. pulse: Sampling rate depends on fine/ély, seteine, 0,02 of full emge 1 sample 1 Sanple 2 Semple = 0,0258 of full = 0,2 of full record = 0,05t 0€ full record = 0,28 of full record Display in vonsgnified position26 cuazactearstics * Acquisition tine foal-eine 80,3 s/aiv, 5 e/a. a'masaiv... 0,5 welaiv sources * Acquisition Modes coanwens A AND & Lover Input in 3C inc Upper orm: coupling portion Tinsiene 15043590) netability: Jump Cigbient 1s. 35e) between any tine/aiv. prife Temperature coefficient 10,2 x tine/aiv. 30 m9. 50 mt 50 mo...70 ma coannet A Channel 3 1 channel onty 2 channels cee 2 20 mz (-3 a8) 0,3 atv, 0,5 div. Oy1 avai 20,08 atv. se Exclusive delay tine Exclusive delay tine Poll monory availeble for 1 channel Simultaneously sampled; 2 channels there senory 2 source = 25 ohn Deviation max 3,¥ie for dablentr 001-40%C. Add 255 for Anbient: Odor Meatured in 20 nl/civ, position Measured in 20 nV/eiv. positiona7 29 cunacrentstics SPECIFICATION ADDITIONAL THRORMATION TIME BASE + Tine coveftctente tn Recurrent In single shot and multiple shot + trigger detay: accuracy trigger Lovet Tneceuraey * wonory size: Tnscovracy Regiscer Depth: Wordiengeh + Functions Single shot oll 0,5 us/aiv... 0,5 siaiv. 0,53 uslaive. 50 s/eiw, 250 giv. 0,5 div. 0.75 aw, iz 4096 words 4096 8 bite Lock tp to 2 shots MiLl'be stoppad by erizger ambient: 15...35%: Add 0,82 for Anbient: Adjurtable in divisions Indication in 260 contents of acquisition are saved in vegieser Nenory aysten iz locked. 1f Tock fe not aczive the signal Es weiteen into the2.10 aa aaa aaa cuRActeRrstics sPECTFrcartoN DrsPuar + sources canned & Channel 8 Register A Repister + Dieptay Expansion Horizontal tate + display Dot join Manipulations range forizontat ful senory CALCULATION FACILITIES Rise or Fall tine Frequency * cacsors ott calculations off cexasons resolution: in single 1: 4096 fn dual 1 2068 @ 2 nssaiv, bis 0,5 ue/aiv 1: Lone Including digital interpolation at 0,5 ue/div, Diee/aie. ‘The displayed part of the inagnified menory can be chosen. Betunen cursors inkicated by ‘analogue node. aieplay in dove Sieplay in dot joieaad eal CHARACTERISTICS SPECIFICATION __ADDTTONAL, INFORMATION + Vertical 1: 256 resolution * Readout 3 siaite resolution + voltage cursors: Recor Lint 38 Referred to Seput at BNC, dnbient * terror of probes ete. exciuded. Triste Aad 3t for ambient 0.+-80°C cursor Range Diaplayed part Cursors cannot pase each of memory, other. (Keposition is neglected) * Tine eursore Error Limit, 40,28 owen SUPPLY 4 Line input vot tare AC one range, oninst 100 ~ 240 ¥ Limits of ope ration 90 = 266 v Nosinal 50 ~ 400 Be Limite of ope ation 43 = 485 ae nena within Specification of Tee’ 348 class x tL 160 voe 41 ck 356 8 * Power consumption 70 H ‘Ae nominal source voltage (at source)couanacten:stics SPECIFICATION ADorTTOWAL TAFORMATION + pata ana Settings Nonory Back-up Corrent Drain Recomended type quancicy Temperature Hee of batteries Temperature Range + doalogue Plot outpue Functions Soneitivicy Pen Let Plot tine Plot sequence ay 16 aK typical 5 years 0.470% Memory Danp 4 vipat aenoey an TTL compatible 20 98...2000 me channel A first ‘hen insteunent is evicched Off or during MAING failure According to TEC 285, CikaLine Hanganess Fentiene Battery), eng. PALIPS LR6 (299° 006 26954), Afcer warning-up period of 2 23°C, vith recomended Ceeesh) betteriee ~10...0% settings roten- sed to renove batteries from instrument vben it is scored during logger period (24 ») Below’ -30°E or above 60%, THE INSTRUMENT @ TIMPERATURES AEYOND THE RATED RANGE” OF THE Rogister selectable Wortzoatal and vertical Fon-up is software selectable (Over 1). Open collector ueput; sax 12 ¥ Sofeuare eoleceable In dual channel operation leh more repisters starting with the Lowest numbers216 CHARACTERISTICS SPECIFICATION _—_ADDITTONAL INFORMATION AUXILIARY INPUTS oR OUTUTS van > 2,09 Blanka diepley. vin f0;8¥ Max, intensiey snd VIL Le possible. + can To calibrate drop oF eilt Output voltage 1,2. 4/- 1% Rectangular output pulse. Fresuency Pha The output may be short= cireulted to ground. [ESVIROWENTAL, CHARACTERISTICS ‘the enviromental date sentioned in this manual are based on the re~ fules of the manufacturer's checking procedure Details on these procedures end failure criteria are supplied on Fequett by the PHILIPS organisation in your country, or by PHILIPS, ERNISERIAL AXD ELECTRO-ACOUSTIC SYSTINS DIVISION, EINDIOVEN, ‘THE NETHERLANDS. + Meets environ MiL-T-28800 ¢, ental requires type TIT, CLASS 5 ents of; style E * Tonporature Operating temp. 10° - 40% wit=1-26600 ¢ ner. Penge vithio tested, Specification Linies of ope- 0 = 50% iden, tore range Non-operating = 40°C/+ 75° MrL~1-28800 ¢ var, 3.9.2.3. (Storage) tested, par. £55.11, operating 95% RE nenvoperacing Max, atestude NaL=T-28800 6 aes 3.9.3. tested, par. 8.5.5.2. operating 4,5 tm (15000 feet) Maximum (Operasing” Cemperstare derated 396 for cach kay for teach 3000 feet, above sea Tevet). Non-opersting 12 im (40 000 feet) (storage)* vibration (oper rating) Freq. 5.0015 Be Seep Tine Excursion (p-p) Freq. 15.4425 Be Sweep Tine Eeeutelon (9p) Max Acceleration Freq. 25.2455 He Sweep Tine Becureton (orp) Nax Acceleration Resonance Dwell Shock (operating) tocal ech axis Shock Wave-form Peak Acceleration Bench handling ests require ents of seructural parts eae rageire= DML (Electronic ference) sects require sente of sPciPrearioN. 7 ain. Lm 1s'nle? (1,3 x 2) 5 nin. 0,5 =, 30 aie? xg) 10 win. 18 in 500'n/s? (30 x g) mai-st9-210 method 516, pro~ eed, naut-stp-s10 ‘pethod 503, pro tution 20% MIL-STO-461 CLASS 8 Vor 0871 and Vor 0875 Grenswere= Masse 3 ADDITIONAL THFORMATION MaL-t-28800 © par, 3.9.4.1. ferted, par. diSei3c1 15 te 225 me e535 me G each resonance fee 453 'ts if no resonance ws found). Bxcurtion, 9.Tel- te 9.7.2, tt-1-28800 ¢ par, 3.9-501 ferted, par. 4e5-Sobs1 (3 in each direction). a Min—t-28800 6 par. 3.9.5.3. tested, par. Ar5-5.6.3. rt-T-28800C par. 3.9.8.1 tested, pars 5.6201. Applicable requirments of part 7": E03, S01, C502, (6806, nEo2, R03cungacreersrics + Magnetic Radie~ ted Susceptibi- fey Maxime De~ Hleceion Factor + Meets require # ax, KRM hon + Recovery tine spect teaTroN ec 348 CLASS Woe 411 ox 1344 ca 556 8 15 ain. 30 nin. 45 als, 60 ain. ADDUYONAL IwFoRMATION Tested in contomity with TEC S5i-i par. Seledele Measured vith instrument io st nonogeneose Gin any direc sagnetic field with respect to" tastement) vith a Alex Enceneity (pep value) of 1,42 aT (14,2 gauss) and of Eymettical sisevave form Sith e frequency of 45,5 6582. Except for power cord, unless shipped with Universal Euro pean pover plus. Except for powir cord, unless hipped with Norch American Meatured @ 5 cx from surface of instrument tor = eargee tea of 10 on 20° 30° er comps + 15% anbient + 25% ambient + 25% andient + 80% ambienta aa 3.42 ne INTRODUCTION TO CIRCUIT DESCRIPTION AND BLOCK DIAGRAM DESCRIPTION INTRODUCTION To CIRCUIT DESCRIPTION Genera ‘the functioning of the circuite is described per printed-circuit board Griese). Por every pecsbs a seperate chapeer’(Url9) Le. availeble Coneatalag the Tay ous of the peesbey the associated circuit diagran(s) Ene cireute description ands signel ‘mane Lise. Explanation of signal name set-up Signal name consiate of to parte = a funce teeleee ls L___reatisacion part functional part ‘me realisation part ie optional, If it 4s used then the functional porte should consist of 6 characters. If necessary dummies (minus sign) Ete aed. in the functional pare, to aake it 6 characters loss. ‘The first character of the realisation part has che folloving meaning: He active high signat Li ceive Tow signed Xi Trrelevant (ergs counter outputs) ‘me second character of the realisation part is used to identify Hnal levels analozse GOS Tv of 15-v ows 5.'v Eel 4,5 vor 3,2. HLS Vor HET a ul ji. tetive Soretines the functional part can slag be used for @ serial nusbor Sips to indicate a bettered version of « #ignal. Example: CHET=-d1a I se ATTENUATOR UNIT [A1) PRE-AMPLIFIER UNIT (2!T Power supecy u TIME BASE UNIT (A4)TT UNIT 143) 1 | — [ERT coTRGT aires | {ema Lo] ene. ! : | ee | | poweR SUPPLY unit tae) a2 aa Signal nen Lise ‘The digfeat unit description in Chapters 12...19 containe « list vith the signal nanes used in that unlt given in alphabetical order. After each nane, 2 description is given and on which unit the signal iis generate Only Lf the signal is generated on the unit itself, ere the other units on which the signal is used (signal destination(s)) sestioned, otherwise e sinus eign is filled in. If the signal flows over more units in sequence, the path is indicated. Sone signals may have more signel sources, becaute the sources have openccollector output circuits, or S-atate output citcuite, Im this case the sources are montioned, separated vith a piua (+) sign. The unit where the signal is generated’ i slvaye indicated a2 signet A number of power supply Lines and ground lines are not mentioned on the signal name Lists Because they appear in alnost Sosre case Location of electrical parte ‘The item numbers of Coecsy Revsey Verevs B been divided into groups vhich relate to the clrcuie and ths peinesd~ circuit board sccording t9 the following tabl Teen nunber wait ao. 1000-1999 al Ateenuator unit 2000-2399 2 Prevamplifier unit 5000-3999 a 4000-4999 ti 3000-5999 a 6000-5999 36 7000-7989 a 8000-6999 a 100-100 an 200- 299 az 500- 398 a 400-499 ae 500-599 als ADC DAC unde 600- 699 ats Adgpeetion nit To0- 199 ay ni ec, 00-999) a8 Pico unea2 a4 n22 M3 /pe BLOCK DIAGRAM DESCRIPTION (ree figure 3.1 and 3.2) Introduction This Dlock diagean description Je based around all. the important Functional blocks end their interconnections, The atercomect ions between alt p.cab."s are given in the interconnection disgean oF Figure 23.6, In order to assist in eroeerreference with the circuit diese the blocks include the item nunbers of the active conponenes thes Furthermore, the blocks are grouped together per printed-cireuit board, or # part of it. To facilitate feference, the nancs of the finetionat blocks are given in text in CAPITALS, Signal waveforms are alto indicated at block interconnections where usefet» Jn this instruene almost all the sviteher (UP-DOW controls, softkeye and potentionster UNCAL svicches) influence the sacilloscope circults Via S microprocessor (uP) aysten, Actonuator unit (ante Al) ‘The vertical channels A and 8 for the signals to be displayed are identical. Each channel comprises an input SIGNAL. COUPLING for AC/DC, 4+ HIGH IMPEDANCE ATTENUATOR which giver signal attenuation of xi-¥10 fr x00, an IMPEDANCE CONVERTER, LOW INPEDANCE. ATTENUATOR vhich fives eignat attenuation of x1-x2,5 or x3. anda CAIN xi-x10 AWPLIFIEN block, incorporated with the GONTISUOUS CIRCUIT. This block hnas a variable gain, influenced by the front-panel YAR control. The ‘sin ie also incrested by 410 in orger £0 obtain 2-3 and T0a¥ ceevings. Similar to the vertical channels, the external chennel attenuator also ‘has an input SIGNAL COUPLING, EGH IMPEDANCE ATTENUATOR snd THPEDANGE CONVERTER in line. Hovever, the external channel hae only #1 attenuation and no LOM IMPEDANCE ATTENUATOR, The output of the f@xternal channel Le fed to both MIB and DID EXT PRE-AMPLIPIERS. AML blocks that are capable of working in different nodes are controlled by the control A or control B signals, These signals are Benerated by the CH.A CONTROL of CH.8 CONTROL blocksCPU UNIT (A12) Pigure 3.2 Block diagean, digital part sal ! lesovr ut a7) [Loo unas [act unt tate)10 5.2.3 Pee-enplifier unit and adaptation unit (umit A2 and 16) the precanplifier unit incorporates the signal eplitters for the Vertical channels Avand B, the trigger level view anplifier, the Celager elrculte. for the fine base and the chopper secillgeor circuit. Tent the adaptation unit is mounted as 4 separate pycrb. on the pre~ Unplificr uit. Ail these functions are controlled by the control X1P Sel AWA signals, generated Sy the {oY CONTROL blocks. Vertical channels A and B oth channels are conpletely identical and receive their input signale feom the ATTENUATOR UNIT. This signal ie applied eo the SIGNAL SPLITEER, whien hae two sutputs = one output is applieé to the SLOPE/TRIGGER SELECTION for the tine bese eriggering. | = A'second output is routed to the edaptation unit. layeation nit, vertical shite of the dleptayed goal Ls meted SPT teoespenel f08Enfon conteel | Switching vetweon the Feal tine path and the digital storage path is Skecinel'a' ene i/o butte block’ The digits elecaie ie given in | etgee"a.2 and deceived separately. Bee acottpt of the EEGECAE CRAM SWITEH Ee couted vie che | DELAY Lite DRIVER to\ the DELAY LINE. ‘The TRIGGER LEVEL VIEW channel enables display of the tine base trigger evel and can be weed to determine the trigger point of the signel. + Trigger circuit: e JE ‘The SLOPE/TRIGGER SELECTION block receives a trigger signal from one Of the vertical channels A cr By fron the EXT SIGNAL SPLITTER or from | the LINE TRIGGER PICK-OFF. Inverting of the trigger signal ie conteolled by the CXYA signals i INVAM and TRVBM eo obtain ene slope function Routed via the TRIGGER PREAMPLIFIER, Block the signal is split up Ka into different patho! = = after sumation of the LEVEL eignal, direct to the TRIGGER AMPLIFIER oe —H EE = to the AUTO LEVEL block, Thir block containe the aifterent erigser = factlities and level ing. of the trigger signal is influenced by che J rite Base unr taal front-panel LEVEL control, The output of this path is roued again to the rimmation point to influence the direct trigger signal = f9 the -DEFL AVWLIFIER for Kedeflection facility. ‘This block Ebcorporates « phase correction circuit for the IY display. var ‘The TRIGGER AMPLIFIER feeds the trigger signal to che tine-base unit. he trigger sigual {rom the sumation point {a sls routed via che ‘TRIGGER LEVEL VIEW AMPLIFIER to the vertical CHANNEL SWITCH stage to Gieplay the erigger point. chopper ofcéiiater efreutes A square-wave tignal for chopper blanking and vertical avitching is generated in the CHOP OSCILLATOR. For chopper blanking the signal is uted to the 2 PRE-AMPLIPIER on the tinerbese unit, AGL UNIT (Ai)nas aa ine-base emit (unit 46) ‘mis unit incorporates the tisecbase (1B), the horizortel anplifier find che 2 enplifior eiveuit, All functions are controlled by’ the CXL ‘Sed OR2 sigeate, generated by the HORIZONTAL CONTHOL CIKCUTT blocks. + Time-baee (8): ‘the teigger signal can be either directly routed to the TIME-BASE CoNTEOL CIRCHTT or First routed via the 1 TRIGGER SEIECTION for the PV erieger coupling. when in the AUTO node, in the absence of trigger Signals, the tine dese vill be free runing. ‘The CURRENT SOURCE applies the sawtooth cherzing current to the Encep circuit, Tis block gonerstes the tine base seveooch eignal, Shieh ie routed 0° the HORIZONTAL DISPLAY NODE S¥ITCH... ‘me HOLD OFF and the ALT CLOCK PULSE blocks are also wnder control of Che TIME BASE CONTROL CIRCUIT. Hold off tine is varied by the Front-panel HOLD OFF control. ‘The output of he HOLD CFF block ie Fouted to the TIME-BASE CONTROL CIRCUIT again. ‘The ALTOLN-pulee applied to the FRE-AMPLIFIER UNIT. vt unit (ante 3) ‘This unit comprises the final amplifiers for the vertical () and horizontal GD deflection and for the Dlanking (2) cireule. In addition to this, the CRT contsol civeuite are also incorporated in the unit. Final vertical amplifier: ‘te output signal from the prevanplifier unit is firee routed via the DELAY LINE to ive sufficfene delay to ensure chat tho stesp leading fdges of iast tignals are displayed and then fed to the DELAY LINE COMPENSATION. This block conpeasater the signal fordistortion Srigineting in the DELAY LINE before it ie applied to che FINAL VERTICAL AMPLIFIER. The output of the FINAL VERTICAL MGLIFIER feeds the vertical deflection plaves of the CET. % Final horizontal eaplifier: ‘the horizontal deflection signal is routed to the FINAL HORIZONTAL AELIFIER, the output of which feede the horizoatal deflection places OF the cer. circuits ‘The output signal fram the Z PRE-AVPLIFIER of the tine-bare unit, thet Gecermines trace blanking or unblanking and modulation ie routed £0 the PINAL 2-A00LIPIER. After saplification the blanking signal is split ineo exo path = the hf, signals are fad via « high voltage capacitor to grid Gl of the cit, = the TE, signals are used to modvtate che ampiitede of aa cucitlator vave-form, which then parses via another high voltage Shpaciter and is denodulaced in the DEMODULATOR bloce to retrieve the original signal Note that the original A.f, and 1.f, signals are again recombined on the aria cl.3.2.6 B27 + okt control circuits: ‘The FOCUS AMPLIFIER block is influenced by both front~pas INTENS controls to provide a focus that is independent of Enteneity, and drives the focusing grid G3 of the CR FOCUS and the ‘The -100 ¥ SLACK LEVEL block provides the correct presetting of che Cathode voleare. ‘The ORT BIAS gives a duc. voltage to the grids G4 and G5 to provide ‘an optional adjustment for geooetry and astignation, Powor supply unit ‘the mains input voltage is féltered and chon applied to the RECTIFIER bigek to obtain & die, voltage cource. another output of the LINE FILTER block is routed vie the LINE TAIGGER PICK-OFF and serves ae 4 YTB LINE Erigger signal. The rectified mains source is roused to the FLYBACK CONVERTER, which generates the necessary voltages for the oscilloscope circuits. Each supply voltage is rectified ic the ‘The Lovevolta The 10. V REP supply serves as # low-voltage reference and is generated fin tho +10'V REFERENCE source Block. This referance voltage is also fed 0 the different circuits on the power tupply or in the ogcilloscope- Supplies are stabilized by eke CONTROL cizcufe to the ‘The ENT CONVERTER generates the “14 KV for the post-accelerator anode of the CRT and the -2 KV for the cathode circuit ‘The CALIBRATION GENERATOR generates the Chl voltage, which is applied fo the output socket XI. The CAL voltage hae a aquare-wave of 1,2 V Prp level vith @ frequency of 2 ie. ‘The ILLIMINATION CIRCUIT determines the amount of curcest passed co the graticule illumination lanp of the CHE, sonerolled by the TLLIM control on the feont=panel. ‘The TRACE ROTATION CIRCUIT determines the strength and sente of the curcent passed to the trace rotation coil around the nack of the ORT. ‘The current ie influenced by the front-panel ecrewdriver-operated ‘Mice ROT conteal: Fcep etreuite and control logic (unit A17 and A18) 2 | Te Pep unit jacorporates two mink CoD unity (one for each Ehannel), the PccD driver circuits and the PéCCD outpst cireutes. ‘The to mini CCD units are mounted ar separate units on the sain bosrd. ‘The vertical channels A and 8 for the signals to be gisplayed are Edcatical. Fach channel comprises an INPUT BUFFER, P4CCD, 6d and ‘even CTH (Clanp Integrace Hold) circuit and the ARALOGUE’ LEAKAGE. onRecrion.3.2.8 329 a3 Signa}s derived fran the A/D avitch on the adaptation unit are passing the heed civeuies, these Profiled Periateleic, Charged Coupled Devices act as analogue shift registers which are able fo store signal Sunples in a rhytim shat depends on the selected tine base speed. This Sayin is generated by the ACE, (Advanced Curtonised ECL) end via the ELGCK DRIVERS applied’ eo the P20CDs. For tingrbase. epeode which Cannot be handled by the ADC any more, che PECCD devices are used for [foe conversions, Teis neans chet sighal sanples can bs sampled by the peeps ina Nigh vhytim and later converced by an ADC circuit in & lover thyvtar This fowce ghyehe fe generates by the READ QUE COUNTER, Each channel contains # P°CoD which contains im ies eurn Evo rections of 256 tinal samples. ‘the Pcp is fully controlled by the ACE which delivers control Signals and which also controle the CLOCK DRIVERS. ‘The output of the PcoDs are applied to fast CIM circuits. These circuits ere able to hold the signal information for a tine that Le long enough for the tracknsndvhold clzcult to take then over. The CTH cireuit is controlled by the CoD and ADC TDANG. ‘The ANALOGUE LEAKAGE CORRECTION corrects the signals for leakage. doc eireuit (unit ALS) ‘The signal derived from the FccD unit must first be clanped into the coreact input signal for the ADC. This ADC converts this signal to fn f-bit digital word and ie able to perform conversios with & maxizim Speed of 50 kis, This coaversion is controlled by the 2CD+ADC TIMING. Signal processing wait (unit AL3 and Als) ‘the signal processing cizcuit consicte of an AVERAGE AD INTERPOLATION circuit, an ACQUISITION circuit and a DISPLAY eizcuit. It takes data Erm the ADC, pecforms calculation on st ané sends the date to. the ¥iphc Latch or it reade/writes the dats froa/to the pisroproceasor. ‘he address of the data ie put into the IODAC Latch. ‘The AVERAGE AND INTERPOLATION eireuit averages the differences decveen the odd and even channels ané calculates also 312 linear interpolated pointe between each of the 512 eanptes, The output data ie transéerred fo the ¥-DKC Tateh of to ehe menories. During tine intervals of 500 no each, che different éa:e teansports Scour in the following sequence: = date Se written in the ACQUISITION MEMORY, addressed by che Acqursition coven. . = data ie copied 0 the Bidirectional Tatch in the CONTROL ARRAY. 2 date is written in the DISPLAY MEMORY, addressed by the DISPLAT ‘coun. Finelly, during che lest tige interval the sieroprocessor ie connected to the DISPLAY RaW via the DATA BUS IATCH and ADDRESS AUS BUFFER. The deca feon the microprocessor can influence several functions such text, plot, dots, ete.a4 a.2.10 3.2011 WAC and DAC efreuies (unit A15) ‘The Y-DAC and X-DAC convert the S-bit data and 13-bit addroos Tnforation into anslogue sigaale again, Clitcher on the output of both Bice are renoved by the DEGLITOMER, Next the eignals are. fed via emackatolD circuit, éot-soin cfecuit, VERTICAL CHANNEL SWITCH e florizontat woot Sw15éH to che analogue eireuies. Microprocessor eystem (unit Al2) ‘the microprocessor aystem mainly consists of a powerful 6£008 uP, a RAM Tor date. snd. 2 ROM containing the system software. Ihe microprocessor iS euoning at a. frequency of 8 Mis provided by a CLOOK GENERATOR. TaLe generator in ite turn is deiven by £16 Mle crystal oscillator. umber of addresses resulting in the various adére ‘Leo the 11¢ busses are DECODERS decode Lines that are fed co the different circuit A SATCHDOG/RESET civeuit detects abnormal program sequencer via es Output port and verses the microprocessor vie the RESET aed HALT Lines in order to restare the program spain. ‘The STATUS input reads the aiéferent statue information of the instrument for the micropeccessor.4a ATTENUATOR UNIT (A1) VERTICAL ATTENUATORS ‘The A and 8 chamel attenuators are identical: therefore only channel A iz described. ‘Agi retey and FEE svitches aro controled by che micracamputer via the 12 Suse the TEA 1017 converte this serial DATA neo the parallel contzol signals for all relay of FET svitches. A list of the control Tines for all attenuator settings is given in the eable below. Figure 4,1 Table of attenvetor settings The channel A attenvator consists of io five stages: aput coupling, where depending on the relay K1001 position, the Tnputrignal ean either be d.cymcoupled (relay activated) of a.c.~ coupled (relay ot activated). igh ingedance attenuator with three attenuator stages for the xl, Sb aad ateo actesuations The 1.f. pare of each stage ta split via a Tesistor élvider and rouved via Ni00] end VI0I9 to the output of this Stage, where it is re-connected vith the A.f, part of the input signal Potentiometers R1O36 (TRACE Jump) serves a6 a offset compensation for wioo1 Lar, RESISTOR Divine a 1004 = no 003 uco7-e1011 x00 1002 1019-81004 Note that, whea "0" (GHD-A) is selected, the output is comected fo growed vie FET VIOUS end ail ather relay: and FET evitches are twitched off.The inpedance converter sever as an inverting buffer etvecit for ‘Te Tigh iupedance-aetenvstor. for the 1-f,-feodback the sutpue rigoal of thie stage ie routed to the L.f, summation poiat MIO0I-2 ‘The low inpedance attenuator reduces the gain by x1, x2.5 and x5, ‘Hepending Ge WaGN velay Te activated, ” 2s 3 1033 vs 1056, £1057 and R108 21053, "1056 and 81037 ve RLOSE The continuows circuit (090203), the differential input voltages ‘ST wick are foi to plore) and 3. ‘This stage comprises the following functions: = continuously variable control (pia 11). = Gain si (pin 2 end 3) with offset ajustment R1054 (R116) and pain sdjusement #1069" (R116). Gein r10 (pin § and 7) with offret adjusting RIO72 (R1172) and gein gjustnene BLOTS (RLII6)- = H1/x10 control to select the 2,5 and 10 a¥/01¥ sectinge ‘The differential output current from pin 13 and pin 14 is routed via ¢ circuit 1065, 1060 and applied to the pre-anglifier unit. EXTERNAL INPUT The external input can be subdivided into four stage Input coupling, basically einilar to ehe ch. input courting. igh impedance attenuator for the x1 attenuator only, vhere the ‘Toi equarecsave can be adjusted wien trimmer €1206.'Te Lif. part is Sffece compensation for RI20L. For 1.é.-feedbeck the output of the fnpedance converter is also routed to this tumation point lao reconstituted version of Note that the outpet of thie stege the input signal ec similar to the ch.A impedance Ingedance converter, te b hs differential mplifier VI2I1, 1212 converts the voltage feom ‘Zietevstellower VINO Tato the differential current vignele EXIe and EXT-. This signal ie applied co the prevenplifier unit and cerves a= external trigger signal or a¢ an external deflection signal, The current for this stage is applied fron current source T2139.[ee]sa sa PRE-AMPLIFIER UNIT (A2) ‘the preveaplifier unit consists of = Vertical pre-anplifier = telgger premaplitior I Precstifier control, incl, CHOPPER oxciliator Neyt, the adaptation unit AIG is mounted on this bosrd. This unit fe described separately in chapter 17. 11 control pulaes for ug spit are generated by the prevamptifier Control circuit, via the 190 bur (see Section 5.4). VERTICAL PRE-AMPLIFTER suse sue S82 Cosimo a ONT AB sn tocee{ of P| Poeuline Figure 5.1 The three stages of che vertical pre~aplifier ‘te vertical pre-anplifier consiste of three stages. ‘the signal splitter (0205) receives ite input signal for channel & THR tae rrectuator unit and copies thie signal into too identical aifferencial output current signals for: = Vertical channel (pin 7 and 10) Cte teiggering (pin 5 and 12), see section 5.2. ‘he output of pin 7 and 10 is applied to the edaptation unit Als. Stage 2 (unit 416), see the description of Al6. Stage 3 (02203) serves as delay Line driver whore the output current ‘SE both OWNTZD is convereed into voltage signel applied to the delay ine, The current for ehis stage and for 02001 snd 02202 {a fed vie 223i and R245. ‘The corrent regulation for the conmor-ode circuit is achieved by teameiator 02203 (12, 13, 14).5a ‘Th TRIGGER FRE-AMPLIFTER ‘Trigger possibilities are: Hoverted by: Signal fname, routed to nese outed t0 vas 0230202) em A [rmane, eae 2302(3,4) |e 02302(10) ch [fame, TaaM- 12302(5,6) |e 230201) [rma 0230207) Exiesa (Erte, "ext 2303(3;4) [een 02303(10) [awa 230302) line [uaKe pesos} ime 52303(11) lama 0230307) 02301 serves at a eignsl eplitcer and receives ies input signal from the attenuator unit, This Empat current elgeal {9 copied Into a [dentical differential output curzese sigeals for EXD MTB signal (pin 6 and 11) ‘te eymocrical output currents fron 02302 (13, 14) and 02303 (13, 14) tre converted into # symmetrical voltage again’ in the conmn-baze Eltcute ve16, V2319 folloved by @ shunt feedback circuit C2318 and Yabal, Note thet he eoneivivity ae the collectore of V2318 and V221 Te 110 aW/orv. point the wignal path is divided into: = a trigger path, fed to both ¥2333 and V2534, where depenting on the current to the base, levelling of the trigger signal ie sbeained. ip separate series feedback circuits take care of volsagercomcurrent # v2R41 and V2342 for tine-base exiggeris ‘The erigger output signal, TRIGI- and TRIGK are fad to the time bene unit Ad. + ¥2547'and ¥2349 for erigger level view. This smmatrienl output em be balanced by potentionetsr 2407. ‘The TAlove and TRIGH™ signals are fea to the agaptacion unit Al6. Integrated circuit D206 seeves as an auto Level circuit, The following Functions are poteible, Peskcpente in thie cave the amplitude of the trigger signal applied to 02306 (3,7) is maneured by poak-peak detectors on 12304 (2,43,8) . ‘The output current fron D206 (14,15) is dependent on tre pesk-peak Tovel and is adjusteble vith the LEVEL control RJ012, esmnected to paso). >. Triggering in thls case the level range {a 16 div. The level ip adjustable with 87012 and che current variation on 02304 (14,15) ean be varied Between ser 0,604. os I triggering The level control is nade ineffective. tn TV triggering, the LEVEL must be eet to a fixed value, This in done by applying & high Level current to. pin 1 via diode ¥2326,sa 53 4. ate Tn auto the signal LAVEL ZERO La high and via diode 2325 the output evel 2304 (15) is asymmetrical vith output Level b2904 (14). ‘Thus the maximum signal axpLicude is 2 Vprp. = an oyternal deflection path, routed via the series feedback circuit 72386 and 2957, the X DEFL? and X DEFL- signals are fed ro the tine Dave une a2. RDs16, K2422" and 2350 gives phase correction for the ICY display. PRE-AWPLIFIER CONTROL ‘the precanptifier control converte the data from the 1%¢ bus (SDA and Sci), derived from the nicroconpater, into the control pulses for the peevaaplifier unit, To eliminate interference the SDA and SCL Tines Con be evitehed off vie D2601. his integrated circuit serves ae 4 digital switch, controlled by the WET 116 line, Logic high connects the outputs D2601(414,15) to the Enpue "I" concact (avitehed on); logic Lov connects the outputs to the Ap Contact, (owltched off) and giver SDA's logic Low level and SCL a opie high level. sen D260] is avitehed on, the serial data information is converted {nee pareilel control pulses vie 02602 snd 02603, provided that D2602 Er cgabled (D2602-5 ia high). The control Lines ere active when the Level of the Tine {2 highs utput 12-02602(9) serves as a pover up not Line for 02603: when the Cecilloscope is in the power-up routine, Q12 is high and resets 02603, After the power-up routine, QI? goes lov snd enables 12603, Integrated circuit D2603 relieves the microcomputer of a number of = chop/att = trigger select I tlnerbase aelece (ed co cine base unit At) Adaptation of this 1.C. to the oscilloscope version is made by the ADO find ADL inputs 02603015, 16). For this escilloseope, ADO aust be HIGH and ADI must te LOW. ‘ining for alternate and chopped mode is derived by ee ALTCLN and cHoRct pulses. ‘the chopper oscillator formed by V2611 and V2612 eupplicn a square wave voltage of 1,5 Yprp with frequency of 1 Hz. Ee = 11 te determined by: ¥2612(e-e), C2611, R2627 and 82625. 112 Es determined by: V261L(ere), C2611 82628 and RI625. ‘the duty eyele (I1/TL+T2) fa 12% approx. frequency is defined by two current Loope: ‘the square wave on the collector of Y2612 serves ae a chopper clock Pulse for D2603 and gives 500 4s diaplay for 2 charnele CHOP, Bete aieplay for J channels COP and'250 kits for 4 channels CHOP Cacsereie VIE¥ADD). Note that 22603(8) serves as the chopper switch, which Le high vhen the CHOP eoftkey is depressed.et 62 63 XYZ-AMPLIFIER UNIT (A3) Unit A3 incorporates two separate pob’s which are connected via 13001. ‘One peb includes among other ehings the CRT socket an is connected at eonpeising the. proper final X and Z Snplifiere is situated at the upper side of the CRT. for ease of description, nit Ad is described as one unit. The XiZ-anplifier unit consists of = Final vertical (¥) omplifier. Z inel horizontal (3) amplifier, I Final omblaniing (2) amplifier, incl. ok. FINAL VERTICAL (¥) AMPLIFIER ‘the final Yanplifier receives its signal from the delay Line and fupplies the correct vertical eignel to the Y-deflection plates of the GRE. For this the eignal ie processed in four stages = ¥9001, 13002 as a seriee feedback amplifier, including « delay line compensation network snd potentiometer £3007 contrclling current: Source 13003 for coreaction af any unbalance in che Y-deflection Plates of the CHT, These circuits are connected betveen the emitters Of both transistors 4m thie stage the input voltage is converted into a current signal. ¥3004, 2006 as @ shunt feedback amplifier, which gives a voltage signal to the next stage. ¥9008, 3009 as a series feedback amplifier, including @ final RO~ correction network and potentioneter 43038 for geln adjustecnt oupensate the different CRT sensitivities. V3007 supplies « constant current of 60 mA, ive. 30.mA for each sida, Note that the output agsia supplies @ current signal. VS011, V3012 ae 2 common-base amplifier for bufferieg che final = seplifier to the Y-deflection plates, The maximum plitude on each Eefleceion plate ir: 30 mh x 655 2 = 20 ¥ approx. FINAL HORIZONTAL (3X) AMPLIFIER ‘me input current for X-deflection is obtained from tte tine-base Unit: (ref: X and Xe) end processed in three stages, vith cireuite in the following configurations: = VRIO1, 3102 as a common-base amplifier, The current "I" on the collector of both transistors determines the voltage scrose E3102 fd RO116, This voltage is about 1,5 V prp sod feeds the next stage = V3103, V3106 a8 a series feedback amplifier, including a RC correction network for optimus linearity of the trace. and potentioneter R118 for x1 anplifier adjustment, mowted between the emitters of both transistors, VS10h serves ae current source,64 = va112, V3114 are comected az a shunt feedback nplifier, with Teslotors R026 and A194 af che fecsback resistors, The transistor Cource are enitter followers V3109, V3Il1, This cigcuit server as the ftual final amplifier, wtich converes the deflection current into the proper deflection toltage for the X-deflection plates of the CRT. Hansiecors W108, W116 supply the bie FINAL BLANEING (2) ANPLIFTER AND CRT ‘The blanking current derived fron the 2 pr mit is routed. via conmon bare. amplifier’ V3200 and emitter-follover Vi201 to the ehunt-feecback amplifier V3202. This stage is fed by Corrent source ¥3203, shich gives @ constant current of wh. The Voltage on the collector of ¥5202 can vary between #5 V for unblanking sed.o35 V for fully blanking. Tele Zepulee way contain deer, 1of. and bof. componente to be applicd to grid Gi of the cit, Since Gl is at a cathode potential of ~2000 Y, Blocking capacitors ave required between Cl and the Z-anplifir Gerpute The hefs Component ie direstly routed vis blocking eapscitor call to cl. However, the dsc. and Lf, componente are blocked, s0 chess components five first modulated on a 300 kis carrier signal by V3207 aad V3208 to pene blocking capacitor ©3209, Then the signal is demodulated again by ¥i209 and VS211. Finally, the reconstituted dic. and 1-£, components fre added to the els component. Transistor V3251 forms a nominal 70 V zener circuit which provides the Woltage difference between the cathode and Cl of the CRT. hie Bi Voltage ensures blanking when ehere Le a0 iopue signal. For adaptation qo each ERT, this voltage can be varied becweon about 40 Vand 100 ¥ by means of F252 (SLACK LEVEL). Reristor B3254 maintains the filament AAC the sane potential as the cathode. Any ripple on the cathode voltage ie fed-back via transistor V3213 to the input of the Final 2-amplifier and added to the blankiag signal. his meane ther the differential voltage between Cl end the cathode of the CRI ie alvays fixed, Because this differential voltage determines the intensity of the spot, ae a result, the intensity is almost Endependent of ene rippte™ the amplifier stage V3253, ¥3254 and V3256 provides enplification for the range of the FOCUS control. The range of 0...+10 V gives a final Penge on G3 of the CRT of “1350 Vive» 1600 V. Resistor £2257 connects the INTENS control to the focus aijustment to neintain @ sharply defined trace at varying beightnes or optinun presetting of the GEOMETRY, the voltage on GS of the CRT Eset toa fixed Level of ~30 V. The ASTIGNATISN can be varied by sans of potentioneter #5257.a fire | a al [ te Al iF PEa TIME-BASE UNIT (A4) ‘the tinerbese unit consists of = Tringer amplifier © Sueep generator I x'bePt amplifier, incl. display mode evitch = torizontal premanplifier = Panplitier Ag a supplement, the timing diagram for ceveral conditions of che tine base is given in tection 76. ALL control pulses, for this unit are generated by the tinewbese contro! Glrenie, via the 12C bus. Integrated clecuics D4001 and D002 Convert this series DATA {nto the parallel control pulses, provided that LEN TBL, and DLEN 732 are HIGH. [TRIGGER AMPLIFIER + trignering ‘The eymetrical trigger current signals TRIO and TRIG are derived Fron the pre-anplifier unit and converted into the asymmetrical trigger voltage via the shunt feedback amplifier ¥4003 and V6006, The amplifier Of this trigger signal is the sumetion of the voltage svings acrore i002 and R003, whLen are proportional co che current sving of TREGN* fand TRIO, Ov teiggerio hon the signal TVMTB goes LOM, the nomal trigger peth is blocked via vi00S and V4007 and che trigger signal is routed via the 1 Telazer stage V4003.cc04018, Transistor 4009 serves to clip the synchronisation pulse and LINE/FRAME selection is obtained by 4016.na TIMING CIRCUIT (see figure 7.1) ‘The timing for the entice tine-base circuit is obtained by D103 Together with Lte associated components Figure 7.1 04103 configurationi103 has the folloving relevant pin connections Pin Name: INPUT-OUTPUT _ Description 1 stots ‘Tieinpot Selects the single cine-bete node. 2 Reser ‘ileinput __Stope the aveep and eterte the hold off sweep: 3 aro ‘Tileinput Selects the AUTO Erigger mode, the fine base ie freecromning after the last trigger polse. 4 mesti TMininput Selects the possibility to drive several functions (IESTOUT) in Combination with SHIGLE and RESET, 5 Tesrour Toupee 6 x oer TMisinput Activates the 21 ant 22 outpute, 1 we - 41,5. ¥ supply input. 8 avroriNg = fnput Re-time determination (100 wa) for 9 acme ‘Ti-output Discharges the TB-rveep capacivor(s). 10 sur SCIDUTT-input Determines the end of the TB-sweep. Monee SCHITT-input Determines che star: of the TB non iL-output Determines che blaning of the CRT. Bon TMl-output Determines the blanking of the CRT. ow - Ground. 15 vee - 45-V supply input 16 ore - not used 17 oma - not used, connected to ground. 18 om - sot used 19 asKoTB - ‘not weed 20° sore - sot used a) ‘Ti-output Determines the ALT clock pulse 2 suo SCHMTT-input Determines the end of the Hold-oft veep. 23 pms - ‘not uteds connected to +5 A. th 0s - ot used; conneeted to +5 A. 25 Ts aTL-input Determines the TE-wblanking (area) 26 Toa TML-input Determines che STARTS condition (Lou) or TRIG"D condition (HIGH) of the Drs. vom TTL-input } Determines the tine base display 2 ‘Tiieinput ) mode (both Low). ALL ScwurTT-inpues are at +2,5 7 level.ay 7.2 SWEEP GENERATORS 1% mm evap generator (see figure 7.2) su J [oe if ke t Figure 7.2 Simplified diagram of the tine-bace sueep generator he sawtooth charging current RolGT (and RUT) determines the sweep Speed via Cal13 (#cel14). ‘The efveuit dx controlled by the following adére = W40..MA2, for interconnection of 4102-3 to an input pin, hus iving six different voltage levels Ul with respect to a1h,6 V. = HAEED, for addition of Belts eo the seveooth charging circuit. I Gy. fr addition of CL1I4 to the sawtooth charging cireuit and for wltching over between calibration pot sneters R107 (30s8..-100u8) Sand RELOS (200 us. 00,5 )- ‘The voltage Ul can be continuously varied by moving che YAR TB Control £7009 fram the CAL position, Thus a sveep variation of 1:2,1s ‘he fuetion table for the eveep generator is given below: seep speed mao _| HEED | HC 50 na tae a 10 20 So 2 is 5 10 50 fe a rea NOTE: then MREED is lov, then RELAY is switched om. ‘the sawtooth current in fod to the buffer circuit, where the hf. sweep Componente (to 2.usec) are routed via GH16 and Vil18, V4119. She L.ts sweep components (0,5 sec+.-2usec) is routed via Néi03. Finally the time-base sueep voltage Je applied to the horizontal Aeplay mode skitehe + old-ote ofreute Dering the tine base aveep, capseitor Ch304 ie discharged. In the Tower swvepepeeds (lower then I0ve) capacitor chi02 te also discharged in W608, Alter che svoep, the capacitor(s) are charged via current Tource Vei04 uneil the voltage across Chi00 reaches the +2,5 V Level. This voltage is applied to Di103 as the SHO signal enc determines if the tine bese can generate a nev sweeps Depending on the HOLD OFF control potentioneter R701] adjustment, a part of the charging current Leaks avay via W430] and ehus Continuously varsation of the cherging tine (i.e, Rolé-oft tine) is btsined. shen BSIMTB goes LOA, the tine base starts to run again and Sie the sane tine C4304 (and C4302) are discharged again via ¥4309.6 1a. ns XX DEFL AMPLIFIER AND DISPLAY MODE SKITCH 4 DEFL anpti fier: ‘The circuit for converting the symmetrical X DEFL* and X DEPL~ signals into the ssyinetrical voltage, applied to che display gode evitch is Hlaneical to the trigger input. Aowever, his eircuie can be switched~ off by Hodes 14500 and V4S0S, provided that the X DEFL signal is HICH + Horizontal display node eviteh: ‘he three deflection signals for real tine base, digital tine base or K deflection are ovitched to the horisontal.prevenplificr via diode Svitches, These svitehes are under conerol of the signals X DEFL and 45, The output of the circuit ts applied to RiJOL on the horizontal preveeplifier stage, The logic table is given below: XpERL_[ 795 _| output 1 x DEFL eignat ° Digitel eine base ° Real tine base ‘The Zaviteh NAGOI is configured ax two differential amplifiers with ts comon current output Eo A625. The atage ie supplicd by a constant Current source vie pin 1 and pin’8. The inputs 21 end 22 re derived from the tines atage D6103 and determine the nbLanking of the ckT. For this oscilloscope 21 and 22 must be HIGH for normel intensity of The amplitude of the Z-curcent can be varied by the front-panel INTENS control AS001. The slider of this control potentiometer drives. the bese pin 2 and pin 7 of both current sourc O,s'ace+.50 usse, signal 2B is LOW and reduces the voltage to pin 2 and pin 7. Signal 24 is 2 sofevarercontrolled pulse to blank the trace when the AWPL/DIV avlteh Ls used. tn nomal condition, the fully current for CRT blanking derived feom A601 ie routed vie R4625, VSI? and R2626 to the 32 Aaplifier AS. However, there are tvo conditions for additional blanking: = tm the chopped node of the vertical channele the dfeplay is blanked ducing evitching over betwen channels. This happens by connecting the CHOPALW pulse co Vé6lI. Men this pulae is HIGH, traae Conducts anda part of the blanking current flove vie Vasll the #5 ky rails Af m HIGH tevel {2 applied to the external Z NOD input on the rear panel, chis signal causes conducting of W616 ao thet e part of the Blanking current flows via W6i6 ee eo the #5 kV rails16 m ‘TmMING DIAGRAM ‘te folloving figure gives the timing diegran for D416} for a free Funning tine bese sweep. ssc RESET avro fest xoerL. ‘Tors. H m bras Figure 7.3 Freerrunning sweeprtining diagranras 7.7 Time-baee uni8 CRT CONTROL UNIT (AS) jeter that control the ORT INTENS (RL), seveniriver operated TL (i between 0. 0 ve cee thea on of the Figure 6.2 CRT control unit pred.a on POWER SUPPLY UNIT (A6) Basically, the power supply unit consists of: = input efzeuit tecondary output receifiers BT supply (ht osefttacor oat control eireuie nur crrcvit ‘The insteument way be powered from # nominal maine volsage of 90 V.e.266 Vasc. The meine voltage {4 priary protected by a fuse of 1 AT, which is Tocated on the tear of the instrument After rectification by the diode Dridge V6001...V6004 4 d.c. voltage Es applieé to tne converter circuic. This voltage is smoothed by capacitors C6007, C6008 ani choke L6001. Depending on the maine voltage, the rectified voltage is 120 ¥...370 V, [A fined pare of the maing voltage serves as s LiNEcerigger signal. ‘he amplitude of the LINE trigger signal ie 1/22e MAINS. NOTE: The LINE trigger signal is not present when 4 dus. voltage serves NAINS. COMMERTER CIRCUIT (see figure 9-1 and figure 9.2) ‘the flyback converters consists of transistor V6OI4 anf V6OI8 and their Aesociated components, Te converter frequency depends on the LINE IN Gnplituie and is for 110 Vaer 30 hie appror end for 220 Vac! 45 ke Transistors V6014 and T6018 conduct on the forverd stroke and charge Transformer T6001, The thyristor V6OL3 fires when the voltage on the ete reaches the firing Level (0,6 V approm). Consequestly, V60I8 Stocks = Veo1s Blocks, for the duration of the flyback stroke, during which the secondary windings discharge via the diode ractifiers into the smoothing capacitors. The NIC resistor REOOS provides temperature Eoepeneation for the firing point of the thyristor. During the flyback, capacitor C6009 charges again vie the path 001"1,N6012, 16009, R600L, C6009, 16002 end 6001-2. sme voltage stabilizer with transistor V6009 giver » square-wave £0 The gate of traneietor W60l4 with a maximum amplituge 3f 15 Vs ‘tae dv/de Limiter with 16004, 16006, 6017 and 6019 serves to Glininate the witching spikte present on the collector of V6OI8 (oeaturing point X46).33 x SECONDARY OUTPUT RECTIFIERS he output voltages taken fron the secondary windings of transformer TOOL are rectified by diodes and smoothed by capecicors ia conventional cireuite, AU"CROWDAR" cizcuie with transistor V6137 and V6I12 protects the +5. supply. linen the +5 V level {a too Aigh, transistor V6137 (and V6112) conduct and the power supply goes into short circuit sade, A voltage protection circuit using V6134, 6136 and Y6l12 protects lagsinst overloads protection. When the power supply is overloaded, These components conduct and the pover supply goes into in the short= cireuit nodes Figure 9.3 HT oscillator he HT aupply consists of an oscillator and « regulator eircuit. ‘Teansformer T6201 determines che frequency (50 tlle appros.) of che ofcillator. The output signal voltage on the secondary wioding of T5201 4s rectified by diode ¥6209 and smoothed by C6211, The “2,1 KY fa aleo converted £0 -14,5 AV in the HT multiplier Dé201 and routed via connecter ¥6030 to the postnacceleration anode of the CATs ‘To rogulate this HT voltage the -2 KV is fed to the input of OPAMP é002, The output level of N6OO2 determine the explitude of the HT-voltase. the enerey to T6201, and thus caLTBRATOR The calibrator circuit conelate of two analogue svitches 06501(8-9) and 6S01(11-12) controlled by the active HIGH enable inpute.6 and 12 respectively, chat are connected ae an 2 kis asteble oseiflecor. Capacitor cb02 and resistor R6S04 determine the 2 Kil frequency. The oscillator outputs, applied to enable inputs 5 and 12 of the eecond Stage are in anci-phase with each other. Gepending on the Level of input 5 and 13, che CAL voltage will have a 1,2 Vilevel or #0 V level.ot ins lo-t FRONT UNIT (AT=AB) ‘The front unit consiate of: = the front controls end indicator T the 60 atsptay ‘The key matrix is connected to two remote 8 bit 1/0 ports RoW 1.1.8 is applied to D7001 and COLUM 1.4.8 ie applied to D7002. Dependig on the softkey which ts depressed, a certain ROX and COLA vill be influenced. Tis iz read by the SOA} Lise and thes by che The lines ROW 1, COL 1, COL 3, COL 5, COL 6 and COL 7 are also connected to the cursor nit 49 and ead the cursor softheys. [FRONT CONTROLS AND INDICATOR The frone-panel controls give a voltage between 0.4.10 V to the various circuits, To determine the UNCAL position of VAR A, VAR B or VaR DC, he de voltages on the slider of the potentioneter are applied to comparator 1001. When the voleege level of the control te lower thea O;7'v, the 1°0 bas reade a lopic highs Then the wictoproce the LED display to indicate the CAL avatus (e.g. no fla ssognent visible) Integrated circuit 07004 (OQUOKE) detects the kind of probe which ia connected to the oscilloscope. Deponding on the resistance between the probe indication input (pin 3 for channel A and pin 16 for ehannel 8) {ind ground, the V/DIV reading of the LCD automatically increases ‘ccording to the falloving table: Pin 316) [Pin 6 (17) _| Pin 7 (12) _| V/DIV attenuation py 6x98 Toe ‘cp piseLay exncurt ‘The LOD fe driven by three drivers DEOOL, 98002 and D8003 (PCP8S77), The temperature dependent supply voltage VOPCF in 4 V approx. at 25°C When the tenperature increares, thie voltage decreas The single-pin built-in oscillator on pin 37 of D800! provides the modulation frequency for the LED segnent driver outpute, Capacitor [7008 and cesistor A70IS are connected to thie pin to fore the oscillator, with « frequency of 150 Re approx. Fig 36 end’ pin 37 are ‘Sted to devermine the LCD river address tn the T2C busy outputs BPL and BP2 (pin 33 and pin 34) drive the COMMON pin of the pin 32 directly drive the LeD.Figure 10.1 Circuit diagram of fec narao12 aeee al | a we Figure 10.3 Circuit diagram of front unit, front controls and probe indicationmar ore tary of front unit, front controls and probe indication Figure 10.3 circuit diaFigure 10.4 Ud unit pred.10-10 w OO we Sa acne ‘Auevetview alr Bano cHor com mut acu sani Xe ‘AEATBACOE LM trot 2888851 ec STATUS ROU DOTS. or dactoeadensnondt = igure 10.5 circuit diagram of LoD unit1". MOTHERBOARD UNIT Figure [1.1 Yotherboard unit pic.2 OPTIONS (A11) ‘The optionslot on the Motherboard (connector X65) ie reserved for Optional expansions for this ineteument. Description of the option will be given in separate manuals.1B aa ae (CPU UNIT (A12) ergopvctrox ‘this unit mainly consiste of = powerful 68008 micropr Configuration with PROM, sédrest decoders, 1/0 buffers anda clock generator. The microprocessor rans at a clock frequency of 8 Mi. {he wicropraceasor has am asynchronous bus structure vith a 20-bit ldzese bus and an B-bit databor, Asynchronous geans tnat the Rieroprocessor.vaite for a "data acknowledge” signal before continuing. Jain enables the microprocessor to handle aifterent aztess tines in to provide specific serial data transfer,possibitities, the Rlefogeocessor aysten also contains an 12C bus interfe The ie bus is for Zway, Seline communication between different 103 Or modules, The three Lines are a serial data line (S00), serial Chock Line (SCL) and ground. Both Lines ust be connected £0 « positive supply via a pellvsp resistor vhen connected to the output Teages of a device, Data transfer may be initiated only when che bus fe'not busy. enone AP addgere range is uted, according to the sp gives ale the memory select #ignals, only a part of tho complet: following nenory nap. The penerated By device D201,Acdreas (hex) | Decoding Signet comected to ‘00000 na ronicst | 216-26 rere 20000 row nowzest - (aot sed) ower “0000 «0000 | soro0-ur warzo-ua ‘e000 | mbret-Lt MpovT-ut] werocsir | 202s 50000 S S serre 58000 | aseue-er— £0000) Ra rancs-tt | 217-20 ‘30000 1st terecsir | ps8 (optional) orrer roER macseut | ogtt-21 £0000 0000 | igital control bagel and verresir | pattie poo | nae "0000 verious psocs-t | nate ‘he signal MFIOCSLT is decoded again by 0202. shen ROWR—HT is high, thie determines the read statue of the decodsd siguale; when it ie Low Unis determines the urite reatur, The coding of MFlOCSET is ee follows: Read Write Addrers range (lex) 0000-478 worco-t | wmrre-tr ‘48000-4FFFF rorel-ut | wrovr-ur 50000-57FFF a . 58000-5559 aspirit 5 ‘Te signal DCPICSLT is decoded by D213 and, controlled by 416, gives the DAGCS-LT and DGPTCS-LT signals ‘The signal Ds0cS-UF is applied to che DCL unit AL3 and selects anos other things the acquisition RAM oF the diapley RAM.Bs 133 ccrncurr pescereTioN ‘the aferoprocessor D214 i connected vie the DATA bus 99...07 to the PROW D216, to che RIM D2i7, to the TOMER D2i8 and to the DoL wait al3, D216 containg 128K x 8 Read Only Memory, shile D217 contains aK x 8 Randon Accers Memory. Both devices are addressed via che ADDAESS bus. ‘me TIMER D218 consists of three seperate timers which are controlled by the microprocessor = GATE G forms the delay counter T chte 1 forms the read-out counter [GATE 2 toms the slow tine base. counter After the tiner has counted the value determined by the value on che Gata bur, the output becones Low. ‘The C-B08 DECODER decodes che DLEN eignats for the various circuits che tive that the signal MFOUT-LT {2 lov. Bt gives the folloving decoding Address (Hex) Signal ‘8000 ed Aa001 DLENT-a7 ‘e002 DLeNT2-aT 48003 ventic-aT ‘e008 DuEN-ar ‘e005 DUKA ‘006 Duna ‘48007 DUENA-aT Note that for servicing, soldering joints are added io the p.c.b. tracks egonecting the eiscuies, These can be usod co localize « fault [s'the 120 bus by means of Enterrupting the bus connes14 fete Figure 19.1 12¢ bur structure ‘The TIC bus interface 0222 decades the I2c bus and other signals at the Eine when WHIEGCLT Ls low, It gives the following decoding: Addrese Signal Detertpeion ‘40000 soa Serial date ‘0001 seu Serial elec ‘0002 see Selection TC bus 8 ‘0003 seul Selection 1¢ bus f ‘005 aera Resets 20 me einer 0207 40006 terng=et Wetehdog control ‘0007 weworeit | Monory on signal pet the slgnaly SDA, SCL, SELB and SELL are decoded to the TEC o bee ane Tc 1 bus by B228,ies ‘The STATUS INPUT device 0221 serves a6 an input port to read the Following statue logo! DELIRGLE, indication for delay erigger input sul; = SDA} indication for 10 1 bus zea} TCL | indication for 120 6 by Crestor! indication for triggered mode Topr-aiz, adapes the sofevare for optional expsnsfont Jinen the enable inputs RDICB-LT and RDICI“LT become lov, the statue Ynpue {a read and copied in the accuulator of the the deta bes. ‘The CLOCK GENERATOR consiste of # complete integrated oscillator of 16 mis (C201) and « nuabor of divider stages. ‘The table below giv the érequency of the generated signals. Nae Frequency soci 16 tie Pvc 8 te irreix | 160 we ‘The 20 ae interrupt device D207 interrupts the sicroprocessor each 20 me so that s new acreen can be wriecen. ‘The DIACK GENERATOR basically consists of D212, 0209 end D211. 1 ah Figure 13.2 OTACK generator ‘me microprocessor generates the address strobe ADSTo-iT as a message Chae the address pot on the address bus Lo valid. Thie signal is applied o212-3 and converted into che date acknovledge DIACK-LT siqnat.tais signal indicates chat the data is valid. She DIAGR-LT signal can be interrupted in two ways = display interrupt; ebie searee veiting @ nev trace A, By RA or RB. Nov FOB, Fl and #C2 are high wien the reqult that a lov Level is Sprtied ‘co 0209-13, This blocks the ADST path. = 20 me interrupt, this starts writing a new screen, Wen address Line AIS fe high, a tow Level is applied to D209-2 which also blocks the ADST path. Now DSOACKLT controls the DIACK-L pulae via B2l1-3 010206 takes care for a peripheral acknowledge.1.4 ‘moe MICROPROCESSOR RESET circuit consiete of the pouer-up reset and the vetendog circuit. After sviteningron, cransistor V204 conducts so that che RESET-LT and AALTILT signals are lovy initiating the main prosrax. Afcer the supply Noteages ere within their specifications the signals are released and the mleroprocestor {a ready for usa. ‘The wATCHb0e ie a facility co control the corract function of che Tofeweres In normal condition the WIDG-“AT fe highs his causes Ecpacitor C201 to charge. fot each 1,5 2 the MIDG—HT is low for Short wonent.so thet C20i in discharged again. hen the WIDG--HT signal Fernot active high, C201 will charge until D203-13 is lov 40 that’ pioscit goes high. Thie results in ¥203 conduceing 6o HALT-LT and RESEE-LT Secone lov, thus initiating the main progran again. SIONAL nase List Signal ome Description Signal Signal source destination() Wo16 Address bus pai baie - 0217 301 = 302, aost-ut Address strobe paz aie rect cru clock 208 pate cvewsvit Conversion counter ready 0218 03 - DA0s DO.e07 Dees bas pais Dale = BII6 ~ 303 DAGGS-LT Digital analog conversion D213 Diol chip selece ecu Detay counter cleck —_RBB6 pas DELTRGHT Delay eriager baie 22k - pace DoPresLt Digital potsmeter chip 0213, pia elect DisNA-A Data Latch enable ch. A 0219 xg6is - x9716 DIENB-NT Data Latch enable eh. B D219 x9el8 = 39718 DLENP-RT Data Latch enable D213 xo614 > x9714 prevanplifier putin ata Latch enable tine 219 x9613 ~ x9713, base 1 purwrant Bata Latch enable tise 0219 x9617 ~ x9717 base 2 DLENK-HT Bata Latch enable x p29 pai BSOACKLT —-—Digitel storage ose D314 2208 scknovlegpe soci Digicel storage one, R226 pais psocs-it Digital storage chip D201 paid select peruumit Display interrupt pais pate - R217 DIACK-LT Data acknovledge batt baie DIST-LT Data strobe pala aol ~ p202 - 06 ~ p213 — Dsi4 — D316 prre-Lt Delay trigger terminal D218 peelSignal mane Desceiption Signa Signet destination(s) 221 - peol ery Riot enevewtn 406 pais ¥00...2, Functional. cade 0, pate D209 maLicit ele v207 pale IACK-LT —_Taterrupt acknowledge D212 D201 ~ n209 - p211 TEEECIX EEE clsck aoe bits IEHECSLT IEEE chlop selece D201 208 YP120-LT __Tnterrupt priority Level 0208 Data MrTocstt MF input/output chip 20 202 Mrour-it AP output enable 202 pais MemoR-HT == Memory on paz Réol ~ R602 RANCS-IT Ram ship select D201 pai HOICO-LT Read THC bve 0 D202 paz RDICI-LT Read T1¢ bus 1 D202 Daal RDWR-ET ——Read/ Wrdte 303 aiz - pais - 306 = D303 READ-LT Read pais Dae REST--HT Reset wor DLU6 ~ D314 - pais RESET-LT east v208 RIO! = Dale > Dus ROMICS-LT ROW’ chip select pao pale RoW2OS-LT «ROM 2 chip select D201 = ASwI-iT. Reset incertupe poze 2207 RSTACOLT Reset acquisition 202 Déo2 - D403 set. Serial clock paz 223 scuo Serial elock 0 peal 223 ~ mio2 = 7001 ~ 7002 seul Serial clock 1 p22 22i ~ pata soa Serial date paz 2223 soto Serial asta 0 peal 223 - mol - 7001 ~ 7002 soa Serial daca 1 vaaa 222 ~ pala seo Select 0 paz p23 Select I D222 D223 Sweep ready Dios, baal Slow tine base baie Dalz - peor Slow tine Base clock 0d aia = ball TESYNCHT Time base ayachronisation D403 pais TESTO-AT Test out pels a2 TMRCS-LT Hace chip select aot 208 - 218 wenticnr Vertical 11C relect 219 ao. VLPRADLT Valid peripheral address 212 pais werio-ut —irdee Tie 202 222 WRITELT Write 213 DUG ~ 0217 ~ pata ‘re etchtog oa 3200rey Figure 13.3 circuit diagram of cPU wait, pert 1 oroia Figure 13.4 CPU unit p.e.b. a Se 8 BBD se Figure 13.5 circuit dlagran of CPU unie, part 24 He Be 24 Be Be 2 yb arsor3 my eriots Figure 13,5 Circuit diagram of PU wnit, pert 214 tat wa DCL UNIT (A13) ‘te DL unit consists of = acquisition menory with associated components 2 HiSptay wenory with sazociaced components control array, dots + plotter control OROANISATION OF THE MEMORY ‘The menory consiste of ¢ 6k x 6 static RAM (Random Access Menory) Di0e, and a 32 x8 acetic RAY D304. D308" is called the acquiition memory. DI04 is called the display memory, This device Le divided into: = dk cegister back-up memory © ik text memory Figure 14.1 organisation of the menory Notice that the display nenory is provided with ¢ betters back-up Cirevity then the insttunent ia svitched-off, che RAM D304 Keeps che Zale addrees in menory, provided thet the batteries are present. Addressing of the nenories is achieved by te counters, COUNTER 1 (5308) ané COUNTER 2 (D)06), oF by the mleroprocescor, Both count tre divided in three sinilar 12-Bft counters selected by the OS9-) 52 and Ost-pin 31 inputs, The TC output, pin 9 detects an overflow Counters These aignels ave applied co the control array D314, IWTRODUCTEON TO THE SAMPLE TRANSPORTS. he digital processor unit ining signals for the Eolloving sanple-tranepores = transport of signal samples from the ADC unit AIS to che acquisition enory. = Temaport of sigeal sanpl ainpley (trace) aenory. = transport of signal sanples fom the display (trace) memory to the = Reading/writing of signal samples by the ‘ieplay menory: sem the acquisition menory to the cor from/to the18.3 Ar woll as the counters, the acroprocessor is connected to the address bos BAB.ci 1h, the microprocessor is buffered with « lusbir eeivecate buffer Di01 and 0302, ‘The counters have access to the aidross bus Eequentially. Tea counter requires ascors to che address bus, this occurs in a certain eine interval of 500 ne and is controlled by the ‘signals ScB...sct, SC2 and SCS are inside the control array D3Ié and tee not visible, igure 14,2 Display cycle controlled by SOP... ‘me different sample transport are described separately in the next STONAL ACQUISITION Figure 14.3 Block diagran of signal acquisition During SoD and if WESMP is high the samples are taken from the fsverage circuit on unit Al4. These samples are put on the daca bus P00..7 and written in the acquisition memory D308, The addressing is obtained by the acquisition counter of D303.ae 5. ‘COPYING SAMPLES FROM ACQUISITION MEMORY TO DISPLAY MENORY Toa Figure 14.4 Block diagram of copying samples fron acquisition memory to display memory during SCI the date fron the acquisition manory ie rest by counter 1 309 and As written into the bicirectionel leteh of Dil&. Then during $2 the copy destination counter of D306 zoade the data from the latch and weites this data ineo ene display eenory D304. DISPLAYING OF TRACE AND RECISTER aE al fee Figure 14,5 Block aiagran of trace/regieter display flow During 803, the data from the display menory D304 Le seed by counter D306 and ie written to the T-DAC Latch Dll} on unit Ale, The ¥ addres: [edeterined by counter 0309 and is Latched fa D311 and D312, These addresses are clocked by the signal XYDLE generated by D314.MICROPROCESSOR MANIPULATION During Sch the signal DSOSEL-LT i lov, provided that DCOCS-LT is also Tov. his means that the addvest Lines’ AB...t4 from the buffers D301 fand D302 are enabled, AE tho sane cine the Reroprocessor bus Db.+.7 ie also ensbled via D303. Thi Tnflucnce. all micropraccssor controtled functions such a6 text, plot, dotay also addressed by the microprocessor. Durine Set ehe signal ZOE-LY applies eo pin 8 of D909 and 0306 is high Decause both counters are in their erivetate condition. For PLOT, the Eine that the dats is velteen to.che Y-DAC and che address ievwritten to the X-DAC ig adjustable in the service sons. DISPLAYING OF TEXT AND CURSORS west} -—[ae}- ve “mar L==e Figure 16,6 Block diagran of text/eursore dleplay flov ‘The text ig read from the display menory and addressed by the DISPLAY Y This text de displayed per vereical column. When the T-DAC data has lashed the control character AFF, the displey X counter receives Clockepulee, This neana thet che next colum is displayed.es 14,8 CLEARING THE DISPLAY wEWoRY Figure 14,7 Block diagram of the clear function lien the clear function is active by means of the elcroprocestor, the Gisptey wenory ia written vith £88 (BOB) by the C.P.U. This seane est the complete dieplay menory is cleared.6 14.9 CLEARING THE ACQUISITION xeMORY Figure 14.8 Block-dlagran of the clear function After the microprocessor has cleared the display menory, these fre written into the bidirectional Lateh by means of the copy source Counter of D305. Then the acquisition counter of D309 writes these Samples fron the Latch into the sequiaition memory. 14,10. ex0R 0307 1p P and Dl mode, the samples from the average circuit contain the fanples fron chatnels A and ® and also the interpolated sazplee. from Channels A and 3, This happens in ehe following sequence: adress 4095 9 1 2 3 8 5 6 ample ALA BLOB AL A BLA On behalf of the acquisition menory thie sequence must be face: address 4095 8 1 2 3 4 5 6 ample AC BL AB AL BL A ‘Te signal MWAS-HT is high for sanple A and interpolated sample B. ‘Tele rignsl te applied to input 10 of the exclusive Ok-pat> D307. ‘The other input is comnected to PAB. For address B, input 9 is low; because of the high level of INVAB-T the Gucput pin 8 vill be high. For address 1, input 9 is high; decause of the high Level of INVAB-ET the Gutput pin & vill be low, ete. Thus inverting of sdérees Line PAO doting canple A and Sa jarple B is obtained.ten waa 7 cup setecr Figure 14.9 Chip select circuit Lines AB and A13...A16 are applied to the control array led by the signi DSOCS-LT. The resulting enable signal EXCS-LT is low for the eddeesses £5000...$a5F7F, This signal te applied to the decoder device 0316 ar an active iow enable inpuc. then ioe, depending on the addressing of Al2.ort4y a chip setget ovtpat. te active Tov. Three Lines are used to seicct DEOL on the PAccD units two lines are used to select the two counters D306 or D309 and one Tine {2 used to select D313, OTS AND PLOTTER CONTROL Addressed by BAB...0A2 which are simultaneously with APs. A2 the aca on FOB Le appiied to one of the six output Linear These seat Vines DOTS-HT, PLOT-HE, PLPT, XPOSOF-HT, TRIGEN-HT aad OSGON-LT control several functions in the instrument such as among other things, the Dors end plotter.8 14.13 Tee racRAM ‘The folloving figure gives the tining diagran for the gate array D314 for the display cycles 1. im ens U amen A A A J l Figure 14.10 Timing diagram for D314 14.16 SIONAL wane LIST Signal name Desceiption Sigel Signal fource __deatination(s) foal ‘Adress bus ala baie ~ 027 ~ 301 ~ B303 BAD...2 Buffered address bus D318 306 = 0307 - D313, Do.lo7 Data bas Dae Dive = bal4 = bai? ~ n303, DATEN-RT Data enable poi bare Dow Due aol Duraost baoz Bate ~ D406 ors D3, 503 = D505Signal same Description Signa Signet destinacion() brerur DsoncK-t psoseL-at Dsoes-it excsit NOOESLT ovcux-rr slr osco8 Posxor-at PD0...7 Purr Resi-Lt Res2-Lt Resla-it Resae-Lt Rome RESET-H aeser-it aw Eu Sco-nt sel-at Swen TeWE-LT rel reir resleir your? sit Tort ‘TerceN-a 240,..18 2oNLt PAO 12 Digitel storage ofc. acknowledge Digital eeorage osc. Digital storage omc. Display interrupe eternal chip relect Invert address 0 WOH chip select NO output enable Mi clock Output logic clock Oueput setese I Oreiilator on control x Pos Buffered bidirectional Control signal plot Control signal peniise Rot chip select 1 Baw chip select 2 Raw chip eelect 1 buttered RAM chip select 2 Read/wrice Reset, bigh active Read? write Ra weite state counter 0 Seate counter 1 Tine base write Terminal count 1 Terminal coune 2 Terminal count ia Teller chip select Tellerchip select 2 Teller clock | Teller clock 2 Teller data ateobe Teller output enable Trigger eonble rite sample Bate fork DAC XAG and ¥ DAC Late Buffered trinstate larees us Control intensity pais pois aol pais baie Dior Dae pais pale pala pai 303 pai Dai pata Dai 307 pais pais Du v208 303 pate pais pais bai bale 309 Dans pate Dai pas pais pale ais Date D313 Buz D3t1/a12 pat 2206 aie 2309 ‘01 ~ paoa — 206 ~ 0213 — paid = D316 5203 203 Dua pus 307 Baia bal Dios aol 3306 aod 2555 308 ~ pai eos D303 hos - a6 ps2 Bsa Dae 3308 p30, paz pus naz Rist 3306 304 aor éo7 ~ pao D406: sol aot baa ste D308 306 0309 306 306 ~ 309 306 = 0309 io? - Dé02 ~ 40s Dae xso7 302 ~ D304 pais - wait — R213 ~ ost Date > bala 309 - D314 308 aoe = 204 soe 308went ssnersacnszones cen HEALEY EEE | a eras eecuaruies sence: pad # ® i eer nayaces Figure Ih.11 Cizcuit disgran of DCL wait, acquisition memory ereFigure 16.12 DCL unit puesbs wea Figure 14.13 cf17 Figure 15.5 Circuit diagram of ACL unit, part 218. 1s ‘ACL UNIT (A14) ‘The ACL unit consists of = trigger control 2 cep'# aDe timing C fverage and interpolation circuit the trigger control dotermines the start of the acquisition, 2 Ciging diageas of the trigger control ie given ia figure 13.1. econ WT was ES Figure 15.1 Tining diagean of the trigger control for TR = 5 us and PRE-TRIG =" 8 Ac the moment that TRIGIN-AT is low and RSPLI-LT becomes low, flip {ops 9403 and. DADE are reset. Now ICINV-LT, generated by the microprocessor, can go high after the fequitition counter hae counted the pre-trigger value. ‘Then TAIGEN-BT Es'high again so that the acquisition ie enabled. The high Level of TCINLT clocks D604, an a result D4OM~9 Le high and ‘LDL? ie enabled waiting for s new trigger signal BSIMTB-LT. Whon this fignal is low, then EDC-LT {a lov end starts the delay counter. At the moment’ that the EOC has counted, sigasl OTUF-HT is high which Snables 5402 and therefore SWIB is clocked through.15.3 cep + ane TENG ‘The clock pulse OLCIK-HT La derived from D314, The pulse is 800 Kz, for the P-aode and’ 640 kil for ‘the Denode end is appliog to the timer D409, Enabled by ¢ high level on pia 10, this counter operates and. the Sutpute QB (400/320 kia), Ql (200/160 wis) and Qz_ (100/80 KHz) are fed fo BUll, B408 serves for’ synchronisation between SCP and WISWD-IT. ‘the PAL (Programmable Array Logic) chip Déll generetes several control pulser for the display logic. The signals DISH-HT, DISODUET, RSTO, RESTEV, SAMPLE, NID end INTEV ve fed to the PecCD output circuit on unit Al. The signals STCON= Ty CHSELO-NT end CHSELL-HT are fed to the ADC on unit 415, Figure 15.2 Timing diagram CCD and ADC timing AVERAGE AND INTERPOLATION CIRCUIT ‘te ADC bus is generated on the ADCDAC unit AIS, This bus ts apptied fo thy signal processor device Del? The Picto‘is apiit up into two parce (EVEN and ODD channel) and the Eenples of he VEN channel have another gain and offset cian the ODD Ehuinel. DAl2 averages these differences ascording to the formula an + Gin = 1) ‘the output bus FOS... PO7 is applied to the memories on unit A13 for slay manipulation and £0 the YoDAC Leteh Dal. ‘When WOLE-HT is high, this device is enabled to teeeive the PD-bus and transfers it to the {OAOD... YOACT bes, Sle bus ie fed to the YodAC on the ADCDAC unit ALS. four least-rigaificant bits EDV... B03 are epplicd to the Piecd panel Ai8; These Lines preset the ACE on ehis unit.1s. STONAL me Lest Signal name Description asa RSELINT ven. Duna AOD Drsev-a DIsOD-#T Duraeat ure ED0..3 vA0-AT TnrEV-AT eto oueuxeat oscow 00.47 RetAcKLT RSTEV-LT RSTHRT RSTOD-LT SDA sco--er scl-et Seu Samp STCONT Sat sur reren-aT ‘route voaco.. Date bus from ADC eleeuit ‘cco read Channel select 0 Channel select 1 Sonversion counter ready Data enable Deta latch enable x Direct ode Direct mode Delay trigger Delay trigger underelow Buffered data bus Enable delay counter Enable conversion counter Invert & Invert aaére Integrate odd Mid clock NO output enable Output’ Logie clock 1 auffored bidirectional Reset acquisition Reset odd Reset slow clock Serial dete 1 Seate couter 0 State comter 1 Seriar clock 1 Sample clock Cr Beart conversion Slow clock Slow tine bare clock Sweep ready Slow eine base Tine base synchronisation ine base synchronisation Transport clock even Terminal count is trigger enable iirite sample pag and” Y DAC Latch, coable Data bus for ¥ DAC Signal signal fource _dertination(s) 501 Die pelos Baad 83 aod pant pall D501 pall 501 218 403 - DAos Das Bae Dag Dee pala baie Dalz base macs pati - 922 aoe oil ~ 922 pace 3:4 = B46 eae boiz RAIS... .RAI7 BNL Ra ant - pgor Be Da paz Dao? Duo? ban? Rall Dail R409 sot Date Daz pala pag pala int ~ D409 pais Dott = D408 = Dent = Ra62 03 Daa 202 aoa ~ D403 Rio? a7 Dae baat biot bana R406 a R07 Deo. a2 na13 ~ D412 paid Duo? = D408 bale aoe baa Bula R08 Dull ~ D922 pall 50 Ral? er 609 pale = pai bios Dank ios Daa pais. bald ~ peor ios buoa = Dal? 403, bala Bae Dadi = Déog ~ DAIL paid ia bu03 bala pais lod ~ p4os ~ D406 Dalz Baia baie ma? pais 506