AC wall attach or

DC plug attach
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V_5P0STBY tV1P1STBY
from PSU

V_1P1STBY
from VREG

VREG_1P1STBY_PWRGD tV1P8STBY
from VREG to VREG_V1P8STBY_EN

V_1P8STBY, V_BAT
from VREG
VREG_1P8STBY_PWRGD tV3P3STBY
from VREG to VREG_V3P3STBY_EN

VREG_3P3STBY_IN_SEL
from SMC to VREG
seqStandbyPowerUp (page 2/8)

V_3P3STBY
from VREG

VREG_3P3STBY_PWRGD tOSC
from VREG to TestPoint tPOR

25 MHz XTAL
from SB.OSCO to SB.OSCI

SMC_RST_N
from SB.POR to SMC Clock/ Power stabilization
time in SMC
sb_stby_rst_n tSMCS tSMCBOOT
SMC Firmware is running
(SB internal)
TODO: Add 25MHz Ethernet clock?
Or must that be enabled by the OS after
first boot?
VREG_V5P0_DUAL_SEL0
VREG_V5P0_DUAL_SEL0 may change during console operation,
from SMC to VREG but from here on V_5P0DUAL
V_5P0DUAL should always be powered by
TODO: add configSBPowerUp V_5P0STBY or V_5P0, except in fault
from FET SWITCH
conditions

Console Operating SMCBoot and

StandbyInit Standby
Mode SMCInit

Power Sequences seqStandbyPowerUp seqStandbyInit

 Power On request from
Front Panel, IR, ODD….

PSU_V12P0_EN tV12P0_PG
from SMC to PSU

V_12P0 from PSU

V12P0_PWRGD tV5P0
from SB.VEXT_OK to SMC/Bleeder

VREG_V5P0_EN tV5P0_PG
from SMC to VREG

V_5P0
from VREG

VREG_V5P0_PWRGD tV5P0DUAL_MAIN
from VREG to SMC

V_SB1P8PLL, V_SB1P8IO
from VREG to SB

V_SBCORE, V_SB1P1PLL
from VREG to SB

VREG_V5P0_DUAL_SEL0 tVGROUPA
from SMC to VREG

V_5P0DUAL
from FET Switch

VREG_PWRGPA_EN tVGROUPA_PG
from SMC to VREGs

V_3P3
from VREG
Once these signals transition, they remain in
V_SOC1P8PLL (VDD_18) their respective states until seqPowerDown*.
from VREG to SOC
* -- V_CPUCORE and V_GFXCORE are
V_MEMIO(AB|CD) (1.5 V) under the control of the OS’s power manager,
seqPowerUp (page 3/8)

from VREG to SOC/Memory per the AMD SVID2 Specification.

VTT_[ABCD] (0.75 V)
from VREG to SOC/Memory

SVC & SVD “Boot-VID” or “Metal Strap”

from SOC to VREG value by SOC

VREG_PWRGPA_PWRGD tV3P3STBY_MAIN
from VREGs to SMC
tSBPU tSBPU_DONE
VREG_3P3STBY_IN_SEL
tVGROUPB
from SMC to VREG
SMC runs
VREG_PWRGPB_EN tVGROUPB_PG
seqSBPowerUp
from SMC to VREGs

V_FUSE (0.85 V – VDD_085)

from VREG to SOC

V_SOCPHY (0.95 V – VDD_095)

from VREG to SOC

V_NBCORE (VDD_NB)
from VREG to SOC

V_MEMCORE (VDDCR_MEM)
from VREG to SOC

VREG_PWRGPB_PWRGD tVCPU
from VREGs to SMC

V_CPUCORE (VDD_CORE) Enabled by

from VREG to SOC SMC via I2C
tVGFX

V_GFXCORE (VDD_GFX) Enabled by

from VREG to SOC SMC via I2C
tVCPUGFX_PG

VREG_CPUGFX_PWRGD tCLOCK
from VREGs to SMC

SOC_*_100M_CLK[PN] Clocks enabled

from SB to SOC by SMC
Note that this is a part of seqUnReset,
SOC_PWR_OK (PWROK) tCLOCK_OK
but is shown here to give context
from SMC to SOC
to how seqPowerUp flows into seqUnReset.

Console Operating SMC runs seqSBUnreset

Standby GoingActive
Mode

Power Sequences seqPowerUp

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