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Realization of Direct Digital Synthesis Generators Based on FPGA and PSoC

Integrated Circuits

Conference Paper · June 2010

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 Realization of Direct Digital Synthesis Generators
Based on FPGA and PSoC Integrated Circuits
Eltimir Ch. Stoimenov1 , Georgi S. Mihov2 and Ivailo M. Pandiev3
Abstract – This paper presents an implementation of a Direct
Digital Synthesis (DDS) generator incorporating FPGA and
”System on Chip“ (PSoC) technologies. The DDS is a digitally-
controlled method of generating multiple frequencies from a
reference frequency source. An evaluation board equipped with a
FPGA Spartan-3A and a PSoC (from Cypress Inc.) integrated
circuits were used for development. PSoC is a programmable
integrated circuit obtaining certain analog and digital recourses
with general purpose. In the current research the FPGA is
synthesize sinusoidal, or other, signal in digital form. The
synthesis itself is achieved by a Look-Up Table (LUT) containing
256 samples. An UART interface is used to transfer the
information from the FPGA to a PSoC where an 8 bit digital-to-
analog conversion (DAC) took place. Moreover, a two pole low
pass filter (LPF) and a programmable gain amplifier (PGA) is
incorporated in the PSoC. In addition the parameters of the
created DDS generators can be controlled by a personal
computer through a USB interface.
the signal at each location drives a Digital-to-Analog
Converter (DAC) which in turn generates the analog output
signal. Nowadays, one of the most effective techniques for
realization of DDS generators is by using Application Specific
Integrated Circuits (ASICs) with fixed electrical parameters
(such as the DDS function generators from Analog Devices)
or by developing electronic circuit based on FPGA (Field
Programmable Gate Array) and PSoC (Programmable-
System-On-a-Chip). The FPGA ICs are becoming more
popular and are used in many mixed-signal applications [6-8].
To the authors’ knowledge, DDS function generators based on
FPGA and PSoC ICs have not yet been reported in the
literature. It is, therefore, the purpose of this paper to present a
programmable DDS function generator employing FPGA and
PSoC ICs.

Keywords – Mixed-signal systems, Function generators, Direct

II. DIRECT DIGITAL SYNTHESIS (DDS) : GENERAL
Digital Synthesis, FPGA, PSoC. OVERVIEW
A frequency synthesizer, including DDS, generates mul-
tiple frequencies from one or more frequency references.
I. INTRODUCTION The block diagram of a classical DDS system is shown in
Fig.1.
n
The function generators have been found useful in many
n = 24 - 48
applications, such as analogue and mixed-signal processing,
Phase Phase to
telecommunications, and measurement systems. Additionally, Serial or
parallel
n Delta
phase
n n
register n amplitude

the principals of oscillation can be extended to construct other load

register
register
M
+ converter

Clock
types of generators, such as voltage-controlled oscillators n = 10-14
Frequency control Phase truncation
(VCOs), quartz crystal resonator sensors, voltage-to-frequency M = tuninig word 12 bits
fc
converters, etc. [1-4]. The traditional hardware realization of System clock
DAC

function generators uses closed-loop analog circuits with Amplitude

active and passive elements or digitally-controlled method of
generating multiple frequencies from a reference frequency
source called Direct Digital Synthesis (DDS) [1]. The main
advantage of the DDS generators is that the typical amplitude
stabilization is not higher than 0,01% and the typical THD is
0,1% [5]. Generally, the DDS generators are a type of
frequency synthesizer used for creating arbitrary waveforms.
In them stable clock oscillator drives a Programmable-Read-
Only-Memory (PROM) which stores one or more integral
number of cycles of a sine waveform (or other arbitrary wave-
form, for that matter). As the address counter steps through
each memory location, the corresponding digital amplitude of
1 from 0° to 360° . The LUT contains the corresponding digital
Eltimir Ch. Stoimenov is with the Faculty of Electronics, TU-
Sofia, Kl. Ohridski 8, 1000 Sofia, Bulgaria, E-mail:
e_stoimenov@tu-sofia.bg
2
Georgi S. Mihov is with the Faculty of Electronics, TU-Sofia, Kl.
Ohridski 8, 1000 Sofia, Bulgaria, E-mail: gsm@tu-sofia.bg
3
Ivailo M. Pandiev is with the Faculty of Electronics, TU-Sofia,
Kl. Ohridski 8, 1000 Sofia, Bulgaria, E-mail: ipandiev@tu-sofia.bg
truncation
OUT
LPF
Fig. 1. Block diagram of DDS system.
The heart of the system is the phase accumulator whose
content is updated once each clock cycle. Each time the phase
accumulator is updated, the digital number, М stored in the
delta phase register is added to the number in the phase
accumulator register.
The truncated output of the phase accumulator serves as the
address to a sine (or cosine) look up table. Each address in the
look up table corresponds to a phase point on the sine wave
amplitude information for one complete cycle of a sinewave.
The LUT therefore maps the phase information from the
phase accumulator into a digital amplitude word, which in
turns drive the DAC. Because of the symmetry of the sine
wave, only data for 90° could be use for reconstruction.

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 For an n-bit phase accumulator (n generally ranges from 44
to 32 in most DDS systems), there are 2 n possible phase
points. The digital word in the delta phase register, M,
represents the amount the phase accumulator is incremented
each clock cycle. If f c is the clock frequency, then the
frequency of the output sinewave is equal to
M × fc
f0 = . (1)
2n
This equation is known as the DDS “tuning equation”. The
frequency resolution of the system is equal to f c / 2 n . For n =
32, the resolution is greater than one part in four billion [1].
III. DDS FUNCTION GENERATOR DEVELOPMENT
BASED ON FPGA AND PSOC
In our development the DDS generating core is
implemented on a FPGA, which allows best versatility and
makes the design open for constant improvement. VHDL is
used for programming FPGA IC. On the other hand the DAC
function is accomplished by a PSoC from Cypress Inc. Using
the PSoC technology also allows implementation of the LPF
and PGA on the same integrated circuit. The above functions
of DAC, LPF and PGA are realized by the graphical editor of
PSoC Designer IDE from Cypress Inc.
Xilinx® Spartan®-3A Evaluation Kit from Avnet is used as
a development platform for realization the circuits. It poses
the following key features related to the current design [9]:
-Xilinx XC3S400A-4FTG256C Spartan-3A FPGA;
-Cypress 8C24894 PSoC;
-USB connectivity.
The block diagram of the Evaluation Kit is shown in Fig. 3.
The blocks of interest are patterned.

I2C Two 8-pin

The current paragraph discusses the particular hardware and Headers

software realization of DDS function generator. Also the I2C_temp

_sens
objectives and the approach are presented. User
I/Os
SPI

Done

A. Objectives SPI_ LED

memory

12MHz Clock User

USB LEDs
32kHz
Spartan-3A
Design a function generator with the following parameters: Controller
(PsOC) GPIOs
UART
XC3S400A
Ft256
JTAG

Parallel Flash
- Output signal forms : sine, triangular, square; JTAG
conn
Memory 4M x 8
/ 2M x 16

- Frequency band : 0 – 2 MHz;

- Frequency tuning method : digitally - minimum 8bits USB
Conn
Config
Mode

resolution;
- Amplitude tuning method : digitally;
16 MHz

- Output signal amplitude : ±10V; “Push”

- THD: 0.1% Buttons

- PC connectivity: via standard USB ports. 5V_USB

Power
3.3V

5V Supply 1.2V

B. Approach
Power
Jack

Fig. 3. Spartan 3A Evaluation board.

In order the above objectives to be achieved a DDS function
generator is designed with the block schematic shown in Fig.
2.
DDS_core DAC LPF PGA
U0
Fig. 2. DDS development block diagram.
The DDS core, shown on Fig. 2, generates a digital signal
with a sine, triangle or square shape and passes it to a DAC.
After the conversion the analog signal is filtered by an anti-
imaging second-order Low-Pass Filter (LPF) and amplified by
a Programmable Gain Amplifier (PGA).
The block diagram of our DDS function generator develop-
ment is presented on Fig. 4.
As it shown the FPGA contains the DDS core which
generates different waveform signals, according to our
objectives. The generated signal is transmitted through UART
interface to the PSoC for further processing.
The PSoC itself contains all the necessary blocks for digital
to analog conversion, filtering and amplifying the output
signal. Moreover the embedded USB interface is used for
communication with a PC. The control unit block decodes the
commands sand by a PC. Than it adjust the gain of the PGA
or transmit a command to the FPGA for frequency tuning or
signal form. The programming of the PSoC is done on C
programming language. The algorithm flowchart of the
control unit is shown in Fig. 5.

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 Uo
Contr. Unit UART UART DAC LPF PGA

GAIN
SINE_wave TRIANGLE_
wave

SQUARE_ DDS_core Control options:

wave
- wave form Contr Unit USB
- frequency tuninig
-amplitude tuning

FPGA PSoC

Fig. 4. Block diagram of DDS function generator.

On the other hand the digital section contains an UART

START interface for communication with the FPGA. Also a 16-bits
Timer for FPGA reset impulse production is implemented.
The reset impulse duration is about 1s .

Valid command NO
from the USB?
DBB00 DBB01 DCB02 DCB03
3
TIMER16_1 UART UART
TIMER16_1
TIMER16_LSB TIMER16_MSB TX RX
TX Clock Out
YES Capture CompareOut
TermCountOut
RX Input
RX Clock Out
Command for:
Command for:
-Wave form
-frequency

DIGITAL CONFIGURATION
-Gain

BLOCKS
7 GIO 0 7 GIE 0 7 GOO 0 7 GOE 0
RIO[0]
RIO[1]
RIO[2]
RIO[3]

DBB00 DBB01 DCB02 DCB03

Send the Adjust the 3

TIMER16_1 TIMER16_1 UART

UART
RX
TX
command to gain of the PORT_2_1
TIMER16_LSB

Capture
TIMER16_MSB

CompareOut TX Clock Out

RX Input

RX Clock Out

the FPGA! PGA! TerminalCountOut TX Output RX Output

RIO[0]
RIO[1]
RIO[2]

Fig. 5. Control unit flowchart. RIO[3]

PORT_5_0
PORT_5_2

The DDS core block from Fig. 4 incorporates three sub PORT_0_3
PORT_0_5

blocks. Each of these blocks produces one of the three output 2

ACB00
2
ACB01
PGA
GAIN

shapes – sine, triangle or square. The sine wave sub block has
Input
AGND
AnalogBus
Reference

the block scheme represented in Fig. 6. ASC10

DAC8
ASD11

LPF2
MSB FLOUT
CompBus

AnalogBus AnalogBus

ftw_i(N-1...0) phase(M-3...0)
ASD20 ASC21
+ z
-1
+ z
-1
0
1/4 sin
0 ampl_o(P-1...0) DAC8 LPF2
- + 1
LUT
-
LSB FLIN
Input

1
buf 0 buf 1

M-2
2 -1

phase(M-2)
phase(M-1)
phase_i(N-1...0) phase_o(N-1...0)

ACB00 ACB01
Fig. 6. Sine wave sub block. 2 PGA
GAIN
Input
ANALOG CONFIGURATION

AnalogBus
AGND
Reference

As it can be seen from the figure only one quarter of the

ASC10 ASD11
sine-wave is stored in the LUT, the rest is computed by simple
BLOCKS

DAC8 LPF2
operations (negating, subtraction), resulting in a reduced MSB FLOUT
AnalogBus VompBus
memory requirement. The resolution of the frequency tuning
word (FTW), the phase and the amplitude can be defined ASD20 ASC21

DAC8 LPF2
separately [10]. LSB FLIN

A screen shot taken from PSoC Designer IDE (Cypress Input

inc.) is presented in Fig. 7. As is shown in the “Analog buf 0

buf 1

Configuration Blocks” section the 8-bits DAC is connected

with a second-order anti-imaging LPF. The filtered out signal
is passed to a PGA for an output signal amplitude adjustment. Fig. 7. PSoC Designer IDE – DDS project screen shot.

789
 Fig. 8. Sinusoidal output signal. Fig. 9. Triangle output signal. Fig. 10. Square output signal.

Solution: Buffering and amplifying the signal from the

IV. EXPERIMENTAL RESULTS AND DISCUSSIONS PSoC will resolve the problem.
This chapter presents some oscillograms from the experi-
mental studies. The following technical equipment was used: IV. CONCLUSION
Xilinx Spartan – 3A Evaluation Kit; Tektronix 1002B
Oscilloscope (oscilloscope setup: AC mode and 10X probe In conclusion we can restate that DDS is very modern and
attenuation); Personal computer. pliable technology. It allows flexible control of all the para-
Fig. 8 through Fig. 10 shows the sinusoidal, triangle and meters of interest. Moreover the technology is not resource
square output signals respectively. The signals amplitude and demanding and is convenient for implementation in micro-
frequency are 1V and 114 Hz , respectively. processor and mixed signal systems. Also using a FPGA and
After analyzing the results a comparative table between the PSoC ICs greatly reduces the design workload and makes the
desired and achieved results could be make (Table 1). system even more flexible.
By our personal opinion the objectives stated in chapter III
TABLE I are fulfilled sufficiently. Of course, the main problems,
COMPARISON BETWEEN DESIRED VALUES AND ACHIEVED described in chapter IV, should be addressed in future deve-
EXPERIMENTAL RESULTS lopments.
Parameter Desired Achieved
sine, triangular, ACKNOWLEDGEMENT
Output signal shapes DONE
square
Frequency band 0 – 2 MHz 0 – 200 Hz This paper is a part of a project under contract №
Frequency tuning digitally / minimum 102pd209-3/2010, which is sponsored by the research
DONE program of the Technical University of Sofia, Bulgaria.
method 8bits resolution
Amplitude tuning DONE – 16
digitally
method levels REFERENCES
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±10V 0 - 3.3V
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