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  • Feb 2021

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    DK Chaitanyaraj Singh
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    Feb-2021 (3)

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    3 views2 pages

    Feb 2021

    Uploaded by

    DK Chaitanyaraj Singh

    Copyright:

    © All Rights Reserved
    Download as PDF or read online from Scribd
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    Save trees use e-Question Paper Go green DOWNLOAD THIS FREE AT www.viuresource.com 5 eer, compuly dw apn nson erm Ha ein pelea reat wien op, 3e8- #0 ib reed a mpi, : 1 Note: Onconpleia 30 2 Ayame CBCSISCHEN we [TIT] U ames ‘Third Semester B.E. Degree Rxamination, Jan/Feb, 202 Digital System Design > Tine: 3 es Masa 00 Nees Aner ay FIVE el question chasing ONE fl modal ‘Medule-1 ningfhe combinational logic (06) amples. (o4stass) 4 Define combinational logic. List the various circuit and explain witha block dingram. 'b. Explain the canonical mintem und maxterm form’ ‘¢. Simplify the Boolean function using Kemap fol P= feb, c,d) = Fm(2,3,4, 5, 13,15) +268, % > fs 2) MCE, 3, 1 12, 13, comans) a t s sion and implement the funetion using 20,22,25,27,28,30). au ntarksy (2 Marks) 8. Design a combin that will convert BCD digit to Fxcess-3 RCD digit sing gates, Je and simplify each output equation using K-maps. 0 Marks) b. Design a binary er usigB only 2-input NAND gates. Construct a truth table and write | Boolean expiassion ‘and CARRY. (7M) © Design a4 Ui line decoder by cascading 2 to 4 line decoders which has the active low ‘output enable input (05 Marks) or a 'g Boolean function using 8 | MUX with ‘wy as select inputs 3m(0, 1, 2,5, 7,8,9, 12,13). (soars) parallel adder/eubtact using 4-fill adders blocks. Explain its operation if it should act as adder and if C= 1 the circuit at as subleaclor. (08 Marks) sign #Wo-bit magnitude comparator with help ofthe truth table and simplitiation of the ut equations using K-maps. Draw a logic diagram. (00 Marks) Modute-3 ‘Explain the operation of SR Latch act a

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