Sample Question Format

(For all courses having end semester Full Mark=50)

KIIT Deemed to be University

Online End Semester Examination(Spring Semester-2022)

Subject Name & Code: COA(CS- 2006)

Applicable to Courses: B.Tech 4th Semester

Full Marks=50 Time:2 Hours

SECTION-A(Answer All Questions. Each question carries 2 Marks)

Time:30 Minutes (7×2=14 Marks)

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Q. M Question -1 on concept 1 CO A
No: C Consider a main memory size is 1024words, cache memory size is 64 4
1 Q words and block size is 8 words. If 570 word of main memory is
mapped to cache memory then obtain to which cache block it will map
to and the tag value of respective cache block in direct mapping?

A. CB-7, TAG-1000
B. CB-6, TAG-100
C. CB-7, TAG-1100
D. CB-6, TAG-110
M Question -2 on concept 1 CO A
C Consider a main memory size is 1024words, cache memory size is 64 4
Q words and block size is 8 words. Find no. of tag comparator for direct,
associative and 4 way set associative mapping?

A. Direct-1, Associative-8, Set associative-4

B. Direct-1, Associative-4, Set-associative-8
C. Direct-1, Associative-4, Set-associative-4
 D. Direct-1, Associative-8, Set-associative-8

M Question -3 on concept 1 CO A
C Consider a main memory size is 1024words, cache memory size is 64 4
Q words and block size is 8 words. Find tag memory for direct,
associative and 4 way set associative mapping?

A. Direct-32 bits, Associative- 56bits, Set-associative-48bits

B. Direct-24 bits, Associative-48 bits, Set-associative-56 bits
C. Direct-32bits, Associative-48 bits, Set-associative-56bits
D. Direct-24bits,Associative-56bits, Set-associative-48bits
M Question -4 on concept 1 CO A
C Consider a main memory size is 1024words, cache memory size is 64 4
Q words and block size is 8 words. How many multiplexer are used for
direct, associative and 4 way set associative mapping?

A. Direct-4, Associative-0, Set associative-24

B. Direct-4, Associative-0, Set-associative-6
C. Direct-0, Associative-4, Set-associative-24
D. Direct-0, Associative-4, Set-associative-6

Q. M Question -1 on concept 2 CO A
No: C Which memory chip provides least no. of external connection to 4
2 Q provide 2048 memory cell.
A. 1024 x 2
B. 512 x 4
C. 256 x 8
D. 128 x16

M Question -2 on concept 2 CO A
C Which two memory chip provides same no. of external connection to 4
Q provide 2048 memory cell.

A. 1024 X 2, 2048 X 1
B. 64 X 32, 1024 X 2
C. 128 X 16, 512 X4
D. 256 X 8, 128 X16

M Question -3 on concept 2 CO A
C How many chips required of size 128 x 16 to design 512 x 32. Also 4
Q find the decoder size.

A. No. Of chips=8, Decoder size=2:4

B. No. Of chips=8, Decoder size=3:8
C. No. Of chips=4, Decoder size=2:4
No. Of chips=4, Decoder size=3:8
M Question -4 on concept 2 CO A
C Consider a cache with write back protocol where cpu will write only 4
Q in cache, where write hit is 80%, cache access time is 2msec, data
transfer time between cache and main memory is 100msec per word.
 If block size is 8 words then find average access time.

A. 322 msec
B. 284msec
C. 162msec
D. 150msec

Q. M Question -1 on concept 3 CO B
No: C Which one is exponent value and matissa value to represent a NaN(Not a 5
3 Q Number)
A. E'=0, M is not equal to 0
B. E'=255, M is not equal to 0
C. E'=255, M =0
D. E'=0, M =0
M Question -2 on concept 3 CO B
C Find the Hexa decimal number represention of memory to save a number - 5
Q 37. 25 in IEEE single precission format.
A. 4 2 1 5 0 0 0 0
B. C 2 1 5 0 0 0 0
C. 4 2 1 7 0 0 0 0
D. C 2 1 7 0 0 0 0
M Question -3 on concept 3 CO C
C In division process after subtraction, the content of accumulator is negative, 5
Q then which option is not true
A. 2A+M
B. Left shift of accumulator and then add M to A
C. Subtract M from A, then Left shift of accumulator and then add M to A
D. Add M to A, then Left shift of accumulator and then subtract M from A
M Question -4 on concept 3 CO A
C Find the Hexa decimal number represention of memory to save a number - 5
Q 15. 75 in IEEE single precission format.
A. C 1 6 C 0 0 0 0
B. C 2 1 5 0 0 0 0
C. 4 6 1 C 0 0 0 0
D. 4 2 6 5 0 0 0 0
Evaluation Scheme: Full Mark will be given if attempted this question.
Q. M Question -1 on concept 4 CO B
No: C How many clock cycles required to obtain sum and carry in 12 bit carry look 5
4 Q ahead adder.
A. 7
B. 8
C. 9
D. 10

Evaluation Scheme: Mark will be given if attempted this question.

M Question -2 on concept 4 CO A
C Find booth recording pattern of a number +41 5
Q A. +1 -1 +1 -1 0 +1 -1
B. +1 -1 +1 -1 0 +1
C. -1 +1 -1 0 +1 -1
D. -1 -1 +1 -1 0 +1 -1
M Question -3 on concept 4 CO A
C Find bit pair recording pattern of a number +41 5
 Q A. +1 -1 -2 +1
B. +1 -1 +2 +1
C. +1 -1 -1 +1
D. -1 +1 -1 +1
M Question -4 on concept 4 CO B
C In carry save addition of summands methods, find out no. of CSA level and 5
Q no. of clock cycles are required to complete the multiplication if Q=8 bits,
and final sum and carry is 16 bit.
A. 4, 22
B. 4, 19
C. 3, 15
D. 3, 17
Q. M Question -1 on concept 5 CO B
No: C If a 10GHz computer takes 5 clock cycles for ALU instructions, 10 clock 1
5 Q cycles for branch instructions and 3 clock cycles for data transfer
instructions. Then Find the total time taken by the computer to execute
the program. The program has 200 instructions and 50% ALU instructions,
25% branch instructions and 25% data transfer instructions.
A. 57.5nsec
B. 115nsec
C. 58nsec
D. 100nsec
M Question -2 on concept 5 CO C
C The content of register R1 is 11100101. What will be the decimal value after 1
Q execution of AshiftR #2, R1.
A. 7
B. 14
C. -7
D. -14
M Question -3 on concept 5 CO D
C The contents of memory locations 1000, 1200 and 1500 are 100, 1500 and 20 1
Q respectively before the following program is executed.
(i) MOV #1000, R1
(ii) ADD 200(R1),(1200)
(iii) SUB 1500, 1200.
What will be the contents memory locations 1000, 1200, 1500 after the
program is executed?
A. 100, 20, 1500
B. 100, -20, 1500
C. 100, 20, 1520
D. 100, -20, 1520
M Question -4 on concept 5 CO C
C Which one is not correct for the expression in stack based organization: X = 1
Q A-B+C*D
A. PUSH A, PUSH B, SUB, PUSH C, PUSH D, MULT, ADD, POP X
B. PUSH C, PUSH D, MULT, PUSH A, PUSH B, SUB, ADD, POP X
C. PUSH A, PUSH B, PUSH C, PUSH D, MULT, ADD, SUB, POP X
D. None of these
Q. M Question -1 on concept 6 CO D
No: C 6
6 Q Direct memory access is direct data transfer between
A. CPU and main memory
B. CPU and I/O processor
C. CPU and I/O device
 D. Main memory and I/O devices
M Question -2 on concept 6 CO D
C Which is not a program data transfer scheme 6
Q A. Synchronous data transfer scheme
B. Asynchronous data transfer scheme
C. Interrupt driven data transfer scheme
D. DMA data transfer scheme
M Question -3 on concept 6 CO A
C For the daisy chain scheme of connecting I/O devices, which of the following 6
Q statement is true?
A. It gives non-uniform priority to various devices
B. It gives uniform priority to all devices
C. It is only useful for connecting slow devices to a processor device
D. It requires a separate interrupt pin on the processor for each device.
M Question -4 on concept 6 CO B
C The correct matching of the following pairs is 6
Q a. DMA I/O 1. High speed RAM
b. Cache 2. Disk
c. Interrupt I/O 3. Printer
d.Condition code register 4. ALU
A. a-4, b-3, c-1, d-2
B. a-2, b-1, c-3, d-4
C. a-3, b-1, c-2, d-4
D. a--2, b-3, c-4, d-1

Q. M Question -1 on concept 7 CO A
No: C Which of the following control steps are required to execute the instruction “mov 3
7 Q R1, NUM”? [Where R1 is the source operand].
A) 1. Address_field_of_IRout, MARin
2. R1out, MDRin,Write,
3. WMFC
4. End

B) 1. R1out,Addrress_field_of_IRin, end

C) 1. WMFC
2.Addrress_field_of_IRout, MARin
3. MDRin, R1out, end

D) 1.Address_field_of_IRout, MARin
2.R1out, MDRin,Read
3.WMFC
4. end

M Question -2 on concept 7 CO B
C Which of the following control steps are required to execute the instruction “mov 3
Q #100, R1”? [Where R1 is the destination operand ]
A) 1. Address_field_of_IRout, MARin,Read
2. WMFC
3. MDRout,R1in,end

B) 1.Addrress_field_of_IRout,R1in end

C) 1.Addrress_field_of_IRout, MARin
2.MDRin,R1out,Write
3.WMFC
4. end
 D) 1.Address_field_of_IRout, MARin
2.R1out, MDRin,Read
3.WMFC
4. end

M Question -3 on concept 7 CO C
C The CONSTANT 4 at input A of the ALU is useful ----------------------------- 3
Q --, in a Three-bus organization
of the datapath inside of a processor.
A. for Branching
B. to add 4 to the contents of PC for updating its location to point to the
next instruction in the given
sequence in memory.
C. to increment other addresses like memory addresses in
LOADMULTIPLE and STOREMULTIPLE type
instructions.
D. None of the Above
M Question -4 on concept 7 CO A
C In Three-bus organization of the datapath inside of a processor, Which one of the 3
Q following is the correct Sequence of Control Steps for Fetching an instruction from
memory?

A.
1. PCout, R=B, MAR in, Read
2. IncPC, WMFC
3. MDRoutB, R=B, IRin

B.
1. PCout, R=B, MAR in,
2. IncPC, Read, WMFC
3. MDRoutB, R=B, IRin

C.
1. PCout, R=B, MAR in, IncPC
2. Read, WMFC
3. MDRoutB, R=B, IRin

D.
None of the above

SECTION-B(Answer Any Three Questions. Each Question carries 12

Marks)

Time: 1 Hour and 30 Minutes (3×12=36 Marks)

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Q Q.No:8-1st question CO
. A. Define memory interleaving technique with proper diagram. Why is 4
N memory interleaving technique used? [6]
o B. Consider a memory of 32 words per block. If 1 clock cycle are required
: to transfer address from CPU to main memory and 8 clock cycle to access
8
the 1st word and 4 clock cycle each for consecutive words and 1 clock
cycle for transferring the word from memory to cache. Then calculate the
total clock cycle required to transfer the block with inter leaving and
without interleaving if the number of module is eight. [6]

Solution:

A. Define memory interleaving technique with proper diagram. Why is

memory interleaving technique used?

Ans:
B. Consider a memory of 32 words per block. If 1 clock cycle are required
to transfer address from CPU to main memory and 8 clock cycle to access
the 1st word and 4 clock cycle each for consecutive words and 1 clock cycle
for transferring the word from memory to cache. Then calculate the total
clock cycle required to transfer the block with inter leaving and without
interleaving if the number of module is eight.
Ans:

Explanation of with interleaving

Q.No:8-2nd question

A. Define and discuss the different mapping function with hardware

diagram. Discuss the merit and demerit of the different types of mapping
function. (6 marks) [2+2+2]
B. Consider a main memory of 1GByte and a cache memory of 1MBytes
partitioned into 512 words. Each word consumes 64bits
[6]
( i ) Find out the physical address length.
(ii) How many bits are there in each of the TAG, BLOCK and WORD field
in case of direct mapping?
( iii )How many bits are there in each of the TAG and WORD field in case
of associative mapping?
( iv)How many bits are there in each of the TAG, SET, and WORD field in
case of 4-way set-associative mapping?
(v) How many tag comparators for each of the mapping techniques
(vi) Obtain tag memory for each of the mapping techniques.

Direct mapping- Direct mapping is a procedure used to assign

each memory block in the main memory to a particular line in
the cache. If a line is already filled with a memory block and a
new block needs to be loaded, then the old block is discarded
from the cache. Direct mapping divides an address into three
parts: t tag bits, l line bits, and w word bits. The word bits are the
least significant bits that identify the specific word within a block
of memory. The line bits are the next least significant bits that
identify the line of the cache in which the block is stored. The
remaining bits are stored along with the block as the tag which
locates the block’s position in the main memory.

Associative Mapping: In the associative mapping function,

any block of main memory can probably consist of any cache
block position. It breaks the main memory address into two parts
- the word ID and a tag as shown in the figure. To check for a
block stored in the memory, the tag is pulled from the memory
address and a search is performed through all of the lines of the
cache to see if the block is present.

Set Associative Mapping: Set associative mapping combines

direct mapping with fully associative mapping by arrangement
lines of a cache into sets. The sets are persistent using a direct
mapping scheme. However, the lines within each set are treated
as a small fully associative cache where any block that can save
in the set can be stored to any line inside the set.
Evaluation Scheme: If the student has assumed word addressing and the
answers are correct than he/she will get full marks.
If the student has assumed byte addressing then step marking will be done.
Q.No:8-3rd question

A. How many 512X8 RAM chips are needed to provide a memory capacity
of 4096X32 ? Give the specifications with suitable diagram.
[6]
B. Consider a cache with 4 cache blocks (0-3). The memory block requests
are in the order- 2, 3, 4, 7, 8, 6, 5, 8, 6, 5, 2, 4, 3, 5, 4
Calculate the hit ratio and miss ratio using [3+3]
(i) Direct mapping
(ii) LRU Replacement policy
A. How many 512X8 RAM chips are needed to provide a memory capacity
of 4096 X 32 ? Give the specifications with suitable diagram.
For correct answer student will get full marks else step marking will be done,
B. Consider a cache with 4 cache blocks (0-3). The memory block requests
are in the order- 2, 3, 4, 7, 8, 6, 5, 8, 6, 5, 2, 4, 3, 5, 4
Calculate the hit ratio and miss ratio using
(I) Direct mapping ::

(II) LRU Replacement policy

 E.S.- For correct answar full marks will be awarded.
Q Q.No:9-1st question CO
. 5
N A. Perform the following division operation using restoring and non-restoring method. 17
o ÷d
: Where d= your roll number last digit
9 If your roll no is 2005325, then d= 5 [3+3] [6+2+2+2]
B. Perform the addition of the following two numbers represented in IEEE format and
give the result in IEEE format.
Number 1:
S=0
E’= 1001 0101
M=0111 0000 0000 0000 0000 000
Number 2:
S=0
E’= 1000 1010
M=0101 0000 0000 0000 0000 000

Solution:
 Evaluation Scheme: Full marks will be given for correct answer.

Q.No:9-2nd question
A. Multiply (-13 X M) using BOOTH ALGORITHM.
Where M= your roll number last digit
If your roll no is 2005236, then M= 6 [6+2+2+2]

B. Subtract Number 2 from Number 1. (Numbers are represented in IEEE format and
give the result in IEEE format.
Number 1:
S=0
E’= 1000 0100
M=0110 0000 0000 0000 0000 000
Number 2:
S=0
E’= 1000 0011
M=0100 0000 0000 0000 0000 000
Solution:
B. Subtract Number 2 from Number 1. (Numbers are represented in IEEE format and
give the result in IEEE format.
Number 1:
S=0
E’= 1000 0100
M=0110 0000 0000 0000 0000 000
Number 2:
S=0
E’= 1000 0011
M=0100 0000 0000 0000 0000 000

[1]

[1]

[2]

Evaluation Scheme: Full marks will be given for correct answer.

Q.No:9-3rd question
A. Multiply (-11 X M) using Bit pair recording technique.
Where M= your roll number last digits
If your roll no is 2005123, then M= 3 [6+2+2+2]

B. Perform the addition of the following two numbers represented in IEEE format and
give the result in IEEE format.
Number 1:
S=0
E’= 1001 0111
M=0101 0000 0000 0000 0000 000
Number 2:
S=0
E’= 1000 1011
M=0001 0000 0000 0000 0000 000
Q Q.No:10-1st question CO
. A.Distinguish between memory mapped I/O and I/O mapped I/O 1,
N [4] CO
o B. Write an assembly language program to derive the expression 6
:1 X = A-(R+C)+H*I/T+E-(C*T)/(U-R)+E [4+4]
0
i) in a stack based computer with zero address instructions.
ii) in a accumulator based CPU with one address instructions.

a)
Memory mapped I/O I/O mapped I/O
Memory and I/O can't have same address. Memory and I/O devices will be addressed
by the same address.
Total number of memory and I/O devices are Total number of memory and I/O devices
more as they use all address space. will be less in number.
Instructions used are LDA and STA. Separate instructions for IO data transfer
( IN and OUT).

b)
Assemble code for Assemble code for
X = A-(R+C)+H*I/T+E-(C*T)/(U-R)+E X = A-(R+C)+H*I/T+E-(C*T)/(U-R)+E
( ZERO ADDRESS INSTRUCTIONS) (ONE ADDRESS INSTRUCTIONS)
1. PUSH A 1. LOAD A
2. PUSH R 2. SUB R
3. PUSH C 3. SUB C
4. ADD 4. STORE P
5. SUB 5. LOAD H
6. PUSH H 6. MUL I
7. PUSH I 7. DIV T
8. MUL 8. STORE Q
9. PUSH T 9. LOAD C
10. DIV 10. MUL T
11. ADD 11. STORE V
12. PUSH C 12. LOAD U
 13. PUSH T 13. SUB R
14. MUL 14. STORE W
15. PUSH U 15. LOAD V
16. PUSH R 16. DIV W
17. SUB 17. STORE Y
18. DIV 18. LOAD P
19. PUSH E 19. ADD Q
20. SUB 20. ADD E
21. ADD 21. SUB Y
22. POP X 22. ADD E
23. STORE X

Q.No:10-2nd question
A. Explain different techniques for data transfer. [4]
B. Write an assembly language program to derive the expression
X = O-(R+G)+A*N/I+Z-(A*T)/(I-O)+N [4+4]
i) in a stack based computer with zero address instructions.
ii) in a accumulator based CPU with one address instructions.

A. Explain different techniques for data transfer.

The data transfer between i/o device and CPU that has various modes:
1)Programmed i/o
2)Interrupt initiated i/o
3)DMA Direct Memory access

Prog. I/o:
1) whatever instruction you have provided for the I/O operations the result
of these instructions are written here.
2) Data you transfer from or to(CPU-external device)or(external device to
CPU), whatever is sent are monitored by the CPU.
3) This data transfer is done by instruction program
4) once you have done the data transfer, the data is transferred is monitored
by the CPU by using interface. Else what next time they could sent data
again.

Interrupt i/o initiated input/output:

1) We are using Interrupt facility to avoid time consumption that we face
from Programmed I/O method
2) Prog. I/O method keeps processor busy between program loops
3)Interrupt: to stop voluntarily: they ask interface to generate interrupt signal
when data is available from the device 4) with the help of interrupt, they able
to stop current program and move to another so this way the data is not comes
under program loop. This how processor does not need to work
unnecessarily.

DMA:
1) Whatever data we transfer we do with the help of memory bus and data
is transfer between CPU and external Device.
2) It transfers data with the help of interface. As soon as it starts to supply.
The interface collect the starting address and it also collect the number of
words and they jump to another work
3) DMA request for memory cycles from memory bus. As it granted by the
Memory unit It directly transfer data to memory with the help of the bus.
4)Work faster than other modes.

B. Write an assembly language program to derive the expression

X = O-(R+G)+A*N/I+Z-(A*T)/(I-O)+N
i) in a stack based computer with zero address instructions.
ii) in a accumulator based CPU with one address instructions.

Q.No:10-3rd question
A. Distinguish between cycle stealing and burst mode data transfer in DMA.
[4]
B. Explain FLYNN’S classification with neat diagram [4]
C. Write an assembly language program to derive the expression using
RICS instruction [4]
X = A-(R+C)+H*I/T+E-(C*T)/(U-R)+E
 1. Distinguish between cycle stealing and burst mode data transfer in
DMA.
Total Marks =4
Cycle stealing Brust Mode
In a cycle stealing In this mode Burst of data (entire data or
mode in which DMA controller take over burst of block containing data) is transferred
the bus for each byte of before CPU takes control of the buses back
data to be transferred and then return control from DMA controller
to the
CPU.
Slow mode of data transfer Fast mode of data transfer
High CPU utilization Low CPU utilization

2. Explain FLYNN’S classification with neat diagram

Total Marks =4 (Diagram =2 marks Explanation = 2 marks)
Based on FLYNN’s classification there are four types of computing systems:
1. SISD (Single Instruction Single Data)
2. SIMD (Single Instruction Multiple Data)
3. MIMD (Multiple Instruction Multiple Data)
4. MISD ( Multiple Instruction Single Data)

1. Single Instruction Single Data (SISD) :

An SISD computing system is a uniprocessor machine which is

capable of executing a single instruction, operating on a single data
stream. In SISD, machine instructions are processed in a sequential
manner and computers adopting this model are popularly called
 sequential computers. Most conventional computers have SISD
architecture. All the instructions and data to be processed have to be
stored in primary memory.

The speed of the processing element in the SISD model is

limited(dependent) by the rate at which the computer can transfer
information internally. Dominant representative SISD systems are
IBM PC, workstations.

2. Single-instruction, multiple-data (SIMD) –

An SIMD system is a multiprocessor machine capable of executing

the same instruction on all the CPUs but operating on different data
streams. Machines based on an SIMD model are well suited to
scientific computing since they involve lots of vector and matrix
operations. So that the information can be passed to all the processing
elements (PEs) organized data elements of vectors can be divided
into multiple sets(N-sets for N PE systems) and each PE can process
one data set.

Dominant representative SIMD systems is Cray’s vector processing

machine.
3 Multiple-instruction, single-data (MISD)

An MISD computing system is a multiprocessor machine capable of

executing different instructions on different PEs but all of them operating
on the same dataset .

The system performs different operations on the same data set.

Machines built using the MISD model are not useful in most of the
application, a few machines are built, but none of them are available
commercially.

3. Multiple-instruction, multiple-data (MIMD)

An MIMD system is a multiprocessor machine which is capable of

executing multiple instructions on multiple data sets. Each PE in the
MIMD model has separate instruction and data streams; therefore
machines built using this model are capable to any kind of
application. Unlike SIMD and MISD machines, PEs in MIMD
machines work asynchronously.
 3 Write an assembly language program to derive the expression
using RICS instruction

X = A-(R+C)+H*I/T+E-(C*T)/(U-R)+E

Total Marks = 4

23. PUSH A
24. PUSH R
25. PUSH C
26. ADD
27. SUB
28. PUSH H
29. PUSH I
30. MUL
31. PUSH T
32. DIV
33. ADD
34. PUSH C
35. PUSH T
36. MUL
37. PUSH U
38. PUSH R
39. SUB
40. DIV
41. PUSH E
42. SUB
43. ADD
44. POP X

Evaluation Scheme: Marks will be given for 1, 2, 3 address instruction.

Q Q.No:11-1st question CO
. A. Write the sequence of control steps for the given instructions for 2,
N single bus architecture and design the logic function for MARin and CO
o Yin control signal with reference to given instructions. 3
:1
1 i) ADD #10, (R1) [2+2+1+1]
 ii) SUB (R1), R2

B. Given the following program fragment [1.5x4]

Main Program Subroutine SUB1 Subroutine SUB2
1000: ADD R1, R2 2050: MUL A, B 200: MUL A, B
1004: SUB R3, R4 2054: CALL SUB2 204: DIV 100, R1
1008: CALL SUB1 2058: ADD #10, R2 208: RETURN
1012: ADD R5, R6 2062: RETURN

Initially stack pointer SP contains 5000 and top of stack is 500.

What are the content of SP, PC, top of stack?
I) After the subroutine call instruction is executed in the main program?
II) After the subroutine call instruction is executed in the subroutine SUB1?
III) After return from the subroutine SUB2?
IV) After return from the subroutine SUB1?

Solution: QUESTION11.1
A. Write the sequence of control steps for the given
instructions for single bus architecture and design the
logic function for MARin and Yin control signal with
reference to given instructions.
i) ADD #10, (R1)
ii) SUB (R1), R2
SOLUTION:
MARK
I)1.PCout,MARin,read,select 4,ADD,Zin
[3]
2.Zout,PCin,Yin ,WMFC
3.MDRout,IRin
4.R1out,MARin,read
5.data field of IRout,Yin,WMFC
6.MDRout,select y,ADD,Zin
7.R1out,MARin
8.Zout,MDRin,write
9.WMFC
10.end
Ii)1.PCout,MARin,read,select4,ADD,Zin
[3]
2.Zout,PCin,Yin ,WMFC
3.MDRout,IRin
4.R1out,MARin,read
5.R2out,Yin,WMFC
6..MDRout,select y,SUB,Zin
7.Zout,R2in,end

MARin=T1+T4(ADD+SUB)+T7.ADD+….
[1]
 Yin=T2+T5(ADD+SUB)+……..

[1]

B. Given the following program fragment

Main Program
Main Program Subroutine SUB1 Subroutine SUB2
1000: ADD R1,R2 2050: MUL A, B 200: MUL A, B
1004: SUB R3, R4 2054: CALL SUB2 204: DIV 100, R1
1008: CALL SUB1 2058: ADD #10,R2 208: RETURN
1012: ADD R5,R6 2062: RETURN

Initially stack pointer SP contains 5000 and top of stack is 500.

What are the content of SP, PC, top of stack?
I) After the subroutine call instruction is executed in the main
program?
PC=2050 SP=4996 TOS=1012
[1]
II) After the subroutine call instruction is executed in the
subroutine SUB1?
PC=200 SP=4992 TOS=2058
[1]

III) After return from the subroutine SUB2?

PC=2058 SP=4996 TOS=1012
[1]

IV) After return from the subroutine SUB1?

PC=1012 SP=5000 TOS=500
[1]
 Q.No:11-2nd question
A. Write the sequence of control steps for the given instructions using
multiple bus architecture. [6+6]
i. ADD #10, (R1)
ii. SUB (R1), R2
iii. MUL (1000), R2
B. Assume that each memory word consumes 4 bytes and computer is byte
addressable. The memory stores numbers from 1 to 20 sequentially starting
from memory location 1000. The register R2 and R3 contain value 10 and
20 respectively.
Move #1000, R0
Move #5, R1
LOOP: Add R2, 4(R0)
Add #4, R0
Add (R0), R3
Move R3, 4(R0)
DEC R1
Branch>0 LOOP
Find out the contents of first ten words locations starting at 1000.

Solution: A. Write the sequence of control steps for the given

instructions using multiple bus architecture.
iv. ADD #10, (R1)
v. SUB (R1), R2
vi. MUL (1000), R2
Solution: Assuming, 2nd operand as the destination
I. ADD #10, (R1)
1. PCout, R=B, MARin, Read, IncPC
2. WMFC
3. MDRoutB, R=B, IRin
4. R1outB, R=B, MARin, Read
5. WMFC
6. MDRoutB, Address_field_of_IRout, SelectA, Add, R2in
7. R1outB, R=B, MARin
8. R2outB, R=B, MDRin, Write
9. WMFC
10.End

II. SUB (R1), R2

1. PCout, R=B, MARin, Read, IncPC

2. WMFC
3. MDRoutB, R=B, IRin
4. R1outB, R=B, MARin, Read
5. WMFC
6. MDRoutB, R2outA, SelectA, SUB, R2in, end

III.MUL (1000), R2
1. PCout, R=B, MARin, Read, IncPC
2. WMFC
3. MDRoutB, R=B, IRin
4. Address_field_IRoutB, R=B, MARin, Read
5. WMFC
6. MDRoutB, R2outA, SelectA, Mul, R2in, end

B. Assume that each memory word consumes 4 bytes and computer is byte
addressable. The memory stores numbers from 1 to 20 sequentially starting
from memory location 1000. The register R2 and R3 contain value 10 and
20 respectively.
Move #1000, R0
Move #5, R1
LOOP: Add R2, 4(R0)
Add #4, R0
Add (R0), R3
Move R3, 4(R0)
DEC R1
Branch>0 LOOP
Find out the contents of first ten words locations starting at 1000. C

Solution: R2= 10, R3= 20→32→74→158→326

R1= 5→4→3→2→1→0

Initially 1st 2nd 3rd 4th 5th

Iteration Iteration Iteration Iteration Iteration
1000 1
1004 2 12
1008 3 32 42
1012 4 74 84
1016 5 158 168
1020 6 326 336
1024 7 762
1028 8
1032 9
1036 10

Q.No:11-3rd question
A. Write the micro-instruction for the following instruction
MUL (R1), R2 [6+6]
B. A computer has 32 bit instruction. It uses two register operands and one
memory operand. There are 64 general purpose registers and 32K bytes of
RAM. How many different operations the computer can perform? If there
are 10 three address operations which uses two registers and one memory,
then how many one address operations (which use only memory) are
possible.