IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—I: REGULAR PAPERS, VOL. 68, NO.
2, FEBRUARY 2021 667
A Logic-Compatible eDRAM Compute-In-Memory
With Embedded ADCs for Processing
Neural Networks
Chengshuo Yu , Graduate Student Member, IEEE, Taegeun Yoo , Member, IEEE,
Hyunjoon Kim , Student Member, IEEE, Tony Tae-Hyoung Kim, Senior Member, IEEE,
Kevin Chai Tshun Chuan, Senior Member, IEEE, and Bongjin Kim, Member, IEEE
Abstract— A novel 4T2C ternary embedded DRAM (eDRAM)
cell is proposed for computing a vector-matrix multiplication
in the memory array. The proposed eDRAM-based compute-
in-memory (CIM) architecture addresses a well-known Von
Neumann bottle-neck in the traditional computer architecture
and improves both latency and energy in processing neural
networks. The proposed ternary eDRAM cell takes a smaller
area than prior SRAM-based bitcells using 6-12 transistors.
Nevertheless, the compact eDRAM cell stores a ternary state
(−1, 0, or +1), while the SRAM bitcells can only store a binary
state. We also present a method to mitigate the compute accuracy
degradation issue due to device mismatches and variations.
Besides, we extend the eDRAM cell retention time to 200µs
by adding a custom metal capacitor at the storage node. With
the improved retention time, the overall energy consumption of
eDRAM macro, including a regular refresh operation, is lower
than most of prior SRAM-based CIM macros. A 128×128 ternary
eDRAM macro computes a vector-matrix multiplication between
a vector with 64 binary inputs and a matrix with 64 × 128
ternary weights. Hence, 128 outputs are generated in parallel.
Note that both weight and input bit-precisions are programmable
for supporting a wide range of edge computing applications
with different performance requirements. The bit-precisions are
readily tunable by assigning a variable number of eDRAM cells
per weight or adding multiple pulses to input. An embedded
column ADC based on replica cells sweeps the reference level for
2N −1 cycles and converts the analog accumulated bitline voltage
to a 1-5bit digital output. A critical bitline accumulate operation
is simulated (Monte-Carlo, 3K runs). It shows the standard
deviation of 2.84% that could degrade the classification accuracy
of the MNIST dataset by 0.6% and the CIFAR-10 dataset by
1.3% versus a baseline with no variation. The simulated energy is
1.81fJ/operation, and the energy efficiency is 552.5-17.8TOPS/W
(for 1-5bit ADC) at 200MHz using 65nm technology.
Manuscript received June 6, 2020; revised October 13, 2020; accepted
November 1, 2020. Date of publication November 16, 2020; date of current
version January 12, 2021. This work was supported by the Singapore
government’s Research, Innovation and Enterprise 2020 Plan Advanced Man-
ufacturing and Engineering Domain under Grant A1687b0033. This article
was recommended by Associate Editor M.-F. Chang. (Corresponding author:
Bongjin Kim.)
Chengshuo Yu is with the School of Electrical and Electronic Engineering,
Nanyang Technological University, Singapore 639798, and also with Institute
of Microelectronics, A∗ STAR, Singapore 138634.
Taegeun Yoo, Hyunjoon Kim, Tony Tae-Hyoung Kim, and Bongjin Kim
are with the School of Electrical and Electronic Engineering, Nanyang
Technological University, Singapore 639798 (e-mail: bjkim@ntu.edu.sg).
Kevin Chai Tshun Chuan is with the Institute of Microelectronics, A∗ STAR,
Singapore 138634.
Color versions of one or more of the figures in this article are available
online at https://ieeexplore.ieee.org.
Digital Object Identifier 10.1109/TCSI.2020.3036209
1549-8328 © 2020 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission.
See https://www.ieee.org/publications/rights/index.html for more information.
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Index Terms— Embedded DRAM, compute-in-memory, hard-
ware accelerator, current-mode, vector-matrix multiplication,
SRAM.
I. I NTRODUCTION
T HE Von Neumann architecture has been applied to most
electronic devices since it was first introduced in 1945.
The central concept of this architecture is the separation of
memory from its central processing unit (CPU). In general,
a traditional computer consists of three separate parts: arith-
metic logic unit (ALU), control unit, and memory. A typical
compute operation is performed in three stages as follows.
First, both instructions and data stored in memory are trans-
ferred from memory to ALU before the compute begins. Sec-
ond, the fetched instructions and data are stored in temporary
registers and used for computation in ALU. Finally, the com-
puted results are sent back to memory. In recent years, the fun-
damental limits of the conventional Von Neumann architecture
are brought into spotlights. The memory access usually dom-
inates the entire energy consumption of the modern micro-
processors and the limited communication band-width limits
the compute performances in both throughput and latency.
Due to such limitations, the Von Neumann architecture is no
longer the best choice, especially for processing artificial deep
neural networks (DNNs) in resource-constrained mobile edge
computing devices.
One of the alternative architectures that could significantly
improve the performance in processing DNNs is a compute-
in-memory (CIM) architecture. As shown in Fig. 1, the in-
memory architecture enables the memory to compute essential
functions by embedding them in its macro. As a result, we can
minimize both energy consumption and compute latency by
eliminating a large portion of energy-hungry data communi-
cations between ALU and memory. Besides, massively parallel
computations in the large memory array maximizes throughput
and fully utilize memory capacity. In conclusion, the DNN
processing in mobile devices will become much faster and
more energy-efficient by adopting the CIM architecture.
Fig. 2(a) illustrates a brain-inspired neuron which computes
a dot-product between ‘n’ pairs of inputs and weights. The
dot-product is followed by a nonlinear activation, which
generates an output. A CIM macro with embedded brain-
inspired neurons is shown in Fig. 2(b). The macro consists of
668 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—I: REGULAR PAPERS, VOL. 68, NO. 2, FEBRUARY 2021
Fig. 1. A comparison between (a) conventional architecture and (b) compute-
in-memory architecture.
a two-dimensional memory cell array and a row of nonlinear
activations. A column of ‘n’ memory cells with an activation at
the bottom represents a neuron. Each column neuron computes
a dot-product between ‘n’ inputs coming from the left and the
same number of weights stored in the memory cells. Note that
the macro consists of ‘m’ columns, and hence its throughput is
proportional to ‘m’ thanks to the fully-parallel column-based
operations.
Recently, various SRAM-based bitcells for CIM
macros [1]–[10] have been developed for energy-efficient
DNN processing. A standard 6T SRAM bitcell is used
for storing a binary weight while it typically requires
extra transistors for accumulation via shared bitlines.
J. Zhang et al. [1] first presented a standard 6T SRAM-based
CIM macro for a machine learning classification.
A programmable positive short-pulse is applied to a
wordline (WL) causing one of the bitlines (BL/BLB) to
discharge while the other remains unchanged. Note that such
an operation is equivalent to a multiplication between the input
and the stored binary weight. The operations are performed
all in parallel, and hence the voltage drop at BL/BLB
is equivalent to the sum of the individual multiplication
results (i.e., accumulation). The standard 6T SRAM bitcell
is compact and does not require extra transistors. However,
it has fundamental limitations, including a memory cell
write disturbance and a narrow dynamic range in shared
bitlines for accumulation. Besides, the ADC overhead is
significant for applications that require high-precision outputs.
Biswas et al. [3] proposed a 10T SRAM bitcell having four
extra transistors to decouple bitlines for read/write operations
(i.e., RBL/WBL). Hence, the 10T bitcell is free from the
write disturbance issue during accumulation. Moreover,
the voltage-based operation enables a rail-to-rail dynamic
range in the read bitline. However, the 10T bitcell occupies
a larger area than the standard 6T bitcell, and hence results
in the reduced integration density. Besides, it also requires
extra circuits for accumulation based on charge redistribution,
and the ADC overhead issue is not resolved yet. Yin et al.
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Fig. 2. (a) A functional block diagram of brain-inspired neuron. (b) Embed-
ded neurons in a CIM macro with ‘m x n’ memory cells and ‘m’ activations.
and Kim et al. [4], [5] proposed voltage-driver based
SRAM bitcells, where the accumulation is performed by
programming the ratio between pull-up and pull-down drivers
that are embedded in their bitcells. However, both suffer
from the low integration density due to large bitcell size.
Recently, Yu et al. [6] presented an 8T SRAM bitcell having
two extra transistors for decoupled read/write operations.
While having a moderate dynamic range and a relaxed ADC
overhead, the inherently large SRAM bitcell size is an issue
to overcome. Emerging resistive memory (ReRAM/RRAM)
based compute-in-memory (CIM) macro designs [11], [12]
have shown higher memory density compared to the proposed
eDRAM macro with smaller bitcell area (0.25μm2 and
0.2025μm2) than the proposed cell (1.08μm2). However,
the RRAM technology demonstrated the lower energy
efficiency (19.2 and 53.17TOPS/W at 1bit) due to the
relatively large cell current compared to the eDRAM bitcell
(552.5TOPS/W at 1bit). Besides, the RRAM-based in-memory
computing suffers from the unstable resistance value, which
is caused by the inherent filament formation process.
This paper presents a logic compatible eDRAM-based CIM
macro for energy-efficient processing of DNNs in mobile
edge devices. A novel 4T2C ternary eDRAM cell (two 2T
eDRAM bitcells and two capacitors) is proposed. Both input
and weight bit-precisions are readily reconfigured by assigning
a variable number of bitcells per weight or using multiple
pulses per input. We also propose a replica-based analog-to-
digital converter, which is embedded in each column of the
CIM macro along with 128 eDRAM cells.
YU et al.: LOGIC-COMPATIBLE eDRAM COMPUTE-IN-MEMORY WITH EMBEDDED ADCs
TABLE I
C OMPARISON OF E MBEDDED M EMORY C ANDIDATES FOR C OMPUTE -I N -M EMORY M ACRO
The rest of the paper is as follows. Section II introduces
the proposed ternary eDRAM cell with its basic operations.
Section III presents the reconfigurability of the CIM macro
based on the proposed eDRAM cells. The design challenges
are discussed in Section IV. Section V introduces the embed-
ded ADC and the offset-calibration approach. Section VI
describes the overall architecture and simulation results, fol-
lowed by a conclusion in Section VII.
II. E DRAM C OMPUTE -I N -M EMORY M ACRO
A. Proposed 4T2C Ternary eDRAM Cell
In this work, we propose an embedded DRAM (eDRAM)
based CIM macro for the first time. Different styles of
eDRAM bitcells have been introduced, as shown in Table I.
Barth et al. [13] presented a 1T1C bitcell. The highest
integration density and the low power consumption of the
1T1C structure facilitate it to become a promising bitcell
candidate for an eDRAM-based CIM. However, the compact
1T1C bitcell shares a bitline for reading/writing a storage
capacitor, and hence suffers from the write disturbance issue.
The dynamic nature of eDRAM bitcell necessitates a reg-
ular refresh operation with associated energy consumption.
Besides, it requires low leakage access transistors and a deep
trench capacitor, which is not available in the generic logic
process. Chun et al. [14], [15] have proposed gain-cell based
eDRAM macros based on compact 3T [14], 2T [15], and
2T1C [16] bitcell structures using only standard logic process.
The logic-compatible eDRAM bitcells decouple read and write
operations, and the manufacturing cost is lower than the 1T1C
eDRAM [13]. The memory density is higher than 6T SRAM
but lower than 1T1C eDRAM. A logic compatible 2T eDRAM
bitcell circuit comprising of a PMOS and an NMOS transistor
is shown in Fig. 3. The PMOS transistor is used for accessing
the internal storage node through write bitline (WBL) when
its gate node (WWL) voltage is low. The NMOS transistor
works as a storage capacitor as well as a read access transistor
to read the stored value when the source (RWL) node voltage
is low. In this work, we use a pair of 2T eDRAM bitcells
as a ternary-weight compute-in-memory unit. Each eDRAM
bitcell on the left and the right works as a current discharging
unit, and contributes to a finite voltage drop in read bitlines
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669
(RBLL/RBLR) when a negative short pulse is applied to RWL,
and the stored weight is high. Note that the eDRAM bitcell
decouples read and write operation, and hence is free from
a write disturbance issue. Besides, the proposed eDRAM cell
stores a ternary state (−1, 0, or +1) using four transistors only
while a standard SRAM bitcell shares a read/write bitline and
stores a binary state using six transistors.
B. Compute-In-Memory Multiplication
Fig. 4 describes a compute-in-memory dot-product opera-
tion using the proposed 4T2C ternary eDRAM cell. Before
computing, two read bitlines in the middle are pre-charged to
a high voltage. Fig. 4(a), top shows the circuit of the eDRAM
cell. A single cell consists of four transistors and six control
lines; two pairs of write and read bitlines, a write wordline,
and a read wordline. The stored weights on the left/right
bitcells are WL and WR . The table in Fig. 4(a) summarizes
a default ternary-weight binary-input multiply operation in a
cell. Here, note that the high or the low voltage is denoted
by ‘H’/’L’ while ternary state values are represented by ‘−1’,
‘0’, and ‘1’. A ternary weight is stored in an eDRAM cell
as −1 (WL = H, WR = L), 0 (WL = L, WR = L), or +1
(WL = L, WR = H). A binary input is represented by a
transient voltage at an RWL node. The input is ‘0’ when
RWL is ‘H’ and is ‘1’ when a negative short pulse is applied
to the RWL node. After a cycle of operation, the ternary-
weight binary-input multiplication result is accumulated in a
differential read bitline (RBLL/RBLR) as a voltage difference
(−V, 0, or +V) based on weight and input combinations
as shown in Fig. 4(a).
Fig. 4(b) describes how the proposed 4T2C ternary eDRAM
cell operates for each weight (W) and input (X) combination.
When the RWL node is high (i.e., input is 0), no current flows
through RBLL/RBLR and hence results in ‘no change’ in the
voltage difference between the two read bitlines as shown in
all three diagrams in Fig. 4(b), left. When a negative pulse is
applied to RWL, either RBLL or RBLR is discharged through
an NMOS read access transistor on the left or right bitcell
when the storage node voltage is ‘H’. As a result, the voltage
difference between RBLL and RBLR decreases or increases
by ‘V’ as highlighted in Fig. 4(b), right. When both weight
670 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—I: REGULAR PAPERS, VOL. 68, NO. 2, FEBRUARY 2021
Fig. 3. A 2T eDRAM bitcell when operating as a memory: (a) write mode
and (b) read mode. (c) A pair of 2T eDRAM bitcells works as a ternary-weight
compute-in-memory unit cell.
Fig. 4. (a) A circuit schematic of the proposed 4T2C ternary eDRAM cell
and a table summarizing ternary-weight binary-input multiplication results.
(b) Cell operations for all six weight (W) and input (X) combinations.
voltages are ‘L,’ there will be no change in RBLL/RBLR
regardless of the input.
C. Current-Mode Bitline Accumulation
Fig. 5(a) describes the accumulate operation in a column
of the ternary eDRAM cells. As shown in Fig. 5(a), left, a
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Fig. 5. (a) Dot-product operation in a column (i.e. a neuron) of eDRAM array.
(b) A read bitline (RBLL or RBLR) discharge plot of all possible outputs.
column consists of ‘n’ unit cells that are stacked in a vertical
direction. A pair of PMOS transistors precharge RBLL/RBLR
before the current-mode accumulation induces voltage drops
at the shared read bitlines. The precharge voltage is set
to 0.7V for reducing leakage current flowing through read
bitlines from the disabled bitcells. To maximize the linearity
in accumulate operations, we use only a limited voltage range
(i.e., ∼250mV), as depicted in Fig. 5(a). Each 2T1C bitcell
discharges a unit current (Iunit ) when the stored weight is
‘H’ and a negative pulse is applied to RWL. When a read
bitline capacitance is ‘C’ and an RWL short pulse width is
‘τ ,’ the resulting voltage difference generated by each enabled
bitcell is ‘V= τ · (Iunit /C).’ Since the number of eDRAM
cells in a column is ‘n,’ the accumulated voltage difference at
I n
RBLL/RBLR is ‘Vdi f f = τ · diCf f Wi · X i ’.
i=1
Fig. 5(b) shows a transient simulation result of a single
read bitline (RBLL or RBLR) discharge operation when a
negative short pulse is applied to RWL. For verifying the
linearity of the proposed eDRAM-based bitline accumulation,
we swept the number of enabled bitcells from 0 to 128 with
YU et al.: LOGIC-COMPATIBLE eDRAM COMPUTE-IN-MEMORY WITH EMBEDDED ADCs 671

the step size of 1 when the number of eDRAM cells per

column is 128. Note that the SRAM core supply voltage is
0.5V, and the read bitlines are pre-charged to 0.7V before the
accumulate operation. The RWL short pulse width is 1ns, and
the simulated unit current (Iunit ) is 97.65nA.

III. R ECONFIGURABILITY
The weight and input bit-precisions of the proposed
eDRAM macro can be reconfigured from ternary/binary to
the higher bit-precisions for processing DNNs having more
stringent accuracy requirements. Fig. 6 describes how we
reconfigure the input and weight bit-precisions using RWL
input pulses and the number of eDRAM cells per weight.
Fig. 6(a) shows the programmable input precision based on
the number of short pulse cycles per input. A pulse train
instead of a single pulse can be applied to an RWL node to
increase the number of input levels. Note that the number of
pulses corresponds to the number of input levels, and it can
be increased as long as the accumulated voltage level does not
exceed the limited operating range of the read bitlines. As for
the implementation of multi-level weights, we can group
multiple eDRAM cells to represent a weight. For instance,
two or three ternary eDRAM cells are combined to work as a
5- or 7-level (−2 to 2 or −3 to 3) weight storage, as shown
in Fig. 6(b). Note that each eDRAM cell adds two more levels, Fig. 6. Reconfigurable (a) input and (b) weight precisions using multiple
RWL pulses and ternary eDRAM cells to represent an input or a weight.
and the RWL node has to be shorted between cells.
Fig. 7 shows an example of reconfigured column with
ternary eDRAM cells for a dot-product between ‘n’ pairs of
multi-level inputs and weights. A group comprising of four
eDRAM cells represents a 9-level (−4 to 4) weight, and a
shared RWL with three negative pulse cycles represents a
4-level (0 to 3) input. Fig. 8 shows a reconfigured column
with 5-level weights and 3-level inputs, as well as the timing
diagrams of essential signals and the simulated waveforms.
A pre-charged RBL voltage (0.7 V) drops twice for each of the
two negative short pulses, and the level of each voltage drop is
proportional to the number of enabled eDRAM bitcells, which
is swept from 0 to 64, as shown in Fig. 8(c). Note that the RBL
voltage levels settled after two-cycles of the bitline accumulate
operation still do not exceed the predefined dynamic range
(∼250mV) to ensure the linearity.
Fig. 7. An example of reconfigured column with 4T2C ternary eDRAM
cells: 4-level inputs and 9-level weights.
IV. D ESIGN C HALLENGES
One of the critical design challenges of the eDRAM macro time. Tikekar et al. [19] proposed the on-demand power-up
is the short retention time of its dynamic memory cell having scheme that can minimize the excessive power from eDRAM
the limited storage capacitance and the substantial leakage access. Park et al. [20] and Choi et al. [21] used eDRAM as
currents. The situation becomes more severe in the eDRAM a temporary buffer.
macro with 2T gain cells since it relies on a small (<1fF) The 2T eDRAM bitcell (i.e., a half-circuit of the proposed
gate and parasitic capacitance while a 1T1C structure utilizes 4T2C ternary eDRAM cell) was originally developed [15] to
a dedicated storage capacitor such as a 20fF deep trench capac- increase its retention time by eliminating a pulling-down gate
itor [13]. Various approaches [17]–[22] have been introduced leakage of the NMOS access transistor, as shown in Fig. 9, left.
to make the retention time longer while maintaining a high Note that the NMOS transistor is off when the bitcell is not
integration density. Cho et al. [17] applied different refresh accessed, and hence its gate leakage is negligible. However,
cycle times to different memory blocks based on the priority the retention time of eDRAM bitcell for CIM macro has to be
of data to optimize refresh operation and the associated energy. redefined since it not only flips the stored data but also degrade
Kazimirsky et al. [18] presented an algorithm that schedules the computation accuracy in the bitline accumulation. A unit
the refresh operations to happen only during the unoccupied discharging current is directly affected by the stored voltage in

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672 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—I: REGULAR PAPERS, VOL. 68, NO. 2, FEBRUARY 2021

Fig. 10. A retention time comparison with 10K Monte Carlo iterations.
‘P’ represents a write access PMOS and ‘N’ represents a read access NMOS.

Fig. 8. Proposed multiple unit cells computing module. (a) Schematic.

(b) Timing diagram. (c) Simulated RWL and RBLL waveforms during
transition with Input 2 (two down-pluses).

Fig. 9. Leakage Current and Retention Time Theory of eDRAM; the impact
of retention time on computation.

each eDRAM bitcell, and hence the bitcell has to be refreshed

much earlier than the eDRAM bitcell only for memory usage.
Therefore, the more stringent retention time constraints have
to be considered when designing an eDRAM CIM macro.
Note that the bitcell with the stored data ‘0’ is dominant
when determining the retention time of the asymmetric 2T
Fig. 11. (a) Illustration of the custom MOMCAP using four metal layers
eDRAM bitcell with unbalanced leakage components. In this (M4-M7) (b) A 4T2C ternary eDRAM cell layout.
work, we set the maximum allowed voltage level at the internal
storage node for data ‘0’ to be 221mV, as shown in Fig. 9,
right. The voltage level is calculated based on the maximum Typically, a generic CMOS logic process provides multiple
allowed leakage current (i.e., Iunit /256) when the number of sets of PMOS and NMOS transistors with different threshold
eDRAM cells in a column is 128. In other words, we set the voltages. In this work, we use a 65nm logic process with
maximum low-level storage node voltage to ensure the sum of three different threshold devices: HVT (high Vth ), RVT (reg-
leakage currents through NMOS read access transistors is less ular Vth ), and LVT (low Vth ). Thus, we can consider nine
than a half of the unit discharging current, and hence does not PMOS/NMOS combinations as candidates for the design of
affect the accumulate operation. 2T eDRAM bitcell. Fig. 10 shows the simulated retention

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YU et al.: LOGIC-COMPATIBLE eDRAM COMPUTE-IN-MEMORY WITH EMBEDDED ADCs
Fig. 12. Retention time comparison with three different metal capacitor
layouts: (a) Schematic Only (b) Covered with grounded M4-M7 (c) Custom
MOMCAP.
Fig. 13. Operating principle of the column ADC [6]. The ADC comprises a
sense amplifier (SA) and replica eDRAM cells generating an ADC reference.
The reference is swept for 2N −1 cycles of N-bit ADC operation (e.g., N = 5).
time of the nine different combinations based on 10K Monte-
Carlo iterations. The core supply voltage of 0.5V and the
minimum size PMOS/NMOS transistors were used for the
simulations. The simulation results show the bitcell with HVT
PMOS and HVT NMOS achieves the longest retention time,
as shown in Fig. 10, bottom right. Note that the impact of
PMOS transistor type on retention time is more significant
than that of the nominally-off NMOS read access transistor.
As shown in the bottom three cases in Fig. 10, the bitcell
with HVT PMOS results in the longer retention time with
less variation compared to other candidates. The maximum
allowed voltages for the three cases are also indicated. Here,
‘clearly off’ state means that the bitcell is operating in a valid
region where the sum of NMOS leakage currents at the bitline
is negligible and minimally affects the accumulate operation.
Based on the computed maximum allowed voltage for data
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673
Fig. 14. Timing diagram of the proposed column ADC Reference with two
different dot-product results, 17 and 25.
Fig. 15. Simulation result of proposed ADC (1-5bits mode).
‘0,’ we are able to calculate a ‘valid’ retention time. However,
the calculated retention time is only a few μs, even in the
best case where HVTs are used for both PMOS and NMOS.
To extend the retention time, we designed a customized metal-
oxide-metal (MOM) capacitor that maximizes the storage node
capacitance without increasing the eDRAM cell size, as shown
in Fig. 11.
Fig. 11(a) illustrates the designed custom MOM capacitors
that are connected to the internal storage nodes on the left and
right bitcell of the proposed ternary eDRAM cell. The outer
ring of metals is grounded, and the ‘H’ shaped central metals
are connected to the storage nodes. The capacitors are drawn
using four metal layers (from M4 to M7), and their layouts are
drawn in the way to maximize the overall fringe capacitances
between the storage nodes and the ground surrounding them.
The ternary eDRAM cell layout, including both front- and
back-end metal layers, is shown in Fig. 11(b). The first two
metal layers (M2 and M3) are used to build a frontend
design of ternary eDRAM cell with four vertical and two
horizontal interconnects for read and write access. The size of
the proposed 4T2C eDRAM cell is 1.8μm × 0.6μm. Without
affecting the cell size, the added MOM capacitor maximizes
bitcell storage capacitance. A 128 × 128 ternary eDRAM cell
array layout is drawn, and its parasitic RCs are extracted to
674 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—I: REGULAR PAPERS, VOL. 68, NO. 2, FEBRUARY 2021
Fig. 16. Operating concept of the binary-searching based offset calibration.
Note that the white grid in the top image represents the bitcell with a weight
‘+1’ while the black grid represents the bitcell with a weight ‘−1’.
Fig. 17. A column neuron with 128 eDRAM cells. Each column consists
of 64× cells for dot-product, 32× for ADC reference, and 32× for offset
calibration.
verify the extended valid retention time. Fig. 12 compares
the simulated retention time with different eDRAM unit cell
designs. Fig. 12(a) shows the shortest retention time (few μs)
with schematic only (i.e., the same result with Fig. 10, bottom-
right). The eDRAM cells with extra metal capacitors are
shown in Fig. 12(b-c). The retention time of the proposed
eDRAM cell with custom MOM capacitors demonstrates the
longest retention time of 200 μs, which is twice longer
than the one with four ground plates. The extended retention
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Fig. 18. (a) Overall architecture with 128 × 128.4T2C eDRAM cell array.
(b) CIM operating sequence including a regular refresh cycle.
Fig. 19. Power and area breakdown.
time contributes to reducing the frequency of refresh and
saving refresh & computation energy. As retention time rises
from 15μs to 200μs, the energy efficiency has increased
by 14.48 times. The total energy efficiency of the eDRAM
macro with 15μs retention time is 26.2fJ/OP while the total
energy efficiency of the eDRAM macro with 200μs retention
time is 1.81fJ/OP. Note that the MOM capacitor also plays a
significant role in minimizing the variation of the stored data
‘1,’ as shown in Fig. 12.
V. C OLUMN ADC AND O FFSET C ALIBRATION
The overhead of area-consuming analog-to-digital converter
(ADC) is one of the key challenges in the design of analog
CIM macros. A bulky ADC is typically shared by many
column- or row-based neurons in a macro, and hence results in
the reduced throughput and the increased latency. To address
the challenges, we adopted a column ADC [6] embedded in
each column of the CIM macro by reusing replica cells and
a sense amplifier as an ADC reference and a bit quantizer.
The proposed ADC converts the bitline analog voltage (i.e., a
dot-product result) to a digital thermometer code from cycle
YU et al.: LOGIC-COMPATIBLE eDRAM COMPUTE-IN-MEMORY WITH EMBEDDED ADCs 675

Fig. 20. Size and density comparison of 16 kb CIM macro layout between 8T SRAM [6] and the proposed 4T2C eDRAM.

to cycle while sweeping a replica-based ADC reference from

the highest to the lowest level.
Fig. 13 illustrates an example of the column ADC oper-
ation. For each column, 64× eDRAM cells are used for a
dot-product computation, and the other 32× cells are assigned
for generating the ADC reference level. The ADC reference
level is generated by swept weights (i.e. from −32 to +32 with
the step 2) and fixed inputs as ‘1’ (i.e. RWL = down pulse).
It takes 2N − 1 cycles for a single N-bit ADC operation (i.e.,
31 cycles for 5bit ADC). A sense amplifier for memory read
operation is reused for converting the analog dot-product result
in the bitlines to a series of thermometer code from the highest
to the lowest code. Note that one of the weights need to be
flipped from ‘+1’ to ‘−1’ before the new cycle arrives. After
31 cycles, a complete 31bit thermometer code is generated and
transformed into a 5bit binary code.
Timing diagrams of the ADC operations are illus- Fig. 21. Simulated bitline accumulation results with statistical mismatch.
trated in Fig. 14 for two different dot-product results
(e.g., 17 and 25). While the two dot-product results are fixed
throughout the conversion cycles, the ADC reference level 32× replica cells. The blue lines indicate the offset error of the
generated by the replica cells is swept for generating a ther- dot-product part (64x cells) while the black lines represent the
mometer code from cycle to cycle. When the dot-product result actual calibration value of offset calibration part (32x cells).
is 25, the sense amplifier output is zero for the first three cycles Before calibration, the offset calibration setting is reset to ‘0,’
since the ADC reference levels are higher than the dot-product and then it searches the optimal offset calibration code using
result. The reference levels are kept lower than the dot-product a binary-searching method. For instance, replica cells are set
result starting from the cycle #3, and hence the remaining to +2 when the offset is −3, as shown in Fig. 16(a), and
thermometer code is all ones. Similarly, the sense amplifier the calibration is set to −6 when the offset is +5, as shown
outputs are zeros at the beginning, and then it switches to one in Fig. 16(b). It takes five cycles to finish a calibration per each
when the ADC reference level crosses the dot-product result. column, and the calibration is performed individually from
Finally, the generated 31bit thermometer code is converted into column to column. Note that the programmed data of offset
a 5bit binary code (i.e., B [4:0] = 11100 or 11000 when the calibration block should be fixed with specific value before we
dot-product result is 25 or 17). Fig. 15 shows the simulated apply the column ADC to generate a digital thermometer code.
ADC characteristic over the swept dot-product result from Fig. 17 illustrates a complete block diagram of the
−32 to +32 with the step size of 2 for 1-to-5bit mode. column-based neuron comprising of 64× eDRAM cells for
The offset calibration is proposed to compensate the dot-product, 32× cells for ADC reference, 32× cells for
offset error occurring in ADC. Fig. 16 illustrates the offset calibration, a precharge driver, and a sense amplifier.
concept of the binary-searching based offset calibration using A dot-product between 64× binary inputs (X [0:63]) and

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676 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—I: REGULAR PAPERS, VOL. 68, NO. 2, FEBRUARY 2021
Fig. 22. Simulated classification accuracy versus Vdiff standard deviation
using MNIST/MLP and CIFAR-10/VGG-like CNN. The simulated variation
of our design is 2.84% (i.e., 14.2mV/500mV).
Fig. 23. The simulated MNIST classification accuracy difference between
binary weights and ternary weights.
64× ternary weights (WL0 /WR0 , WL1 /WR1 , · · · , WL63/WR63 )
is performed, and the resulting analog bitline voltage is
converted to a thermometer code based on the setting of
ADC reference (R [0:31]) along with the calibration code
(C [0:31]). Note that all three operations (i.e., dot-product,
ADC, and calibration) in the proposed column-based neuron
are performed via shared read bitlines (RBLL/RBLR).
VI. OVERALL A RCHITECTURE AND S IMULATION R ESULTS
Fig. 18(a) shows the overall architecture of the proposed
4T2C ternary eDRAM CIM macro. The macro is comprised
of a 16K (i.e., 128 × 128) eDRAM cell array with 128×
sense amplifiers for 128× parallel dot-product computations
and I/O periphery that includes write bitline (WBL) drivers,
read (RWL) and write wordline (WWL) decoders, output
registers, precharge drivers, and an RWL pulse generator.
A total of 128× eDRAM cells in a row share a write wordline
(i.e., WWL[i], i = 0 to 127) and a read wordline (i.e., RWL[i],
i = 0 to 127). Similarly, 128× cells in a column share
four bitlines including two write bitlines (i.e., WBLL[i] and
WBLR[i], i = 0 to 127) and two read bitlines (i.e., RBLL[i]
and RBLR[i], i = 0 to 127). For memory write operation,
each row is selected one by one via WWL decoders, and
WBL drivers are used to drive write bitlines and program
the selected bitcells. Prior to a compute-in-memory operation,
read bitlines are pre-charged by a pair of PMOS drivers.
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TABLE II
S UMMARY OF VGG-L IKE CNN M ODEL
TABLE III
S UMMARY OF MNIST/CIFAR-10 C LASSIFICATION R ESULTS
Once pre-charged, RWL decoders create either a negative short
pulse (for input ‘1’) or a DC high voltage (for input ‘0’)
for each row. Then, parallel multiply-and-accumulate (MAC)
computations are executed in every dot-product cells and
column-based neurons. A row of 128× sense amplifiers and
a shift-register based readout circuit is located towards the
bottom of the eDRAM array. Each sense amplifier converts
the dot-product result into a thermometer bit by sensing the
voltage difference in RBLL and RBLR. It takes multiple
cycles for a complete ADC operation depending on the output
precision mode, as described in section V. Although it is not
shown in Fig. 18(a), we also have write-back drivers for the
regular eDRAM cell refresh operation. The operating sequence
of the proposed eDRAM CIM macro, including a write/refresh
and compute-in-memory operations, is shown in Fig. 18(b).
The operating clock frequency is 200MHz, and the refresh
cycle is 200μs. It takes 12.8μs for a complete refresh operation
of 16K ternary eDRAM cells, and hence the throughput
of the proposed macro is 187.2M dot-products/sec per each
column, including the regular refresh operation. To minimize
the overall energy consumption while ensuring the accurate
computation results, we use 0.5V supply for both memory
core and RWL decoders and 0.7V supply for pre-charging
read bitlines.
Fig.19 presents the power and area breakdowns. eDRAM
array occupy the major area of this design (i.e. 54.72%).
On the other hand, the main power is eDRAM array
(i.e. 62.6%).
YU et al.: LOGIC-COMPATIBLE eDRAM COMPUTE-IN-MEMORY WITH EMBEDDED ADCs
TABLE IV
P ERFORMANCE C OMPARISON W ITH S TATE -O F -T HE -A RTS
Fig. 20 shows a comparison between 8T SRAM [6] and
the proposed 4T2C ternary eDRAM based macro and cell
layout. The SRAM based CIM macro performs a similar
bitline accumulate operation using two extra transistors for
decoupling read/write on top of the standard 6T SRAM bitcell.
Hence, it can store a binary weight and is free from retention
time issue. However, the size of its bitcell is significantly
larger than our 4T2C eDRAM cell. As shown in Fig. 19,
the proposed ternary 4T2C eDRAM cell only occupies 0.32×
area than the SRAM bitcell. The eDRAM memory density is
0.866Mb/mm2, which is 2.97× higher than the 8T SRAM.
Note that the layouts for both 8T SRAM and 4T2C eDRAM
follows the same standard logic design rule.
Fig. 21 shows the bitline accumulation transfer charac-
teristic based on 3K runs of Monte-Carlo simulation using
a column of 128× eDRAM cells. For verifying both lin-
earity and variation of the proposed eDRAM-based bitline
accumulation, we swept dot-product results from −128 to
+128 and measured the bitline voltage difference. Based
on the simulation result, we achieved the standard-deviation
of 13.7mV, 14.2mV, and 13.6mV, and the mean accu-
mulated bitline voltage difference of −121.9mV, 0V, and
121.4mV when the dot-product result is −64, 0, and +64,
respectively.
The impact of process variations in the bitline accumulation
has been assessed by measuring image classification accuracy
using two different neural network configurations and datasets.
The Vdiff std-dev/full-range of this design (i.e. 2.84%) is
from the Monte-Carlo simulation with PVT and mismatch
information, as shown in Fig.21. To show the trend of accuracy
with Vdiff std-dev/full-range, we sweep Vdiff std-dev/full-
range from 0 to 10.5%. In testing phase, we introduce the
noise obeying normal distribution with different variation
in each layer between convolution and batch normalization
layers, the error/variation generated within the hardware will
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677
represent itself as a random noise distribution at the output.
The red curve of fig. 22 shows the simulated classification
accuracy versus the worst-case standard-deviation (std-dev) of
the bitline voltage difference (Vdiff ) using a multi-layer per-
ceptron (MLP) network with two hidden layers (784-256-64-
10) and MNIST dataset. And the blue curve of fig. 22 shows
the simulated classification accuracy using a VGG-like con-
volutional neural network (CNN) with six convolution layers
and three fully-connected (FC) layers with CIFAR-10 dataset.
These two curves show a similar decreasing trend with the
increase of variation. Fig. 23 shows the classification accuracy
of using binary weight and ternary weights with the sweeping
variation (i.e. 0% to 10.5%). The simulated results clearly
illustrate that the ternary weight provides better accuracy
under all variation conditions. Table II summarizes detailed
configurations of the simulated VGG-like CNN model. A bina-
rized neural network [25] is used for training and testing
MLP and CNN models. The simulated MNIST classification
accuracy initially degrades slower than CIFAR10 results when
std-dev is lower, and then it decreases much quicker as std-
dev exceeds 4% of the full dynamic range. Based on the
simulated worst-case variation (i.e., σ = 2.84%) in Fig. 20,
the estimated classification accuracies are 96.78% for MNIST
using MLP and 82.8% for CIFAR-10 using the VGG-like
CNN model. The results show 0.6% and 1.3% accuracy
degradations, respectively, from the baseline results with no
variation. Table III summarizes the simulated MNIST/CIFAR-
10 classification results.
Table IV summarizes a performance comparison between
the proposed 4T2C eDRAM macro and prior CIM macros
based on 6-to-12T SRAM bitcells. Note that the proposed
work realizes a compact DRAM based CIM macro for the
first time. Compared to the previous SRAM-based works,
eDRAM offers its unique advantages, including the inherently
decoupled read/write ports and the high memory density.
678 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—I: REGULAR PAPERS, VOL. 68, NO. 2, FEBRUARY 2021
Besides, the proposed eDRAM macro is highly-reconfigurable
in terms of bit-precisions, and it embeds ADC per each
column-based neuron.
VII. C ONCLUSION
In this paper, we presented a novel 4T2C ternary eDRAM
cell for energy-efficient processing of DNN. The proposed
eDRAM cell consists of a pair of asymmetric 2T1C eDRAM
bitcells with decoupled read and write ports. Hence, one of the
critical issues (i.e., write disturbance) in analog compute-in-
memory has been eliminated. The compact eDRAM cell stores
a ternary weight and occupies 0.32× area (or 2.97× higher
memory density) than the 8T SRAM-based bitcell, which can
only store a binary state. The read wordline (RWL) is used
as an input port, and it can be reconfigured by programming
the number of short pulses in a pulse train. To address the
short retention time issue of eDRAM, we added custom metal
capacitors on the internal storage node without increasing the
cell size. We embedded column ADCs [6] in each column of
our eDRAM macro to address the ADC overhead issue, one of
the critical challenges in the analog CIM macro design. The
proposed ADC performs a reconfigurable 1-5bit conversion,
and it takes 1-31 conversion cycles (i.e., 2N − 1 cycles for
N-bit). A column of 128× eDRAM cells is comprised of
64× cells for dot-product, 32× for ADC reference, and 32×
for calibration. A Monte-Carlo simulation result demonstrates
both high linearity and the reasonable variation in the bit-
line accumulate operation. The simulated worst-case standard
deviation is 14.2 mV, which is 2.84% of the full dynamic
range of 500mV. The simulated MNIST classification result
using a three-layer MLP (784-256-64-10) architecture results
in the estimated accuracy of 96.78%, which is 0.6% lower than
the baseline with no process variation. The simulated CIFAR-
10 classification using a VGG-like CNN model results in an
estimated 82.8% accuracy, which is only 1.3% lower than the
baseline accuracy. The proposed ternary eDRAM cell presents
the smallest area (i.e., 1.08μm2) and the highest density
among the published CIM bitcells using 65nm technology.
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YU et al.: LOGIC-COMPATIBLE eDRAM COMPUTE-IN-MEMORY WITH EMBEDDED ADCs
Chengshuo Yu (Graduate Student Member, IEEE)
received the B.S. degree in electronic engineering
from Feng Chia University, Taiwan, in 2019. He is
currently pursuing the Ph.D. degree with the School
of Electrical and Electronic Engineering, Nanyang
Technological University, Singapore.
His research interests include in-memory comput-
ing and time-domain hardware accelerator.
Taegeun Yoo (Member, IEEE) received the B.S.,
M.S., and Ph.D. degrees in electrical and electron-
ics engineering from Chung-Ang University, Seoul,
South Korea, in 2009, 2011, and 2015, respectively.
From 2015 to 2016, he was with the Chung-Ang
University as a Research Professor. In 2016,
he joined Nanyang Technological University, Sin-
gapore, as a Research Fellow. His research inter-
ests include analog mixed-signal ICs and low-power
memory architecture. He received encouragement
award and silver award at the Human-Tech Paper
Award hosted by Samsung Electronics Company Ltd., in 2011 and 2014,
respectively. He also received the Silkroad Award at the IEEE International
Solid State Circuits Conference (ISSCC) in 2014.
Hyunjoon Kim (Student Member, IEEE) received
the B.A. degree in physics from the Oberlin Col-
lege, Oberlin, OH, USA, in 2008, and the M.S.
degree in electrical engineering from the University
of Minnesota, Minneapolis, MN, USA, in 2012.
He is currently pursuing the Ph.D. degree in digital
compute-in-memory (CIM) circuits and architecture
for machine learning applications with Nanyang
Technological University, Singapore.
From 2013 to 2018, he was with Gainspan Cor-
poration, San Jose, CA, USA, where he worked
as an RF Test Engineer for IEEE 802.11 standards. In 2018, he joined
Nanyang Technological University. His research interests include memory
centric systems, neural network accelerators, and its design methodologies.
Tony Tae-Hyoung Kim (Senior Member, IEEE)
received the B.S. and M.S. degrees in electrical
engineering from Korea University, Seoul, South
Korea, in 1999 and 2001, respectively, and the
Ph.D. degree in electrical and computer engineering
from the University of Minnesota, Minneapolis, MN,
USA, in 2009.
From 2001 to 2005, he was with Samsung Elec-
tronics Company Ltd., Hwasung, South Korea,
where he performed the research on the design of
high-speed SRAM memories, clock generators, and
IO interface circuits. From 2007 to 2009, he was with the IBM T. J. Watson
Research Center, Yorktown Heights, NY, USA, and Broadcom Corporation,
Edina, MN, USA, where he performed the research on circuit reliability,
low-power SRAM, and battery-backed memory design. In 2009, he joined
Nanyang Technological University, Singapore, where he is currently an
Associate Professor. He has authored or coauthored over 160 journal and
conference articles and holds 17 U.S. and Korean patents registered. His
current research interests include low-power and high-performance digital,
mixed-mode, and memory circuit design, ultralow-voltage circuits and sys-
tems design, variation and aging-tolerant circuits and systems, and circuit
techniques for 3-D ICs.
Dr. Kim received the Best Demo Award at APCCAS2016, the Low Power
Design Contest Award at ISLPED2016, the best paper awards at 2014 and
2011 ISOCC, the AMD/CICC Student Scholarship Award at the IEEE
CICC2008, the Departmental Research Fellowship from the University of
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679
Minnesota in 2008, the DAC/ISSCC Student Design Contest Award in 2008,
the Samsung Humantech Thesis Award in 2008, 2001, and 1999, and the
ETRI Journal Paper of the Year Award in 2005. He was the Chair of the IEEE
Solid-State Circuits Society Singapore Chapter. He has served on numerous
conferences as a Committee Member. He also serves as an Associate Editor for
the IEEE T RANSACTIONS ON V ERY L ARGE S CALE I NTEGRATION (VLSI)
S YSTEMS , IEEE A CCESS , and the IEIE Journal of Semiconductor Technology
and Science.
Kevin Chai Tshun Chuan (Senior Member, IEEE)
received the B.Eng. (Hons.) and Ph.D. degrees in
electronic and electrical engineering from the Uni-
versity of Glasgow, U.K., in 2002 and 2007, respec-
tively, developing tissue cell imaging solution based
on Electrical-Impedance-Tomography on a CMOS
chip.
He joined the Institute of Microelectronics,
A∗ STAR, Singapore, in 2008, as a Research Scien-
tist and developed a silicon-nanowire based biosen-
sor readout system for the detection of biomarkers
in cardiac disease. He received several competitive A∗ STAR grants as a
PI/Co-PI for MEMS sensor-related applications in temperature, motion and
sound detection, cell counting, electronic stethoscope system for the early
detection of diastolic dysfunction in hypertensive heart disease, and so on.
He currently heads a department of more than 30 IC designers working
on various topics from AI powered hardware accelerators looking at both
deep learning and neuromorphic methodologies, compute-in-memory using
emerging memories, hardware security for edge IOT, power management
solution with IVR, mmWave IC, and design acceleration techniques using
machine learning.
Bongjin Kim (Member, IEEE) received the B.S.
and M.S. degrees from POSTECH, Pohang, South
Korea, in 2004 and 2006, respectively, and the Ph.D.
degree from the University of Minnesota, Minneapo-
lis, MN, USA, in 2014.
He spent two years with Rambus, Sunnyvale, CA,
USA, where he was a Senior Staff Member and
worked on the research of high-speed serial link
circuits and microarchitectures. He was as a Post-
doctoral Research Fellow with Stanford University,
Stanford, CA, USA, for a year. From 2006 to 2010,
he was with Samsung Electronics Company Ltd., Yongin, South Korea, where
he performed research on clock generators for high-speed serial links and
clock generators. He also worked as a Research Intern with Texas Instruments,
Dallas, TX, USA, IBM TJ Watson Research, Yorktown Heights, NY, USA,
and Rambus, during his Ph.D., from 2012 to 2014. He joined Nanyang Tech-
nological University (NTU), Singapore, in September 2017, as an Assistant
Professor. His current research interests include memory-centric computing
devices, circuits, and architectures, hardware accelerators, alternative com-
puting, and mixed-signal circuit design techniques and methodologies. His
research works appeared at top integrated circuit design and automation
conference proceedings and journals, including ISSCC, VLSI Symposium,
CICC, ESSCIRC, ASSCC, ISLPED, DATE, ICCAD, IEEE J OURNAL OF
S OLID -S TATE C IRCUITS (JSSC), and IEEE T RANSACTIONS ON V ERY
L ARGE S CALE I NTEGRATION (VLSI) S YSTEMS (TVLSI).
Dr. Kim was a recipient of the Prestigious Doctoral Dissertation Fellowship
Award based on his Ph.D. research works, the International Low Power Design
Contest Award from ISLPED, and the Intel/IBM/Catalyst Foundation Award
from CICC.