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Name:S.

Srikrishnakaushik roll no:21BEC0042

Subject: DSD lab

Question: Simplify the given Function using only NAND gate write the gate level HDL for the same
Circuit Diagram:
Truth Table:
Verilog code:

module taska(A,B,C,D,F);

input A,B,C,D;

output F;

wire H,J,K,L,M,N,O,P;

nand g1(H,A,A);

nand g3(J,C,C);

nand g4(K,D,D);

nand g5(L,H,J);

nand g6(M,J,B);

nand g7(N,H,K);

nand g8(O,A,K);

nand g9(P,L,M,N,O);

nand g10(F,P,P);

endmodule
Output Graph:

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