10:05 PM | 35.7KB/s © OQ @ scribd.com/doc/1588 = §} SCRIBD ( Search Q ) Download now W 08.503 Computer Organization and Architecture Module 1 Module | A computer consists of five functionally independent main parts: input, memory, arithmetic and logic, output, and control units, as shown below. — = = Joput Unit © Computers accept coded information through input units. # The most common input device is the keyboard. Whenever a Key is pressed, the corresponding: letter or digit is automatically translated into its corresponding binary code and transmitted to the processor © Many other kinds of input devices for human-computer interaction are: touehpad, mouse, Joystick, trackball ete. These are ofien used as graphic input devices in conjunction with display. © Microphones can be used to ea codes for storage and processing, © Cameras can be used to capture video input ipture audio input which is then sampled and converted into digital + Digital communication facilites, such as the Internet, can also provide input to a computer from ‘other computers and database servers. Output Unit The output unitis the counterpart ofthe input unit, #Itsends processed results to the outside world. * A familiar example of output device is a printer: # Some units, such as graphie displays, provide both an output function, showing text and graphics and an input function, through touch screen capability. The dual role of such units is the reason for using the single name input/output (1/0) unit in many cases. Memory Unit The function of the memory unit is to store programs and data, © There are two classes of storage, called primary and secondary Primary Memory * Primary memory, also called main memory, is a fast memory that operates at electronic speeds, © Programs must be stored in this memory while they are being executed. © The memory consists of a large number of semiconductor storage cells, each capable of storing ‘one bit of information, These cells are rarely read or written individually. Instead, they are Dept, of ECE, VKCET $ CH 63 z Home Books Audiobooks Documents10:05 PM | 21.8KB/s © Download now 08.503 Computer Organization and Architecture Module 1 handled in groups of fixed size called words. The memory is organized so that one word can be stored or retrieved in one basic operation. The number of bits in each word is referred to as the ‘word length of the computer, typically 16, 32, or 64 bits. To provide easy access to any word in the memory, a distinct address is associated with each word location. Addresses are consecutive numbers, starting from 0, that identily successive locations. A memory in which any location can be accessed in a short and fixed amount of time after speci’ sees memory (RAM), The time required to access one word is called the memory access time. This time is independent of the location of the word being accessed. It typically ranges from a few nanoseconds (ns) to about 100 ns for current RAM units its address is called a random © Cache Memory: As an adjunet to the main memory, a smaller, faster RAM unit, called a cache, used to hold sections of a program that are currently being executed, along with any associated data, The cache is tightly coupled with the processor and is usually ¢ integrated-circuit chip. The purpose of the cache is to facilitate high instruction execution rates. Secondary Storage Although primary memory is essential, it tends to be expensive and does not retain information when power is tumed off, Thus additional, less expensive, permanent secondary storage is used when large amounts of data and many programs have to be stored, particularly for information that is accessed infrequently. # Access times for secondary storage are longer than for primary memory + A wide selection of secondary storage devices is available, including magnetic disks, optical disks (DVD and CD), and flash memory devices. Arithmetic and Logic Unit Most computer operations are executed in the Any arithmetic or logic operation, such as addition, subtraction, multiplication division, or comparison of numbers, is initiated by bringing the required operands into the processor, where the operation is performed by the ALU thmetie and logic unit (ALU) of the processor For example, if two numbers located in the memory are to be added, they are brought into the processor. and the addition is carried out by the ALU. The sum may then be stored in the memory ‘or retained in the processor for immediate use. Control Unit © The memory, arithmetic and logic, and VO units store and process information and perform input and output operations. © The operation of these units must be coordinated by the contro! unit ‘© The control unit is effectively the nerve center that sends control signals to other units and senses their states. © Control circuits are responsible for generating the timing signals that govern the transfers and determine when a given action is to take place. © Data transfers hetween the processor and the memory are also managed by the control unit through timing signals, © Control unit as a well-defined, physically separate unit that interacts with other parts of the computer. Dept. of ECE, VKCET Page 2 MN ayela is Scribd? $ Home M 62 Es) Books Audiobooks DocumentsIl GC n O wy W u o a 2) Download now W 08.503 Computer Organization and Architecture Module 1 Yon-Neumann architecture © Only one bus which is used for both data transfers and instruction fetches, and therefore data transfers and instruction fetches must be scheduled - they cannot be performed at the same time address| memory | data Crogan | on and Data) Only one memory, holds data and programs + Need minimum two cycles to complete memory fetching # Poor memory throughput # Pipelining is not possible # Allows easy storing and loading of program between main memory and processor * Older architecture, only used for economic and general purpose processors rvard architecture © Separate data and instruction busses, allowing transfers to be performed simultaneously on both busses address datamemory | a4, address ~ program memory | date ‘© Possible to have two separate memory systems for data and program © Allow two simultaneous memory fetching operations © Greater memory bandwidth (throughput) © Ibis easier to pipeline instructions © Most of the DSP processor uses this architecture Dept, of ECE, VKCET What is Scribd? Home Books Audiobooks DocumentsIl GC n O wy W u o a 2) Download now W 08.503 Computer Organization and Architecture Module 1 © CPU executes binary representation of instruction called machine codes. © Program Counter (PC) is used to determine which instruction is executed and based on the instruction itis updated accordingly to the next instruction to be run, Consider the connection between processor and main memory Mai swemoey MAR MR | Control aL * There are five major steps to execute a single instruction, They are: Step 1: Fetch instruction To fetch an instruction involves the following steps: © CPU place an address to the Memory Address Register (MAR) fiom PC. © CPU place MAR contents to the address bus, * CPU sends read signal to memory * Memory unit puts instruction on the data bus. + Memory sends acknowledge signal to CPU, * CPU loads the instruetion to the Memory Data Register (MDR), © CPU transfers instruction from MDR to Instruction Register (IR). * CPU sends acknowledex Step 2: Decode instruction and fetch operands: (CPU decodes instruction in TR and if needed it fetches operands. To fetch an operand in memory involves the following steps: * CPU places the address of operand to MAR. signal to memory that fetching the instruction is over * CPU place MAR content to ackiress bus. * CPU sends read signal to memory © Memory unit puts operand on the data bus, © Memory sends acknowledge signal to CPU. Dept. of ECE, VKCET What is Scribd? $ CH 63 z Home Books Audiobooks Documents10:05 PM | 2.2KB/s © Download now W 08.503 Computer Organization and Architecture Module 1 © CPU loads the operand to the Memory Data Register (MDR). © CPU moves the operand to ALU Ifone operand is in CPU, itis moved to ALU for operation, Step 3: Perform operation ‘CPU performs the operation encoded in instruction, If it is an ALU operation, CPU performs it using operands, Step 4: Store the result If the result is to store in memory, CPU involves the following steps * CPU places the address of the result to MAR and to address bus, # CPU places the result io MDR. * CPU sends the write signal to memory © Memory store the result to the address in address bus © Memory sends acknowledge signal to CPU. Step 5: Update Program Counter (PC), CPU update (either incremented by 1, 2 or 4) the PC content to point next instruction to be executed ‘* Includes opcode and implicit or explicit operands) ‘© Usually there are several instruction formats in an instruction set ‘+ Variety of instruction formats have been designed; they vary widely from processor to provessor The length of instruction depends on: —Memory size = Memory organization — Bus structore — CPU complexity — CPU speed © Using large instruction set small programs can be created and small instruction set results la programs © Fixed le ‘© Variable length instructions may need extra bus eyeles, Survey of addressing modes: © Fora given instruction set architecture (ISA), addressing modes define how machine langu: instructions identify the operand (or operands) of each instruction, © An addressing mode specifies how to calculate the effective memory address of an operand by using information held in registers and/or constants contained within a machine instruction or elsewhere th instructions of same size or multiple of bus width results fast fetch Different types of addresses involve tradeoffs between instruction length, addressing flexibility, and complexity of address calculation = Common addressing modes are: 1. Direct Addressin 2, Immediate Add sing Dept. of ECE, VKCET Page 5 What is Scribd? $ CH 63 z Home Books Audiobooks DocumentsIl GC n oO 7 w o Search Q ) Download now W (08.503 Computer Organization and Architecture Module 1 3. Indirect Addressing 4. Register Addressing 5. Reuister indirect Addressing 6. Displacement Address Implied (stack) Addressing Direct Addressing © The instruction tells where the value can be found, but the value itself is out in memory. + The address field contains the address of the operand Effective address (FA)= address field (A) + Inahigh level language, direct addressing is frequently used for things like global variables, Advantages: Si memory reference to ac Instruction a operand © The instruction itself contai instruction the operand to be used; located in the address field of the © The operand is stored in memory immediately afier the instruction opcode in memory © Similar to using a constant in a high level language Instruction operand Addressing # The memory cell pointed to by the address field contains the address of (pointer to) the operand ee ee operand Page 6 What is Scribd? $ CH 63 z Home Books Audiobooks Documents10:05 PM | 5.8KB/s © = §3 SCRIBD ( Search Download now W 08.503 Computer Organization and Architecture Module 1 Addi Operands are registers There isa limited number of registers Very fast execution Very limited address space Multiple registers can help performance Requires good assembly programming or compiler writing Instruction R — operand Renisters ect addressing COperand is in memory cell pointed to by contents of register R # Large address space instruction operand | Registers Displacement Addressing © Combines register-indirect addressing and direct addressing © BA=A+(R) © Address field holds two values: A= base value and R = register that holds displacement or vice-versa operand Aegis ‘Types of Displacement Addressing LL Relative Addressing 2. Base-register addressing 3. Dept. of ECE, VKCET Page 7 What is Scribd? $ CH 63 z Home Books Audiobooks Documents10:05 PM | 7.8KB/s © Download now W 08.503 Computer Organization and Architecture Module 1 Relative Addressing © EA=A+(PC) © Addn ‘© Fetch operand from PC+A © Can be very efficient because of locality of reference & cache usage. But in large programs code and data may be widely separated in memory field A is treated a to allow backward references complement integ Base-Register Addressing * A holds displacement © Rholds pointer to base address ‘© R may be explicit or implicit Indexed Addressing + A=Base © R= displacement * BATAGR Stack Addressing © Operand is implicitly on top of stack Performance measurement and benchmarking: © The performance of computers can be differentiated by the response time - the time between the start and the completion of an event also referred to as execution time as well as throughput - the total amount of work done in a given time, © To compare the relative performance of wo different computers, X and Y. The phrase "X is faster than Y" is used to mean that the response time or execution time is lower on X than on Y for the given task. In particular, "X is m times faster than Y" will mean Execution time y Execution timex ‘© The execution time is the reciprocal of performance, then Execution timey — Pe Y _ Performance, Execution timey * Performancey ex This shows that the performance of X is n times higher than Y. # The execution time can be defined in different ways clock time, response time, or elapsed time, which is the latency to complete a task, including disk accesses, memory accesses, input/output activities, operating system overhead ete Processor Performance Equation | ©All computers are constructed usin led ticks, clock ticks, clock periods, clocks, a clock running at a constant rate, These discrete time events cles, or clock cycles. © Computer designers refer to the time of a clock period by its duration (e.g., 1 ns) or by its rate (eg. 1 GH) # CPU time fora program can then be expressed as CPU time = CPU clock eycles fora program x Clock eycle time Dept, of ECE, VKCET What is Scribd? Home Books Audiobooks Documents10:05 PM | 9.9KB/s © Download now W (08.503 Computer Organization and Architecture Module 1 <2 Rites Clock rate © This is referred as performance equation 1. Problem: A program runs in 20 seconds on a computer A which has a SGHz clock. Another computer B is built that will run this program in 12 seconds. For this, computer B requires 2.4 times as many as clock cycles as computer A for this program. What isthe clock rate of B? Solution: CPU time of A = 20 sex Clock rate of A = 8GHz CPU clock eycles for a program of A = CPU time of A x Clock rate of A =20x 8 x 107 CPU time of B = 12 seconds CPU clock cycles for the program of B =24x20x8x 10" Clock rate of B= CPU clock eyeles for the program of B / CPU time of B (24x 20x8x 10°)/ 12 2GHz mds Ax CPU clock cycles for the program of A Processor Performance Equation | © Inaddition to the numb, of clock eycles needed to execute a program, we can also count the number of instructions executed or instruction count (IC), If we know the number of clock cycles and the instruction count, we can calculate the average number of clock eyeles per instruction (CPP). # Itis easier to work with and designers sometimes also use instructions per clock (IPC), which is the inverse of CPI * CPLis computed as CPU clock cycles fora pro Instruction count © This allows us to use CPI in the execution time formula and is, CPU time = Instruction count x CPI x Clock eyele time Instruction count x CPL or CPU time = ——— Clock rate © This called performance equation 2 © Expanding the performance equation | into the units of measurement shows how the pieces fit together: Instructions ,. Clock e Seconds _ Seconds Program "Instruction ~ Clock cycle ~ Program = CPU time + This formula demonstrates, processor performance is dependent upon three characteristics clock cyele (orrate), clock cycles per instruction (CPI), and instruction count Dept. of ECE, VKCET Page 9 What is Scribd? $ CH 63 z Home Books Audiobooks Documents10:05 PM | 2.5KB/s © Download now W (08.503 Computer Organization and Architecture Module 1 * CPU time is equally dependent on these three characteristics: A 10% improvement in any one of them leads to 2 10% improvement in CPU time. isolation from others because the basie each characteristic are interdependent: % Clock eyele time - Hardware technology and organization © It is difficult to change one parameter in comple technologies involved in chan; > CPI- Organization and instruction set architecture > Instruction count - Instruction set architecture and compiler technology Problem: c c Clock 30Hz 3GHz cP 1s 1 No.of instructions billion 9 billion Which computer is faster and by how much? Solution: Instruction count of Cx CPlof G, _8x10° x15 CPU time of 4 seconds Clock rate of Cy 3x10" cpu og, = [mstructioncount of C2 CPI of Cz _9X10°X1 yg mee Clock rate of Cy gq? ees CPU performance ofC _ CPU time of Cy _ 3 CPU performance of C,~ CPUtime of C, 4 ‘The computer C2 is 1.33 time faster than C, 075 CISC and RISC: cI (Complex I © CISC chips that are easy to program and which make eflicient use of memory. S nce the earliest machines were programmed in assembly language and memory was slow and expensive, the CISC philosophy made sense, and was commonly implemented in such large computers as the PDP-11 and the DEC system 10 and 20 n * Most common microprocessor designs such as the Intel 80x86 and Motorola 68K series followed the CISC philosophy © CISC was de generating machine instructions to the process eloped to make compiler development simpler. It shifts most of the bunten of 1. For example, instead of having to make a compiler write long machine instructions to calculate a square-root, a CISC processor would have a built-in ability to do this © Some common characteristies of CISC instruction are: 1. Two operand format, whe: Register to Multiple addressing modes for memory, including specialized modes for indexing through nstructions have a source and a destination sister, register to memory, and memory to register commands. 4, Variable length instructions where the length often varies according to the addressing mode 5. Instructions which require multiple clock eycles to execute, © E.g, Pentium is considered a modern CISC processor Dept. of ECE, VKCET Page 10 What is Scribd? $ CH 63 z Home Books Audiobooks Documents10:05 PM | 10.3KB/s © Download now W (08.503 Computer Organization and Architecture Module 1 CISC hardware architectures have several characteristics in common and are: 1. Complex instructionsecoding logic, driven by the need for a single instruction to support multiple addressing modes. A smnall number of general purpose registers. This is the direct result of having instructions which can operate directly on memory and the limited amount of chip space not dedicated to instruction decoding, execution, and microcode storage. 3. Several special purpose registers. Many CISC designs set aside special registers for the stack pointer, interrupt handling, and so on, This can simplify the hardware design somewhat, at the expense of making the instruction set more complex 4, A ‘Condition code” register which is set as a side-effect of most instructions. This register reflects whether the result of the last operation is less than, equal to, or greater than zero and records if certain error conditions occur + Advantages of CISC processors: 1. Microprogs 1 than hardwiring a control unit 2, ‘The ease of micro-coding new instructions allowed designers to make CISC machines upwardly compatible: a new computer could run the same programs as earlier computers because the new computer would contain a superset of the instructions of the earlier computers. 3. As each instruction became more capable, fewer instructions could be used to implement a given task, This made more efficient use of the relatively slow main memory 4, Because microprogram instruction sets can be written to match the constructs of high-level languages, the compiler does not have to be as complicated. ming is as easy as assembly language to implement, and much less expensive # Disadvantages of CSIC processors 1, Earlier generations of a pro version ~ so instruction set & chip hardware became more complex with each generation of computers. 2, So that as many instructions as possible could be stored in memory with the least possible ‘wasted space, individual instructions could be of almost any length - this means that different instructions will take different amounts of clock time to execute, slowing down the overall performance of the 3. Many specialized instructions aren't used frequently enough to justify their approximately 20% of the available instructions are used in a typical program. 4. CISC instructions typically set the condition codes as a sid does setting the condition codes take time, but program the condition code bits before a subsequent instruction changes them, e contained as a subset in ever ssor family generally we machine. fence - effect of the instruction, Not only es have to remember to examine A type of microprocessor architecture that utilizes a small, highly-optimized set of instructions, rather than a more specialized set of instructions often found in other types of architectures. # Some characteristic of most RISC processors are: 1. One eyele execution time: RISC processors have a CPI (clock per instruction) of one cycle This is due to the optimization of each instruction on the CPL 2. Pipelining: A technique that allows for simultaneous execution of parts, or stages, of instructions to more efficiently process instructions. Dept. of ECE, VKCET Page 11 What is Scribd? $ CH 63 z Home Books Audiobooks Documents10:05 PM | 7.2KB/s ©& Download now W (08.503 Computer Organization and Architecture Module 1 3. Large number of registers: The RISC design philosophy generally incorporates a larger ‘number of registers to prevent in large amounts of interactions with memory. + In comparison with CISC, RISC processors have the following features: Redu Less complex, simple instructions. Hardwired control unit and machine inst Few addressing schemes for memory operands with only two basic instructions LOAD and STORE. 5. Many symmetric registers which sd instruction tions. anized into a register file, CISC and RISC process cise RISC Emphasis on hardware Emphasis on software Includes multi-clock Single-clock, complex instructions reduced instruction only Memory-to-memory Register to register: "LOAD" and "STORE" "LOAD" and "STORE" incorporated in instructions | areindependent instructions Small code sizes, high Low eycles per second, cycles per second lange code sizes Transistors used for storing | Spends more transistors complex instructions on memory registers Computer Arithmetis: Addition/Subtraction: * Addition and subtraction of two numbers are basic operations at the machine-instruction level in all computers * These operations, as well as other arithmetic arithmetic and logic unit (ALU) of the processor jon and Subiraction of Signed Numbers ‘The truth table for the sum and carry-out functions for adding equally weighted bits x j and yin and logic operations, are implemented in the ‘ovo numbers X and Y is shown below. oy Campane, | Sums, Canyon ey, o 0 0 o © o oo 4 1 © o 1 0 1 0 oo ron o 1 too o4 o 1 bo4 oe ° 1 Horo 1 1 Dept. of ECE, VKCET Page 12 What is Scribd? $ CH 63 z Home Books Audiobooks Documents