= Optimization framework for energy—delay trade-off = Dynamic-power optimization — Multiple supply voltages hnology mapping = Static-power optimization Multiple thresholds — Transistor stacking Practical Transistor Sizing = Continuous sizing of transistors only an option in custom design . = In ASIC design flows, options set by available library = Discrete sizing options made possible in standard-cell design methodology by providing multiple options for the same cell . — Leads to larger libraries (> 800 cells) = (00 © elke. — Easily integrated into technology mappingTechnology Mapping em a nen- (md < Poth x _ Larger gates reduce capacitance, but are slowerhs allw + reanth He Br) wane OU lm vee cnr ea ae) nl 4 [wma BE emer ae) ee ee eee oy Re ae a eee SiC ae ze orn | fm feces ia bat! I me sai (Fca ac rE ee Ht =Technology Mapping Example: four-input AND _ = (a) Implemented using four-input NAND + INV) ~~ = (b) Implemented using two-input NAND + two-input NOR ~~ Library 1: Library 2: High-Speed —_ Low-Power Area Input unit) | cap. (fF) 3 4 5 22.7 + 10.20, 3 16.7 + 8.9C, 12.0+6.0C, 16.3 + 8.80, (delay formula: C\in fF) (numbers calibrated for 90 nm)Technology Mapping — Example put AND | (@) NAND4 + | (b) NAND2 + INV Area 8 HS: Delay (ps) | 31.0+3.8C, LP: Delay (ps) | 53 Sw Energy (fF) 0.1 = Area Four-input more compact than two-input (two gates vs three gates) = Timing — Both implementations are two-stage realizations Second-stage INV (a) is better driver than NOR2 (b) — For more complex blo mpler gates will show better performance = Energy Internal switching increases eneray in the two-input case Low-power library has worse delay, but lower leakage (see later) saa gals twepl™ Pe OLSO MENS OL ema aes ane AeALO) Sal VD) an aeaee Man P3 Was es NTO Ly Ove anata kubbs. A EN Banal ny eRee Lea oo ELIF Tate ears aa Gate-Level Trade-offs for Power = Technology mapping " Gate selection = Sizing = Pin assignment * Logical Optimizations * Factoring * Restructuring " Buffer insertion/deletion = Don't-care optimizationA im eee v ia vs ci ace Be eer reer = Ls Ts re : Aer ece eee =e a: gb ey Ewe : Sa ReL ee Se ee Saar e i pemowees a ane) f a Caene- 3 ccd Pai fone es Am Pao i ri mm 4 % BI N ie ReLogic Restructuring Buffer insertion for path balancing PPO ION) TMM ano SOU 6 UF ut ba . 0 cm craw iva pL Synod TaAlgebraic Transformations Factoring Idea: Modify network to reduce capacitance Caveat: This may increase activity!| A | 4 | ; : & | 4 ry ied en ene F aa: Se Sar Scene 4 ira re eee) Es eae rae ia Pind aia aie a bia i.| 4 ar rae =aCan See ce se Pr |Lessons from Circuit Optimization Joint optimization over multiple design parameters possible using sensitivity-based optimization framework = Equal marginal Energy-efficient design Peak performance is VERY power inefficient — About 70% energy reduction for lelay penalty — Additional variables for higher energy-efficiency Two supply voltages in general sufficient; three or more supply voltages only offer small advantage Choice between sizing and supply voltage parameters depends upon circuit topology But ... leakage not considered so far