Compal

A B C D E
MODEL NAME : VAW11

PROJECT CODE : ANRVAW1100
PCB NO : LA-9102P (Mars Pro)
1
DA60000UU00 LA-9102P M/B 1
DA40001G400 LS-9105P POWER BUTTON/B

DA40001FP00 LS-9102P USB/B
DA40001FQ00 LS-9103P TP BUTTON/B
DA40001FR00 LS-9104P ODD/B
Dell / Compal Confidential

2
Schematic Document 2
Intel Chief River

Ivy Bridge(BGA) + Panther Point
OAK 17" UMA/DIS AMD Mars Pro
2012-09-25
3 Rev: 1.0 3
46@ : for 46 level

@ : Nopop Component R1@ : R1 P/N i3R1@ : CPU i3-3217 1.8G DIS@ : Only for Discrete
CONN@ : Connector Component R3@ : R3 P/N i3VOSR1@ : CPU i3-2365 1.4G TH@/THR1@ : Thames-XT
KB9012@ : ENE KB9012 Implemented i5R1@ : CPU i5-3317 1.7G MS@/MSR1@ : Mars Pro
UMA@ : Only for UMA i7R1@ : CPU i7-3517 1.9G X76@ :
EMC@ : EMI/ESD parts CELR1@ : CPU Celeron 887 1.5G SPI-ROM & VRAM Group
PENR1@ : CPU Pentium 997 1.6G
GCLK@ : Green CLK implemented
4
GCLKUMA@ : Green CLK for UMA ZZZ R1@ ZZZ R3@ 4
GCLKDIS@ : Green CLK for DIS PCB 0T3 LA-9102P REV0 M/B PCB-MB
DA60000UU00 DA80000R911
XTAL@ : X'tal implemented Security Classification Compal Secret Data Compal Electronics, Inc.
WWW.MANUALS.CLAN.SU Issued Date 2012/09/25 2013/09/30 Title
Deciphered Date
XTALDIS@ : X'tal with DIS implemented THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size
Custom
Cover Page
Document Number Rev
1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-9102P
Date: Tuesday, September 25, 2012 Sheet 1 of 57
A B C D E
A B C D E
Fan Control CPU XDP

64M*16 128M*16 P.40 Conn. P.6
VRAM * 4 VRAM * 4 Intel
DDR3 P.30 DDR3 P.30
64bit
Ivy Bridge Memory Bus (DDR3)
1
64M*16 Dual Channel DDRIII-DIMM X2 1
VRAM * 4 AMD PEG 2.0 x8

Processor BANK 0, 1, 2, 3, 4 ,5 ,6 ,7
1.5V DDR3 1333 MHz P.11~12
DDR3 P.31
Thames-XT 17W DC
128M*16 64bit
24-26 W P.24~29 8GB Max
VRAM * 4 BGA 1023
DDR3 P.31
AMD Mars Pro, 128b, P.5~10
Radeon HD8650M,
P7000-P8000 FDI x8 DMI x4
1GB DDR3 (8-64Mx16), 100MHz 100MHz
2GB DDR3 (8-128Mx16) 2.7GT/s 5GB/s
SATA3.0 Port 0
LVDS SATA HDD Conn.
P.41
LVDS Conn.
P.21
Port 2 SATA ODD Conn.
HDMI P.41 Daughter board
2 HDMI Conn. 2
P.22
Intel
Panther Point
PCH HM77 USB 3.0 Port 1,2
USB 3.0 Conn. 1
P.36
Port 0,1 USB 3.0 Conn. 2
USB2.0
Port 2,3 USB 3.0 Conn. 3
PCI-E x1
BGA 989 Balls USB 2.0 Conn. 4 P.37
Daughter board
Port 11 Digital Camera
Port 2 Port 1 (With Digital MIC) P.21
Mini Card Ethernet Port 8 Mini Card
WLAN/BT4.0 RTL8105E WLAN (Half) P.38
Half P.38 P.32

Port 10 Card Reader P.34
RTS5170/RTS5179 3 in 1 Socket
P.34
3 3
RJ45 Port 9 Touch Screen

P.32
P.21
HD Audio
P13~20
Digital Mic.
SPI
RTC CKT. SPI ROM
P.44 4MB P.13 LPC Bus Audio Codec Headphone Jack / Mic. Jack combo P.33
33MHz ALC3221
Power On/Off CKT. SPI P.33 Int. Speaker R / L P.33
P.40 SPI ROM
2MB P.13
DC/DC Interface CKT. ENE KBC

P.35
KB9012 P.39
PS/2
4 4
Int.KBD Touch Pad

P.40 P.40
Security Classification Compal Secret Data Compal Electronics, Inc.

2012/09/25 2013/09/30 Title
WWW.MANUALS.CLAN.SU
Issued Date Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Block diagram
Size Document Number Rev
1.0
LA-9102P
A B C D E
A B C D E
Compal Confidential
Project Code : VAW11
File Name : LA-9102P
LS-9104P (ODD/B)
LS-9105P (PWR/B)
1 1
UE5
Lid (SA00003VQ00)
SW1 4 pin-Hot Bar JBTB2

(SN100004Y00)
12 pin
PBATT
Battery
JMINI
JODD
PWR-BTN FFC MINI Card JLVDS
4 pin 40 pin
PJPDC JKB
5 pin 30 pin
JTP LS-9102P (USB/B)

2 2
6 pin
HDMI
JHDMI JBTB1
JFAN
12 pin
JPWR 3 pin USB JUSB4
4 pin
USB-DB FFC 8 pin
XDP 8 pin Hot Bar
JLAN RJ-45
JXDP
LA-9102P M/B JDB
8 pin
JUSB1 USB Top Side JHDD

RTC JRTC
Bottom Side
2 pin
JUSB2 USB
(OAK 17")
JUSB3 USB
JREAD
3
JSPK 3
4 pin
Card
TP-MB FFC JHP HP Reader
6 pin
Led1 Led3
Led2 Led4
TP-Module
4
TP-BTN FFC 4
4 pin
LS-9103P (TP-BTN/B)
4 pin Issued Date 2012/09/25 Deciphered Date 2013/09/30 Title
Hot Bar DB block diagram
WWW.MANUALS.CLAN.SU
SW2 SW3
1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-9102P
A B C D E
A
Board ID Table for AD channel

Vcc 3.3V +/- 5%
Ra 100K +/- 5% BOARD ID Table Project ID Table
Board ID Rb V AD_BID min V AD_BID typ V AD_BID max EC AD3 ID PCB Revision ID Project Revision USB PORT# DESTINATION
0 0 0 V 0 V 0.155 V 0x00-0x0C 0 0.1 0
1 8.2K +/- 5% 0.168 V 0.250 V 0.362 V 0x0D-0x1C 1 0.1 0.1 1 0 USB conn.2
2 18K +/- 5% 0.375 V 0.503 V 0.621 V 0x1D-0x30 2 0.2 2
3 33K +/- 5% 0.634 V 0.819 V 0.945 V 0x31-0x49 3 0.2 0.2 3 1 USB conn.1
4 56K +/- 5% 0.958 V 1.185 V 1.359 V 0x4A-0x69 4 0.3 4
5 100K +/- 5% 1.372 V 1.650 V 1.838 V 0x6A-0x8E 5 0.3 0.3 5 UMA 2 USB conn.3
6 200K +/- 5% 1.851 V 2.200 V 2.420 V 0x8F-0xBB 6 1.0 6 DIS THAMES
7 NC 2.433 V 3.300 V 3.300 V 0xBC-0xFF 7 1.0 1.0 7 DIS MARS PRO 3 USB conn.4 (DB)
UMA THM MARS
4 NC
SMBUS Control Table
Express Thermal VGA Thermal
SOURCE MINI1 MINI2 BATT SODIMM Card Sensor FFS Sensor VGA XDP Charger 5 NC
PCH 6 NC
EC_SMB_CK1
EC_SMB_DA1
KB9012 V V
EC_SMB_CK2 KB9012 V V 7 NC
EC_SMB_DA2
PCH_SML0CLK PCH Link 8 MINI CARD (WLAN)

PCH_SML0DATA
PCH_SML1CLK PCH 9 NC
PCH_SML1DATA
MEM_SMBCLK PCH V V V V V V 10 Card Reader

MEM_SMBDATA
11 Camera
12 NC
DIFFERENTIAL DESTINATION FLEX CLOCKS DESTINATION
1 1
CLKOUT_PCIE0 10/100 LAN CLKOUTFLEX0 None 13 NC
CLKOUT_PCIE1 MINI CARD WLAN CLKOUTFLEX1 None

SATA DESTINATION PCI EXPRESS DESTINATION
CLKOUT_PCIE2 None CLKOUTFLEX2 None
SATA0 HDD Lane 1 10/100 LAN
CLK CLKOUT_PCIE3 None CLKOUTFLEX3 None
SATA1 None Lane 2 MINI CARD (WLAN)
CLKOUT_PCIE4 None
CLKOUT_PCIE5 None SATA2 ODD Lane 3 None

CLKOUT DESTINATION
SATA3 None Lane 4 None
CLKOUT_PCIE6 None
PCI0 PCH_LOOPBACK
CLKOUT_PCIE7 None
PCI1 EC LPC
CLKOUT_PEG_B None
PCI2 None
Lane 7 None
PCI3 None
Symbol Note :
Lane 8 None
PCI4 None
: means Digital Ground
: means Analog Ground

Issued Date 2012/09/25 Deciphered Date 2013/09/30 Title
WWW.MANUALS.CLAN.SU THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
Notes List
Document Number Rev
1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-9102P
A
5 4 3 2 1
UC1 i3R1@ UC1 i3R3@ UC1 i3VOSR1@ UC1 i3VOSR3@
SA00005L52L SA00005L53L SA00005UH1L SA00005UH2L
AV8063801058401-SR0N9-L1-1.8G_BGA1023~D AV8063801058401-SR0N9-L1-1.8G_BGA1023~D AV8062701313000-SR0U3-J1-1.4G_BGA1023~D AV8062701313000-SR0U3-J1-1.4G_BGA1023~D

UC1 i5R3@ UC1 i7R1@ UC1 i7R3@
SA00005K62L SA00005K53L SA00005K52L
(1)PEG_RCOMPO (G4) use 4mil connect to PEG_ICOMPI, then use 4mil connect to RC1. AV8063801058002-SR0N8-L1-1.7G_BGA1023~D AV8063801057605-SR0N6-L1-1.9G_BGA1023~D AV8063801057605-SR0N6-L1-1.9G_BGA1023~D
(2)PEG_ICOMPO use 12mil connect to RC1 UC1 CELR1@ UC1 CELR3@
D D
PEG_RCOMPO (G4) R_COMP place close to CPU SA00006021L SA00006022L

width 4 mils
PEG_ICOMPI (G3) VCC_IO AV8062701085401-SR0VA-Q0-1.5G_BGA1023~D AV8062701085401-SR0VA-Q0-1.5G_BGA1023~D
Trace length width 12 mils UC1 PENR1@ UC1 PENR3@
Max is 500 mils PEG_ICOMPO (G1) R_COMP
SA00005ZZ1L SA00005ZZ2L
+VCCP
AV8062701084801-SR0V5-Q0-1.6G_BGA1023~D AV8062701084801-SR0V5-Q0-1.6G_BGA1023~D
1
RC2
24.9_0402_1%
SA00005K63L UC1I i5R1@
2
UC1A i5R1@
G3 PEG_COMP PEG_ICOMPI and RCOMPO signals should be shorted and routed
PEG_ICOMPI G1
PEG_ICOMPO with - max length = 500 mils - typical impedance = 43 mohms
<15> DMI_CRX_PTX_N0
M2 G4 BG17 M4
P6 DMI_RX#[0] PEG_RCOMPO PEG_ICOMPO signals should be routed with - max length = 500 mils BG21 VSS[181] VSS[250] M58
<15> DMI_CRX_PTX_N1 DMI_RX#[1] - typical impedance = 14.5 mohms VSS[182] VSS[251]
<15> DMI_CRX_PTX_N2
P1 BG24 M6
P10 DMI_RX#[2] H22 BG28 VSS[183] VSS[252] N1
<15> DMI_CRX_PTX_N3 DMI_RX#[3] PEG_RX#[0] VSS[184] VSS[253]
J21 BG37 N17
N3 PEG_RX#[1] B22 BG41 VSS[185] VSS[254] N21
<15> DMI_CRX_PTX_P0 DMI_RX[0] PEG_RX#[2] VSS[186] VSS[255]
<15> DMI_CRX_PTX_P1 P7 D21 BG45 N25
DMI_RX[1] PEG_RX#[3] VSS[187] VSS[256]
DMI
<15> DMI_CRX_PTX_P2
P3 A19 BG49 N28
P11 DMI_RX[2] PEG_RX#[4] D17 BG53 VSS[188] VSS[257] N33
<15> DMI_CRX_PTX_P3 DMI_RX[3] PEG_RX#[5] VSS[189] VSS[258]
B14 BG9 N36
K1 PEG_RX#[6] D13 C29 VSS[190] VSS[259] N40
<15> DMI_CTX_PRX_N0 DMI_TX#[0] PEG_RX#[7] VSS[191] VSS[260]
M8 A11 PEG_GTX_C_HRX_N7 PEG_GTX_C_HRX_N7 <24> C35 N43
N4 B10 PEG_GTX_C_HRX_N6 PEG_GTX_C_HRX_N6 <24> C40 N47
C R2 G8 PEG_GTX_C_HRX_N5 PEG_GTX_C_HRX_N5 <24> D10 N48 C
A8 PEG_GTX_C_HRX_N4 PEG_GTX_C_HRX_N4 <24> D14 N51
K3 PEG_RX#[11] B6 PEG_GTX_C_HRX_N3 D18 VSS[195] VSS[264] N52
<15> DMI_CTX_PRX_P0 DMI_TX[0] PEG_RX#[12] PEG_GTX_C_HRX_N3 <24> VSS[196] VSS[265]
M7 H8 PEG_GTX_C_HRX_N2 PEG_GTX_C_HRX_N2 <24> D22 N56
<15> DMI_CTX_PRX_P1 DMI_TX[1] PEG_RX#[13] VSS[197] VSS[266]
P4 E5 PEG_GTX_C_HRX_N1 PEG_GTX_C_HRX_N1 <24> D26 N61
T3 K7 PEG_GTX_C_HRX_N0 PEG_GTX_C_HRX_N0 <24> D29 P14
D35 P16
K22 D4 VSS[200] VSS[269] P18
PEG_RX[0] K19 D40 VSS[201] VSS[270] P21
PEG_RX[1] C21 D43 VSS[202] VSS[271] P58
<15>
<15>
FDI_CTX_PRX_N0
FDI_CTX_PRX_N1
FDI_CTX_PRX_N0
FDI_CTX_PRX_N1
U7
W11 FDI0_TX#[0]
FDI0_TX#[1]
PEG_RX[2]
PEG_RX[3]
PEG_RX[4]
D19
C19
D46
D50
VSS[203]
VSS[204]
VSS[205]
VSS VSS[272]
VSS[273]
VSS[274]
P59
P9
FDI_CTX_PRX_N2 W1 D16 D54 R17
<15> FDI_CTX_PRX_N2 FDI0_TX#[2] PEG_RX[5] VSS[206] VSS[275]
FDI_CTX_PRX_N3 AA6 C13 D58 R20
FDI_CTX_PRX_N4 W6 D12 D6 R4
FDI_CTX_PRX_N5 V4 C11 PEG_GTX_C_HRX_P7 PEG_GTX_C_HRX_P7 <24> E25 R46
<15> FDI_CTX_PRX_N5
PCI EXPRESS -- GRAPHICS
FDI_CTX_PRX_N6 Y2 FDI1_TX#[1] PEG_RX[8] C9 PEG_GTX_C_HRX_P6 E29 VSS[209] VSS[278] T1

<15> FDI_CTX_PRX_N6 FDI1_TX#[2] PEG_RX[9] PEG_GTX_C_HRX_P6 <24> VSS[210] VSS[279]
FDI_CTX_PRX_N7 AC9 F8 PEG_GTX_C_HRX_P5 PEG_GTX_C_HRX_P5 <24> E3 T47
Intel(R) FDI
C8 PEG_GTX_C_HRX_P4 PEG_GTX_C_HRX_P4 <24> E35 T50

PEG_RX[11] C5 PEG_GTX_C_HRX_P3 E40 VSS[212] VSS[281] T51
PEG_RX[12] PEG_GTX_C_HRX_P3 <24> VSS[213] VSS[282]
FDI_CTX_PRX_P0 U6 H6 PEG_GTX_C_HRX_P2 PEG_GTX_C_HRX_P2 <24> F13 T52
<15> FDI_CTX_PRX_P0 FDI0_TX[0] PEG_RX[13] VSS[214] VSS[283]
FDI_CTX_PRX_P1 W10 F6 PEG_GTX_C_HRX_P1 PEG_GTX_C_HRX_P1 <24> F15 T53
FDI_CTX_PRX_P2 W3 K6 PEG_GTX_C_HRX_P0 PEG_GTX_C_HRX_P0 <24> F19 T55
FDI_CTX_PRX_P3 AA7 F29 T56
<15> FDI_CTX_PRX_P3 FDI0_TX[3] VSS[217] VSS[286]
FDI_CTX_PRX_P4 W7 G22 F35 U13
<15> FDI_CTX_PRX_P4 FDI1_TX[0] PEG_TX#[0] VSS[218] VSS[287]
FDI_CTX_PRX_P5 T4 C23 F40 U8
FDI_CTX_PRX_P6 AA3 D23 F55 V20
FDI_CTX_PRX_P7 AC8 F21 G51 V61
H19 G6 W13
FDI_FSYNC0 AA11 PEG_TX#[4] C17 G61 VSS[222] VSS[291] W15
<15> FDI_FSYNC0 FDI0_FSYNC PEG_TX#[5] VSS[223] VSS[292]
<15> FDI_FSYNC1 FDI_FSYNC1 AC12 K15 H10 W18
FDI1_FSYNC PEG_TX#[6] F17 H14 VSS[224] VSS[293] W21
FDI_INT U11 PEG_TX#[7] F14 PEG_HTX_GRX_N7 CC9 1 2 DIS@ 220nF_0402_16V7K H17 VSS[225] VSS[294] W46
<15> FDI_INT FDI_INT PEG_TX#[8] PEG_HTX_C_GRX_N7 <24> VSS[226] VSS[295]
A15 PEG_HTX_GRX_N6 CC10 1 2 DIS@ 220nF_0402_16V7K PEG_HTX_C_GRX_N6 <24> H21 W8
FDI_LSYNC0 AA10 PEG_TX#[9] J14 PEG_HTX_GRX_N5 CC11 1 2 DIS@ 220nF_0402_16V7K H4 VSS[227] VSS[296] Y4
<15> FDI_LSYNC0 FDI0_LSYNC PEG_TX#[10] PEG_HTX_C_GRX_N5 <24> VSS[228] VSS[297]
<15> FDI_LSYNC1 FDI_LSYNC1 AG8 H13 PEG_HTX_GRX_N4 CC12 1 2 DIS@ 220nF_0402_16V7K PEG_HTX_C_GRX_N4 <24> H53 Y47
FDI1_LSYNC PEG_TX#[11] M10 PEG_HTX_GRX_N3 CC13 1 2 DIS@ 220nF_0402_16V7K H58 VSS[229] VSS[298] Y58 @
PEG_TX#[12] PEG_HTX_C_GRX_N3 <24> VSS[230] VSS[299]
B F10 PEG_HTX_GRX_N2 CC14 1 2 DIS@ 220nF_0402_16V7K PEG_HTX_C_GRX_N2 <24> J1 Y59 RC20 B
+VCCP PEG_TX#[13] D9 PEG_HTX_GRX_N1 CC15 1 2 DIS@ 220nF_0402_16V7K J49 VSS[231] VSS[300] G48 1 2
PEG_TX#[14] PEG_HTX_C_GRX_N1 <24> VSS[232] VSS[301]
J4 PEG_HTX_GRX_N0 CC16 1 2 DIS@ 220nF_0402_16V7K PEG_HTX_C_GRX_N0 <24> J55
1 2 +EDP_COM AF3 PEG_TX#[15] K11 VSS[233] 1K_0402_5%
RC36 24.9_0402_1% AD2 eDP_COMPIO F22 K21 VSS[234]
2 1 AG11 eDP_ICOMPO PEG_TX[0] A23 K51 VSS[235]
RC158 10K_0402_5% eDP_HPD# PEG_TX[1] D24 K8 VSS[236] A5
PEG_TX[2] E21 L16 VSS[237] VSS_NCTF_1 A57
@ PEG_TX[3] VSS[238] VSS_NCTF_2
AG4 G19 L20 BC61
AF4 eDP_AUX# PEG_TX[4] B18 L22 VSS[239] VSS_NCTF_3 BD3
eDP_AUX PEG_TX[5] K17 L26 VSS[240] VSS_NCTF_4 BD59
PEG_TX[6] VSS[241] VSS_NCTF_5
eDP
G17 L30 BE4

PEG_TX[7] VSS[242] VSS_NCTF_6
NCTF
AC3 E14 PEG_HTX_GRX_P7 CC25 1 2 DIS@ 220nF_0402_16V7K PEG_HTX_C_GRX_P7 <24> L34 BE58
AC4 eDP_TX#[0] PEG_TX[8] C15 PEG_HTX_GRX_P6 CC26 1 2 DIS@ 220nF_0402_16V7K L38 VSS[243] VSS_NCTF_7 BG5
eDP_TX#[1] PEG_TX[9] PEG_HTX_C_GRX_P6 <24> VSS[244] VSS_NCTF_8
eDP_COMPIO and ICOMPO signals should be shorted near AE11 K13 PEG_HTX_GRX_P5 CC27 1 2 DIS@ 220nF_0402_16V7K PEG_HTX_C_GRX_P5 <24> L43 BG57
AE7 eDP_TX#[2] PEG_TX[10] G13 PEG_HTX_GRX_P4 CC28 1 2 DIS@ 220nF_0402_16V7K L48 VSS[245] VSS_NCTF_9 C3
balls and routed with typical impedance <25 mohms eDP_TX#[3] PEG_TX[11] PEG_HTX_C_GRX_P4 <24> VSS[246] VSS_NCTF_10
K10 PEG_HTX_GRX_P3 CC29 1 2 DIS@ 220nF_0402_16V7K PEG_HTX_C_GRX_P3 <24> L61 C58
AC1 PEG_TX[12] G10 PEG_HTX_GRX_P2 CC30 1 2 DIS@ 220nF_0402_16V7K M11 VSS[247] VSS_NCTF_11 D59
eDP_TX[0] PEG_TX[13] PEG_HTX_C_GRX_P2 <24> VSS[248] VSS_NCTF_12
AA4 D8 PEG_HTX_GRX_P1 CC31 1 2 DIS@ 220nF_0402_16V7K PEG_HTX_C_GRX_P1 <24> M15 E1
AE10 eDP_TX[1] PEG_TX[14] K4 PEG_HTX_GRX_P0 CC32 1 2 DIS@ 220nF_0402_16V7K VSS[249] VSS_NCTF_13 E61
eDP_TX[2] PEG_TX[15] PEG_HTX_C_GRX_P0 <24> VSS_NCTF_14
AE6
eDP_TX[3]
AV8063801058002-SR0N8-L1-1.7G_BGA1023~D
AV8063801058002-SR0N8-L1-1.7G_BGA1023~D
A A

Deciphered Date
PROCESSOR(1/6) DMI,FDI,PEG
1.0
LA-9102P
5 4 3 2 1
5 4 3 2 1
+VCCP +VCCP
+3VALW <15,40> PCH_PWROK +3V_PCH
+3VS
0.1U_0402_16V7K
JXDP RC129
<15> SYS_PWROK +1.5V_CPU_VDDQ
1 2
GND0 GND1
1
@ XDP_PREQ#_R 3 4 +VCCP @
D
OBSFN_A0 OBSFN_C0 1 D
CC33
RC49 XDP_PRDY#_R 5 6 RC132 @ RC6
0_0402_5%
OBSFN_A1 OBSFN_C1
1
1K_0402_5% 7 8 0_0402_1% 10K_0402_5%
GND2 GND3
0.1U_0402_16V7K
0.1U_0402_16V7K
XDP_BPM#0 9 10 @ RC8
XDP_BPM#1 11 OBSDATA_A0 OBSDATA_C0 12 2
1 1 200_0402_1%
2
OBSDATA_A1 OBSDATA_C1
1
13 14 UC2
GND4 GND5
CC35
CC36
SYS_PWROK_XDP XDP_BPM#2 15 16 1 5
2
XDP_BPM#3 17 OBSDATA_A2 OBSDATA_C2 18 1 @ 2D_PWG 2 B VCC
OBSDATA_A3 OBSDATA_C3 <15> PM_DRAM_PWRGD A
19 20 2 2 RC11 0_0402_1% 3 4 VDDPWRGOOD
0_0402_5% 2 @ 1 RC13 CFG10_R 21 GND6 GND7 22 GND Y
<8> CFG10 OBSFN_B0 OBSFN_D0
0_0402_5% 2 @ 1 RC15 CFG11_R 23 24 RC5 74AHC1G09GW TSSOP 5P RC8
<8> CFG11 OBSFN_B1 OBSFN_D1
25 26 +3V_PCH 1 2 CRB 1.1K
GND8 GND9
2
XDP_BPM#4 27 28 200_0402_1%
XDP_BPM#5 29 OBSDATA_B0 OBSDATA_D0 30 RC28
CHECK LIST 0.7 --> 4.75K
31 OBSDATA_B1 OBSDATA_D1 32
Place near JXDP1 @ INTEL recommand 1.1K
39_0402_1%
XDP_BPM#6 33 GND10 GND11 34 PDG 0.71 rev -->200
XDP_BPM#7 35 OBSDATA_B2 OBSDATA_D2 36
1
37 OBSDATA_B3 OBSDATA_D3 38
H_CPUPWRGD 1K_0402_5% 1 @ 2 RC22 H_CPUPWRGD_XDP 39 GND12 GND13 40 CLK_CPU_ITP CLK_CPU_ITP <14>
1
0_0402_5% 1 @ 2 RC31 CFD_PWRBTN#_XDP 41 PWRGOOD/HOOK0 ITPCLK/HOOK4 42 CLK_CPU_ITP#
<15,40> PBTN_OUT# HOOK1 ITPCLK#/HOOK5 CLK_CPU_ITP# <14>
43 44 D
1K_0402_5% 1 @ 2 RC38 XDP_HOOK2 45 VCC_OBS_AB VCC_OBS_CD 46 XDP_RST#_R 1 @ 2 PLT_RST# RUN_ON_CPU1.5VS3# 2 QC1 @
<8> CFG0 HOOK2 RESET#/HOOK6 <10,35> RUN_ON_CPU1.5VS3#
<15,52> VGATE
0_0402_5% 1 @ 2 RC34 SYS_PWROK_XDP 47 48 XDP_DBRESET# RC55 1K_0402_5% G 2N7002K_SOT23-3
49 HOOK3 DBR#/HOOK7 50 S
51 GND14 GND15 52 XDP_TDO RC33 1 @ 2 0_0402_5%
<11,12,14,38> PCH_SMBDATA PCH_JTAG_TDO <13>
3
53 SDA TD0 54 XDP_TRST#_R
<11,12,14,38> PCH_SMBCLK SCL TRST#
<13> PCH_JTAG_TCK
1 2 RC30 XDP_TCK1 55 56 XDP_TDI RC37 1 @ 2 0_0402_5% PCH_JTAG_TDI <13>
0_0402_5% @ XDP_TCK_R 57 TCK1 TDI 58 XDP_TMS_R RC39 1 @ 2 0_0402_5%
TCK0 TMS PCH_JTAG_TMS <13>
59 60
GND16 GND17 +3VALW
The resistor SAMTE_BSH-030-01-L-D-A
+VCCP
0.1U_0402_16V7K
for HOOK2 should be CONN@
placed such that the 1
SP02000L900
1
stub is very small
CC34
on CFG0 net RC59
2 75_0402_5%
C C
2
UC3
1 5
2 NC VCC RC58
<16,32,38,40> PLT_RST# A
3 4 BUFO_CPU_RST# 1 2 BUF_CPU_RST#
GND Y 43_0402_1%
SN74LVC1G07DCKR_SC70-5~D
0.1U_0402_16V7K
1
1 @
@ RC62
CC63
0_0402_5%
+VCCP
2
2
@
1 2 H_THERMTRIP#
RC127 @ 56_0402_1% UC1B i5R1@
1 2 H_CATERR#
RC128 49.9_0402_1%~D J3 CLK_CPU_DMI <14>
1 2 H_PROCHOT#
BCLK H2
BCLK# CLK_CPU_DMI# <14>
MISC
RC44 62_0402_5%~D
CLOCKS
F49
<17> H_SNB_IVB# PROC_SELECT# AG3 CLK_CPU_DPLL_R RC65 1 2 1K_0402_1%
DPLL_REF_CLK AG1 RC77 1 2 1K_0402_1%
DPLL_REF_CLK#
CLK_CPU_DPLL#_R +VCCP PU/PD for JTAG signals
RC124 2 @ 110K_0402_5% C57
PROC_DETECT# Remove DPLL Ref clock (for eDP only) +VCCP
N59
PROC_DETECT (Processor Detect): pulled to BCLK_ITP N58
ground on the processor package. There is no BCLK_ITP#
connection to the processor silicon for this H_CATERR# C49 XDP_TMS_R 51_0402_5% 1 2 RC47
signal. System board designers may use this
CATERR#
THERMAL
signal to determine if the processor is present XDP_TDI_R 51_0402_5% 1 2 RC46
A48 AT30 H_DRAMRST# H_DRAMRST# XDP_PREQ# 51_0402_5% 1 @ 2 RC48

<17,40> H_PECI PECI SM_DRAMRST# H_DRAMRST# <7>
1
H_PECI @ XDP_TDO 51_0402_5% 1 2 RC106
1
VR1 TOPOLOGY BF44 SM_RCOMP0 140_0402_1% 1 2 RC86 CC143
SM_RCOMP[0]
DDR3
MISC
B 1 2 H_PROCHOT#_R C45 BE43 SM_RCOMP1 25.5_0402_1%1 2 RC83 0.1U_0402_25V6K B

<40,46> H_PROCHOT# PROCHOT# SM_RCOMP[1] 2
@ CC151 RC57 56_0402_1% BG43 SM_RCOMP2 200_0402_1% 1 2 RC85
0.1U_0402_10V7K~D SM_RCOMP[2] XDP_TCK_R 51_0402_5% 1 2 RC105
place RC57 near CPU 300mils ~1530mils
2
DDR3 Compensation Signals
1 @ 2 H_THERMTRIP#_R D45 Place close to CPU XDP_TRST#_R 51_0402_5% 1 2 RC104
<17> H_THERMTRIP# THERMTRIP#
RC130 0_0402_1%
Place on BOTTOM(-4059,5169) area.
place RC129 near CPU 250mils~2530 mils N53 XDP_PRDY# RC125 1 @ 2 0_0402_5% XDP_PRDY#_R
PRDY# N55 XDP_PREQ# RC135 1 @ 2 0_0402_5% XDP_PREQ#_R
PREQ#
L56 XDP_TCK RC136 1 @ 2 0_0402_5% XDP_TCK_R
TCK L55 XDP_TMS RC137 1 @ 2 0_0402_5% XDP_TMS_R
TMS
PWR MANAGEMENT
J58 XDP_TRST# RC126 1 @ 2 0_0402_5% XDP_TRST#_R

TRST#
JTAG & BPM
<15> H_PM_SYNC H_PM_SYNC C48 M60 XDP_TDI_R RC50 1 @ 2 0_0402_5% XDP_TDI

PM_SYNC TDI L59 XDP_TDO_R RC92 1 @ 2 0_0402_5% XDP_TDO +3VS
TDO RC42
XDP_DBRESET#_R 1 2
<17> H_CPUPWRGD 1 2 VCCPWRGOOD_0_R B46
RC25 1K_0402_5% UNCOREPWRGOOD K58 XDP_DBRESET#_R RC89 1 2 0_0402_5% XDP_DBRESET# XDP_DBRESET#_R 1K_0402_5%
DBR# XDP_DBRESET# <15>
1
RC64 VCCPWRGOOD_0_R 1 2
VDDPWRGOOD 1 2 VDDPWRGOOD_R BE45 G58 XDP_BPM#0_R RC95 1 @ 2 0_0402_5% XDP_BPM#0 CC144 10K_0402_5% RC45
SM_DRAMPWROK BPM#[0] E55 XDP_BPM#1_R RC91 1 @ 2 0_0402_5% XDP_BPM#1 0.1U_0402_25V6K
1 BPM#[1]
VDDPWRGOOD_R CC141 130_0402_1% E59 XDP_BPM#2_R RC101 1 @ 2 0_0402_5% XDP_BPM#2 2
@ BPM#[2] G55 XDP_BPM#3_R RC102 1 @ 2 0_0402_5% XDP_BPM#3
1 BPM#[3]
@ 0.1U_0402_25V6K G59 XDP_BPM#4_R RC103 1 @ 2 0_0402_5% XDP_BPM#4
CC142 2 BUF_CPU_RST# D44 BPM#[4] H60 XDP_BPM#5_R RC97 1 @ 2 0_0402_5% XDP_BPM#5 Place close to CPU
0.1U_0402_25V6K RESET# BPM#[5] J59 XDP_BPM#6_R RC88 1 @ 2 0_0402_5% XDP_BPM#6 Avoid stub in the PWRGD path
2 BPM#[6] J61 XDP_BPM#7_R RC87 1 @ 2 0_0402_5% XDP_BPM#7
BPM#[7] while placing resistors RC25 & RC130
XDP_BPM#4 RC90 1 @ 2 0_0402_5%
CFG12 <8>
Place close to CPU ESD request to reserve CC141 XDP_BPM#5 RC96 1 @ 2 0_0402_5%
CFG13 <8>
XDP_BPM#6 RC93 1 @ 2 0_0402_5%
CFG14 <8>
XDP_BPM#7 RC94 1 @ 2 0_0402_5%
CFG15 <8>
AV8063801058002-SR0N8-L1-1.7G_BGA1023~D
A A

Deciphered Date
PROCESSOR(2/6) PM,XDP,CLK
1.0
LA-9102P
5 4 3 2 1
5 4 3 2 1
UC1C i5R1@ UC1D i5R1@

<11> DDR_A_D[0..63] <12> DDR_B_D[0..63]
DDR_A_D0 AG6 DDR_B_D0 AL4
DDR_A_D1 AJ6 SA_DQ[0] AU36 M_CLK_DDR0 DDR_B_D1 AL1 SB_DQ[0] BA34 M_CLK_DDR2
D M_CLK_DDR0 <11> M_CLK_DDR2 <12> D
DDR_A_D2 AP11 SA_DQ[1] SA_CK[0] AV36 M_CLK_DDR#0 DDR_B_D2 AN3 SB_DQ[1] SB_CK[0] AY34 M_CLK_DDR#2
SA_DQ[2] SA_CK#[0] M_CLK_DDR#0 <11> SB_DQ[2] SB_CK#[0] M_CLK_DDR#2 <12>
DDR_A_D3 AL6 AY26 DDR_CKE0_DIMMA DDR_B_D3 AR4 AR22 DDR_CKE2_DIMMB
SA_DQ[3] SA_CKE[0] DDR_CKE0_DIMMA <11> SB_DQ[3] SB_CKE[0] DDR_CKE2_DIMMB <12>
DDR_A_D4 AJ10 DDR_B_D4 AK4
DDR_A_D5 AJ8 SA_DQ[4] DDR_B_D5 AK3 SB_DQ[4]
DDR_A_D6 AL8 SA_DQ[5] DDR_B_D6 AN4 SB_DQ[5]
DDR_A_D7 AL7 SA_DQ[6] DDR_B_D7 AR1 SB_DQ[6]
DDR_A_D8 AR11 SA_DQ[7] DDR_B_D8 AU4 SB_DQ[7]
DDR_A_D9 AP6 SA_DQ[8] AT40 M_CLK_DDR1 DDR_B_D9 AT2 SB_DQ[8] BA36 M_CLK_DDR3
SA_DQ[9] SA_CK[1] M_CLK_DDR1 <11> SB_DQ[9] SB_CK[1] M_CLK_DDR3 <12>
DDR_A_D10 AU6 AU40 M_CLK_DDR#1 DDR_B_D10 AV4 BB36 M_CLK_DDR#3
SA_DQ[10] SA_CK#[1] M_CLK_DDR#1 <11> SB_DQ[10] SB_CK#[1] M_CLK_DDR#3 <12>
DDR_A_D11 AV9 BB26 DDR_CKE1_DIMMA DDR_B_D11 BA4 BF27 DDR_CKE3_DIMMB
SA_DQ[11] SA_CKE[1] DDR_CKE1_DIMMA <11> SB_DQ[11] SB_CKE[1] DDR_CKE3_DIMMB <12>
DDR_A_D12 AR6 DDR_B_D12 AU3
DDR_A_D13 AP8 SA_DQ[12] DDR_B_D13 AR3 SB_DQ[12]
DDR_A_D14 AT13 SA_DQ[13] DDR_B_D14 AY2 SB_DQ[13]
DDR_A_D15 AU13 SA_DQ[14] DDR_B_D15 BA3 SB_DQ[14]
DDR_A_D16 BC7 SA_DQ[15] DDR_B_D16 BE9 SB_DQ[15]
DDR_A_D17 BB7 SA_DQ[16] BB40 DDR_CS0_DIMMA# DDR_B_D17 BD9 SB_DQ[16] BE41 DDR_CS2_DIMMB#
SA_DQ[17] SA_CS#[0] DDR_CS0_DIMMA# <11> SB_DQ[17] SB_CS#[0] DDR_CS2_DIMMB# <12>
DDR_A_D18 BA13 BC41 DDR_CS1_DIMMA# DDR_B_D18 BD13 BE47 DDR_CS3_DIMMB#
SA_DQ[18] SA_CS#[1] DDR_CS1_DIMMA# <11> SB_DQ[18] SB_CS#[1] DDR_CS3_DIMMB# <12>
DDR_A_D19 BB11 DDR_B_D19 BF12
DDR_A_D20 BA7 SA_DQ[19] DDR_B_D20 BF8 SB_DQ[19]
DDR_A_D21 BA9 SA_DQ[20] DDR_B_D21 BD10 SB_DQ[20]
DDR_A_D22 BB9 SA_DQ[21] DDR_B_D22 BD14 SB_DQ[21]
DDR_A_D23 AY13 SA_DQ[22] DDR_B_D23 BE13 SB_DQ[22]
DDR_A_D24 AV14 SA_DQ[23] AY40 M_ODT0 DDR_B_D24 BF16 SB_DQ[23] AT43 M_ODT2
SA_DQ[24] SA_ODT[0] M_ODT0 <11> SB_DQ[24] SB_ODT[0] M_ODT2 <12>
DDR_A_D25 AR14 BA41 M_ODT1 DDR_B_D25 BE17 BG47 M_ODT3
SA_DQ[25] SA_ODT[1] M_ODT1 <11> SB_DQ[25] SB_ODT[1] M_ODT3 <12>
DDR_A_D26 AY17 DDR_B_D26 BE18
DDR_A_D27 AR19 SA_DQ[26] DDR_B_D27 BE21 SB_DQ[26]
DDR_A_D28 BA14 SA_DQ[27] DDR_B_D28 BE14 SB_DQ[27]
DDR_A_D29 AU14 SA_DQ[28] DDR_B_D29 BG14 SB_DQ[28]
DDR_A_D30 BB14 SA_DQ[29] DDR_B_D30 BG18 SB_DQ[29]
SA_DQ[30] DDR_A_DQS#[0..7] <11> SB_DQ[30] DDR_B_DQS#[0..7] <12>
DDR_A_D31 BB17 AL11 DDR_A_DQS#0 DDR_B_D31 BF19 AL3 DDR_B_DQS#0
DDR_A_D32 BA45 SA_DQ[31] SA_DQS#[0] AR8 DDR_A_DQS#1 DDR_B_D32 BD50 SB_DQ[31] SB_DQS#[0] AV3 DDR_B_DQS#1
DDR_A_D33 AR43 SA_DQ[32] SA_DQS#[1] AV11 DDR_A_DQS#2 DDR_B_D33 BF48 SB_DQ[32] SB_DQS#[1] BG11 DDR_B_DQS#2
DDR_A_D34 AW48 SA_DQ[33] SA_DQS#[2] AT17 DDR_A_DQS#3 DDR_B_D34 BD53 SB_DQ[33] SB_DQS#[2] BD17 DDR_B_DQS#3
DDR_A_D35 BC48 SA_DQ[34] SA_DQS#[3] AV45 DDR_A_DQS#4 DDR_B_D35 BF52 SB_DQ[34] SB_DQS#[3] BG51 DDR_B_DQS#4
DDR_A_D36 BC45 SA_DQ[35] SA_DQS#[4] AY51 DDR_A_DQS#5 DDR_B_D36 BD49 SB_DQ[35] SB_DQS#[4] BA59 DDR_B_DQS#5
DDR_A_D37 AR45 SA_DQ[36] DDR SYSTEM MEMORY A SA_DQS#[5] AT55 DDR_A_DQS#6 DDR_B_D37 BE49 SB_DQ[36] SB_DQS#[5] AT60 DDR_B_DQS#6
SA_DQ[37] SA_DQS#[6] SB_DQ[37] SB_DQS#[6]
DDR SYSTEM MEMORY B

C DDR_A_D38 AT48 AK55 DDR_A_DQS#7 DDR_B_D38 BD54 AK59 DDR_B_DQS#7 C
DDR_A_D39 AY48 SA_DQ[38] SA_DQS#[7] DDR_B_D39 BE53 SB_DQ[38] SB_DQS#[7]
DDR_A_D40 BA49 SA_DQ[39] DDR_B_D40 BF56 SB_DQ[39]
DDR_A_D41 AV49 SA_DQ[40] DDR_B_D41 BE57 SB_DQ[40]
DDR_A_D42 BB51 SA_DQ[41] DDR_B_D42 BC59 SB_DQ[41]
DDR_A_D43 AY53 SA_DQ[42] DDR_B_D43 AY60 SB_DQ[42]
DDR_A_D44 BB49 SA_DQ[43] DDR_B_D44 BE54 SB_DQ[43]
SA_DQ[44] DDR_A_DQS[0..7] <11> SB_DQ[44]
DDR_A_D45 AU49 AJ11 DDR_A_DQS0 DDR_B_D45 BG54
SA_DQ[45] SA_DQS[0] SB_DQ[45] DDR_B_DQS[0..7] <12>
DDR_A_D46 BA53 AR10 DDR_A_DQS1 DDR_B_D46 BA58 AM2 DDR_B_DQS0
DDR_A_D47 BB55 SA_DQ[46] SA_DQS[1] AY11 DDR_A_DQS2 DDR_B_D47 AW59 SB_DQ[46] SB_DQS[0] AV1 DDR_B_DQS1
DDR_A_D48 BA55 SA_DQ[47] SA_DQS[2] AU17 DDR_A_DQS3 DDR_B_D48 AW58 SB_DQ[47] SB_DQS[1] BE11 DDR_B_DQS2
DDR_A_D49 AV56 SA_DQ[48] SA_DQS[3] AW45 DDR_A_DQS4 DDR_B_D49 AU58 SB_DQ[48] SB_DQS[2] BD18 DDR_B_DQS3
DDR_A_D50 AP50 SA_DQ[49] SA_DQS[4] AV51 DDR_A_DQS5 DDR_B_D50 AN61 SB_DQ[49] SB_DQS[3] BE51 DDR_B_DQS4
DDR_A_D51 AP53 SA_DQ[50] SA_DQS[5] AT56 DDR_A_DQS6 DDR_B_D51 AN59 SB_DQ[50] SB_DQS[4] BA61 DDR_B_DQS5
DDR_A_D52 AV54 SA_DQ[51] SA_DQS[6] AK54 DDR_A_DQS7 DDR_B_D52 AU59 SB_DQ[51] SB_DQS[5] AR59 DDR_B_DQS6
DDR_A_D53 AT54 SA_DQ[52] SA_DQS[7] DDR_B_D53 AU61 SB_DQ[52] SB_DQS[6] AK61 DDR_B_DQS7
DDR_A_D54 AP56 SA_DQ[53] DDR_B_D54 AN58 SB_DQ[53] SB_DQS[7]
DDR_A_D55 AP52 SA_DQ[54] DDR_B_D55 AR58 SB_DQ[54]
DDR_A_D56 AN57 SA_DQ[55] DDR_B_D56 AK58 SB_DQ[55]
DDR_A_D57 AN53 SA_DQ[56] DDR_B_D57 AL58 SB_DQ[56]
DDR_A_D58 AG56 SA_DQ[57] DDR_B_D58 AG58 SB_DQ[57]
DDR_A_D59 AG53 SA_DQ[58] DDR_B_D59 AG59 SB_DQ[58]
DDR_A_D60 AN55 SA_DQ[59] DDR_B_D60 AM60 SB_DQ[59]
SA_DQ[60] DDR_A_MA[0..15] <11> SB_DQ[60] DDR_B_MA[0..15] <12>
DDR_A_D61 AN52 BG35 DDR_A_MA0 DDR_B_D61 AL59 BF32 DDR_B_MA0
DDR_A_D62 AG55 SA_DQ[61] SA_MA[0] BB34 DDR_A_MA1 DDR_B_D62 AF61 SB_DQ[61] SB_MA[0] BE33 DDR_B_MA1
DDR_A_D63 AK56 SA_DQ[62] SA_MA[1] BE35 DDR_A_MA2 DDR_B_D63 AH60 SB_DQ[62] SB_MA[1] BD33 DDR_B_MA2
SA_DQ[63] SA_MA[2] BD35 DDR_A_MA3 SB_DQ[63] SB_MA[2] AU30 DDR_B_MA3
SA_MA[3] AT34 DDR_A_MA4 SB_MA[3] BD30 DDR_B_MA4
SA_MA[4] AU34 DDR_A_MA5 SB_MA[4] AV30 DDR_B_MA5
SA_MA[5] BB32 DDR_A_MA6
SB_MA[5] BG30 DDR_B_MA6
BD37 SA_MA[6] AT32 DDR_A_MA7 BG39 SB_MA[6] BD29 DDR_B_MA7
<11> DDR_A_BS0 SA_BS[0] SA_MA[7] <12> DDR_B_BS0 SB_BS[0] SB_MA[7]
BF36 AY32 DDR_A_MA8 BD42 BE30 DDR_B_MA8
BA28 AV32 DDR_A_MA9 AT22 BE28 DDR_B_MA9
BE37 DDR_A_MA10 BD43 DDR_B_MA10
SA_MA[10] BA30 DDR_A_MA11 SB_MA[10] AT28 DDR_B_MA11
SA_MA[11] BC30 DDR_A_MA12 SB_MA[11] AV28 DDR_B_MA12
BE39 SA_MA[12] AW41 DDR_A_MA13 AV43 SB_MA[12] BD46 DDR_B_MA13
<11> DDR_A_CAS# SA_CAS# SA_MA[13] <12> DDR_B_CAS# SB_CAS# SB_MA[13]
B BD39 AY28 DDR_A_MA14 BF40 AT26 DDR_B_MA14 B
<11> DDR_A_RAS# SA_RAS# SA_MA[14] <12> DDR_B_RAS# SB_RAS# SB_MA[14]
AT41 AU26 DDR_A_MA15 BD45 AU22 DDR_B_MA15
<11> DDR_A_WE# SA_WE# SA_MA[15] <12> DDR_B_WE# SB_WE# SB_MA[15]
AV8063801058002-SR0N8-L1-1.7G_BGA1023~D AV8063801058002-SR0N8-L1-1.7G_BGA1023~D
+1.5V
1
1 @ 2 RC108
RC107 0_0402_5% 1K_0402_5%
QC2
BSS138_SOT23
2
DDR3_DRAMRST#
S
<6> H_DRAMRST# H_DRAMRST# 3 1 DDR3_DRAMRST#_R 1 2 1

DDR3_DRAMRST# <11,12>
RC110 1K_0402_5% @
CC145
0.1U_0402_25V6K
G
1
2
RC109 1 @ 2
DRAMRST_CNTRL_PCH <14>
4.99K_0402_1% RC111 0_0402_1%
Place close to RC110
DRAMRST_CNTRL
DRAMRST_CNTRL <11>
2
A A
1
CC37
.047U_0402_16V7K
2

Deciphered Date
PROCESSOR(3/6) DDRIII
1.0
LA-9102P
5 4 3 2 1
5 4 3 2 1
CFG Straps for Processor

D D
CFG2
1
RC116
1K_0402_1%
2
UC1E i5R1@
+SA_DIMM_VREFDQ +SA_DIMM_VREFDQ
PEG Static Lane Reversal - CFG2 is for the 16x

<6> CFG0 CFG0 B50 BE7 +SA_DIMM_VREFDQ
PAD~D T91 @ C51 CFG[0] RSVD28 BG7 +SB_DIMM_VREFDQ
CFG2 B54 CFG[1] RSVD29
CFG[2] 1:(Default) Normal Operation; Lane #
PAD~D T92 @ D53 CFG2
CFG[3] definition matches socket pin map definition
1
CFG4 A51 N42 @ T14 PAD~D
CFG5 C53 CFG[4] RSVD30 L42 @ T15 PAD~D @ @
CFG6 C55 CFG[5] RSVD31 L45 @ T16 PAD~D RC117 RC115
CFG7 H49 CFG[6] RSVD32 L47 @ T17 PAD~D 1K_0402_1% 1K_0402_1%
*0:Lane Reversed
+VCC_CORE PAD~D T66 @ A55 CFG[7] RSVD33
2
PAD~D T41 @ H51 CFG[8] CFG4
CFG10 K49 CFG[9] M13 @ T22 PAD~D
<6> CFG10
1
CFG11 K53 CFG[10] RSVD34 M14 @ T21 PAD~D
<6> CFG11 CFG[11] RSVD35
<6> CFG12 CFG12 F53 U14 @ T19 PAD~D RC112
2
+VCC_GFXCORE_AXG @ CFG13 G53 CFG[12] RSVD36 W14 @ T20 PAD~D @ 1K_0402_1%

<6> CFG13 CFG[13] RSVD37
RC121
<6> CFG14 CFG14 L51 P13 @ T18 PAD~D
CFG15 F51 CFG[14] RSVD38
50_0402_1% <6> CFG15 CFG[15]
2
PAD~D T69 @ D52
2
@ PAD~D T89 @ L53 CFG[16] AT49

CFG[17] RSVD39
1
RC119 K24 @ T23 PAD~D

RSVD40
C 50_0402_1% C
RESERVED
VCC_VAL_SENSE H43
1 2 VSS_VAL_SENSE K43 VCC_VAL_SENSE AH2 @ T28 PAD~D
VSS_VAL_SENSE RSVD41
1
@ AG13 @ T27 PAD~D Display Port Presence Strap

RC123 RSVD42 AM14 @ T25 PAD~D
VCC_AXG_VAL_SENSE 50_0402_1% H45 RSVD43 AM15 @ T26 PAD~D
VSS_AXG_VAL_SENSE K45 VAXG_VAL_SENSE RSVD44
VSSAXG_VAL_SENSE
CFG4
* 1 : Disabled; No Physical Display Port
@ N50 @ T29 PAD~D attached to Embedded Display Port
1 2 TP_VCC_DIESENSE F48 RSVD45
RC21 1K_0402_5% VCC_DIE_SENSE
0 : Enabled; An external Display Port device is
connected to the Embedded Display Port
2
@ PAD~D T46 @ H48

RC120 PAD~D T36 @ K48 RSVD6
50_0402_1% RSVD7 A4 TP_DC_TEST_A4 @ T121 PAD~D
DC_TEST_A4 C4
BA19 DC_TEST_C4 D3 DC_TEST_C4_D3 CFG6
RSVD8 DC_TEST_D3
1
PAD~D T32 @ AV19 D1 TP_DC_TEST_D1 @ T118 PAD~D

AT21 RSVD9 DC_TEST_D1 A58 TP_DC_TEST_A58 @ T119 PAD~D CFG5
PAD~D T34 @ BB21 RSVD10 DC_TEST_A58 A59
1
PAD~D T35 @ BB19 RSVD11 DC_TEST_A59 C59 DC_TEST_A59_C59
AY21 RSVD12 DC_TEST_C59 A61 RC114 RC113
BA22 RSVD13 DC_TEST_A61 C61 DC_TEST_A61_C61 1K_0402_1% 1K_0402_1%
AY22 RSVD14 DC_TEST_C61 D61 TP_DC_TEST_D61 @ T120 PAD~D @
PAD~D T40 @ AU19 RSVD15 DC_TEST_D61 BD61 TP_DC_TEST_BD61 @ T122 PAD~D
RSVD16 DC_TEST_BD61
2
AU21 BE61
PAD~D T42 @ BD21 RSVD17 DC_TEST_BE61 BE59 DC_TEST_BE59_BE61
BD22 RSVD18 DC_TEST_BE59 BG61
BD25 RSVD19 DC_TEST_BG61 BG59 DC_TEST_BG59_BG61
PAD~D T47 @ BD26 RSVD20 DC_TEST_BG59 BG58 TP_DC_TEST_BG58 @ T132 PAD~D
PAD~D T71 @ BG22 RSVD21 DC_TEST_BG58 BG4 TP_DC_TEST_BG4 @ T123 PAD~D
BE22 RSVD22 DC_TEST_BG4 BG3
PAD~D T72 @ BG26 RSVD23 DC_TEST_BG3 BE3 DC_TEST_BE3_BG3
PAD~D T51 @ BE26 RSVD24 DC_TEST_BE3 BG1
RSVD25 DC_TEST_BG1
PCIE Port Bifurcation Straps
PAD~D T68 @ BF23 BE1 DC_TEST_BE1_BG1
PAD~D T49 @ BE24 RSVD26 DC_TEST_BE1 BD1 TP_DC_TEST_BD1 @ T124 PAD~D
RSVD27 DC_TEST_BD1
11: (Default) x16 - Device 1 functions 1 and 2 disabled
B B
CFG[6:5] *10: x8, x8 - Device 1 function 1 enabled ; function 2
AV8063801058002-SR0N8-L1-1.7G_BGA1023~D disabled
01: Reserved - (Device 1 function 1 disabled ; function
2 enabled)
00: x8,x4,x4 - Device 1 functions 1 and 2 enabled
CFG7
1
@
RC118
1K_0402_1%
2
PEG DEFER TRAINING
CFG7
*1: (Default) PEG Train immediately
following xxRESETB de assertion
0: PEG Wait for BIOS for training
A A

Deciphered Date
PROCESSOR(4/6) RSVD,CFG
1.0
LA-9102P
5 4 3 2 1
5 4 3 2 1
UC1F i5R1@ POWER +VCCP
+VCC_CORE
D 8.5A D
AF46
VCCIO[1] AG48
33A VCCIO[3] AG50 Iccmax current changed for PDDG Rev0.7
A26 VCCIO[4] AG51
A29 VCC[1] VCCIO[5] AJ17
A31 VCC[2] VCCIO[6] AJ21
CPU Power Rail Table
ULV 17W , Max Current VCC[3] VCCIO[7]
A34 AJ25 S0 Iccmax
in Turbo Mode or HFM A35 VCC[4] VCCIO[8] AJ43
VCC[5] VCCIO[9] Voltage Rail Voltage Current (A)
A38 AJ47
A39 VCC[6] VCCIO[10] AK50
A42 VCC[7] VCCIO[11] AK51
VCC[8] VCCIO[12]
VCC 0.65-1.3 53
C26 AL14
C27 VCC[9] VCCIO[13] AL15
VCC[11] VCCIO[15] VCCIO 1.05/1 8.5
C34 AL20
VCC[14] VCCIO[18]
VAXG 0.0-1.1 33
C42 AL45
D27 VCC[15] VCCIO[19] AL48
D32 VCC[16] VCCIO[20] AM16
VCC[17] VCCIO[21] VCCPLL 1.8 1.2
D34 AM17
VCC[20]
VDDQ 1.5 5
PEG IO AND DDR IO

D42 VCCIO[24] AM47
E26 VCC[21] VCCIO[25] AN20
VCC[23] VCCIO[27] VCCSA 0.65-0.9 6
E32 AN45
E37 VCC[25] VCCIO[29]
VCC[26]
+1.5V_MEM 1.5 12-16 *
E38
VCC[27]
CORE SUPPLY
F25
F26 VCC[28]
F28 VCC[29]
F32 VCC[30] +VCCP
VCC[31] * Description
F34
F37 VCC[32] AA14
C
VCC[33] VCCIO[30] 5A to Mem controller(+1.5V_CPU_VDDQ) C
F38 AA15
F42 VCC[34] VCCIO[31] AB17
5-6A to 2 DIMMs/channel
G42 VCC[35] VCCIO[32] AB20 2-5A to +1.5V_RUN & +0.75V_DDR_VTT
H25 VCC[36] VCCIO[33] AC13
H26 VCC[37] VCCIO[34] AD16
H32 VCC[40] VCCIO[37] AE14
H34 VCC[41] VCCIO[38] AE15
H35 VCC[42] VCCIO[39] AF16
H40 VCC[45] VCCIO[42] AG15
J25 VCC[46] VCCIO[43] AG16
J32 VCC[50] VCCIO[47] AJ14
J34 VCC[51] VCCIO[48] AJ15
J35 VCC[52] VCCIO[49]
J37 VCC[53]
J38 VCC[54] +3VS
J40 VCC[55]
J42 VCC[56]
VCC[57] VCCP_PWRCTRL Pull high on power side
K26 W16
2
K27 VCC[58] VCCIO50 W17
K29 VCC[59] VCCIO51 RC141
K32 VCC[60] @ 10K_0402_5%
K34 VCC[61]
K35 VCC[62]
VCC[63]
1
K37
K39 VCC[64]
K42 VCC[66] BC22 1 2 VCCP_PWRCTRL
L25 VCC[67] VCCIO_SEL @ RC140 0_0402_5%
L28 VCC[68]
L33 VCC[69]
L36 VCC[70] +VCCP
B B
L40 VCC[71] +VCCP
N26 VCC[72]
VCC[73]
Note: Place the PU resistors close to CPU
1U_0402_6.3V6K
N30 AM25
QUIET
RAILS
VCC[74] VCCPQE[1] RC145 close to CPU 300~1500mils

N34 AN22 1
VCC[75] VCCPQE[2]
CC573
N38 RC147 close to CPU

VCC[76]
1
1
RC147 RC145
2 130_0402_1% 75_0402_5%
2
2
A44 H_CPU_SVIDALRT# RC142 1 2 43_0402_1%
<BOM Structure>
VIDALERT# VR_SVID_ALRT# <52>
B43 H_CPU_SVIDCLK RC146 1 @ 2 0_0402_1%
VIDSCLK VR_SVID_CLK <52>
SVID
C44 H_CPU_SVIDDAT RC144 1 @ 2 0_0402_1%

VIDSOUT VR_SVID_DAT <52>
CAD Note: Place the PU +VCC_CORE
resistors close to CPU
RC147 close to CPU 300~1500mils
1
RC138
100_0402_1%
2
F43 VCCSENSE_R RC139 1 @ 2 0_0402_1%
VCC_SENSE VCCSENSE <52>
SENSE LINES
G43 VSSSENSE_R RC122 1 @ 2 0_0402_1%

VSS_SENSE VSSSENSE <52>
1
2 1 +VCCP
RC98 10_0402_1% RC131
AN16 100_0402_1%
VCCIO_SENSE VCCIO_SENSE <49>
AN17
VSS_SENSE_VCCIO VSSIO_SENSE_R <49>
2
1 2
RC133 10_0402_1%
A AV8063801058002-SR0N8-L1-1.7G_BGA1023~D Place RC98 close to CPU A

Deciphered Date
PROCESSOR(5/6) PWR,BYPASS
1.0
LA-9102P
5 4 3 2 1
5 4 3 2 1
+1.5V_CPU_VDDQ Source
+1.5V QC3 +1.5V_CPU_VDDQ
+3VALW B+_BIAS AO4304L_SO8 +1.5V +V_DDR_SMREF +1.5V_CPU_VDDQ
8 1
7 2 1 2
1
6 3 @ RC134 0_0402_5%
20K_0402_5%
1
5 RC80 RC84
10U_0805_10V6K
1
RC151 @ 1K_0402_1% @ QC5 1K_0402_1%
CC38
RC152
RC143 470K_0402_5% NTR4503NT1G_SOT23-3~D
4
100K_0402_5% 2
2
1 3 +V_SM_VREF_CNT
RUN_ON_CPU1.5VS3
3
QC7B
1
0.1U_0603_50V_X7R
2N7002DW-7-F_SOT363-6
1
D 1 RC81 RC78 D
RUN_ON_CPU1.5VS3# 5 RC150 @ 1K_0402_1% 2 1K_0402_1%
CC39
2M_0402_5%~D
2
2
2
RC149 QC7A
0_0402_5% 2N7002DW-7-F_SOT363-6 RUN_ON_CPU1.5VS3
<35,40,48,49,50> SUSP#
1 2 2
@
1
<40> CPU1.5V_S3_GATE 1 @ 2
RUN_ON_CPU1.5VS3# <35,6>
UC1H i5R1@
RC148
0_0402_1%
1
@
CC40
UC1G i5R1@ POWER +V_SM_VREF_CNT
0.1U_0402_10V7K~D 33A
2 +VCC_GFXCORE_AXG A13 AM38
AY43 A17 VSS[1] VSS[91] AM4
AA46 SM_VREF A21 VSS[2] VSS[92] AM42
VREF
AB47 VAXG[1] A25 VSS[3] VSS[93] AM45
AB50 VAXG[2] A28 VSS[4] VSS[94] AM48
VAXG[3]
+V_SM_VREF should VSS[5] VSS[95]
AB51 have 10 mil trace width A33 AM58
AB52 VAXG[4] A37 VSS[6] VSS[96] AN1
AB58 VAXG[8] 5A CC178 2 1 0.1U_0402_10V7K~D A53 VSS[10] VSS[100] AN33
AC61 VAXG[10] +1.5V_CPU_VDDQ AA1 VSS[12] VSS[102] AN40
AD47 VAXG[11] CC179 2 1 0.1U_0402_10V7K~D AA13 VSS[13] VSS[103] AN43
AD48 VAXG[12] AA50 VSS[14] VSS[104] AN47
AD50 VAXG[13] 6A AA51 VSS[15] VSS[105] AN50
AD51 VAXG[14] AJ28 CC149 2 1 0.1U_0402_10V7K~D AA52 VSS[16] VSS[106] AN54
VAXG[15] VDDQ[1] +1.5V VSS[17] VSS[107]
- 1.5V RAILS
AD52 AJ33 AA53 AP10
AD53 VAXG[16] VDDQ[2] AJ36 AA55 VSS[18] VSS[108] AP51
AD55 VAXG[17] VDDQ[3] AJ40 CC150 2 1 0.1U_0402_10V7K~D AA56 VSS[19] VSS[109] AP55
AD56 VAXG[18] VDDQ[4] AL30 AA8 VSS[20] VSS[110] AP7
C C
AD58 VAXG[19] VDDQ[5] AL34 AB16 VSS[21] VSS[111] AR13
AD59 VAXG[20] VDDQ[6] AL38 AB18 VSS[22] VSS[112] AR17
AE46 VAXG[21] VDDQ[7] AL42 AB21 VSS[23] VSS[113] AR21
N45 VAXG[22] VDDQ[8] AM33 AB48 VSS[24] VSS[114] AR41
P47 VAXG[23] VDDQ[9] AM36 AB61 VSS[25] VSS[115] AR48
P48 VAXG[24] VDDQ[10] AM40 AC10 VSS[26] VSS[116] AR61
P50 VAXG[25] VDDQ[11] AN30 AC14 VSS[27] VSS[117] AR7
VAXG[26] VDDQ[12] VSS[28] VSS[118]
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
330U_D2_2VM_R6M~D
P51 AN34 1 1 1 1 1 1 1 1 1 AC46 AT14
P52 VAXG[27] VDDQ[13] AN38 AC6 VSS[29] VSS[119] AT19
VAXG[28] VDDQ[14] VSS[30] VSS[120]
CC181
CC180
CC161
CC162
CC163
CC164
CC165
CC166
CC167
P53 AR26 + AD17 AT36
DDR3
P55 VAXG[29] VDDQ[15] AR28 AD20 VSS[31] VSS[121] AT4
GRAPHICS
P56 VAXG[30] VDDQ[16] AR30 2 2 2 2 2 2 2 2 AD4 VSS[32] VSS[122] AT45
P61
T48
VAXG[31]
VAXG[32]
VAXG[33]
VDDQ[17]
VDDQ[18]
VDDQ[19]
AR32
AR34
2 AD61
AE13
VSS[33]
VSS[34]
VSS[35]
VSS VSS[123]
VSS[124]
VSS[125]
AT52
AT58
T58 AR36 AE8 AU1
T59 VAXG[34] VDDQ[20] AR40 AF1 VSS[36] VSS[126] AU11
T61 VAXG[35] VDDQ[21] AV41 AF17 VSS[37] VSS[127] AU28
U46 VAXG[36] VDDQ[22] AW26 AF21 VSS[38] VSS[128] AU32
V47 VAXG[37] VDDQ[23] BA40 AF47 VSS[39] VSS[129] AU51
V48 VAXG[38] VDDQ[24] BB28 AF48 VSS[40] VSS[130] AU7
V50 VAXG[39] VDDQ[25] BG33 AF50 VSS[41] VSS[131] AV17
V51 VAXG[40] VDDQ[26] AF51 VSS[42] VSS[132] AV21
VAXG[41] VSS[43] VSS[133]
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
V52 AF52 AV22
V53 VAXG[42] AF53 VSS[44] VSS[134] AV34
VAXG[43] 1 1 1 1 1 1 1 1 1 1 VSS[45] VSS[135]
CC250
CC251
CC252
CC253
CC254
CC255
CC256
CC257
CC258
CC259
V55 AF55 AV40
V59 VAXG[46] 2 2 2 2 2 2 2 2 2 2 AF59 VSS[48] VSS[138] AW13
W50 VAXG[47] AG10 VSS[49] VSS[139] AW43
W53 VAXG[50] AG47 VSS[52] VSS[142] AY14
+VCC_GFXCORE_AXG Y48 VAXG[54] AH4 VSS[56] VSS[146] AY4
Y61 VAXG[55] AH58 VSS[57] VSS[147] AY41
B B
VAXG[56] AJ13 VSS[58] VSS[148] AY45
VSS[59] VSS[149]
1
@ AJ16 AY49
RC99 RC76 +1.5V_CPU_VDDQ AJ20 VSS[60] VSS[150] AY55
100_0402_1% 100_0402_1% AJ22 VSS[61] VSS[151] AY58
2 1 AJ26 VSS[62] VSS[152] AY9
VSS[63] VSS[153]
QUIET RAILS
AM28 AJ30 BA1

SENSE
LINES
2
VCCDQ[1] VSS[64] VSS[154]
1U_0402_6.3V6K
F45 AN26 AJ34 BA11
<52> VCC_AXG_SENSE VAXG_SENSE VCCDQ[2] VSS[65] VSS[155]
G45 1 AJ38 BA17
<52> VSS_AXG_SENSE VSSAXG_SENSE VSS[66] VSS[156]
AJ42 BA21
VSS[67] VSS[157]
1
CC574
AJ45 BA26
RC100 AJ48 VSS[68] VSS[158] BA32
100_0402_1% 2 AJ7 VSS[69] VSS[159] BA48
+1.8VS AK1 VSS[70] VSS[160] BA51
1.2A
1.8V RAIL
AK52 VSS[71] VSS[161] BB53

2
BB3 AL10 VSS[72] VSS[162] BC13

VCCPLL[1] VSS[73] VSS[163]
330U_D2_2.5VM_R6M~D
1 BC1 AL13 BC5

1U_0402_6.3V6K
1U_0402_6.3V6K
1 1 BC4 AL17 BC57

CC176
+ AL21 BD12
VSS[76] VSS[166]
CC174
CC175
AL25 BD16
AL28 VSS[77] VSS[167] BD19
2 2 2 BC43 AL33 VSS[78] VSS[168] BD23
+VCCSA VDDQ_SENSE BA43 AL36 VSS[79] VSS[169] BD27
VSS_SENSE_VDDQ VSS[80] VSS[170]
SENSE LINES
AL40 BD32
6A L17 AL43 VSS[81] VSS[171] BD36
L21 VCCSA[1] AL47 VSS[82] VSS[172] BD40
N16 VCCSA[2] AL61 VSS[83] VSS[173] BD44
VCCSA[3] VSS[84] VSS[174]
330U_D2_2VM_R6M~D
N20 AM13 BD48

VCCSA[4] VSS[85] VSS[175]
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
N22 AM20 BD52

SA RAIL
P17 VCCSA[5] AM22 VSS[86] VSS[176] BD56

1 1 1 1 1 1 1 1 1 1 1 VCCSA[6] VSS[87] VSS[177]
CC264
CC263
CC262
CC261
CC260
P20 U10 AM26 BD8

VCCSA[7] VCCSA_SENSE VCCSA_SENSE <51> VSS[88] VSS[178]
CC172
CC171
CC170
CC169
CC168
CC183
+ R16 AM30 BE5

R18 VCCSA[8] AM34 VSS[89] VSS[179] BG13
2 2 2 2 2 2 2 2 2 2 R21 VCCSA[9] VSS[90] VSS[180]
2 U15 VCCSA[10]
VCCSA VID
V16 VCCSA[11]
V17 VCCSA[12] D48
VCCSA[13] VCCSA_VID[0] VCCSA_VID0 <51>
lines
A V18 D49 A
VCCSA[14] VCCSA_VID[1] VCCSA_VID1 <51>
V21 AV8063801058002-SR0N8-L1-1.7G_BGA1023~D
W20 VCCSA[15]
VCCSA[16]
AV8063801058002-SR0N8-L1-1.7G_BGA1023~D

Deciphered Date
PROCESSOR(6/6) PWR,VSS
1.0
LA-9102P
5 4 3 2 1
5 4 3 2 1
+1.5V +1.5V
JDIMM1
+V_DDR_REFA +V_DDR_REFA 1 2
<7> DDR_A_DQS#[0..7] +1.5V VREF_DQ VSS1
3 4 DDR_A_D4
VSS2 DQ4
2.2U_0603_6.3V6K
0.1U_0402_16V7K
DDR_A_D0 5 6 DDR_A_D5
<7> DDR_A_DQS[0..7]
1
DDR_A_D1 7 DQ0 DQ5 8
RD1 9 DQ1 VSS3 10 DDR_A_DQS#0
D <7> DDR_A_D[0..63] 1 1 VSS4 DQS#0 D
1K_0402_1% 11 12 DDR_A_DQS0
DM0 DQS0
CD1
CD2
13 14
<7> DDR_A_MA[0..15] +V_DDR_REFA VSS5 VSS6
DQ2 DQ6
2
2 2 DDR_A_D3 17 18 DDR_A_D7
19 DQ3 DQ7 20
DDR_A_D8 21 VSS7 VSS8 22 DDR_A_D12
1
DDR_A_D9 23 DQ8 DQ12 24 DDR_A_D13
25 DQ9 DQ13 26
RD3 DDR_A_DQS#1 27 VSS9 VSS10 28
1K_0402_1% DDR_A_DQS1 29 DQS#1 DM1 30 DDR3_DRAMRST#
DQS1 RESET# DDR3_DRAMRST# <12,7>
31 32
VSS11 VSS12
2
37 DQ11 DQ15 38
43 DQ17 DQ21 44
DDR_A_DQS#2 45 VSS15 VSS16 46
DDR_A_DQS2 47 DQS#2 DM2 48
49 DQS2 VSS17 50
Layout Note: All VREF traces should
VSS18 DQ22
DDR_A_D22
have 10 mil trace width DDR_A_D18 51 52 DDR_A_D23
Place near JDIMM1 DDR_A_D19 53 DQ18 DQ23 54
55 DQ19 VSS19 56 DDR_A_D28
DDR_A_D24 57 VSS20 DQ28 58 DDR_A_D29
DDR_A_D25 59 DQ24 DQ29 60
61 DQ25 VSS21 62 DDR_A_DQS#3
63 VSS22 DQS#3 64 DDR_A_DQS3
+1.5V 65 DM3 DQS3 66
71 DQ27 DQ31 72
VSS25 VSS26
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1 1 1 1
CD3
CD4
CD5
CD6
<7> DDR_CKE0_DIMMA DDR_CKE0_DIMMA 73 74 DDR_CKE1_DIMMA DDR_CKE1_DIMMA <7>

75 CKE0 CKE1 76
2 2 2 2 77 VDD1 VDD2 78 DDR_A_MA15
C C
DDR_A_BS2 79 NC1 A15 80 DDR_A_MA14
<7> DDR_A_BS2 BA2 A14
81 82
DDR_A_MA12 83 VDD3 VDD4 84 DDR_A_MA11
DDR_A_MA9 85 A12/BC# A11 86 DDR_A_MA7
87 A9 A7 88
DDR_A_MA8 89 VDD5 VDD6 90 DDR_A_MA6
DDR_A_MA5 91 A8 A6 92 DDR_A_MA4
93 A5 A4 94
+1.5V DDR_A_MA3 95 VDD7 VDD8 96 DDR_A_MA2
DDR_A_MA1 97 A3 A2 98 DDR_A_MA0
99 A1 A0 100
M_CLK_DDR0 101 VDD9 VDD10 102 M_CLK_DDR1
<7> M_CLK_DDR0 CK0 CK1 M_CLK_DDR1 <7>
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
<7> M_CLK_DDR#0 M_CLK_DDR#0 103 104 M_CLK_DDR#1 M_CLK_DDR#1 <7>

105 CK0# CK1# 106 +1.5V
VDD11 VDD12
220U_2V_D2
@ 1 DDR_A_MA10 107 108 DDR_A_BS1 DDR_A_BS1 <7>

DDR_A_BS0 109 A10/AP BA1 110 DDR_A_RAS#
1 1 1 1 1 1 1 <7> DDR_A_BS0 BA0 RAS# DDR_A_RAS# <7>
CD7
CD8
CD9
CD10
CD11
CD12
CD13
CD14
+ 111 112
1
DDR_A_WE# 113 VDD13 VDD14 114 DDR_CS0_DIMMA#
<7> DDR_A_WE# WE# S0# DDR_CS0_DIMMA# <7>
<7> DDR_A_CAS# DDR_A_CAS# 115 116 M_ODT0 M_ODT0 <7>
RD4
2 2 2 2 2 2 2 2 117 CAS# ODT0 118 1K_0402_1%
DDR_A_MA13 119 VDD15 VDD16 120 M_ODT1
A13 ODT1 M_ODT1 <7>
<7> DDR_CS1_DIMMA# DDR_CS1_DIMMA# 121 122
S1# NC2
2
123 124
125 VDD17 VDD18 126 +VREF_CA
127 NCTEST VREF_CA 128
VSS27 VSS28
2.2U_0603_6.3V6K
0.1U_0402_16V7K
DDR_A_D32 129 130 DDR_A_D36
DQ32 DQ36
1
DDR_A_D33 131 132 DDR_A_D37
133 DQ33 DQ37 134 RD5
VSS29 VSS30 1 1
DDR_A_DQS#4 135 136 1K_0402_1%
DQS#4 DM4
CD15
CD16
Layout Note: DDR_A_DQS4 137 138
139 DQS4 VSS31 140 DDR_A_D38
Place near JDIMM1.203,204
2
DDR_A_D34 141 VSS32 DQ38 142 DDR_A_D39 2 2
DDR_A_D35 143 DQ34 DQ39 144
145 DQ35 VSS33 146 DDR_A_D44
DDR_A_D41 149 DQ40 DQ45 150
151 DQ41 VSS35 152 DDR_A_DQS#5
B B
153 VSS36 DQS#5 154 DDR_A_DQS5
155 DM5 DQS5 156
+0.75VS DDR_A_D42 157 VSS37 VSS38 158 DDR_A_D46
DDR_A_D43 159 DQ42 DQ46 160 DDR_A_D47
161 DQ43 DQ47 162
DDR_A_D49 165 DQ48 DQ52 166 DDR_A_D53
DQ49 DQ53
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
167 168 @ RD8 1 2 0_0402_5%

1 1 1 1 DDR_A_DQS#6
DDR_A_DQS6
169
171
VSS41
DQS#6
DQS6
VSS42
DM6
VSS43
170
172 M3
CD17
CD18
CD19
CD20
173 174 DDR_A_D54 QD1

VSS44 DQ54
D
DDR_A_D50 175 176 DDR_A_D55 +SA_DIMM_VREFDQ 3 1 BSS138_NL_SOT23-3 +V_DDR_REFA
2 2 2 2 DDR_A_D51 177 DQ50 DQ55 178
179 DQ51 VSS45 180 DDR_A_D60
G
DQ56 DQ61
2
DDR_A_D57 183 184
185 DQ57 VSS47 186 DDR_A_DQS#7 DRAMRST_CNTRL
VSS48 DQS#7 <7> DRAMRST_CNTRL
187 188 DDR_A_DQS7
189 DM7 DQS7 190
DDR_A_D59 193 DQ58 DQ62 194 DDR_A_D63
195 DQ59 DQ63 196 @ RD9 1 2 0_0402_5%
1 2 197 VSS51 VSS52 198
RD6 10K_0402_5% 199 SA0 EVENT# 200 PCH_SMBDATA
+3VS VDDSPD SDA PCH_SMBDATA <12,14,38,6>
0.1U_0402_16V7K
2.2U_0603_6.3V6K
1 2 201 202 PCH_SMBCLK QD2

SA1 SCL PCH_SMBCLK <12,14,38,6>
D
1 1 RD7 10K_0402_5% 203 204 +0.75VS +SB_DIMM_VREFDQ
3 1 BSS138_NL_SOT23-3 +V_DDR_REFB
VTT1 VTT2
CD21
CD22
+0.75VS
205 206
G1 G2
G
2
2 2 BELLW_80001-5021
CONN@ DRAMRST_CNTRL
M3 Circuit (Processor Generated SO-DIMM VREF_DQ)

SP07000LZ00
A A

Deciphered Date
DDRIII DIMMA
1.0
LA-9102P
5 4 3 2 1
5 4 3 2 1
+1.5V +1.5V
JDIMM2
+1.5V +V_DDR_REFB 1 2
+V_DDR_REFB VREF_DQ VSS
3 4 DDR_B_D4
VSS DQ4
2.2U_0603_6.3V6K
0.1U_0402_16V7K
DDR_B_D0 5 6 DDR_B_D5
DDR_B_D1 7 DQ0 DQ5 8
D D
1
9 DQ1 VSS 10 DDR_B_DQS#0
1 1 VSS DQS0#
11 12 DDR_B_DQS0
DM0 DQS0
CD27
CD26
RD15 13 14
1K_0402_1% DDR_B_D2 15 VSS VSS 16 DDR_B_D6
+V_DDR_REFB 2 2 DDR_B_D3 17 DQ2 DQ6 18 DDR_B_D7
DQ3 DQ7
2
19 20
DDR_B_D8 21 VSS VSS 22 DDR_B_D12
<7> DDR_B_DQS#[0..7] DQ8 DQ12
25 DQ9 DQ13 26
<7> DDR_B_DQS[0..7] VSS VSS
1
DDR_B_DQS#1 27 28
DDR_B_DQS1 29 DQS1# DM1 30 DDR3_DRAMRST#
<7> DDR_B_D[0..63] DQS1 RESET# DDR3_DRAMRST# <11,7>
RD16 Note: 31 32
1K_0402_1% DDR_B_D10 33 VSS VSS 34 DDR_B_D14
<7> DDR_B_MA[0..15] Check voltage tolerance of DDR_B_D11 35 DQ10 DQ14 36 DDR_B_D15
2
VREF_DQ at the DIMM socket 37 DQ11 DQ15 38
DDR_B_D17 41 DQ16 DQ20 42 DDR_B_D21
43 DQ17 DQ21 44
DDR_B_DQS#2 45 VSS VSS 46
DDR_B_DQS2 47 DQS2# DM2 48
49 DQS2 VSS 50 DDR_B_D22
DDR_B_D18 51 VSS DQ22 52 DDR_B_D23
DDR_B_D19 53 DQ18 DQ23 54
55 DQ19 VSS 56 DDR_B_D28
All VREF traces should VSS DQ28
have 10 mil trace width DDR_B_D24 57 58 DDR_B_D29
DDR_B_D25 59 DQ24 DQ29 60
63 VSS DQS3# 64 DDR_B_DQS3
65 DM3 DQS3 66
67 VSS VSS 68
Layout Note: DDR_B_D26
DQ26 DQ30
DDR_B_D30
Place near JDIMMB 71 DQ27 DQ31 72
VSS VSS
<7> DDR_CKE2_DIMMB DDR_CKE2_DIMMB 73 74 DDR_CKE3_DIMMB DDR_CKE3_DIMMB <7>

75 CKE0 CKE1 76
77 VDD VDD 78 DDR_B_MA15
C C
DDR_B_BS2 79 NC A15 80 DDR_B_MA14
<7> DDR_B_BS2 BA2 A14
81 82
+1.5V DDR_B_MA12 83 VDD VDD 84 DDR_B_MA11
DDR_B_MA9 85 A12/BC# A11 86 DDR_B_MA7
87 A9 A7 88
DDR_B_MA8 89 VDD VDD 90 DDR_B_MA6
A8 A6
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
DDR_B_MA5 91 92 DDR_B_MA4
93 A5 A4 94
1 1 1 1 VDD VDD
CD28
CD29
CD30
CD31
DDR_B_MA3 95 96 DDR_B_MA2
DDR_B_MA1 97 A3 A2 98 DDR_B_MA0
99 A1 A0 100
2 2 2 2 M_CLK_DDR2 101 VDD VDD 102 M_CLK_DDR3
<7> M_CLK_DDR2 CK0 CK1 M_CLK_DDR3 <7>
<7> M_CLK_DDR#2 M_CLK_DDR#2 103 104 M_CLK_DDR#3 M_CLK_DDR#3 <7>
105 CK0# CK1# 106 +1.5V
DDR_B_MA10 107 VDD VDD 108 DDR_B_BS1
A10/AP BA1 DDR_B_BS1 <7>
<7> DDR_B_BS0 DDR_B_BS0 109 110 DDR_B_RAS# DDR_B_RAS# <7>
111 BA0 RAS# 112
1
DDR_B_WE# 113 VDD VDD 114 DDR_CS2_DIMMB#
<7> DDR_B_WE# WE# S0# DDR_CS2_DIMMB# <7>
<7> DDR_B_CAS# DDR_B_CAS# 115 116 M_ODT2 M_ODT2 <7>
RD17
+1.5V 117 CAS# ODT0 118 1K_0402_1%
DDR_B_MA13 119 VDD VDD 120 M_ODT3
A13 ODT1 M_ODT3 <7>
<7> DDR_CS3_DIMMB# DDR_CS3_DIMMB# 121 122
S1# NC
2
123 124
VDD VDD
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
125 126 +VREF_CB

127 TEST VREF_CA 128
VSS VSS
220U_2V_D2
2.2U_0603_6.3V6K
0.1U_0402_16V7K
@ 1 DDR_B_D32 129 130 DDR_B_D36
DQ32 DQ36
1
1 1 1 1 1 1 1 DDR_B_D33 131 132 DDR_B_D37
DQ33 DQ37
CD32
CD33
CD34
CD35
CD36
CD37
CD38
CD39
+ 133 134 1 1 RD18

DDR_B_DQS#4 135 VSS VSS 136 1K_0402_1%
DQS4# DM4
CD40
CD41
DDR_B_DQS4 137 138
2 2 2 2 2 2 2 2 139 DQS4 VSS 140 DDR_B_D38
2
DDR_B_D34 141 VSS DQ38 142 DDR_B_D39 2 2
DDR_B_D35 143 DQ34 DQ39 144
145 DQ35 VSS 146 DDR_B_D44
DDR_B_D41 149 DQ40 DQ45 150
B B
155 DM5 DQS5 156
DDR_B_D43 159 DQ42 DQ46 160 DDR_B_D47
161 DQ43 DQ47 162
Layout Note: VSS VSS
DDR_B_D48 163 164 DDR_B_D52
Place near JDIMMB.203,204 DDR_B_D49 165 DQ48 DQ52 166 DDR_B_D53
167 DQ49 DQ53 168
DDR_B_DQS#6 169 VSS VSS 170
DDR_B_DQS6 171 DQS6# DM6 172
173 DQS6 VSS 174 DDR_B_D54
DDR_B_D51 177 DQ50 DQ55 178
179 DQ51 VSS 180 DDR_B_D60
+0.75VS DDR_B_D56 181 VSS DQ60 182 DDR_B_D61
DDR_B_D57 183 DQ56 DQ61 184
189 DM7 DQS7 190
VSS VSS
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
DDR_B_D58 191 192 DDR_B_D62

DDR_B_D59 193 DQ58 DQ62 194 DDR_B_D63
1 1 1 1 DQ59 DQ63
195 196
+3VS VSS VSS
CD42
CD43
CD44
CD45
197 198
199 SA0 EVENT# 200 PCH_SMBDATA
2 2 2 2 +3VS VDDSPD SDA PCH_SMBDATA <11,14,38,6>
2 1 201 202 PCH_SMBCLK
SA1 SCL PCH_SMBCLK <11,14,38,6>
+0.75VS
203 204 +0.75VS
1
VTT VTT
0.1U_0402_16V7K
2.2U_0603_6.3V6K
RD19
10K_0402_5%
10K_0402_5% 205 206

GND1 GND2
RD20
1 1 207 208
BOSS1 BOSS2
CD46
CD47
2
BELLW_80001-1021
2 2 CONN@
A
SP07000P700 A

Deciphered Date
DDRIII DIMMB
1.0
LA-9102P
5 4 3 2 1
5 4 3 2 1
PCH_RTCX1 +3VS
XTAL@
1 2 PCH_RTCX2
RH1 10M_0402_5% SERIRQ RH10 2 1 10K_0402_5%
YH1 @ +RTCVCC
1 2 2 1 HDA_SDOUT HDD_DET# RH12 2 1 10K_0402_5%
close to YH1 CH1 10P_0402_50V8J 330K_0402_5%
32.768KHZ_12.5PF_9H03200019 GCLK@ PCH_INTVRMEN RH13 2 1 PCH_SATALED# RH14 2 1 10K_0402_5%
D XTAL@ 1 2 PCH_RTCX1 @ D
<23> PCH_RTCX1_R
RH30 0_0402_5% 2 1 HDA_BIT_CLK PCH_INTVRMEN RH16 2 @ 1
18P_0402_50V8J
CH2 10P_0402_50V8J UH1 R3@

330K_0402_5% +3VS
1 1
CH3 CH4 XTAL@ INTVRMEN
XTAL@
18P_0402_50V8J
+RTCVCC * H：Integrated
L：Integrated
VRM enable
VRM disable HDA_SPKR RH17 2 @ 1 1K_0402_5%
2 2 Reserve for RF please close to UH1
RH2 1 2 SM_INTRUDER# BD82HM76-SLJ8E-C1_BGA989~D LOW=Default
1M_0402_5%
SA00005FH2L
*HIGH=No Reboot
R1@ SA00005FH1L
UH1A
keep away hot spot HDA_SDO +3V_PCH
+RTCVCC PCH_RTCX1 A20 C38 LPC_AD0
1 LPC_AD0 <40> ME debug mode , this signal has a weak internal PD
1
CMOS RTCX1 FWH0 / LAD0 A38 LPC_AD1
LPC
FWH1 / LAD1 LPC_AD1 <40>
CH5 CLRP1 PCH_RTCX2 C20 B37 LPC_AD2 L=>security measures defined in the Flash HDA_SDOUT RH23 2 @ 1 1K_0402_5%
RTCX2 FWH2 / LAD2 LPC_AD2 <40>
1U_0603_10V6K SHORT PADS C37 LPC_AD3
FWH3 / LAD3 LPC_AD3 <40> Descriptor will be in effect (default)
2
1 2 2 PCH_RTCRST# D20
RH3 20K_0402_5% RTCRST#
FWH4 / LFRAME#
D36 LPC_FRAME#
LPC_FRAME# <40>
*Low = Disabled
High = Enabled
1 2 PCH_SRTCRST# G22 H=>Flash Descriptor Security will be overridden
RH4 20K_0402_5% SRTCRST# E36
1
RTC
LDRQ0#
1
SM_INTRUDER# K22 K36
CH6 CLRP2 INTRUDER# LDRQ1# / GPIO23
1U_0603_10V6K SHORT PADS PCH_INTVRMEN C17 V5 SERIRQ SERIRQ <40>
2
2 ME CMOS INTVRMEN SERIRQ

CLP1 & CLP2 place near DIMM
AM3 SATA_PRX_DTX_N0 <41> HDA_SYNC
1 2 HDA_BIT_CLK HDA_BIT_CLK N34 SATA0RXN AM1
<33> HDA_BITCLK_AUDIO HDA_BCLK SATA0RXP SATA_PRX_DTX_P0 <41>
SATA 6G
RH5 33_0402_5% AP7 SATA_PTX_DRX_N0 CH7 1 2 0.01U_0402_16V7K HDD This signal has a weak internal pull-down
+5VS SATA0TXN SATA_PTX_DRX_N0_C <41>
HDA_SYNC L34 AP5 SATA_PTX_DRX_P0 CH8 1 2 0.01U_0402_16V7K On Die PLL VR is supplied by
HDA_SYNC SATA0TXP SATA_PTX_DRX_P0_C <41>
1 2 HDA_RST#
<33> HDA_RST_AUDIO# 1.5V when smapled high
RH6 33_0402_5% HDA_SPKR T10 AM10
<33> HDA_SPKR
2
SPKR SATA1RXN 1.8V when sampled low

G
AM8
HDA_RST# K34 SATA1RXP AP11 Needs to be pulled High for Huron River platfrom
1 2 HDA_SYNC_R 3 1 HDA_SYNC HDA_RST# SATA1TXN AP10
C <33> HDA_SYNC_AUDIO C
RH7 33_0402_5% SATA1TXP +3V_PCH
S
<33> HDA_SDIN0 HDA_SDIN0 E34 AD7 SATA_PRX_DTX_N2 SATA_PRX_DTX_N2 <41>

QH1 BSS138_SOT23 HDA_SDIN0 SATA2RXN AD5 SATA_PRX_DTX_P2
SATA2RXP SATA_PRX_DTX_P2 <41>
1 2 1 @ 2 G34 AH5 SATA_PTX_DRX_N2 SATA_PTX_DRX_N2 <41> ODD HDA_SYNC 2 1
RH8 1M_0402_5% RH9 0_0402_5% HDA_SDIN1 SATA2TXN AH4 SATA_PTX_DRX_P2 RH32 1K_0402_5%
SATA2TXP SATA_PTX_DRX_P2 <41>
C34
IHDA
HDA_SDIN2 AB8
A34 SATA3RXN AB10
1 2 HDA_SDOUT
HDA_SDIN3 SATA3RXP AF3
<40> ME_EN
RH11 1K_0402_1%
HDA_SDOUT A36
SATA3TXN
SATA3TXP
AF1 RTC Battery
SATA
1 2 HDA_SDOUT HDA_SDO Y7
<33> HDA_SDOUT_AUDIO SATA4RXN
RH15 33_0402_5% Y5
C36 SATA4RXP AD3
HDA_DOCK_EN# / GPIO33 SATA4TXN AD1
N32 SATA4TXP +RTCBATT
HDA_DOCK_RST# / GPIO13 Y3
SATA5RXN Y1
SATA5RXP AB3
2
+3V_PCH +3V_PCH +3V_PCH PCH_JTAG_TCK J3 SATA5TXN AB1
JTAG_TCK SATA5TXP RH34
H7 Y11 +1.05VS_VCC_SATA +CHGRTC
PCH_JTAG_TMS_R 1K_0402_5%
JTAG
JTAG_TMS SATAICOMPO
1
@ @ @ PCH_JTAG_TDI_R K5 Y10 SATA_COMP 1 2

JTAG_TDI SATAICOMPI
1
RH18 RH19 RH20 RH21 37.4_0402_1% W=20mils
200_0402_1% 200_0402_1% 200_0402_1% PCH_JTAG_TDO_R H1 W=20mils
JTAG_TDO
2
AB12 +1.05VS_SATA3
2
PCH_JTAG_TDO_R PCH_JTAG_TMS_R PCH_JTAG_TDI_R SATA3RCOMPO DH1

JP12
AB13 SATA3_COMP 1 2 BAT54CW_SOT323-3
1
SATA3COMPI RH22 49.9_0402_1% 2 1

RH24 RH25 RH26 +CHGRTC 2 1 +3VLP
100_0402_1% 100_0402_1% 100_0402_1% PCH_SPI_CLK T3 AH1 RBIAS_SATA3 1 2 JUMP_43X39
SPI_CLK SATA3RBIAS
1
RH28 750_0402_1%~D
PCH_SPI_CS0# Y14 +RTCVCC
SPI_CS0#
2
W=20mils 1
PCH_SPI_CS1# T1 CH12
SPI
SPI_CS1# P3 PCH_SATALED# 1U_0603_10V6K

B PCH_SATALED# <38> B
SATALED# @
PCH_SPI_SI V4 V14 HDD_DET#_R RH268 1 2 0_0402_1% HDD_DET# 2
SPI_MOSI SATA0GP / GPIO21 HDD_DET# <41>
PCH_JTAG_TCK PCH_SPI_SO U3 P1 BBS_BIT0_R 2 1 10K_0402_5% +3VS
<6> PCH_JTAG_TCK SPI_MISO SATA1GP / GPIO19 RH29
PCH_JTAG_TMS 1 @ 2 PCH_JTAG_TMS_R
<6> PCH_JTAG_TMS
RH44 0_0402_5% BD82HM76-SLJ8E-C1_BGA989~D
PCH_JTAG_TDI 1 @ 2 PCH_JTAG_TDI_R
<6> PCH_JTAG_TDI
RH48 0_0402_5%
PCH_JTAG_TDO 1 @ 2 PCH_JTAG_TDO_R
<6> PCH_JTAG_TDO
RH70 0_0402_5%
+3V_PCH
+3V_PCH
NEC flash issue.
+3V_PCH
+3V_PCH +3V_PCH
0.1U_0402_16V7K
0.1U_0402_16V7K
CH11
1
SPI ROM FOR ME CH98
1
2
@ @
( 4MByte )
2
RH262 RH33 2 @
3.3K_0402_5% 3.3K_0402_5% SPI ROM FOR WIN8( 2MByte ) RH263 2
PCH_JTAG_TCK 1 2 3.3K_0402_5%
RH35 51_0402_5% @ UH6 X76@
1
+3V_PCH PCH_SPI_CS0# 1 RH264 2 0_0402_1% PCH_SPI_CS0#_R 1 8

CS# VCC
1
@ UH2 X76@ PCH_SPI_SO 2 1 PCH_SPI_SO_L 2 7 PCH_SPI_HOLD#
PCH_SPI_CS1# 1 RH36 2 0_0402_1% PCH_SPI_CS1#_R 1 8 RH265 33_0402_5% PCH_SPI_WP# 3 SO/SIO1 HOLD# 6 PCH_SPI_CLK_L 2 RH266 133_0402_5% PCH_SPI_CLK
PCH_SPI_SO 2 RH37 1 33_0402_5% PCH_SPI_SO_R 2 CS# VCC 7 PCH_SPI_HOLD# 4 WP# SCLK 5 PCH_SPI_SI_L 2 1 PCH_SPI_SI
1 2 PCH_SPI_WP# PCH_SPI_WP# 3 SO HOLD# 6 PCH_SPI_CLK_R 2 RH27 133_0402_5% PCH_SPI_CLK GND SI/SIO0 RH267 33_0402_5%
RH38 3.3K_0402_5% 4 WP# SCLK 5 PCH_SPI_SI_R 2 RH39 133_0402_5% PCH_SPI_SI EN25Q32B-104HIP_SO8
GND SI
1 2 PCH_SPI_HOLD# EN25QH16-104HIP_SO8
RH40 3.3K_0402_5% 1
EON
CH99
A
@ 10P_0402_50V8J EN25Q32B-104HIP_SO8 A
2
EON
EN25QH16-104HIP_SO8
ZZZ SPIEON@ ZZZ SPIWB@ ZZZ SPIMXIC@

Deciphered Date
PCH (1/8) SATA/HDA/SPI/LPC
X7644031L07 X7644031L08 X7644031L09 1.0
LA-9102P
5 4 3 2 1
5 4 3 2 1
SMBCLK 1 2 +3V_PCH
RH45 2.2K_0402_5%
UH1B 1 2
SMBDATA
RH46 2.2K_0402_5%
<32> PCIE_PRX_LANTX_N1 PCIE_PRX_LANTX_N1 BG34 SML0CLK 1 2
PCIE_PRX_LANTX_P1 BJ34 PERN1 E12 SMBALERT# RH47 2.2K_0402_5%
<32> PCIE_PRX_LANTX_P1 PERP1 SMBALERT# / GPIO11
10/100 LAN ---> CH19 1 2 0.1U_0402_10V7K~D PCIE_PTX_LANRX_N1_C AV32 SML0DATA 1 2
<32> PCIE_PTX_LANRX_N1 PETN1
CH20 1 2 0.1U_0402_10V7K~D PCIE_PTX_LANRX_P1_C AU32 H14 SMBCLK RH49 2.2K_0402_5%
<32> PCIE_PTX_LANRX_P1 PETP1 SMBCLK
MEMORY SML1CLK 1 2
D <38> PCIE_PRX_WLANTX_N2 PCIE_PRX_WLANTX_N2 BE34 C9 SMBDATA RH50 2.2K_0402_5% D
PCIE_PRX_WLANTX_P2 BF34 PERN2 SMBDATA SML1DATA 1 2
<38> PCIE_PRX_WLANTX_P2 PERP2
WLAN (Mini Card)---> CH21 1 2 0.1U_0402_10V7K~D PCIE_PTX_WLANRX_N2_C BB32 RH51 2.2K_0402_5%
<38> PCIE_PTX_WLANRX_N2 PETN2
CH22 1 2 0.1U_0402_10V7K~D PCIE_PTX_WLANRX_P2_C AY32 SMBALERT# 1 2
SMBUS
<38> PCIE_PTX_WLANRX_P2 PETP2 A12 DRAMRST_CNTRL_PCH RH52 10K_0402_5%
SML0ALERT# / GPIO60 DRAMRST_CNTRL_PCH <7>
BG36 PCH_HOT# 1 2
BJ36 PERN3 C8 SML0CLK RH86 10K_0402_5%
AV34 PERP3 SML0CLK DRAMRST_CNTRL_PCH 1 2
AU34 PETN3 G12 SML0DATA RH53 1K_0402_5%
PETP3 SML0DATA
BF36
BE36 PERN4
AY34 PERP4 C13 PCH_HOT#
PETN4 SML1ALERT# / PCHHOT# / GPIO74 PCH_HOT# <40>
BB34 CLKIN_DMI2# RH54 1 2 10K_0402_5%
PETP4 E14 SML1CLK CLKIN_DMI2 RH55 1 2 10K_0402_5%
PCI-E*
BG37 SML1CLK / GPIO58 CLKIN_DMI# RH56 1 2 10K_0402_5%
BH37 PERN5 M16 SML1DATA CLKIN_DMI RH57 1 2 10K_0402_5%
AY36 PERP5 SML1DATA / GPIO75 CLKIN_DOT96# RH58 1 2 10K_0402_5%
BB36 PETN5 RH59 1 2 10K_0402_5%
PETP5 Total device 20090512 CLKIN_DOT96
1 2
CLKIN_SATA# RH60 10K_0402_5%
BJ38 add double mosfet prevent CLKIN_SATA RH61 1 2 10K_0402_5%
BG38 PERN6 ATI M92 electric leakage CLK_PCH_14M RH62 1 2 10K_0402_5%
PERP6
Controller
AU36 M7
AV36 PETN6 CL_CLK1
PETP6 If use extenal CLK gen, please place close to CLK gen
Link
BG40 T11 +3V_PCH else, please place close to PCH
BJ40 PERN7 CL_DATA1
AY40 PERP7 No support iAMT
BB40 PETN7 P10
2
PETP7 CL_RST1#
BE38 RH64 +3VS +3VS
BC38 PERN8
PERP8 10K_0402_5%
AW38
AY38 PETN8
PETP8
1
M10 PEG_A_CLKRQ# PEG_A_CLKRQ# <25>
RH67 1 @ 2 0_0402_1% PCIE_LAN# Y40 PEG_A_CLKRQ# / GPIO47
<32> CLK_PCIE_LAN# CLKOUT_PCIE0N
C RH68 1 @ 2 0_0402_1% PCIE_LAN Y39 C
<32> CLK_PCIE_LAN CLKOUT_PCIE0P
2
10/100 LAN ---> +3V_PCH
RH69 2 1 10K_0402_5% AB37 CLK_PEG_VGA# CLK_PEG_VGA# <24>
CLOCKS
LAN_CLKREQ# J2 CLKOUT_PEG_A_N AB38 CLK_PEG_VGA RH71 RH72
<32> LAN_CLKREQ# PCIECLKRQ0# / GPIO73 CLKOUT_PEG_A_P CLK_PEG_VGA <24>
2.2K_0402_5% 2.2K_0402_5%
2
RH75 1 @ 2 0_0402_1% PCIE_WLAN# AB49 AV22 CLK_CPU_DMI#
<38> CLK_PCIE_WLAN# CLK_CPU_DMI# <6>
1
RH76 1 @ 2 0_0402_1% PCIE_WLAN AB47 CLKOUT_PCIE1N CLKOUT_DMI_N AU22 CLK_CPU_DMI
<38> CLK_PCIE_WLAN CLKOUT_PCIE1P CLKOUT_DMI_P CLK_CPU_DMI <6>
WLAN (Mini Card)---> +3VS RH77 2 1 10K_0402_5% SMBCLK 6 1
PCH_SMBCLK <11,12,38,6>
<38> WLAN_CLKREQ# WLAN_CLKREQ# M1
PCIECLKRQ1# / GPIO18 AM12 DMN66D0LDW-7_SOT363-6
CLKOUT_DP_N AM13 QH2A
AA48 CLKOUT_DP_P RH78
AA47 CLKOUT_PCIE2N 1 @ 2
CLKOUT_PCIE2P
5
BF18 CLKIN_DMI# 0_0402_5%
RH79 2 1 10K_0402_5% GPIO20 V10 CLKIN_DMI_N BE18 CLKIN_DMI
+3VS PCIECLKRQ2# / GPIO20 CLKIN_DMI_P SMBDATA 3 4
PCH_SMBDATA <11,12,38,6>
Y37 BJ30 CLKIN_DMI2# DMN66D0LDW-7_SOT363-6
Y36 CLKOUT_PCIE3N CLKIN_GND1_N BG30 CLKIN_DMI2 QH2B
CLKOUT_PCIE3P CLKIN_GND1_P RH82
+3V_PCH RH74 2 1 10K_0402_5% GPIO25 A8 1 @ 2
PCIECLKRQ3# / GPIO25 G24 CLKIN_DOT96# 0_0402_5%
CLKIN_DOT_96N E24 CLKIN_DOT96
Y43 CLKIN_DOT_96P
*PCIE REQ power rail: Y45 CLKOUT_PCIE4N
CLKOUT_PCIE4P AK7 CLKIN_SATA# PCH_SMBCLK 1 @ 2 TP_SMBCLK
suspend: 0 3 4 5 6 7 +3V_PCH RH66 1 2 10K_0402_5% GPIO26 L12 CLKIN_SATA_N AK5 CLKIN_SATA RH87 0_0402_1%
PCIECLKRQ4# / GPIO26 CLKIN_SATA_P 1 @ 2
core: 1 2 PCH_SMBDATA
RH93 0_0402_1%
TP_SMBDATA
V45 K45 CLK_PCH_14M

V46 CLKOUT_PCIE5N REFCLK14IN
CLKOUT_PCIE5P +3VS +3VS
+3V_PCH RH83 1 2 10K_0402_5% GPIO44 L14 H45 CLK_PCI_LPBACK
PCIECLKRQ5# / GPIO44 CLKIN_PCILOOPBACK CLK_PCI_LPBACK <16>
AB42 V47 XTAL25_IN

AB40 CLKOUT_PEG_B_N XTAL25_IN V49 XTAL25_OUT
CLKOUT_PEG_B_P XTAL25_OUT
B B
+3V_PCH RH84 1 2 10K_0402_5% GPIO56 E6
PEG_B_CLKRQ# / GPIO56
2
Y47 XCLK_RCOMP 1 2 +1.05VS_VCCDIFFCLKN RH80 RH81
V40 XCLK_RCOMP RH85 90.9_0402_1% 2.2K_0402_5% 2.2K_0402_5%
V42 CLKOUT_PCIE6N
CLKOUT_PCIE6P
2
@ @
1
+3V_PCH RH88 1 2 10K_0402_5% GPIO45 T13
PCIECLKRQ6# / GPIO45 SMBCLK 6 1
TP_SMBCLK <39>
V38 K43 CLK_FLEX0 @ T53 PAD~D
CLKOUT_PCIE7N CLKOUTFLEX0 / GPIO64
FLEX CLOCKS
V37 DMN66D0LDW-7_SOT363-6
5
CLKOUT_PCIE7P F47 CLK_14M_R 1 RH1252 @ T54 PAD~D @
CLKOUTFLEX1 / GPIO65 QH7A
+3V_PCH RH90 1 2 10K_0402_5% GPIO46 K12 22_0402_5%
PCIECLKRQ7# / GPIO46 H47 CLK_LAN_25M_R 2 @ 1 SMBDATA 3 4
CLKOUTFLEX2 / GPIO66 CLK_LAN_25M <32> TP_SMBDATA <39>
CLK_CPU_ITP# RH91 1 @ 2 0_0402_1% CLK_BCLK_ITP# AK14 RH270 22_0402_5%
<6> CLK_CPU_ITP# CLKOUT_ITPXDP_N DMN66D0LDW-7_SOT363-6
CLK_CPU_ITP RH92 1 @ 2 0_0402_1% CLK_BCLK_ITP AK13 K49 DGPU_PRSNT# 2 1 +3VS
<6> CLK_CPU_ITP CLKOUT_ITPXDP_P CLKOUTFLEX3 / GPIO67 RH269 10K_0402_5% @ QH7B
UMA@
2
BD82HM76-SLJ8E-C1_BGA989~D
R1@ RH261
close to YH2 DIS@ 10K_0402_5%
1 2 XTAL25_IN
<23> PCH_X1
1
RH41 0_0402_5%
@ +3V_PCH
GCLK@
@ CH25
RH63 22P_0402_50V8J
CLK_PCH_14M 2 1 1 2
XTAL25_IN 33_0402_5%
XTAL@
2
2 1 XTAL25_OUT
RH89 1M_0402_5% @ close to RH270
@ CH26 SML1CLK 1 6 PCH_SMLCLK <40>
RH65 22P_0402_50V8J 1 2 CLK_LAN_25M
<23> LAN_X1 DMN66D0LDW-7_SOT363-6
CLK_PCI_LPBACK 2 1 1 2 RH31 0_0402_5%
33_0402_5% GCLK@ QH3A
1
Reserve for EMI please close to

25MHZ_10PF_7V25000014
5
1 1
GND OSC
GND OSC
A UH1 A
CH27 YH2 CH28
12P_0402_50V8J 12P_0402_50V8J SML1DATA 4 3 PCH_SMLDATA <40>
XTAL@ XTAL@
XTAL@ 2 2 DMN66D0LDW-7_SOT363-6
QH3B
2

Deciphered Date
PCH (2/8) PCIE/SMBUS/CLK
1.0
LA-9102P
5 4 3 2 1
5 4 3 2 1
UH1C
D <5> DMI_CTX_PRX_N0 DMI_CTX_PRX_N0 BC24 BJ14 FDI_CTX_PRX_N0 FDI_CTX_PRX_N0 <5> D

DMI_CTX_PRX_N1 BE20 DMI0RXN FDI_RXN0 AY14 FDI_CTX_PRX_N1
<5> DMI_CTX_PRX_N1 DMI1RXN FDI_RXN1 FDI_CTX_PRX_N1 <5>
<5> DMI_CTX_PRX_N2 DMI_CTX_PRX_N2 BG18 BE14 FDI_CTX_PRX_N2 FDI_CTX_PRX_N2 <5>
BG20 DMI2RXN FDI_RXN2 BH13 UH1D
<5> DMI_CTX_PRX_N3 DMI_CTX_PRX_N3 FDI_CTX_PRX_N3 FDI_CTX_PRX_N3 <5>
DMI3RXN FDI_RXN3 BC12 FDI_CTX_PRX_N4 ENBKL J47 AP43
FDI_RXN4 FDI_CTX_PRX_N4 <5> <40> ENBKL L_BKLTEN SDVO_TVCLKINN
<5> DMI_CTX_PRX_P0 DMI_CTX_PRX_P0 BE24 BJ12 FDI_CTX_PRX_N5 FDI_CTX_PRX_N5 <5> PCH_ENVDD M45 AP45
DMI0RXP FDI_RXN5 <21> PCH_ENVDD L_VDD_EN SDVO_TVCLKINP
<5> DMI_CTX_PRX_P1 DMI_CTX_PRX_P1 BC20 BG10 FDI_CTX_PRX_N6 FDI_CTX_PRX_N6 <5>
DMI_CTX_PRX_P2 BJ18 DMI1RXP FDI_RXN6 BG9 FDI_CTX_PRX_N7 P45 AM42
<5> DMI_CTX_PRX_P2 DMI2RXP FDI_RXN7 FDI_CTX_PRX_N7 <5> <21> VGA_PWM L_BKLTCTL SDVO_STALLN
<5> DMI_CTX_PRX_P3 DMI_CTX_PRX_P3 BJ20 AM40
DMI3RXP BG14 FDI_CTX_PRX_P0 LVDS_DDC_CLK T40 SDVO_STALLP
FDI_RXP0 FDI_CTX_PRX_P0 <5> <21> LVDS_DDC_CLK L_DDC_CLK
DMI_CRX_PTX_N0 AW24 BB14 FDI_CTX_PRX_P1 FDI_CTX_PRX_P1 <5> <21> LVDS_DDC_DATA LVDS_DDC_DATA K47 AP39
<5> DMI_CRX_PTX_N0 DMI0TXN FDI_RXP1 L_DDC_DATA SDVO_INTN
DMI_CRX_PTX_N1 AW20 BF14 FDI_CTX_PRX_P2 FDI_CTX_PRX_P2 <5>
AP40
<5> DMI_CRX_PTX_N1 DMI1TXN FDI_RXP2 SDVO_INTP
DMI_CRX_PTX_N2 BB18 BG13 FDI_CTX_PRX_P3 FDI_CTX_PRX_P3 <5> CTRL_CLK T45
<5> DMI_CRX_PTX_N2 DMI2TXN FDI_RXP3 L_CTRL_CLK
DMI_CRX_PTX_N3 AV18 BE12 FDI_CTX_PRX_P4 FDI_CTX_PRX_P4 <5> CTRL_DATA P39
DMI
FDI
<5> DMI_CRX_PTX_N3 DMI3TXN FDI_RXP4 L_CTRL_DATA
BG12 FDI_CTX_PRX_P5 FDI_CTX_PRX_P5 <5>
DMI_CRX_PTX_P0 AY24 FDI_RXP5 BJ10 FDI_CTX_PRX_P6 LVDS_IBG AF37 P38
<5> DMI_CRX_PTX_P0 DMI0TXP FDI_RXP6 FDI_CTX_PRX_P6 <5> LVD_IBG SDVO_CTRLCLK PCH_SDVO_CTRLCLK <22>
DMI_CRX_PTX_P1 AY20 BH9 FDI_CTX_PRX_P7 FDI_CTX_PRX_P7 <5>
PAD~D T56 AF36 M39 PCH_SDVO_CTRLDATA <22>
<5> DMI_CRX_PTX_P1 DMI1TXP FDI_RXP7 LVD_VBG SDVO_CTRLDATA
DMI_CRX_PTX_P2 AY18
<5> DMI_CRX_PTX_P2 DMI2TXP
DMI_CRX_PTX_P3 AU18 AE48
<5> DMI_CRX_PTX_P3 DMI3TXP LVD_VREFH
AW16 FDI_INT AE47 AT49
FDI_INT FDI_INT <5> LVD_VREFL DDPB_AUXN AT47
+1.05VS BJ24 AV12 FDI_FSYNC0 DDPB_AUXP AT40 HDMI_DET
DMI_ZCOMP FDI_FSYNC0 FDI_FSYNC0 <5> DDPB_HPD HDMI_DET <22>
LVDS_ACLK- AK39
LVDS
<21> LVDS_ACLK- LVDSA_CLK#
1 2 DMI_IRCOMP BG25 BC10 FDI_FSYNC1 LVDS_ACLK+ AK40 AV42 HDMI_A2N_VGA
DMI_IRCOMP FDI_FSYNC1 FDI_FSYNC1 <5> <21> LVDS_ACLK+ LVDSA_CLK DDPB_0N HDMI_A2N_VGA <22>
RH99 49.9_0402_1% AV40 HDMI_A2P_VGA
DDPB_0P HDMI_A2P_VGA <22>
1 2 RBIAS_CPY BH21 AV14 FDI_LSYNC0 LVDS_A0- AN48 AV45 HDMI_A1N_VGA
RH100 750_0402_1%~D DMI2RBIAS FDI_LSYNC0 FDI_LSYNC0 <5> <21> LVDS_A0-
LVDS_A1- AM47 LVDSA_DATA#0 HDMI DDPB_1N AV46 HDMI_A1P_VGA
HDMI_A1N_VGA <22>
<21> LVDS_A1- LVDSA_DATA#1 HDMI_A1P_VGA <22>
Digital Display Interface

BB10 FDI_LSYNC1 LVDS_A2- AK47 DDPB_1P AU48 HDMI_A0N_VGA
Reserve for ESD 4mil width and place FDI_LSYNC1 FDI_LSYNC1 <5> <21> LVDS_A2- LVDSA_DATA#2 DDPB_2N HDMI_A0N_VGA <22>
AJ48 AU47 HDMI_A0P_VGA
within 500mil of the PCH LVDSA_DATA#3 DDPB_2P HDMI_A0P_VGA <22>
CH105 AV47 HDMI_A3N_VGA
DDPB_3N HDMI_A3N_VGA <22>
2 1 SYS_PWROK_R LVDS_A0+ AN47 AV49 HDMI_A3P_VGA
<21> LVDS_A0+ LVDSA_DATA0 DDPB_3P HDMI_A3P_VGA <22>
A18 DSWODVREN LVDS_A1+ AM49
DSWVRMEN <21> LVDS_A1+ LVDSA_DATA1
0.1U_0402_16V7K LVDS_A2+ AK49
<21> LVDS_A2+ LVDSA_DATA2
AJ47 P46
System Power Management

PAD~D T57 C12 E22 PCH_DPWROK 1 @ 2 PCH_RSMRST#_R LVDSA_DATA3 DDPC_CTRLCLK P42
Please close to PCH SUSACK# DPWROK DDPC_CTRLDATA
0_0402_1%
@ RH128 LVDS_BCLK- AF40
<21> LVDS_BCLK- LVDSB_CLK#
C <6> XDP_DBRESET# XDP_DBRESET# K3 B9 WAKE# 1 2 LVDS_BCLK+ AF39 AP47 C
SYS_RESET# WAKE# PCIE_WAKE# <32,40> <21> LVDS_BCLK+ LVDSB_CLK DDPC_AUXN
RH103 0_0402_5% AP49
LVDS_B0- AH45 DDPC_AUXP AT38
<21> LVDS_B0- LVDSB_DATA#0 DDPC_HPD
SYS_PWROK 1 @ 2 SYS_PWROK_R P12 N3 PM_CLKRUN# LVDS_B1- AH47
SYS_PWROK CLKRUN# / GPIO32 <21> LVDS_B1- LVDSB_DATA#1
RH104 0_0402_1% LVDS_B2- AF49 AY47
<21> LVDS_B2- LVDSB_DATA#2 DDPC_0N
AF45 AY49
1 @ 2 L22 G8 SUS_STAT# T58 PAD~D LVDSB_DATA#3 DDPC_0P AY43
RH105 0_0402_1% PWROK SUS_STAT# / GPIO61 LVDS_B0+ AH43 DDPC_1N AY45
<21> LVDS_B0+ LVDSB_DATA0 DDPC_1P
LVDS_B1+ AH49 BA47
PCH_PWROK 1 @ 2 L10 N14 SUSCLK 1 @ 2
<21> LVDS_B1+
LVDS_B2+ AF47 LVDSB_DATA1 mDP DDPC_2N BA48
APWROK SUSCLK / GPIO62 SUSCLK_R <40> <21> LVDS_B2+ LVDSB_DATA2 DDPC_2P
RH106 0_0402_1% RH107 0_0402_1% AF43 BB47
LVDSB_DATA3 DDPC_3N BB49
PM_DRAM_PWRGD B13 D10 PM_SLP_S5# DDPC_3P
<6> PM_DRAM_PWRGD DRAMPWROK SLP_S5# / GPIO63 PM_SLP_S5# <40>
N48 M43
1 @ 2PCH_RSMRST#_R C21 H4 PM_SLP_S4# P49 CRT_BLUE DDPD_CTRLCLK M36
<40> EC_RSMRST# RSMRST# SLP_S4# PM_SLP_S4# <40> CRT_GREEN DDPD_CTRLDATA
RH108 0_0402_1% T49
CRT_RED
SUSWARN# K16 F4 PM_SLP_S3# AT45
CRT
SUSWARN#/SUSPWRDNACK/GPIO30 SLP_S3# PM_SLP_S3# <40> DDPD_AUXN
Reserve for ESD CRT_DDC_CLK T39 AT43
CRT_DDC_DATA M40 CRT_DDC_CLK DDPD_AUXP BH41
PBTN_OUT# 1 @ 2 E20 G10 CRT_DDC_DATA DDPD_HPD
<40,6> PBTN_OUT# PWRBTN# SLP_A#
1 RH110 0_0402_1% BB43
@ DH4 M47 DDPD_0N BB45
CH103 1 2 AC_PRESENT_R H20 G16 PM_SLP_SUS# T59 PAD~D M49 CRT_HSYNC DDPD_0P BF44
0.1U_0402_16V7K
<25,40,45,46> ACIN ACPRESENT / GPIO31 SLP_SUS# CRT_VSYNC DMC DDPD_1N BE44
2 RB751V-40_SOD323-2 DDPD_1P BF42
GPIO72 E10 AP14 H_PM_SYNC CRT_IREF T43 DDPD_2N BE42
BATLOW# / GPIO72 PMSYNCH H_PM_SYNC <6> DAC_IREF DDPD_2P
T42 BJ42
CRT_IRTN DDPD_3N BG42
Place close to PCH Can be left NC when IAMT is
1
RI# A10 K14 DDPD_3P
RI# SLP_LAN# / GPIO29 not support on the platfrom
If not using integrated BD82HM76-SLJ8E-C1_BGA989~D
LAN,signal may be left as NC. RH115
BD82HM76-SLJ8E-C1_BGA989~D 1K_0402_0.5%
Check EC for S3 S4 LED R1@
2
+3V_PCH
R1@
B GPIO72 RH116 1 2 10K_0402_5% CH29 B
SUSCLK 2 1
RI# RH117 1 2 10K_0402_5% @
+RTCVCC 10P_0402_50V8J
PCIE_WAKE# RH118 1 @ 2 10K_0402_5%
AC_PRESENT_R RH121 1 2 200K_0402_5% DSWODVREN RH119 2 1 330K_0402_5% Reserve for RF please close to UH1 1 2 PM_CLKRUN#
RH120 10K_0402_5%
SUSWARN# RH124 1 2 10K_0402_5% DSWODVREN RH122 2 @ 1 330K_0402_5% 1 2 LVDS_IBG
RH123 2.37K_0402_1%
WAKE# RH126 1 2 10K_0402_5% +3VS 1 2 PCH_ENVDD
DSWODVREN - On Die DSW VR Enable RH132 100K_0402_5%
EC_RSMRST# RH127 1 2 10K_0402_5%

* H：Enable
L：Disable RH134
1 2
100K_0402_5%
ENBKL
1 2 CTRL_CLK
RH133 2.2K_0402_5%
1 2 CTRL_DATA
RH135 2.2K_0402_5%
1 2 PM_CLKRUN#
+3VS RH136 @ 8.2K_0402_5%
1 2 LVDS_DDC_CLK
RH137 2.2K_0402_5%
1 1 2 LVDS_DDC_DATA
RH138 2.2K_0402_5%
CH30 1 2 PCH_SDVO_CTRLCLK
0.1U_0402_16V7K RH233 2.2K_0402_5%
2 1 2 PCH_SDVO_CTRLDATA
RH234 2.2K_0402_5%
5
UH3 1 @ 2 CRT_DDC_CLK
RH238 2.2K_0402_5%
VCC
PCH_PWROK 1 1 @ 2 CRT_DDC_DATA
<40,6> PCH_PWROK IN1 4 SYS_PWROK RH239 2.2K_0402_5%
OUT SYS_PWROK <6>
2
GND
<52,6> VGATE IN2
MC74VHC1G08DFT2G_SC70-5
3
A A

Deciphered Date
PCH (3/8) DMI/FDI/PM/GFX/DP
1.0
LA-9102P
5 4 3 2 1
5 4 3 2 1
+3VS
RH129 1 2 8.2K_0402_5% PCI_PIRQA# UH1E

AY7
RH130 1 2 8.2K_0402_5% PCI_PIRQD# RSVD1 AV7
BG26 RSVD2 AU3
D D
RH131 1 2 8.2K_0402_5% PCI_PIRQB# BJ26 TP1 RSVD3 BG4
BH25 TP2 RSVD4
RH141 1 2 8.2K_0402_5% PCI_PIRQC# BJ16 TP3 AT10
BG16 TP4 RSVD5 BC8
RH142 1 2 8.2K_0402_5% GPIO51 AH38 TP5 RSVD6
AH37 TP6 AU2
RH146 1 2 8.2K_0402_5% GPIO5 AK43 TP7 RSVD7 AT4
AK45 TP8 RSVD8 AT3
RH147 1 2 8.2K_0402_5% GPIO52 C18 TP9 RSVD9 AT1
N30 TP10 RSVD10 AY3
RH148 1 2 8.2K_0402_5% WL_OFF# H3 TP11 RSVD11 AT5
TP12 RSVD12
Intel Anti-Theft Techonlogy
AH12 AV3
RH151 1 2 8.2K_0402_5% ODD_DA# AM4 TP13 RSVD13 AV1
TP14 RSVD14 High=Endabled
AM5 BB1 NV_ALE
RH153 1 2 8.2K_0402_5% GPIO4 Y13 TP15 RSVD15 BA3 Low=Disable(floating)
K24 TP16
TP17
RSVD16
RSVD17
BB5 *
RH154 1 2 8.2K_0402_5% PXS_PWREN L24 BB3
AB46 TP18 RSVD18 BB7
AB45 TP19 RSVD19 BE8
RSVD
TP20 RSVD20 BD4
RSVD21 BF6 +1.8VS
+3VS RSVD22
B21 AV5 NV_ALE @ RH139 1 2 1K_0402_5%
M20 TP21 RSVD23 AV10
AY16 TP22 RSVD24
RH140 2 1 10K_0402_5% DGPU_HOLD_RST# BG46 TP23 AT8
TP24 RSVD25
AY5
RSVD26 BA2
USB3RN1_JUSB2 BE28 RSVD27
<36> USB3RN1_JUSB2 TP25
USB3RN2_JUSB1 BC30 AT12 SSI:
<36> USB3RN2_JUSB1 TP26 RSVD28
BE32 BF3
BJ32 TP27 RSVD29 Port 0 USB Conn 1
USB3RP1_JUSB2 BC28 TP28
<36> USB3RP1_JUSB2
USB3RP2_JUSB1 BE30 TP29 Port 1 USB Conn 4 (DB)
<36> USB3RP2_JUSB1 TP30
SSI: PT: BF32 Port 2 USB Conn 2
BG32 TP31 C24 USB20_JUSB2_N0
C
Port 1 USB Conn 1 Port 1 USB Conn JUSB2 AV26 TP32 USBP0N A24
USB20_JUSB2_N0 <36> Port 3 USB Conn 3 C
<36> USB3TN1_JUSB2
USB3TN1_JUSB2
BB26 TP33 USBP0P C25
USB20_JUSB2_P0
USB20_JUSB2_P0 <36> USB Conn JUSB2 Port 4 Mini Card (WLAN)
Port 2 USB Conn 2 Port 2 USB Conn JUSB1 USB3TN2_JUSB1 USB20_JUSB1_N1
<36> USB3TN2_JUSB1 TP34 USBP1N USB20_JUSB1_N1 <36>
AU28 B25 USB20_JUSB1_P1 USB Conn JUSB1
Port 3 USB Conn 3 Port 3 Cancel AY30 TP35 USBP1P C26 USB20_JUSB3_N2
USB20_JUSB1_P1 <36> Port 6 Card Reader
TP36 USBP2N USB20_JUSB3_N2 <37>
<36> USB3TP1_JUSB2
USB3TP1_JUSB2 AU26 A26 USB20_JUSB3_P2
USB20_JUSB3_P2 <37> USB Conn JUSB3 Port 12 Camera
USB3TP2_JUSB1 AY26 TP37 USBP2P K28 USB20_USBDB_N3
<36> USB3TP2_JUSB1 TP38 USBP3N USB20_USBDB_N3 <37>
AV28 H28 USB20_USBDB_P3 USB Conn 4 (DB)
TP39 USBP3P USB20_USBDB_P3 <37>
AW30 E28
TP40 USBP4N D28
USBP4P C28
PT:
USBP5N A28 Port 0 USB Conn JUSB2
USBP5P C29
USBP6N B29
Port 1 USB Conn JUSB1
PCI_PIRQA# K40 USBP6P N28 Port 2 USB Conn JUSB3
PCI_PIRQB# K38 PIRQA# USBP7N M28 Port 3 USB Conn 4 (DB)
PCI
PCI_PIRQC# H38 PIRQB# USBP7P L30 USB20_MINI1_N8
PIRQC# USBP8N USB20_MINI1_N8 <38>
PCI_PIRQD# G38 K30 USB20_MINI1_P8
USB20_MINI1_P8 <38> Mini Card (WLAN) Port 8 Mini Card (WLAN)
PIRQD# USBP8P G30 USB20_TOUCH_N9
DGPU_HOLD_RST#C46
USBP9N E30
USB20_TOUCH_N9 <41> Port 9 Touch panel
USB20_TOUCH_P9 Touch panel
USB
<24> DGPU_HOLD_RST# REQ1# / GPIO50 USBP9P USB20_TOUCH_P9 <41>
GPIO52 C44 C30 USB20_CR_N10
USB20_CR_N10 <34>
Port 10 Card Reader
E40 REQ2# / GPIO52 USBP10N A30
<26,53> PXS_PWREN
PXS_PWREN
REQ3# / GPIO54 USBP10P L32
USB20_CR_P10
USB20_CR_P10 <34> Card Reader Port 11 Camera
USB20_CAM_N11
USBP11N USB20_CAM_N11 <21>
GPIO51 D47 K32 USB20_CAM_P11 Camera
GNT1# / GPIO51 USBP11P USB20_CAM_P11 <21>
E42 G32
WL_OFF# F46 GNT2# / GPIO53 USBP12N E32
<38> WL_OFF# GNT3# / GPIO55 USBP12P C32
USBP13N A32
G42 USBP13P
G40 PIRQE# / GPIO2
Reserve for ESD <41> ODD_DA# ODD_DA#
C42 PIRQF# / GPIO3 C33
Within
1
500 2mils
GPIO4 USBRBIAS
CH104 GPIO5 D44 PIRQG# / GPIO4 USBRBIAS# RH143 22.6_0402_1%
2 1 PCH_PLTRST# PIRQH# / GPIO5 +3V_PCH
B33
0.1U_0402_16V7K PAD~D T60 @ K10 USBRBIAS
PME#
Please close to PCH PCH_PLTRST# C6 A14 USB_OC0# USB_OC0# 10K_0402_5% 2 1 RH156
<24> PCH_PLTRST# PLTRST# OC0# / GPIO59 USB_OC0# <36>
B K20 USB_OC1# B
OC1# / GPIO40 USB_OC1# <36>
B17 USB_OC2# USB_OC1# 10K_0402_5% 2 1 RH158
OC2# / GPIO41 USB_OC2# <37>
CLK_PCI_LPBACK RH144 2 1 22_0402_5% CLK_PCI0 H49 C16 USB_OC3#
<14> CLK_PCI_LPBACK CLKOUT_PCI0 OC3# / GPIO42 USB_OC3# <37>
CLK_PCI_LPC RH145 1 2 22_0402_5% CLK_PCI1 H43 L16 USB_OC4# USB_OC2# 10K_0402_5% 2 1 RH160
<40> CLK_PCI_LPC CLKOUT_PCI1 OC4# / GPIO43
PAD~D T61 @ CLK_PCI2 J48 A16 USB_OC5#
PAD~D T62 @ CLK_PCI3 K42 CLKOUT_PCI2 OC5# / GPIO9 D14 USB_OC6# USB_OC3# 10K_0402_5% 2 1 RH166
PAD~D T63 @ CLK_PCI4 H40 CLKOUT_PCI3 OC6# / GPIO10 C14 USB_OC7#
CLKOUT_PCI4 OC7# / GPIO14 USB_OC6# 10K_0402_5% 2 1 RH167
CH31
2 1 CLK_PCI1 BD82HM76-SLJ8E-C1_BGA989~D USB_OC5# 10K_0402_5% 2 1 RH170
@ R1@
10P_0402_50V8J USB_OC4# 10K_0402_5% 2 1 RH189
Reserve for RF please close to PCH USB_OC7# 10K_0402_5% 2 1 RH211
+3VS 1 @ 2
RH149 0_0402_5%
2
@ +3VS
RH150 CH101
10K_0402_5% 1 2
0.1U_0402_25V6K
5
UH5
1
1 PCH_PLTRST#
P
4 IN1
<32,38,40,6> PLT_RST# O 2
G
IN2
1
SN74AHC1G08DCKR_SC70-5
3
RH155
100K_0402_5% RH157
@ 10K_0402_5%
2
A A

Deciphered Date
PCH (4/8) PCI/USB/NVRAM
1.0
LA-9102P
5 4 3 2 1
5 4 3 2 1
UH1F
+3V_PCH
D D
T7 C40 ODD_EN#
BMBUSY# / GPIO0 TACH4 / GPIO68 ODD_EN# <41>
GPIO1 A42 B41 GPIO69 @ T64 PAD~D
2 1 PCH_LID_SW_IN# TACH1 / GPIO1 TACH5 / GPIO69
RH240 1K_0402_5% GPIO6 H36 C41 +3VS
TACH2 / GPIO6 TACH6 / GPIO70
2 1 PCH_GPIO28 <40> EC_SCI# EC_SCI# E38 A40
TACH3 / GPIO7 TACH7 / GPIO71
2
RH241 10K_0402_5%
<40> EC_SMI# EC_SMI# C10 RH159
GPIO8
10K_0402_5%
C4
LAN_PHY_PWR_CTRL / GPIO12
1
EC_LID_OUT# 1 @ 2 PCH_LID_SW_IN# G2 P4
<40> EC_LID_OUT# GPIO15 A20GATE GATEA20 <40>
RH73 0_0402_1%
AU16 PCH_PECI_R PCH_PECI_R 1 @ 2
PECI H_PECI <40,6>
GPIO16 U2 0_0402_5% RH161
SATA4GP / GPIO16 P5 KB_RST#
RCIN# KB_RST# <40>
GPIO
<53> VGA_PWRGD VGA_PWRGD D40 AY11 1
H_CPUPWRGD <6>
CPU/MISC
TACH0 / GPIO17 PROCPWRGD @
+3V_PCH +3VS +3VS PCH_GPIO22 T5 AY10 H_THERMTRIP#_C 1 2 H_THERMTRIP# CH102
SCLOCK / GPIO22 THRMTRIP# H_THERMTRIP# <6>
390_0402_5% RH162 0.1U_0402_10V7K~D
KB_DET# E8 T14 INIT3_3V# 2
KB_DET# GPIO24 / MEM_LED INIT3_3V#
1
Place CH102 close to RH161

@ @ @ PCH_GPIO27 E16 AY1 DF_TVS
RH244 RH182 RH181 GPIO27 DF_TVS & PCH.
1
10K_0402_5% 10K_0402_5% 10K_0402_5% PCH_GPIO28 P8 @
GPIO28 AH8 RH163
2
PCH_GPIO57 PCH_GPIO39 PCH_GPIO38 BT_ON# K1 TS_VSS1

<38> BT_ON# 10K_0402_5%
STP_PCI# / GPIO34 AK11
1
GPIO35 K4 TS_VSS2
GPIO35
2
@ @ @ AH10 INIT3_3V
RH179 RH202 RH225 ODD_DETECT# V8 TS_VSS3
<41> ODD_DETECT# SATA2GP / GPIO36
10K_0402_5% 10K_0402_5% 10K_0402_5% AK10 This signal has weak internal
PCH_GPIO37 M5 TS_VSS4
SATA3GP / GPIO37 PU, can't pull low
2
C PCH_GPIO38 N2 P37 C
SLOAD / GPIO38 NC_1
PCH_GPIO39 M3
SDATAOUT0 / GPIO39
PCH_GPIO48 V13 BG2
System ID SDATAOUT1 / GPIO48 VSS_NCTF_15
PCH_GPIO57 PCH_GPIO39 PCH_GPIO38 GPIO49 V3 BG48
SATA5GP / GPIO49 VSS_NCTF_16
LOW VAW00 15'' INSPIRON Entry PCH_GPIO57 D6 BH3
GPIO57 VSS_NCTF_17
PLACE RH150 CLOSE TO THE BRANCHING POINT
HIGH VAW10 17'' VOSTRO Mainstream BH47 ( TO CPU and NVRAM CONNECTOR)
VSS_NCTF_18
Due to remove VCCDFERM
A4 BJ4
VSS_NCTF_1 VSS_NCTF_19 jumper(PJP66), need to
A44 BJ44 change the power rail to +1.8VS
VSS_NCTF_2 VSS_NCTF_20
A45 BJ45
+1.8V_RUN for D12" only
VSS_NCTF_3 VSS_NCTF_21 RH149 need to close to CPU
NCTF
1
A46 BJ46
VSS_NCTF_4 VSS_NCTF_22 RH152
A5 BJ5 2.2K_0402_5%
+3VS A6 BJ6
2
1 2 DF_TVS
<6> H_SNB_IVB#
B3 C2 RH358 1K_0402_1%
B47 C48
10K_0402_5% 2 RH164 1 GPIO1 BD1 D1
BD49 D49
DMI & FDI Termination Voltage
BE1 E1
BE49 E49 Set to Vss when LOW
DF_TVS
GPIO28 BF1 F1 Set to Vcc when HIGH
B On-Die PLL Voltage Regulator B
This signal has a weak internal pull up BF49 F49
H：On-Die voltage regulator enable
* L：On-Die PLL Voltage Regulator disable BD82HM76-SLJ8E-C1_BGA989~D
R1@
1 2 PCH_GPIO28 +3VS
@ RH165 1K_0402_5%
ODD_DETECT# 1 2 200K_0402_5%
RH171
GPIO16 1 2 10K_0402_5%
RH172
BT_ON# 1 2 8.2K_0402_5%
PCH_GPIO37 1 2 PCH_GPIO27 RH174
FDI TERMINATION VOLTAGE OVERRIDE @ RH173 10K_0402_5% KB_RST# 1 2 10K_0402_5%
RH175
LOW - Tx, Rx terminated +3V_PCH VGA_PWRGD 1 2 10K_0402_5%
* to same voltage RH242
PCH_GPIO22 1 2 10K_0402_5%
(DC Coupling Mode) RH176
+3VS GPIO35 1 2 10K_0402_5%

RH177
PCH_GPIO28 needs to be connected to XDP_FN8
RH168 2 @ 1 1K_0402_5% PCH_GPIO37 GPIO49 1 2 10K_0402_5%
PCH_GPIO35 needs to be connected to XDP_FN9 RH180
PCH_GPIO15 needs to be connected to XDP_FN16
RH169 1 2 PCH_GPIO37
10K_0402_5% GPIO6 1 2 10K_0402_5%
Please refer to Huron River Debug Board DG 0.5 RH184
EC_SMI# 1 2 10K_0402_5%
RH183
PCH_GPIO48 1 2 10K_0402_5%
RH245
A ODD_EN# 1 2 10K_0402_5% A
RH178

Deciphered Date
PCH (5/8) GPIO/CPU/MISC
1.0
LA-9102P
5 4 3 2 1
5 4 3 2 1
Reserve for LVDS issue
+VCCA_LVDS
D D
1
CH106 @
1U_0402_6.3V6K
2
+1.05VS
PCH Power Rail Table
UH1G POWER +3VS S0 Iccmax
Voltage Rail Voltage Current (A)
1300mA LH1
AA23 U48 +VCCADAC 2 1
0.01U_0402_16V7K
0.1U_0402_10V7K~D
AC23 VCCCORE[1] 1mA VCCADAC 4.7UH_LQM18FN4R7M00D_20%
VCCCORE[2] 1 1 1 V_PROC_IO 1.05 0.001
CRT
AD21
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1 1 1 1
10U_0805_4VAM~D
AD23 VCCCORE[3] U47 CH34
CH32
CH33
AF21 VCCCORE[4] VSSADAC 10U_0805_4VAM~D
CH35
CH36
CH37
CH38
VCC CORE
VCCCORE[5] V5REF 5 0.001
AF23 2 2 2
2 2 2 2 AG21 VCCCORE[6] +3VS
AG23 VCCCORE[7] RH185
VCCCORE[8]
V5REF_Sus 5 0.001
AG24 AK36 +VCCA_LVDS 1 @ 2
AG26 VCCCORE[9] 1mA VCCALVDS
AG27 VCCCORE[10] AK37 0_0805_1% +1.8VS
VCCCORE[11] VSSALVDS Vcc3_3 3.3 0.266
AG29
AJ23 VCCCORE[12] LH2
Near AP43
LVDS
AJ26 VCCCORE[13] AM37 +VCCTX_LVDS CH41 2 1
VCCCORE[14] VCCTX_LVDS[1]
VccADAC 3.3 0.001
AJ27 CH39 1 1 1 0.1UH_MLF1608DR10KT_10%_1608
+1.05VS AJ29 VCCCORE[15] AM38 0.01U_0402_16V7K 22U_0805_6.3V6M 0.1uH inductor, 200mA
AJ31 VCCCORE[16] VCCTX_LVDS[2] CH40
VCCCORE[17] VccADPLLA 1.05 0.08
AP36 0.01U_0402_16V7K
60mA VCCTX_LVDS[3] 2 2 2
AP37 VccADPLLB 1.05 0.08
+1.05VS RH186 1 @ 2 0_0603_1% +1.05VS_VCCDPLLEXP AN19 VCCTX_LVDS[4]
VCCIO[28]
@ @ LH3 VccCore 1.05 1.3
2 1+VCCAPLLEXP_R 1 2 +VCCAPLLEXP BJ22
RH187 0_0603_5%~D 1UH_LB2012T1R0M_20%~D VCCAPLLEXP RH188
C C
1 V33 +3VS_VCC3_3_6 1 @ 2 VccDMI 1.05 0.042
10U_0805_4VAM~D
+3VS
HVCMOS
AN16 VCC3_3[6]
VCCIO[15] 0_0805_1%
Place CH40 Near BJ22 pin
CH42
1
AN17 VccIO 1.05 2.925
2@ VCCIO[16] V34 CH43
+1.05VS VCC3_3[7]
0.1U_0402_10V7K~D
AN21 2 VccASW 1.05 1.01
VCCIO[17]
AN26
VCCIO[18]
VccSPI 3.3 0.02
AN27 2925mA AT16 +VCCAFDI_VRM
VCCIO[19] VCCVRM[3]
AP21 +VCCP_VCCDMI +VCCP VccDSW 3.3 0.003
VCCIO[20] RH190
@
AP23 AT20 +VCCP_VCCDMI 1 2
VCCIO[21] VCCDMI[1]
1 VccpNAND 1.8 0.19
DMI
AP24 0_0805_1%
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1 1 1 1 1
10U_0805_4VAM~D
RH191
VCCIO
+3VS VCCIO[22] @ CH44
AP26 AB36 +1.05VS_VCC_DMI_CCI 1 2
CH45
CH46
CH47
CH48
CH49
VCCIO[23] 20mA VCCCLKDMI +1.05VS VccRTC 3.3 6 uA

2 1U_0402_6.3V6K
1
2 2 2 2 2 AT24 0_0805_1%
VCCIO[24] CH50 VccSus3_3 3.3 0.119
1
1U_0402_6.3V6K
RH192 AN33 2
VCCIO[25]
0_0805_1% @ VccSusHDA 3.3 / 1.5 0.01
AN34 AG16
VCCIO[26] VCCDFTERM[1] +VCCPNAND
RH193
2
@ 0_0805_1% VccVRM 1.8 / 1.5 0.16

+3VS_VCCA3GBG BH29 AG17 1 2 +1.8VS
190mA VCCDFTERM[2]
DFT / SPI
VCC3_3[3]
1
CH51 VccCLKDMI 1.05 0.02
0.1U_0402_10V7K~D
+1.05VS AJ16 1
0.1U_0402_10V7K~D VCCDFTERM[3]
2 +VCCAFDI_VRM AP16
CH52
VCCVRM[2] VccSSC 1.05 0.095
AJ17
@ VCCDFTERM[4] 2
Place CH53 Near BG6 pin
B 2 1 +1.05VS_VCCAPLL_FDI BG6 VccDIFFCLKN 1.05 0.055 B
RH194 0_0603_5%~D VccAFDIPLL
RH195
@
1U_0402_6.3V6K
1
+1.05VS
1 2+1.05VS_VCCDPLL_FDI AP17 @ VccALVDS 3.3 0.001
VCCIO[27]
FDI
0_0805_1% V1 +3V_VCCPSPI 1 2
CH53
20mA VCCSPI +3V_PCH

RH196 0_0805_1%
2@ AU20 VccTX_LVDS 1.8 0.06
+VCCP_VCCDMI VCCDMI[2] @
2 1 +3VS
BD82HM76-SLJ8E-C1_BGA989~D 1 RH243 0_0603_5%~D
CH54
R1@ 1U_0402_6.3V6K
2
+1.5VS +VCCAFDI_VRM
@ RH197
1 2 +VCCAFDI_VRM
0_0603_1% 1
CH100
1U_0402_6.3V6K
2
A A

Deciphered Date
PCH (6/8) PWR
1.0
LA-9102P
Date: Wednesday, September 26, 2012 Sheet 18 of 57
5 4 3 2 1
5 4 3 2 1
+1.05VS
VCC3_3 = 266mA detal waiting for newest spec
@ VCCDMI = 42mA detal waiting for newest spec
2 1 +VCCACLK
+3V_PCH RH198 0_0603_5%~D +5VALW QH5 +5V_PCH
UH1J POWER AO3419L_SOT23-3
D
D 1 @ 2 0_0603_1% 1 @ 2 3 1 D
RH199 1 AD49 N26 +1.05VS_VCCUSBCORE 1 @ 2 RH201 0_0603_1%
0.1U_0402_10V7K~D
VCCACLK VCCIO[29] +1.05VS
RH200 0_0603_1%
20K_0402_5%
1
CH55 P26 1 1
0.1U_0402_10V7K~D +VCCPDSW T16 VCCIO[30]
RH203
2 VCCDSW3_3 3mA P28 CH56
CH57
VCCIO[31] 1U_0402_6.3V6K
G
+PCH_VCCDSW V12 T27 2 2
DCPSUSBYP VCCIO[32]
2
+1.05VS @ LH4 1 <35> PCH_PWR_EN#
@ RH204 10UH_LBR2012T100M_20% T29
1 2 +VCCAPLL_CPY 1 2 @ CH58 +3VS_VCC_CLKF33 T38 VCCIO[33]
0.1U_0402_10V7K~D VCC3_3[5]
2
10U_0805_10V6K
0_0805_5% @ 1 T23 +3V_VCCPUSB 1 @ 2 +3V_PCH
+1.05VS +VCCAPLL_CPY_PCH BH23 119mA VCCSUS3_3[7] RH205 0_0603_1%
0.1U_0402_10V7K~D
VCCAPLLDMI2
CH59
T24 1 +3V_VCCAUBG 1 @ 2 +3V_PCH
1 @ 2 0_0603_1% +VCCDPLL_CPY AL29 VCCSUS3_3[8] RH206 0_0603_1% +5V_PCH +3V_PCH
0.1U_0402_10V7K~D
2 RH207 VCCIO[14] V23
CH60
1
USB
VCCSUS3_3[9]
2
+VCCSUS1 AL24 V24 2 +VCCA_USBSUS
CH61
DCPSUS[3] VCCSUS3_3[10] RH208 DH2
1U_0402_6.3V6K
1
@ P24 2 100_0402_1% RB751S40T1_SOD523-2~D
VCCSUS3_3[6] 1
CH62
@
1U_0402_6.3V6K AA19
CH63
1
2 VCCASW[1] T26 +1.05VS_VCCAUPLL 1 @ 2 +PCH_V5REF_SUS
VCCIO[34] +1.05VS
AA21 1010mA RH209 0_0603_1% 2
VCCASW[2] 1
AA24 M26 +PCH_V5REF_SUS CH64
VCCASW[3] 1mA V5REF_SUS 1 @ 2 0.1U_0603_25V7K
22U_0805_6.3V6M
22U_0805_6.3V6M
1 1 +3V_PCH
Clock and Miscellaneous

AA26 RH210 0_0603_1% 2
0.1U_0402_10V7K~D
VCCASW[4] AN23 +VCCA_USBSUS
CH65
CH66
DCPSUS[4] 1
AA27
2 2 VCCASW[5] AN24 +3V_VCCPSUS_1
CH67
AA29 VCCSUS3_3[1]
VCCASW[6] 2
+1.05VS AA31 +5VS +3VS
VCCASW[7]
AC26 P34 +PCH_V5REF_RUN
2
VCCASW[8] 1mA V5REF
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
C 1 1 1 C
AC27 RH212 DH3
VCCASW[9] N20 +3V_VCCPSUS 1 @ 2 100_0402_1%
CH68
CH69
CH70
+3V_PCH RB751S40T1_SOD523-2~D
VCCSUS3_3[2]
PCI/GPIO/LPC
AC29 1 RH213 0_0603_1%
+3VS 2 2 2 VCCASW[10] N22
VCCSUS3_3[3]
1
AC31 CH71 +PCH_V5REF_RUN
VCCASW[11] P20 1U_0402_6.3V6K +3VS
VCCSUS3_3[4] 1
AD29 2 @
@ VCCASW[12] P22 +3VS_VCCPCORE 1 2 CH72
1 2 AD31 VCCSUS3_3[5] RH214 0_0805_1% 1U_0603_10V6K
VCCASW[13] 1
RH215 0_0805_1% 2
W21 AA16 CH73
LH5 VCCASW[14] VCC3_3[1] 0.1U_0402_10V7K~D
10UH_LBR2012T100M_20% W23 W16 2 +3VS
1 2 +3VS_VCC_CLKF33 VCCASW[15] VCC3_3[8]
W24 T34 +3VS_VCCPPCI 1 @ 2
10U_0805_10V6K
1U_0402_6.3V6K
1 1 VCCASW[16] VCC3_3[4]
@ 1 RH216 0_0603_1%
W26
CH74
CH75
VCCASW[17] CH76
2 2 W29 +3VS 0.1U_0402_10V7K~D
VCCASW[18] RH217 2
W31 AJ2 +VCC3_3_2 1 2
VCCASW[19] VCC3_3[2] @ 0_0603_1% +1.05VS_SATA3
1
W33 @
VCCASW[20] AF13 CH77 1 2
VCCIO[5] +1.05VS
0.1U_0402_10V7K~D 1 RH218 0_0805_1%
+1.05VS +VCCRTCEXT N16 2
@ DCPRTC AH13 CH78
1 VCCIO[12]
2 1 +1.05VM_VCCSUS 1U_0402_6.3V6K
RH219 0_0603_5%~D CH79 +VCCAFDI_VRM Y49 AH14 +1.05VS_SATA3 2
0.1U_0402_10V7K~D VCCVRM[4] VCCIO[13]
2
+1.05VS AF14 @ LH6 @
+1.05VS_VCCA_A_DPL BD47 VCCIO[6] 10UH_LBR2012T100M_20% RH221
SATA
1 @ 2 +VCCDIFFCLK VCCADPLLA 80mA AK1 +VCCSATAPLL 1 2 +VCCSATAPLL_R 2 1
VCCAPLLSATA +1.05VS
RH220 0_0603_1% +1.05VS_VCCA_B_DPL BF47 +VCCAFDI_VRM
VCCADPLLB 80mA 0_0805_5%
1 1
B CH80 AF11 +VCCAFDI_VRM @ CH81 B
AF17 VCCVRM[1] +1.05VS_VCC_SATA 10U_0805_10V6K
+1.05VS 1U_0402_6.3V6K +1.05VS_VCCDIFFCLKN AF33 VCCIO[7] RH222
2 AF34 VCCDIFFCLKN[1] AC16 +1.05VS_VCC_SATA 1 2 2
1 @ 2 +1.05VS_VCCDIFFCLKN AG34 VCCDIFFCLKN[2] 55mA VCCIO[2] @
+1.05VS
0_0805_1%
RH223 0_0603_1% 1 VCCDIFFCLKN[3] AC17
1U_0402_6.3V6K
VCCIO[3] 1
CH82 +1.05VS_SSCVCC AG33 AD17
CH83
1U_0402_6.3V6K VCCSSC 95mA VCCIO[4]
+1.05VS 2 2
+VCCSST V16 +1.05VS
1 @ 2 DCPSST
RH224 0_0603_1% 1 1 +1.05VM_VCCSUS
CH85 1 T17 T21
CH84 0.1U_0402_10V7K~D @ V19 DCPSUS[1] VCCASW[22]
DCPSUS[2]
MISC
+VCCP 1U_0402_6.3V6K CH86

2 2 1U_0402_6.3V6K V21
2 VCCASW[23]
CPU
1 @ 2 +V_CPU_IO BJ8
0.1U_0402_10V7K~D
0.1U_0402_10V7K~D
RH227 0_0603_1% V_PROC_IO 1mA T19

1 1 1 VCCASW[21]
CH87 +RTCVCC
CH88
CH89
4.7U_0603_6.3V6K
2 2 2
RTC
A22 P32 +VCCSUSHDA 1 @ 2 +3V_PCH If it support 3.3V audio signals

HDA
VCCRTC 10mA VCCSUSHDA RH229 0_0603_1%

1U_0402_6.3V6K
0.1U_0402_10V7K~D
0.1U_0402_10V7K~D
POP:RH244
1 1 1 1 Depop RH245 / RH246
LH7 BD82HM76-SLJ8E-C1_BGA989~D
150_0402_1%
1
10UH_LBR2012T100M_20% 0.1U_0402_10V7K~D CH93
CH90
CH91
CH92
1 2 +1.05VS_VCCA_A_DPL If it support 1.5V audio signals

+1.05VS 2 2 2 R1@ 2 @
RH231
POP:RH245 / RH246
@
1 2 +VCCA_DPLL_L 1 2 +1.05VS_VCCA_B_DPL Depop R244
2
RH232 0_0805_1% LH8
220U_B2_2.5VM_R35
220U_B2_2.5VM_R35
10UH_LBR2012T100M_20%
1U_0402_6.3V6K
1U_0402_6.3V6K
1 1
CH95
1 1
CH94
+ +
CH96
CH97
A A
2 2 2 2

Deciphered Date
PCH (7/8) PWR
1.0
LA-9102P
5 4 3 2 1
5 4 3 2 1
UH1I
AY4 H46
AY42 VSS[159] VSS[259] K18
AY46 VSS[160] VSS[260] K26
AY8 VSS[161] VSS[261] K39
UH1H B11 VSS[162] VSS[262] K46
H5 B15 VSS[163] VSS[263] K7
VSS[0] B19 VSS[164] VSS[264] L18
D D
AA17 AK38 B23 VSS[165] VSS[265] L2
AA2 VSS[1] VSS[80] AK4 B27 VSS[166] VSS[266] L20
AB11 VSS[5] VSS[84] AL16 B7 VSS[170] VSS[270] L48
AB14 VSS[6] VSS[85] AL17 F45 VSS[171] VSS[271] M12
AB39 VSS[7] VSS[86] AL19 BB12 VSS[172] VSS[272] P16
AB4 VSS[8] VSS[87] AL2 BB16 VSS[173] VSS[273] M18
AC19 VSS[12] VSS[91] AL27 BB28 VSS[177] VSS[277] M32
AC34 VSS[17] VSS[96] AM11 BC14 VSS[182] VSS[282] M46
AC48 VSS[18] VSS[97] AM14 BC18 VSS[183] VSS[283] M8
AD10 VSS[19] VSS[98] AM36 BC2 VSS[184] VSS[284] N18
AD11 VSS[20] VSS[99] AM39 BC22 VSS[185] VSS[285] P30
AD12 VSS[21] VSS[100] AM43 BC26 VSS[186] VSS[286] N47
AD24 VSS[24] VSS[103] AM7 BC36 VSS[189] VSS[289] T33
AD26 VSS[25] VSS[104] AN2 BC40 VSS[190] VSS[290] P40
AD34 VSS[28] VSS[107] AN31 BD46 VSS[193] VSS[293] P7
AD36 VSS[29] VSS[108] AP12 BD5 VSS[194] VSS[294] R2
AD37 VSS[30] VSS[109] AP19 BE22 VSS[195] VSS[295] R48
AD38 VSS[31] VSS[110] AP28 BE26 VSS[196] VSS[296] T12
AD39 VSS[32] VSS[111] AP30 BE40 VSS[197] VSS[297] T31
AD4 VSS[33] VSS[112] AP32 BF10 VSS[198] VSS[298] T37
AD42 VSS[35] VSS[114] AP4 BF16 VSS[200] VSS[300] W34
C C
AD8 VSS[39] VSS[118] AR2 BF26 VSS[204] VSS[304] V11
AE2 VSS[40] VSS[119] AR48 BF28 VSS[205] VSS[305] V17
AE3 VSS[41] VSS[120] AT11 BD3 VSS[206] VSS[306] V26
AF10 VSS[42] VSS[121] AT13 BF30 VSS[207] VSS[307] V27
AF12 VSS[43] VSS[122] AT18 BF38 VSS[208] VSS[308] V29
AD14 VSS[44] VSS[123] AT22 BF40 VSS[209] VSS[309] V31
AD16 VSS[45] VSS[124] AT26 BF8 VSS[210] VSS[310] V36
AF16 VSS[46] VSS[125] AT28 BG17 VSS[211] VSS[311] V39
AF26 VSS[49] VSS[128] AT34 BG44 VSS[214] VSS[314] W17
AF27 VSS[50] VSS[129] AT39 BG8 VSS[215] VSS[315] W19
AF29 VSS[51] VSS[130] AT42 BH11 VSS[216] VSS[316] W2
AF4 VSS[54] VSS[133] AU24 BH19 VSS[219] VSS[319] Y12
AF42 VSS[55] VSS[134] AU30 H10 VSS[220] VSS[320] Y38
AF46 VSS[56] VSS[135] AV16 BH27 VSS[221] VSS[321] Y4
AG19 VSS[60] VSS[139] AV38 BH39 VSS[225] VSS[325] BG29
AG2 VSS[61] VSS[140] AV4 BH43 VSS[226] VSS[328] N24
AG31 VSS[62] VSS[141] AV43 BH7 VSS[227] VSS[329] AJ3
AG48 VSS[63] VSS[142] AV8 D3 VSS[228] VSS[330] AD47
AH11 VSS[64] VSS[143] AW14 D12 VSS[229] VSS[331] B43
AH3 VSS[65] VSS[144] AW18 D16 VSS[230] VSS[333] BE10
AH36 VSS[66] VSS[145] AW2 D18 VSS[231] VSS[334] BG41
AH39 VSS[67] VSS[146] AW22 D22 VSS[232] VSS[335] G14
AH40 VSS[68] VSS[147] AW26 D24 VSS[233] VSS[337] H16
AH42 VSS[69] VSS[148] AW28 D26 VSS[234] VSS[338] T36
AJ19 VSS[72] VSS[151] AW36 D34 VSS[237] VSS[343] C22
AJ21 VSS[73] VSS[152] AW40 D38 VSS[238] VSS[344] AP13
B B
AJ24 VSS[74] VSS[153] AW48 D42 VSS[239] VSS[345] M14
AJ33 VSS[75] VSS[154] AV11 D8 VSS[240] VSS[346] AP3
AJ34 VSS[76] VSS[155] AY12 E18 VSS[241] VSS[347] AP1
AK12 VSS[77] VSS[156] AY22 E26 VSS[242] VSS[348] BE16
AK3 VSS[78] VSS[157] AY28 G18 VSS[243] VSS[349] BC16
VSS[79] VSS[158] G20 VSS[244] VSS[350] BG28
BD82HM76-SLJ8E-C1_BGA989~D G26 VSS[245] VSS[351] BJ28
G28 VSS[246] VSS[352]
G36 VSS[247]
R1@ G48 VSS[248]
H12 VSS[249]
H18 VSS[250]
H22 VSS[251]
H24 VSS[252]
H26 VSS[253]
H30 VSS[254]
H32 VSS[255]
H34 VSS[256]
F3 VSS[257]
VSS[258]
BD82HM76-SLJ8E-C1_BGA989~D
R1@
A A

Deciphered Date
PCH (8/8) VSS
1.0
LA-9102P
5 4 3 2 1
5 4 3 2 1
+3VS
LCD PWR CTRL LVDS Conn.
1
@ RV13
@ 4.7K_0402_5%
DV5 JLVDS
2
BKOFF# 1 2 DISPOFF# <15> LVDS_A0- LVDS_A0- 1
+LCDVDD +5VALW <40> BKOFF# 1
<15> LVDS_A0+ LVDS_A0+ 2 41
1
+3VS CH751H-40PT_SOD323-2~D 3 2 G1 42
LVDS_A1- 4 3 G2 43
<15> LVDS_A1-
2
10K_0402_5% 5 4 G3 44
W=60mils DV6 <15> LVDS_A1+ LVDS_A1+
RV15 2 1 RV16 6 5 G4 45
RV14 47K_0402_5% 5P_0402_50V8C LVDS_A2- 7 6 G5 46
CV17 <15> LVDS_A2- 7 G6
2
100_0402_1% CH751H-40PT_SOD323-2~D @
<15> LVDS_A2+ LVDS_A2+ 8
S 1 2 9 8
9
1 1
1
D RV17 QV4
<15> LVDS_ACLK- LVDS_ACLK- 10 D
D CV18 10
56K_0402_5% AO3419L_SOT23-3 5P_0402_50V8C @ <15> LVDS_ACLK+ LVDS_ACLK+ 11
QV3 2 2 1 2 1 2 12 11
2N7002BKW_SOT323-3~D G WCM-2012HS-900T_4P LVDS_B0- 13 12
<15> LVDS_B0-
G
4 3 USB20_CAM_P11_R LVDS_B0+ 14 13
S <16> USB20_CAM_P11 <15> LVDS_B0+
3
D
+LCDVDD 4 3 15 14
1 15
0.1U_0402_16V7K
CV19
DV7
<15> LVDS_B1- LVDS_B1- 16
1
PCH_ENVDD 2 +LCDVDD 1 2 USB20_CAM_N11_R LVDS_B1+ 17 16
<15> PCH_ENVDD W=60mils <16> USB20_CAM_N11 1 2 <15> LVDS_B1+ 17
1
D CE_EN_R 18
1 2 QV5 2 LV24 EMC@ LVDS_B2- 19 18
1 1 CE_EN_R only for reserve. <15> LVDS_B2- 19
G BSS138_SOT23~D CV21 1 2 <15> LVDS_B2+ LVDS_B2+ 20
1
EC_ENVDD 3 CV20 0.1U_0402_16V7K RV210 @ 0_0402_5% DBC_EN_R 21 20
<40> EC_ENVDD S
21
3
4.7U_0805_10V4Z
<15> LVDS_BCLK- LVDS_BCLK- 22
BAT54C-7-F_SOT23-3 RV18 2 2 1 2 LVDS_BCLK+ 23 22
<15> LVDS_BCLK+ 23
10K_0402_5% RV208 @ 0_0402_5% 24
25 24
W=60mils +LCDVDD 25
2
+3VS 26
USB20_CAM_P11_R 27 26
MIC_DATA USB20_CAM_N11_R 28 27
<33> MIC_DATA 28
MIC_CLK 2 1 MIC_CLK_R +3VS_CAM
29
<33> MIC_CLK 29
1 MIC_CLK_R 30
RV30 @ 31 30
0_0402_1% CV29 MIC_DATA 32 31
@ 470P_0402_50V7K~D LCD_TEST 33 32
<40> LCD_TEST 33
2 2 1 EDID_CLK_LCD 34
<15> LVDS_DDC_CLK 34
RV19 @ 2 1 0_0402_1% EDID_DATA_LCD 35
<15> LVDS_DDC_DATA 35
RV20 @ 0_0402_1% INV_PWM 36
DISPOFF# 37 36
@ 38 37
CE_EN RV62 1 2 0_0402_5% CE_EN_R 39 38
<40> CE_EN +3VS +LCDVDD
W=60mils +INV_PWR_SRC
40 39
DBC_EN RV99 1 2 0_0402_5% DBC_EN_R 40
<40> DBC_EN
STARC_107K40-000001-G2
0.1U_0402_16V7K
0.1U_0402_16V7K
10U_0805_10V6K
CONN@
1
1 1 1
CV22
CV23
CV24
@
RV100 RV216
SP01000XE00
C LCD backlight PWR CTRL 0_0402_5% 0_0402_5%
2 2 2
C
2
60mil QV6
Place close to JLVDS
B+ SI3457CDV-T1-E3_TSOP6~D 60mil @
+INV_PWR_SRC_R 1 2 +INV_PWR_SRC
D
6 RV24 0_0805_1%
S
4 5
2
* Reserved for EMI/ESD/RF
1000P_0402_50V7K
CV25
100K_0402_5%
RV25
1
1
1 1 @
CV27
5P_0402_50V8C
3
2 2
CV26
0.1U_0603_50V_X7R
1 2 LVDS_BCLK-
need to close to JLVDS
@
CV28
2
5P_0402_50V8C DV8
PWR_SRC_ON 1 2 LVDS_BCLK+ MIC_CLK_R 6 1 USB20_CAM_P11_R
V I/O V I/O
1
+5VS
5 2
RV26 V BUS Ground
100K_0402_5% MIC_DATA 4 3 USB20_CAM_N11_R
@ V I/O V I/O
B+ RV27 1 2 0_0805_5% +INV_PWR_SRC IP4223CZ6_SO6~D
2
@
1
D
<40> EN_INVPWR 1 @ 2 +LCDVDD_R 2 QV7
RV28 0_0402_1% G 2N7002BKW_SOT323-3~D @
RV31 S 1 2 INV_PWM
<15> VGA_PWM
3
0_0402_5% RV29 0_0402_1%

+LCDVDD
2 1
1
1
@ RV230 CV30
B 100K_0402_5% @ B
680P_0402_50V7K
2
2
Webcam PWR CTRL +3VS +3VS_CAM
* Reserved for LCD
sequence tuning
RV231
1 @ 2
+INV_PWR_SRC
0_0603_1%
+5VALW
1
@
RV32
1
+3VS +3VS_CAM 820_0805_1%

QV8 RV33
SI2301CDS-T1-GE3_SOT23-3 100K_0402_5%
2N7002DW-7-F_SOT363-6
3 2
@
S
3 1 @
D
2
1000P_0402_50V7K
QV9B
1 @
2N7002DW-7-F_SOT363-6
1
CV319 5
G
2
RV34
6
100K_0402_5% @ @
4
@ 2 QV9A
2
A RV209 @ +LCDVDD_R 2 A
2 1
<40> CMOS_ON#
1
47K_0402_5%
2
CV31
0.1U_0402_16V7K @

Deciphered Date
LVDS/webcam
1.0
LA-9102P
5 4 3 2 1
5 4 3 2 1
W=40mils
D
Place close to JHDMI1 D
RV36 0_1206_5%~D
2 1
RV35 1 @ 2 0_0402_5% +VDISPLAY_VCC
WCM-2012HS-900T_4P DV9 FV1

TMDS_TXCN 1 2 TMDS_L_TXCN 2 1 2 1
10U_0603_6.3V6M
0.1U_0402_10V7K~D
1 2 +5VS
3 NC 1 1
CV34
CV32 2 1 0.1U_0402_10V7K~D TMDS_TXCN @ 1.5A_6V_1206L150PR~D
<15> HDMI_A3N_VGA
CV33 2 1 0.1U_0402_10V7K~D TMDS_TXCP TMDS_TXCP 4 3 TMDS_L_TXCP BAT1000-7-F_SOT23-3~D CV35
<15> HDMI_A3P_VGA 4 3
CV36 2 1 0.1U_0402_10V7K~D TMDS_TX0N LV7 EMC@ +3VS 2 2
<15> HDMI_A0N_VGA
CV37 2 1 0.1U_0402_10V7K~D TMDS_TX0P
<15> HDMI_A0P_VGA
RV37 1 @ 2 0_0402_5%
CV38 2 1 0.1U_0402_10V7K~D TMDS_TX1N
<15> HDMI_A1N_VGA
CV39 2 1 0.1U_0402_10V7K~D TMDS_TX1P
<15> HDMI_A1P_VGA
1
RV38 1 @ 2 0_0402_5%
CV40 2 1 0.1U_0402_10V7K~D TMDS_TX2N RV39
<15> HDMI_A2N_VGA WCM-2012HS-900T_4P
CV41 2 1 0.1U_0402_10V7K~D TMDS_TX2P 10K_0402_5%
<15> HDMI_A2P_VGA
TMDS_TX0N 1 2 TMDS_L_TX0N
1 2
2
JHDMI
TMDS_TX0P 4 3 TMDS_L_TX0P HDMI_HPLUG 19
4 3 18 HP_DET
LV8 EMC@ 17 +5V
DDC_DAT_HDMI 16 DDC/CEC_GND
SDA
RV42
RV43
RV44
RV45
RV46
RV47
RV48
RV49
RV40 1 @ 2 0_0402_5% DDC_CLK_HDMI 15
14 SCL
13 Reserved
1
RV41 1 @ 2 0_0402_5% TMDS_L_TXCN 12 CEC 20
CK- GND
680_0402_1%
680_0402_1%
680_0402_1%
680_0402_1%
680_0402_1%
680_0402_1%
680_0402_1%
680_0402_1%
11 21
WCM-2012HS-900T_4P TMDS_L_TXCP 10 CK_shield GND 22
TMDS_TX1N 1 2 TMDS_L_TX1N TMDS_L_TX0N 9 CK+ GND 23
1 2 8 D0- GND
D0_shield
2
TMDS_L_TX0P 7
TMDS_TX1P 4 3 TMDS_L_TX1P TMDS_L_TX1N 6 D0+
4 3 5 D1-
LV9 EMC@ TMDS_L_TX1P 4 D1_shield
C C
TMDS_L_TX2N 3 D1+
RV50 1 @ 2 0_0402_5% 2 D2-
D2_shield
1
0_0402_1% D TMDS_L_TX2P 1
1 2 2 QV11 D2+
+3VS
G LOTES_ABA-HDM-022-K01
1
RV51 @ S 2N7002_SOT23-3 RV52 1 @ 2 0_0402_5% CONN@
3
RV53
100K_0402_5% WCM-2012HS-900T_4P
TMDS_TX2P 1 2 TMDS_L_TX2P
DC232000B00
1 2
2
TMDS_TX2N 4 3 TMDS_L_TX2N
4 3
LV10 EMC@
RV54 1 @ 2 0_0402_5%
TMDS_TXCN @ CV358 1 2 100P_0402_50V8J TMDS_L_TXCN CV349 1 2 3.3P_0402_50V8C~D
TMDS_TXCP @ CV360 1 2 100P_0402_50V8J TMDS_L_TXCP CV350 1 2 3.3P_0402_50V8C~D
TMDS_TX0N @ CV362 1 2 100P_0402_50V8J TMDS_L_TX0N CV351 1 2 3.3P_0402_50V8C~D
TMDS_TX0P @ CV363 1 2 100P_0402_50V8J TMDS_L_TX0P CV352 1 2 3.3P_0402_50V8C~D
TMDS_TX1N @ CV359 1 2 100P_0402_50V8J TMDS_L_TX1N CV353 1 2 3.3P_0402_50V8C~D
B TMDS_TX2N @ CV361 1 2 100P_0402_50V8J TMDS_L_TX2N CV355 1 2 3.3P_0402_50V8C~D B
20111024 EMI ADD 20110805 EMI ADD
+3VS
1
+5VS C RV57
QV13 2 1 2 HDMI_HPLUG
MMBT3904_NL_SOT23-3 B 150K_0402_5%
+3VS E 1
2
<15> HDMI_DET
@ CV42
2
1
RV59 220P_0402_50V8J
@
1
@ 200K_0402_5% 2
0_0402_1%
DV10 RV55 DV11
1
RB751V-40_SOD323-2 RV56 100K_0402_5% BAV99-7-F_SOT23-3
QV12A @
2
2
2
DMN66D0LDW-7_SOT363-6
3
1 6 DDC_CLK_HDMI 1 2 +5V_HDMI_DDC
<15> PCH_SDVO_CTRLCLK
RV58 2.2K_0402_5%
5
+3VS
<15> PCH_SDVO_CTRLDATA 4 3 DDC_DAT_HDMI 1 2
RV60 2.2K_0402_5%
QV12B
A A
46@ ROYALTY HDMI W/LOGO

Part Number Description
RO0000002HM HDMI W/Logo:RO0000002HM

Deciphered Date
HDMI
1.0
LA-9102P
5 4 3 2 1
5 4 3 2 1
D D
UG1 GCLKUMA@
SLG3NB244VTR TQFN 16P CLK GEN
SLG3NB244VTR SA000057I00 Intel-UMA

SLG3NB300VTR SA00005RS00 Intel-DIS
+RTCBATT
+RTCVCC
1
R787 GCLK@
1
330_0402_5%
R788 @
0_0402_5%
2
+1.8VGS +VCCP +LAN_IO +3VLP
2.2U_0603_6.3V6K
C 2 C
C5 GCLK@ 1
C10
GCLK@ 1 1 GCLK@ 1 GCLK@ 1 GCLK@ 22U_0805_6.3V6M GCLK@
Depop if GCLK 1
C6 C7 C8 C9 UG1 2
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
with UMA
2 2 2 2 10 14
VBAT VDD_RTC_OUT
+3VLP 15
+V3.3A
+3VALW
2
VDD 9
32kHz PCH_RTCX1_R <13>
Place close GCLK@

11 12 VGA_X1_R 1 2 R785
to UG1.8 +1.8VGS VDDIO_27M 27MHz 10_0402_1%
VGA_X1 <25>
+LAN_IO
8 6 LAN_X1_R 1 GCLK@ 2 R782
VDDIO_25M_A 25MHz_A LAN_X1 <14>
33_0402_5%
+VCCP
3 5 PCH_X1_R 1 2 R783
VDDIO_25M_B 25MHz_B PCH_X1 <14>
0_0402_5% 1
CLK_X1 1 GCLK@
GCLK@
CLK_X2 16 XTAL_IN C14
XTAL_OUT
GND1
GND2
GND3
GND4
CLK_X1 5P_0402_50V8C
C11 GCLK@ 2
2 1
SLG3NB274VTR_TQFN16_2X3
4
7
13
17
12P_0402_50V8J~D Y1 GCLK@
1 2 GCLKDIS@
OSC GND
3 4
OSC GND
C12 GCLK@ 25MHZ_10PF_7V25000014
2 1
12P_0402_50V8J~D CLK_X2
B B
R784
0_0402_5%
LAN_X1_R 1 2
reserved for swing level adjustment

(close to U2)
A A

Deciphered Date
GCLK
1.0
LA-9102P
5 4 3 2 1
5 4 3 2 1
D D
GFX PCIE LANE REVERSAL

SA00004WI0L
PEG_HTX_C_GRX_P[7..0] UV1A THR1@ PEG_GTX_C_HRX_P[7..0]
<5> PEG_HTX_C_GRX_P[7..0] PEG_GTX_C_HRX_P[7..0] <5>
PEG_HTX_C_GRX_N[7..0] PEG_GTX_C_HRX_N[7..0]
<5> PEG_HTX_C_GRX_N[7..0] PEG_GTX_C_HRX_N[7..0] <5>
PEG_HTX_C_GRX_P0 AA38 Y33 PCIE_CRX_C_GTX_P0 220nF_0402_16V7K 2 1 CV43 DIS@ PEG_GTX_C_HRX_P0

PEG_HTX_C_GRX_N0 Y37 PCIE_RX0P PCIE_TX0P Y32 PCIE_CRX_C_GTX_N0 220nF_0402_16V7K 2 1 CV44 DIS@ PEG_GTX_C_HRX_N0
PCIE_RX0N PCIE_TX0N
LVDS Interface
PEG_HTX_C_GRX_P1 Y35 W33 PCIE_CRX_C_GTX_P1 220nF_0402_16V7K 2 1 CV45 DIS@ PEG_GTX_C_HRX_P1
PEG_HTX_C_GRX_N1 W36 PCIE_RX1P PCIE_TX1P W32 PCIE_CRX_C_GTX_N1 220nF_0402_16V7K 2 1 CV46 DIS@ PEG_GTX_C_HRX_N1
PCIE_RX1N PCIE_TX1N UV1G
PEG_HTX_C_GRX_P2 W38 U33 PCIE_CRX_C_GTX_P2 220nF_0402_16V7K 2 1 CV47 DIS@ PEG_GTX_C_HRX_P2

PEG_HTX_C_GRX_N2 V37 PCIE_RX2P PCIE_TX2P U32 PCIE_CRX_C_GTX_N2 220nF_0402_16V7K 2 1 CV48 DIS@ PEG_GTX_C_HRX_N2
PCIE_RX2N PCIE_TX2N LVDS CONTROL AK27
VARY_BL AJ27
PEG_HTX_C_GRX_P3 V35 U30 PCIE_CRX_C_GTX_P3 220nF_0402_16V7K 2 1 CV49 DIS@ PEG_GTX_C_HRX_P3
DIGON
PEG_HTX_C_GRX_N3 U36 PCIE_RX3P PCIE_TX3P U29 PCIE_CRX_C_GTX_N3 220nF_0402_16V7K 2 1 CV50 DIS@ PEG_GTX_C_HRX_N3
PCIE_RX3N PCIE_TX3N
PEG_HTX_C_GRX_P4 U38 T33 PCIE_CRX_C_GTX_P4 220nF_0402_16V7K 2 1 CV51 DIS@ PEG_GTX_C_HRX_P4 AK35

PEG_HTX_C_GRX_N4 T37 PCIE_RX4P PCIE_TX4P T32 PCIE_CRX_C_GTX_N4 220nF_0402_16V7K 2 1 CV52 DIS@ PEG_GTX_C_HRX_N4 TXCLK_UP_DPF3P AL36
PCIE_RX4N PCIE_TX4N TXCLK_UN_DPF3N
PCI EXPRESS INTERFACE

AJ38
PEG_HTX_C_GRX_P5 T35 T30 PCIE_CRX_C_GTX_P5 220nF_0402_16V7K 2 1 CV53 DIS@ PEG_GTX_C_HRX_P5
TXOUT_U0P_DPF2P AK37
PEG_HTX_C_GRX_N5 R36 PCIE_RX5P PCIE_TX5P T29 PCIE_CRX_C_GTX_N5 220nF_0402_16V7K 2 1 CV54 DIS@ PEG_GTX_C_HRX_N5 TXOUT_U0N_DPF2N
PCIE_RX5N PCIE_TX5N AH35
TXOUT_U1P_DPF1P AJ36
PEG_HTX_C_GRX_P6 R38 P33 PCIE_CRX_C_GTX_P6 220nF_0402_16V7K 2 1 CV55 DIS@ PEG_GTX_C_HRX_P6
TXOUT_U1N_DPF1N
PEG_HTX_C_GRX_N6 P37 PCIE_RX6P PCIE_TX6P P32 PCIE_CRX_C_GTX_N6 220nF_0402_16V7K 2 1 CV56 DIS@ PEG_GTX_C_HRX_N6 AG38
C C
PCIE_RX6N PCIE_TX6N TXOUT_U2P_DPF0P AH37
TXOUT_U2N_DPF0N
PEG_HTX_C_GRX_P7 P35 P30 PCIE_CRX_C_GTX_P7 220nF_0402_16V7K 2 1 CV57 DIS@ PEG_GTX_C_HRX_P7 AF35
PEG_HTX_C_GRX_N7 N36 PCIE_RX7P PCIE_TX7P P29 PCIE_CRX_C_GTX_N7 220nF_0402_16V7K 2 1 CV58 DIS@ PEG_GTX_C_HRX_N7 TXOUT_U3P AG36
PCIE_RX7N PCIE_TX7N TXOUT_U3N
N38 N33 LVTMDP

M37 PCIE_RX8P PCIE_TX8P N32
PCIE_RX8N PCIE_TX8N AP34
TXCLK_LP_DPE3P AR34
M35 N30 TXCLK_LN_DPE3N
L36 PCIE_RX9P PCIE_TX9P N29 AW37
PCIE_RX9N PCIE_TX9N TXOUT_L0P_DPE2P AU35
TXOUT_L0N_DPE2N
L38 L33 AR37
K37 PCIE_RX10P PCIE_TX10P L32 TXOUT_L1P_DPE1P AU39
PCIE_RX10N PCIE_TX10N TXOUT_L1N_DPE1N
AP35
K35 L30 TXOUT_L2P_DPE0P AR35
J36 PCIE_RX11P PCIE_TX11P L29 TXOUT_L2N_DPE0N
PCIE_RX11N PCIE_TX11N AN36
TXOUT_L3P AP37
J38 K33 TXOUT_L3N
H37 PCIE_RX12P PCIE_TX12P K32
PCIE_RX12N PCIE_TX12N
H35 J33
G36 PCIE_RX13P PCIE_TX13P J32 216-0833000-A11-THAMES-XT-M2_FCBGA962~D
THR1@
G38 K30
F37 PCIE_RX14P PCIE_TX14P K29
F35 H33
E37 PCIE_RX15P PCIE_TX15P H32
PCIE_RX15N PCIE_TX15N RV61 2 @ 1 0_0402_5%
B B
+3VGS
CLOCK
CLK_PEG_VGA AB35 1 2 +1.0VGS
<14> CLK_PEG_VGA PCIE_REFCLKP +3VGS
CLK_PEG_VGA# AA36 RV198 MS@1.69K_0402_1%~D
<14> CLK_PEG_VGA# PCIE_REFCLKN
5
VCC
CALIBRATION 1 2
<16> DGPU_HOLD_RST# IN1
Y30 1.27K_0402_1% 1 TH@ 2 RV63 4 GPU_RST# CV326
DIS@ PCIE_CALRP 2 OUT 0.1U_0402_25V6K
GND
<16> PCH_PLTRST# IN2
1 2 AH16 Y29 2K_0402_1% 1 TH@ 2 RV65 +1.0VGS DIS@
RV64 1K_0402_5% PWRGOOD PCIE_CALRN 1K_0402_1% 1 MS@ 2 RV203 UV13 1
MC74VHC1G08DFT2G_SC70-5
3
GPU_RST# AA30 Install 2K for Thames/Seymour DIS@
PERSTB
1
DIS@
RV66 216-0833000-A11-THAMES-XT-M2_FCBGA962~D Place CV326 Close to UV13
100K_0402_5% THAMES XT M2
2
UV1 THR3@
SA00004WI1L
216-0833000-A11-THAMES-XT-M2_FCBGA962~D
UV1 MSR1@ UV1 MSR3@
A SA00005X10L SA00005X10L A
MARS-PRO_FCBGA962~D MARS-PRO_FCBGA962~D
MARS Pro
UV1 CHR1@ UV1 CHR3@

Deciphered Date
Chelsea Pro Chelsea Pro THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
ATI_ThamesXT_M2_PCIE/LVDS
1.0
LA-9102P
5 4 3 2 1
5 4 3 2 1
ZZZ8 Sam 1GR1@ ZZZ4 Sam 1GR3@

UV1B CONFIGURATION STRAPS RECOMMENDED SETTINGS
+1.8VGS
ALLOW FOR PULLUP PADS FOR THESE STRAPS AND IF THESE 0= DO NOT INSTALL RESISTOR
1 = INSTALL 10K RESISTOR
GPIOS ARE USED, THEY MUST NOT CONFLICT DURING RESET X = DESIGN DEPENDANT
RV67 1 2 X76@ 10K_0402_5% VRAM_ID0 AU24
1 2 TXCAP_DPA3P AV23 NA = NOT APPLICABLE
X7644031L01 X7644031L10 RV68 X76@ 10K_0402_5%
TXCAM_DPA3N
RV69 1 2 X76@ 10K_0402_5% VRAM_ID1
RV70 1 2 X76@ 10K_0402_5% AT25 RECOMMENDED
1 2 VRAM_ID2 TX0P_DPA2P AR24
ZZZ5 Micron1GR1@ ZZZ3 Micron1GR3@ RV71 X76@ 10K_0402_5% MUTI GFX STRAPS PIN DESCRIPTION OF DEFAULT SETTINGS SETTINGS
RV72 1 2 X76@ 10K_0402_5% DPA TX0M_DPA2N
AU26 0: 50% swing
TX1P_DPA1P AV25 TX_PWRS_ENB GPIO0 PCIE FULL TX OUTPUT SWING X
TX1M_DPA1N 1: Full swing
AR8 AT27 0: disable
AU8 DVPCNTL_MVP_0 TX2P_DPA0P AR26
X7644031L02 X7644031L11 DVPCNTL_MVP_1 TX2M_DPA0N
TX_DEEMPH_EN GPIO1 PCIE TRANSMITTER DE-EMPHASIS 1: enable X
AP8
AW8 DVPCNTL_0 AR30 +3VGS Advertises PCIE speed 0: 2.5GT/s
AR3 DVPCNTL_1 TXCBP_DPB3P AT29 +3VGS
Vendor VRAM_ID0 VRAM_ID1 VRAM_ID2 AR1 DVPCNTL_2 TXCBM_DPB3N
RSVD GPIO2 when compliance test 1: 5GT/s 0
DVPCLK
1
K4W1G1646G-BC11 VRAM_ID0 AU1 AV31
DVPDATA_0 TX3P_DPB2P
1
AU3 AU30
D
Samsung 1GB VRAM_ID1
VRAM_ID2 AW3 DVPDATA_1 TX3M_DPB2N
RV73 RSVD GPIO8 RESERVED 0 D
ZZZ7 Sam 2GR1@ ZZZ2 Sam 2GR3@

64MX16 (1G)
SA00004GS0L(R1) RV68 RV69 RV72 AP6 DVPDATA_2
DPB
AR32
RV74
DIS@ 10K_0402_5%
DIS@
AW5 DVPDATA_3 TX4P_DPB1P AT31

0 1 0 4.7K_0402_5% BIF_VGA DIS GPIO9 VGA ENABLED 0
SA00004GS1L(R3)
2
AU5 DVPDATA_4 TX4M_DPB1N AC_BATT
2
H5TQ1G63DFR-11C AR6 DVPDATA_5 AT33 QV14B
DVPDATA_6 TX5P_DPB0P
3
AW6 AU32
Hynix 1GB AU6 DVPDATA_7 TX5M_DPB0N
2N7002DW-7-F_SOT363-6 RSVD GPIO21 RESERVED 0
64MX16 (1G)
SA000041S3L RV67 RV70 RV72 AT7 DVPDATA_8 AU14
DIS@
X7644031L05 X7644031L12 DVPDATA_9 TXCCP_DPC3P
0: disable
1 0 0 AV7 AV13 DIS@ PACIN# 5 BIOS_ROM_EN GPIO_22_ROMCSB ENABLE EXTERNAL BIOS ROM 1: enable X
AN7 DVPDATA_10 TXCCM_DPC3N
DVPDATA_11
6
ZZZ6 Hyn2GR1@ ZZZ1 Hyn2GR3@ MT41J64M16JT-107G:G AV9 AT15 QV14A
4
AT9 DVPDATA_12 TX0P_DPC2P AR14
Micron 1GB AR10 DVPDATA_13 TX0M_DPC2N
2N7002DW-7-F_SOT363-6 ROMIDCFG(2:0) GPIO[13:11] SERIAL ROM TYPE OR MEMORY APERTURE SIZE SELECT XXX
64MX16 (1G)
SA00004Y20L(R1) RV67 RV69 RV71 AW10 DVPDATA_14 DPC AU16 1 2 2
AU10 DVPDATA_15 TX1P_DPC1P AV15 <15,40,45,46> ACIN
1 1 1 VIP_DEVICE_STRAP_ENA V2SYNC IGNORE VIP DEVICE STRAPS 0
SA00004Y21L(R3) AP10 DVPDATA_16 TX1M_DPC1N RV250
1
AV11 DVPDATA_17 AT17
X7644031L06 X7644031L13 K4W2G1646E-BC11
DVPDATA_18 TX2P_DPC0P
0_0402_5%
AT11 AR16
Samsung 2GB @ RSVD H2SYNC 0
128Mx16 (2G) RV68 RV69 RV71 AR12 DVPDATA_19 TX2M_DPC0N
SA00005SH0L(R1) AW12 DVPDATA_20
DVPDATA_21 TXCDP_DPD3P
AU20
<40> ACIN_65W
0 1 1 AU12 AT19 RSVD GENERICC 0
SA00005SH1L(R3) AP12 DVPDATA_22 TXCDM_DPD3N
H5TQ2G63DFR-11C DVPDATA_23 AT21 AUD[1] AUD[0]
AJ21 TX3P_DPD2P AR20
Hynix 2GB AK21 SWAPLOCKA TX3M_DPD2N
AUD[1] HSYNC 0 0 No audio function 11
* 128Mx16 (2G)
SA00003YO2L(R1) RV67 RV70 RV71 PT SWAPLOCKB DPD AU22 AUD[0] VSYNC
0 1 Audio for DisplayPort and HDMI if dongle is detected
TX4P_DPD1P 1 0 Audio for DisplayPort only
1 0 1 AV21
SA00003YO3L(R3) TX4M_DPD1N 1 1 Audio for both DisplayPort and HDMI
H5TQ2G63DFR-11C I2C AT23
Micron 2GB
TX5P_DPD0P
TX5M_DPD0N
AR22 AMD RESERVED CONFIGURATION STRAPS
128Mx16 (2G) AK26 ALLOW FOR PULLUP PADS FOR THESE STRAPS BUT DO NOT INSTALL
SA00005XB0L(R1) AJ26 SCL
SDA RESISTOR. IF THESE GPIOS ARE USED, THEY MUST KEEP "LOW" AND
SA00005XB1L(R3) AD39 NOT CONFLICT DURING RESET
GENERAL PURPOSE I/O R AD37
GPU_GPIO0 AH20 RB
GPU_GPIO1 AH18 GPIO_0 AE36 GPIO21 H2SYNC GENERICC GPIO2 GPIO8
VGA_SMB_DA2 TH@ 1 2 GPU_GPIO2 AN16 GPIO_1 G AD35
AH23
VGA_SMB_DA2_R GPIO_2 GB
RV251 0_0402_5%
VGA_SMB_CK2 TH@ 1 2 AJ23
VGA_SMB_CK2_R GPIO_3_SMBDATA AF37
AC_BATT AH17 GPIO_4_SMBCLK B AE38
RV252 0_0402_5%
VDDCI_VID AJ17 GPIO_5_AC_BATT DAC1 BB
+3VGS STRAPS <54> VDDCI_VID AK17 GPIO_6
GPIO_7_BLON HSYNC
AC36 +1.8VGS +1.8VGS +1.8VGS
GPU_GPIO8 AJ13 AC38
C GPIO_8_ROMSO VSYNC C
GPU_GPIO9 AH15
10K_0402_5% 1 TH@ 2 RV75 GPU_GPIO0 GPU_VID5 AJ16 GPIO_9_ROMSI +1.8VGS
<53> GPU_VID5 GPIO_10_ROMSCK
1
10K_0402_5% 1 TH@ 2 RV76 GPU_GPIO1 GPU_GPIO11 AK16 AB34 RV84 1 DIS@ 2 499_0402_1% 65mA
10K_0402_5% 1 @ 2 RV77 GPU_GPIO2 GPU_GPIO12 AL16 GPIO_11 RSET RV237 RV239 RV241
GPU_GPIO13 AM16 GPIO_12 AD34 10mil
+AVDD (1.8V@65mA AVDD) 1 2 8.45K_0402_1% 10K_0402_1% 8.45K_0402_1%
GPU_VID4 AM14 GPIO_13 AVDD AE34 LV12DIS@ @ @ X76@
<53> GPU_VID4 GPIO_14_HPD2 AVSSQ
10K_0402_5% 1 2 RV78 AC_BATT GPU_VID3 AM13 100mA
CV75
CV76
CV77
@ 10mil BLM15BD121SN1D_0402
2
<53> GPU_VID3 GPIO_15_PWRCNTL_0
0.1U_0402_16V7K
1U_0402_6.3V6K
10U_0603_6.3V6M
GPU_VID2 AK14 AC33 (1.8V@100mA VDD1DI) 1
+VDD1DI 2 1 1 1 PS_1 PS_2 PS_3
<53> GPU_VID2 AG30 GPIO_16 VDD1DI AC34 +1.8VGS
THM_ALERT# LV13DIS@ Mars Pro
GPIO_17_THERMAL_INT VSS1DI
1
10K_0402_5% 1 2 RV79 GPU_GPIO8 AN14
CV78
CV79
CV80
@ BLM15BD121SN1D_0402 RV241 RV242 Bits [3:1]
MLPs
1U_0402_6.3V6K
10U_0603_6.3V6M
GPIO_18_HPD3
0.1U_0402_16V7K
10K_0402_5% 1 @ 2 RV80 GPU_GPIO9 RV89 1 @ 2 10K_0402_5% AM17 1 1 1 1 RV238 1 RV240 1 RV242
GPIO_19_CTF
0.68U_0402_10V
0.68U_0402_10V
0.68U_0402_10V
GPU_VID1 AL13 AC30 2 2 2 4.75K_0402_1% 4.75K_0402_1% 2K_0402_1%
DIS@
DIS@
DIS@
<53> GPU_VID1 GPIO_20_PWRCNTL_1 R2/NC
10K_0402_5% 1 TH@ 2 RV81 GPU_GPIO11 GPIO21_BBEN AJ14 AC31 CV329 MS@ CV331 MS@ CV333 X76@ Hynix NC 4.75k 000
10K_0402_5% 1 @ 2 RV82 GPU_GPIO12 T78 AK13 GPIO_21_BB_EN R2B/NC
2
GPIO_22_ROMCSB 2 2 2 2 2 2
10K_0402_5% 1 2 RV83 GPU_GPIO13 VGA_CLKREQ#_R AN13 AD30
DIS@
DIS@
DIS@
@ @ MS@ @
GPIO24_TRSTB AM23 GPIO_23_CLKREQB G2/NC AD31 PS_1 Samsung 8.45k 2k 001
GPIO25_TDI AN23 JTAG_TRSTB G2B/NC
GPIO26_TCK AK23 JTAG_TDI AF30
GPIO27_TMS AL24 JTAG_TCK B2/NC AF31
JTAG_TMS B2B/NC Add 12/6 for MLPS 0402 1% resistors are required. Micron 4.75k NC 111
T79 GPIO28_TDO AM24 RV246
AJ19 JTAG_TDO 1 2 +DPLL_PVDD
AK19 GENERICA AC32 @ 0_0402_5% Transmitter Power Saving Enable
AJ20 GENERICB C/NC AD32
GENERICC Y/NC
RV247 TX_PWRS_ENB GPIO0 0: 50% Tx output swing for mobile mode
+3VGS AK20 AF32 1 2 DPLL_PVSS 1: full Tx output swing (Default setting for Desktop)
AJ24 GENERICD COMP/NC
@ 0_0402_5%
10K_0402_5% 1 2 RV85 GPIO24_TRSTB AH26 GENERICE_HPD4
@ DAC2 PCI Express Transmitter De-emphasis Enable
10K_0402_5% 1 2 RV86 GPIO25_TDI AH24 GENERICF_HPD5 AD29 GENLK_CLK
@
GENERICG_HPD6 H2SYNC/GENLK_CLK
T80 TX_DEEMPH_EN GPIO1 0: Tx de-emphasis diabled for mobile mode
10K_0402_5% 1 @ 2 RV87 GPIO27_TMS AC29 GENLK_VSYNC T81 1: Tx de-emphasis enabled (Defailt setting for desktop)
V2SYNC/GENLK_VSYNC
10K_0402_5% 1 @ 2 RV88 GPIO26_TCK AK24
HPD1 AG31 PS_2
VDD2DI/NC AG32
0.60 V level, Please

VSS2DI/NC +3VGS Internal VGA Thermal Sensor
VREFG Divider ans AG33
+1.8VGS A2VDD/NC
DIS@
cap close to ASIC 20mil AD33 PS_3 +3VGS
A2VDDQ/NC
1
+1.8VGS 2 RV93 1 499_0402_1% +VREFG_GPU AH13 TH@ DIS@ DIS@
VREFG AF33 1 2
(Thames 75mA) DIS@
2 RV95 1 249_0402_1% A2VSSQ/TSVSSQ
RV90 RV91
LV14DIS@ RV207 0_0402_5% 10K_0402_5% 10K_0402_5%
2 1 +DPLL_PVDD
20mil
2
BLM15BD121SN1D_0402 2 1 AA29 NC_TSVSSQ should be tied to GND on Thames/Seymour
2
+DPLL_PVDD AM32 R2SET/NC
CV82
CV83
CV84
CV81 0.1U_0402_16V7K
DPLL_PVDD
1U_0402_6.3V6K
0.1U_0402_16V7K
10U_0603_6.3V6M
1 1 1 DIS@ 1 @ 2 DPLL_PVSS AN32 VGA_SMB_CK2 1 6

B DPLL_PVSS EC_SMB_CK2 <40> B
20mil
5
RV248 DDC/AUX AM26 QV15A DIS@
0_0402_1% +DPLL_VDDC AN31 PLL/CLOCK DDC1CLK AN26 DMN66D0LDW-7_SOT363-6
2 2 2 +3VGS DPLL_VDDC DDC1DATA VGA_SMB_DA2 4 3
DIS@
DIS@
DIS@
AM27 EC_SMB_DA2 <40>

XTALIN AV33 AUX1P AL27
XTALIN QV15B DIS@
XTALIN AUX1N
1
XTALOUT AU34 DMN66D0LDW-7_SOT363-6

Voltage Swing: 1.8 V XTALOUT
RV235 AM19
+1.0VGS DDC2CLK AL19 1 RV92 2 0_0402_5%
(Thames 125mA) 10K_0402_5%
AW34 DDC2DATA
@
LV15DIS@ 0.935V@ Mars Pro @
2 1 +DPLL_VDDC XO_IN AN20 @ 1 RV94 2 0_0402_5%
2
BLM15BD121SN1D_0402 TS_FDO AW35 AUX2P AM20

XO_IN2 AUX2N
CV86
CV87
CV88
1U_0402_6.3V6K
0.1U_0402_16V7K
10U_0603_6.3V6M
1 1 1 AL30
RV236 DDCCLK_AUX3P AM30
DDCDATA_AUX3N
10K_0402_5%
AL29
2 2 2 MS@ DDCCLK_AUX4P
GPU_THERMAL_D+ AF29 AM29
DIS@
DIS@
DIS@
GPU_THERMAL_D- AG29 DPLUS DDCDATA_AUX4N

THERMAL
DMINUS AN21
Add 12/6 for MLPS DDCCLK_AUX5P AM21
TS_FDO AK32 DDCDATA_AUX5N
TS_FDO AJ30
(Thames 5mA) AL31 DDC6CLK AJ31
TS_A/NC DDC6DATA
RV97 XTALDIS@ DIS@ (1.8V@20mA TSVDD)
XTALOUT
1M_0402_5%
XTALIN
+1.8VGS
1
LV16
2 +TSVDD
10mil
AJ32 DDCCLK_AUX7P
AK30
AK29
VGA Thermal Sensor ADM1032ARMZ
BLM15BD121SN1D_0402 AJ33 TSVDD DDCDATA_AUX7N
Closed to GPU
1U_0402_6.3V6K
10U_0603_6.3V6M
TSVSS
0.1U_0402_16V7K
+3VGS +3VGS
DIS@ CV91
DIS@ CV92
DIS@ CV93
YV1 XTALDIS@ 1 1 1
27MHZ_10PF_7V27000050
3 1 216-0833000-A11-THAMES-XT-M2_FCBGA962~D MS@ 2
3 1
2
2 2 2 CV85
GND GND
1
CV94 CV95 THR1@ RV96

10P_0402_50V8J 10P_0402_50V8J 0.1U_0402_16V7K MS@ 4.7K_0402_5%
4 2 1
2
XTALDIS@ XTALDIS@ UV14
1
1 8 VGA_SMB_CK2
VDD SCLK
GPU_THERMAL_D+ 2 7 VGA_SMB_DA2
CV89 D+ SDATA
1 2 3 6 THM_ALERT#
MS@ D- ALERT#
+3VGS close to YV1 GPU_THERMAL_D- 2200P_0402_50V7K 4 5
THERM# GND 1
A A
1 2 XTALIN CV90
<23> VGA_X1 10P_0402_50V8J
RV232 0_0402_5% ADM1032ARMZ-2REEL_MSOP8
1
+3VGS GCLKDIS@ +3VGS MS@ 2 @

RV199
1 2
Address:100_1101
2.2K_0402_5%
@ RV98 4.7K_0402_5%
2
G
Need to CHECK CIS symbol MS@

2
1 3 VGA_CLKREQ#_R
<14> PEG_A_CLKRQ#
D
@
2N7002_SOT23-3
QV28
2 RV200 1 Security Classification Compal Secret Data Compal Electronics, Inc.
0_0402_5% Issued Date 2012/09/25 Deciphered Date 2013/09/30 Title
WWW.MANUALS.CLAN.SU
@ ATI_ThamesXT_M2_Main_MSIC
Size Docum ent Num ber Rev
1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS LA-9102P
Date: Tues day, Septem ber 25, 2012 Sheet 25 of 57
5 4 3 2 1
5 4 3 2 1
Switch circuits in BACO desingns for Thanes/Seymour only

+3VGS
Circuits to support BACO
55mA@1.0V, in BACO mode
2
RV101
10K_0402_5%
DIS@
+1.0VGS +BIF_VDDC +VGA_CORE
D D
1
60mil 60mil
MS@ TH@
1 2 1 2
RV103 0_0805_5% RV234 0_0603_5%~D
for PX4.0 for PX5.0
1
D +3VGS CV99 @
2 QV21 0.1U_0402_16V7K 1
<27> PX_EN
G 2N7002K_SOT23-3 1 2 CV97
S DIS@
1
3
DIS@ 22U_0805_6.3V6M
5
RV104 2
5.11K_0402_1%
VCC
DIS@ 1
IN1 4 PX_MODE
PX_MODE <40,53,54>
2
+3VGS 2 OUT
GND
IN2
PX_MODE=1 for Normal Operation
@
UV16 PX_MODE=0 for BACO mode to shut down power rails expcept VDDR3,PCIE_VDDC and 1.8V rail
1
3
DIS@ MC74VHC1G08DFT2G_SC70-5
RV105
20K_0402_5%
@
DV12
2
RB751V-40_SOD323-2
PXS_PWREN 1 2 RUNPWROK 1 @ 2 PX_MODE
RV102 0_0402_1%
1 @ 2 for PX5.0
@
1
CV100 +3VALW +1.8VS TO +1.8VGS
RV233
0_0402_1% 1U_0603_10V6K
for PX4.0 and PX5.0
1
2 +1.8VS @ +1.8VGS
DIS@
RV109 2 1
C 100K_0402_5% C
2MM J9
2
UV35
PXS_PWREN#
DMN3030LSS-13_SOP8L-8
8 1
1
D 7 2
PXS_PWREN 2 QV25 DIS@ 6 3 1 1
<16,53> PXS_PWREN
1
G 5
S 2N7002_SOT23-3 CV320 CV321
3
DIS@ 10U_0805_10V6K 1U_0603_10V6K RV213
4
2 DIS@ 2 DIS@ 470_0603_5%
Note: @
1 2
PX4.0 +VGA_CORE,VDDCI,+1.5VGS ON B+_BIAS D
2N7002H_SOT23-3 2
PX4.0 +3VGS, +1.0VGS,+1.8VGS OFF QV29 G
1
PX5.0 +3VGS,+VGA_CORE,VDDCI,+1.5VGV,+1.0VGS,+1.8VGS OFF @ S
3
330K_0402_5%
RV128
DIS@
2
1 RV211 2
DIS@ 470K_0402_5% PXS_PWREN# 1 RV214 2
2
1 @ 0_0402_5%
1
D RV212 CV2
+1.5VGPU TO +1.5VGS PXS_PWREN# 2 0_0402_5% 0.1U_0603_25V7K
G QV10 @ DIS@
S 2
1
2N7002H_SOT23-3
Power Seguence of Thames and Mars Pro +1.5VGPU
JP9 @
+1.5VGS DIS@
2 1
2MM
UV17 DIS@
+3VGS AO4304L_SO8
B 8 1 10U_0603_6.3V6M B
10U_0603_6.3V6M 1 10U_0603_6.3V6M 1 7 2 1 1
1
CV309 CV104 6 3 CV105 CV106 DIS@
+VGA_CORE DIS@ DIS@ 5 DIS@ 1U_0603_10V6K RV111 @
470_0603_5%
2 2 2 2
4
+VDDCI
1 2
B+_BIAS D
2
+3.3VS TO +3.3VGS
1
+1.5VGS RV112 S
G
QV26 @
3
+3VALW 300K_0402_5% DIS@ 2N7002K_SOT23-3
20K_0402_5%
DIS@ RV113
+1.0VGS
1
+3VS +3VGS
DIS@
6
RV114 2 JP8 @
100K_0402_5% @ 2 1 10U_0603_6.3V6M 1U_0603_10V6K
+1.8VGS <20ms DIS@ DIS@ RV115
1
PX_MODE# 1 RV116 2 0_0402_5%
3 2
1
PX_MODE# 2 QV27A CV107 DIS@ 2MM 1 1
2M_0402_5%~D 0.1U_0603_25V7K CV101 CV102 RV106

2 DIS@ DIS@ 470_0603_5%
1
DIS@ @
PX_MODE 5 QV27B 3 1 2 2
1
2
4
1
DIS@ RV117 QV22 DIS@ D
100K_0402_5% +5VALW DIS@ DIS@ AP2301GN-HF_SOT23-3 2
2
RV107 RV108 G
2
1 2 S QV23
3
2N7002K_SOT23-3
20K_0402_5% 1K_0402_5% @
1 DIS@ RV110
1
D CV103 PXS_PWREN# 1 2
PXS_PWREN 2 DIS@ 0.1U_0603_25V7K @ 0_0402_5%
G QV24
A A
S 2
3
2N7002H_SOT23-3

Deciphered Date
ATI_ThamesXT_M2_BACO POWER
1.0
LA-9102P
5 4 3 2 1
5 4 3 2 1
UV1F
AB39 A3
E39 PCIE_VSS#1 GND#1 A37
F34 PCIE_VSS#2 GND#2 AA16
F39 PCIE_VSS#3 GND#3 AA18
G33 PCIE_VSS#4 GND#4 AA2
G34 PCIE_VSS#5 GND#5 AA21
H31 PCIE_VSS#6 GND#6 AA23
D D
J31 PCIE_VSS#9 GND#9 AA6
J34 PCIE_VSS#10 GND#10 AB12
K31 PCIE_VSS#11 GND#11 AB15
(Thames 330mA) L31 PCIE_VSS#14 GND#14 AB22
+DPAB_VDD18 +1.8VGS L34 PCIE_VSS#15 GND#15 AB24
M34 PCIE_VSS#16 GND#16 AB27
1.8V@300mA DPAB_VDD18) PCIE_VSS#17 GND#17
+DPAB_VDD18 1 @ 2 M39 AC11
RV118 0_0402_1% N31 PCIE_VSS#18 GND#18 AC13
1 1 1 PCIE_VSS#19 GND#19
N34 AC16
CV108
CV109
CV110
10U_0603_6.3V6M
0.1U_0402_16V7K
1U_0402_6.3V6K
UV1H P31 PCIE_VSS#20 GND#20 AC18
(Thames 330mA) 20mil P34 PCIE_VSS#21 GND#21 AC2
+1.8VGS +DPCD_VDD18 @ 2@ 2@ 2 P39 PCIE_VSS#22 GND#22 AC21
1.8V@300mA DPCD_VDD18) DP C/D POWER DP A/B POWER 20mil PCIE_VSS#23 GND#23
130mA R34 AC23
1 @ 2 +DPCD_VDD18 AP20 AN24 T31 PCIE_VSS#24 GND#24 AC26
AP21 DPCD/DPC_VDD18#1 DPAB/DPA_VDD18#1 AP24 T34 PCIE_VSS#25 GND#25 AC28
RV119 DPCD/DPC_VDD18#2 DPAB/DPA_VDD18#2 (Thames 330mA) T39 PCIE_VSS#26 GND#26 AC6
CV111
CV112
CV113
10U_0603_6.3V6M
1U_0402_6.3V6K
0.1U_0402_16V7K
0_0402_1% +DPCD_VDD10 +DPAB_VDD10 +1.0VGS U31 PCIE_VSS#27 GND#27 AD15
1 1 1 20mil (1.0V@220mA DPAB_VDD10) PCIE_VSS#28 GND#28
20mil 110mA 0.935V@Mars Pro U34 AD17
@ @ @ AP13 AP31 +DPAB_VDD10 1 @ 2 V34 PCIE_VSS#29 GND#29 AD20
AT13 DPCD/DPC_VDD10#1 DPAB/DPA_VDD10#1 AP32 RV120 0_0402_1% V39 PCIE_VSS#30 GND#30 AD22
10U_0603_6.3V6M
1U_0402_6.3V6K
0.1U_0402_16V7K
2 2 2 DPCD/DPC_VDD10#2 DPAB/DPA_VDD10#2 W31 PCIE_VSS#31 GND#31 AD24
CV114
CV115
CV116
W34 PCIE_VSS#32 GND#32 AD27
1 1 1 PCIE_VSS#33 GND#33
AN17 AN27 Y34 AD9
AP16 DP/DPC_VSSR#1 DP/DPA_VSSR#1 AP27 @ @ @ Y39 PCIE_VSS#34 GND#34 AE2
AP17 DP/DPC_VSSR#2 DP/DPA_VSSR#2 AP28 PCIE_VSS#35 GND#35 AE6
AW14 DP/DPC_VSSR#3 DP/DPA_VSSR#3 AW24 2 2 2 GND#36 AF10
(Thames 220mA) +DPCD_VDD10 AW16 DP/DPC_VSSR#4 DP/DPA_VSSR#4 AW26 GND#37 AF16
+1.0VGS DP/DPC_VSSR#5 DP/DPA_VSSR#5 GND#38 AF18
1.0V@220mA DPCD_VDD10) GND#39
0.935V@Mars Pro +DPCD_VDD18 +DPAB_VDD18 AF21
1 @ 2 +DPCD_VDD10 20mil
AP22
DPCD/DPD_VDD18#1 DPAB/DPB_VDD18#1
20mil
AP25 130mA F15
GND#100
GND GND#40
GND#41
GND#42
AG17
AG2
RV121 AP23 AP26 F17 AG20
@ CV117
@ CV118
@ CV119
10U_0603_6.3V6M
1U_0402_6.3V6K
0.1U_0402_16V7K
0_0402_1% DPCD/DPD_VDD18#2 DPAB/DPB_VDD18#2 F19 GND#101 GND#43 AG22

1 1 1 GND#102 GND#44
C +DPCD_VDD10 +DPAB_VDD10 F21 AG6 C
F23 GND#103 GND#45 AG9
20mil 20mil GND#104 GND#46
AP14 AN33 110mA F25 AH21
2 2 2 AP15 DPCD/DPD_VDD10#1 DPAB/DPB_VDD10#1 AP33 F27 GND#105 GND#47 AJ10
DPCD/DPD_VDD10#2 DPAB/DPB_VDD10#2 F29 GND#106 GND#48 AJ11
F31 GND#107 GND#49 AJ2
F33 GND#108 GND#50 AJ28
AN19 AN29 F7 GND#109 GND#51 AJ6
AP18 DP/DPD_VSSR#1 DP/DPB_VSSR#1 AP29 F9 GND#110 GND#52 AK11
AP19 DP/DPD_VSSR#2 DP/DPB_VSSR#2 AP30 G2 GND#111 GND#53 AK31
AW20 DP/DPD_VSSR#3 DP/DPB_VSSR#3 AW30 G6 GND#112 GND#54 AK7
AW22 DP/DPD_VSSR#4 DP/DPB_VSSR#4 AW32 H9 GND#113 GND#55 AL11
DP/DPD_VSSR#5 DP/DPB_VSSR#5 J2 GND#114 GND#56 AL14
J27 GND#115 GND#57 AL17
J6 GND#116 GND#58 AL2
150_0402_1% 2 DIS@ 1 RV122 AW18 AW28 RV123 1 DIS@ 2 150_0402_1% J8 GND#117 GND#59 AL20
DPCD_CALR DPAB_CALR K14 GND#118 GND#60 AL21
+1.8VGS (Thames 330mA) +DPEF_VDD18 +DPAB_VDD18 K7 GND#119 GND/PX_EN#61 AL23
PX_EN <26>
L11 GND#120 GND#62 AL26
1.8V@300mA DPEF_VDD18) 20mil DP E/F POWER DP PLL POWER 20mA 10mil GND#121 GND#63
1 @ 2 +DPEF_VDD18 AH34 AU28 L17 AL32
1
AJ34 DPEF/DPE_VDD18#1 DPAB_VDD18/DPA_PVDD AV27 L2 GND#122 GND#64 AL6
RV124 DPEF/DPE_VDD18#2 DP_VSSR/DPA_PVSS L22 GND#123 GND#65 AL8 RV125
@ CV120
@ CV121
@ CV122
10U_0603_6.3V6M
1U_0402_6.3V6K
0.1U_0402_16V7K
0_0402_1% +DPEF_VDD10 +DPAB_VDD18 L24 GND#124 GND#66 AM11 4.7K_0402_5%

1 1 1 GND#125 GND#67
20mil 20mA 10mil L6 AM31 DIS@
AL33 AV29 M17 GND#126 GND#68 AM9
DPEF/DPE_VDD10#1 DPAB_VDD18/DPB_PVDD GND#127 GND#69
2
AM33 AR28 M22 AN11
2 2 2 DPEF/DPE_VDD10#2 DP_VSSR/DPB_PVSS M24 GND#128 GND#70 AN2
+DPCD_VDD18 N16 GND#129 GND#71 AN30
N18 GND#130 GND#72 AN6
20mA 10mil GND#131 GND#73
AN34 AU18 N2 AN8
AP39 DP/DPE_VSSR#1 DPCD_VDD18/DPC_PVDD AV17 N21 GND#132 GND#74 AP11
+DPEF_VDD10 AR39 DP/DPE_VSSR#2 DP_VSSR/DPC_PVSS N23 GND#133 GND#75 AP7
(Thames 220mA) AU37 DP/DPE_VSSR#3 +DPCD_VDD18 N26 GND#134 GND#76 AP9
+1.0VGS DP/DPE_VSSR#4 N6 GND#135 GND#77 AR5
1.0V@240mA DPEF_VDD10) 20mA 10mil GND#136 GND#78
0.935V@Mars Pro AV19 R15 B11
1 @ 2 +DPEF_VDD10 +DPEF_VDD18 DPCD_VDD18/DPD_PVDD AR18 R17 GND#137 GND#79 B13
DP_VSSR/DPD_PVSS R2 GND#138 GND#80 B15
20mil GND#139 GND#81
RV126 AF34 +DPEF_VDD18 R20 B17
@ CV123
@ CV124
@ CV125
10U_0603_6.3V6M
1U_0402_6.3V6K
0.1U_0402_16V7K
B B
0_0402_1% AG34 DPEF/DPF_VDD18#1 R22 GND#140 GND#82 B19
1 1 1 DPEF/DPF_VDD18#2
20mA 10mil GND#141 GND#83
AM37 R24 B21
+DPEF_VDD10 DPEF_VDD18/DPE_PVDD AN38 R27 GND#142 GND#84 B23
DP_VSSR/DPE_PVSS R6 GND#143 GND#85 B25
2 2 2
20mil GND#144 GND#86
AK33 +DPEF_VDD18 T11 B27
AK34 DPEF/DPF_VDD10#1 T13 GND#145 GND#87 B29
20mA 10mil
DPEF/DPF_VDD10#2 AL38 T16 GND#146 GND#88 B31
DPEF_VDD18/DPF_PVDD AM35 T18 GND#147 GND#89 B33
DP_VSSR/DPF_PVSS T21 GND#148 GND#90 B7
AF39 T23 GND#149 GND#91 B9
AH39 DP/DPF_VSSR#1 T26 GND#150 GND#92 C1
AK39 DP/DPF_VSSR#2 U15 GND#151 GND#93 C39
AL34 DP/DPF_VSSR#3 U17 GND#153 GND#94 E35
PS_0 AM34 DP/DPF_VSSR#4 U2 GND#154 GND#95 E5
DP/DPF_VSSR#5 U20 GND#155 GND#96 F11
U22 GND#156 GND#97 F13
+1.8VGS U24 GND#157 GND#98
AM39 U27 GND#158
DPEF_CALR U6 GND#159
V11 GND#160
1
216-0833000-A11-THAMES-XT-M2_FCBGA962~D V16 GND#161

GND#163
1
RV127 THR1@ V18

RV243 150_0402_1% V21 GND#164
DIS@ V23 GND#165
8.45K_0402_1%
V26 GND#166
MS@ GND#167
2
W2
2
W6 GND#168
AMD recommended setting GND#169
PS_0 MLPS Bit Y15
RV201 MS@ Y17 GND#170
strap R_PU R_PD C GND#171
Y20
1
Y22 GND#172 A39 MECH#1

PS0: 11001 RV243=8.45K RV201=2K CV335=NC
0.68U_0402_10V
1 GND#173 VSS_MECH#1
RV201 Y24 AW1 MECH#2 T82 PAD
0_0402_5% CV335 Y27 GND#174 VSS_MECH#2 AW39MECH#3 T83 PAD
PS1: 11000 RV237=NC RV238=4.75K CV329=NC GND#175 VSS_MECH#3 T84 PAD
TH@ U13
@ 2 V13 GND#152
2K_0402_1% PS2: 00000 RV239=NC RV240=4.75K CV331=0.68u GND#162
2
A Thames/Seymour Only PS3: 11000 RV241=NC RV242=4.75K CV333=NC 216-0833000-A11-THAMES-XT-M2_FCBGA962~D A

THR1@
Do not install for Heathrow/Mars Pro
PS_0 Should be tied to GND on Thames/Seymour

Deciphered Date
ATI_ThamesXT_M2_PWR_GND
1.0
LA-9102P
5 4 3 2 1
5 4 3 2 1
(Thames 440mA) +1.8VGS

(1.8V@504mA PCIE_VDDR) DIS@ LV17
+PCIE_VDDR 2 1
MBK1608121YZF_0603
CV126
CV127
CV128
CV129
CV130
CV131
10U_0603_6.3V6M
0.1U_0402_16V7K
0.1U_0402_16V7K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1 1 1 1 1 1
2 2 2 2 2 2
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
UV1E 40mA +1.8VGS
For DDR3 MVDDQ = 1.5V (1.8V@40mA PCIE_PVDD) DIS@ LV18
+1.5VGS MEM I/O 2 1
D (Thames 1.7)A 40mil MBK1608121YZF_0603
D
CV132
CV133
CV134
PCIE
10U_0603_6.3V6M
1U_0402_6.3V6K
0.1U_0402_16V7K
AC7 AA31 1 1 1
AD11 VDDR1#1 PCIE_VDDR#1 AA32
VDDR1#2 PCIE_VDDR#2
220U_B2_2.5VM_R35
AF7 AA33 TH@ 1 2 +PCIE_VDDR
CV136
CV137
CV138
CV139
CV140
CV141
CV142
CV143
CV144
CV145
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1 VDDR1#3 PCIE_VDDR#3
CV135
1 1 1 1 1 1 1 1 1 1 AG10 AA34 RV244 0_0402_5%
@ + AJ7 VDDR1#4 PCIE_VDDR#4 V28 2 2 2
DIS@
DIS@
DIS@
AK8 VDDR1#5 PCIE_VDDR#5 W29 @ 1 2
VDDR1#6 PCIE_VDDR#6 +BIF_VDDC
AL9 W30 RV245 0_0402_5%
2 2 2 2 2 2 2 2 2 2 2 G11 VDDR1#7 PCIE_VDDR#7 Y31
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
G14 VDDR1#8 PCIE_VDDR#8 AB37 +PCIE_PVDD +1.0VGS
G17 VDDR1#9 PCIE_VDDR/PCIE_PVDD
G20 VDDR1#10 G30
G23 VDDR1#11 PCIE_VDDC#1 G31
G26 VDDR1#12 PCIE_VDDC#2 H29
CV146
CV147
CV148
CV149
CV150
CV151
(Thames 1.1A)
10U_0603_6.3V6M
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
G29 VDDR1#13 PCIE_VDDC#3 H30
VDDR1#14 PCIE_VDDC#4 1 1 1 1 1 1
H10 J29 (1.0V@1920mA PCIE_VDDC)
+1.5VGS J7 VDDR1#15 PCIE_VDDC#5 J30
J9 VDDR1#16 PCIE_VDDC#6 L28
K11 VDDR1#17 PCIE_VDDC#7 M28 2 2 2 2 2 2 (Mars Pro)
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
K13 VDDR1#18 PCIE_VDDC#8 N28
VDDR1#19 PCIE_VDDC#9 (0.935V@2.5A PCIE_VDDC)
K8 R28
CV152
CV153
CV154
CV155
CV156
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
L12 VDDR1#20 PCIE_VDDC#10 T28
1 1 1 1 1 VDDR1#21 PCIE_VDDC#11
L16 U28
L21 VDDR1#22 PCIE_VDDC#12 +VGA_CORE
L23 VDDR1#23
2 2 2 2 2 L26 VDDR1#24 AA15 (Thames 20.5A)
DIS@
DIS@
DIS@
DIS@
DIS@
VDDR1#25 VDDC#1
330U_D2_2VM_R6M~D
L7 CORE AA17
M11 VDDR1#26 VDDC#2 AA20
CV157
CV158
CV159
CV160
CV161
CV162
CV163
CV164
CV165
CV166
CV167
CV168
CV169
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
VDDR1#27 VDDC#3 1
N11 AA22 1 1 1 1 1 1 1 1 1 1 1 1 1
VDDR1#28 VDDC#4
CV327
P7 AA24 +
DIS@
R11 VDDR1#29 VDDC#5 AA27
U11 VDDR1#30 VDDC#6 AB16
+1.8VGS +VDDC_CT U7 VDDR1#31 VDDC#7 AB18 2 2 2 2 2 2 2 2 2 2 2 2 2 2
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
(Thames 250mA) Y11 VDDR1#32 VDDC#8 AB21
DIS@ LV19 Y7 VDDR1#33 VDDC#9 AB23
(1.8V@110mA VDD_CT) VDDR1#34 VDDC#10
1 2 AB26
BLM15BD121SN1D_0402 VDDC#11 AB28
C C
VDDC#12 AC17 +VGA_CORE
CV170
CV171
CV172
CV173
CV174
10U_0603_6.3V6M
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
0.1U_0402_16V7K
VDDC#13 AC20
1 1 1 1 1 VDDC#14
LEVEL AC22
+3VGS 20mil TRANSLATION VDDC#15 AC24
VDDC#16
POWER
AF26 AC27
CV175
CV176
CV177
CV178
CV179
CV180
CV181
CV182
CV183
CV184
CV185
CV186
(Thames 60mA)
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
2 2 2 2 2 AF27 VDD_CT#1 VDDC#17 AD18
DIS@
DIS@
DIS@
DIS@
DIS@
VDD_CT#2 VDDC#18 1 1 1 1 1 1 1 1 1 1 1 1
AG26 AD21
AG27 VDD_CT#3 VDDC#19 AD23
CV187
CV188
CV189
CV190
10U_0603_6.3V6M
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
VDD_CT#4 VDDC#20 AD26

1 1 1 1 VDDC#21 AF17 2 2 2 2 2 2 2 2 2 2 2 2
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
10mil I/O VDDC#22 AF20
AF23 VDDC#23 AF22
2 2 2 2 AF24 VDDR3#1 VDDC#24 AG16
DIS@
DIS@
DIS@
DIS@
AG23 VDDR3#2 VDDC#25 AG18

AG24 VDDR3#3 VDDC#26 AG21 +VGA_CORE
+1.8VGS VDDR3#4 VDDC#27 AH22
DIS@ LV20
20mil VDDC#28 AH27
1 2 +VDDR4 AF13 VDDC#29 AH28
BLM15BD121SN1D_0402 AF15 VDDR4#4 VDDC#30 M26
CV365
CV366
CV367
CV191
CV192
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
22U_0603_6.3V6M
AG13 VDDR4#5 VDDC#31 N24
CV193
CV194
1U_0402_6.3V6K
0.1U_0402_16V7K
VDDR4#7 VDDC#32 1 1 1 1 1
1 1 AG15 N27
VDDR4#8 VDDC/BIF_VDDC#33 R18
VDDC#34 R21
AD12 VDDC#35 R23 2 2 2 2 2
DIS@
DIS@
DIS@
DIS@
DIS@
2 2 AF11 VDDR4#1 VDDC#36 R26
DIS@
DIS@
AF12 VDDR4#2 VDDC#37 T17

AG11 VDDR4#3 VDDC#38 T20
VDDR4#6 VDDC#39 T22 +BIF_VDDC
VDDC#40 T24
+1.8VGS (Thames 150mA)
(M97, Broadway and Madison: 1.8V@150mA MPV18)
VDDC#41 T27 55mA
VDDC/BIF_VDDC#42 U16
LV21 DIS@ M20 VDDC#43 U18
CV195
CV196
For non-BACO designs, connect BIF_VDDC to VDDC.
1U_0402_6.3V6K
1U_0402_6.3V6K
1 2 M21 NC_VDDRHA VDDC#44 U21 1 1
MCK1608471YZF 0603 NC_VSSRHA VDDC#45 U23 For BACO designs - see BACO reference schematics
+1.8VGS (Thames 50mA) VDDC#46 U26
LV22 DIS@ V12 VDDC#47 V17
CV197
CV198
CV199
(1.8V@75mA SPV18)
10U_0603_6.3V6M
1U_0402_6.3V6K
0.1U_0402_16V7K
1 2 U12 NC_VDDRHB VDDC#48 V20 2 2
DIS@
DIS@
B 1 1 1 NC_VSSRHB VDDC#49 B
BLM15BD121SN1D_0402 V22
VDDC#50 V24
CV200
CV201
CV202
10U_0603_6.3V6M
1U_0402_6.3V6K
0.1U_0402_16V7K
VDDC#51 V27
1 1 1 VDDC#52
2 2 2 Y16
DIS@
DIS@
DIS@
PLL VDDC#53 Y18

VDDC#54 Y21
2 2 2 20mil VDDC#55 Y23
DIS@
DIS@
DIS@
+MPV18 H7 VDDC#56 Y26

H8 MPV18#1 VDDC#57 Y28
MPV18#2 VDDC#58
(GDDR3/DDR3 1.12V@4A VDDCI)
+VDDCI +VGA_CORE
+1.0VGS (Thames 100mA)
0.935V@Mars Pro
10mil +SPV18 AM10 (GDDR5 1.12V@16A VDDCI) LV25 MS@
LV23 DIS@ (120mA SPV10)
SPV18 AA13 4A 1 2
1 2 20mil +SPV10 AN9 VDDCI#1 AB13 BLM15BD121SN1D_0402
MCK1608471YZF 0603 SPV10 VDDCI#2 AC12 LV26 MS@
CV203
CV204
CV205
CV206
CV207
CV208
CV209
CV210
CV211
CV212
CV213
CV214
10U_0603_6.3V6M
22U_0603_6.3V6M
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
+VDDCI +VGA_CORE AN10 VDDCI#3 AC15 1 2
CV215
CV216
CV217
10U_0603_6.3V6M
1U_0402_6.3V6K
0.1U_0402_16V7K
SPVSS VDDCI#4 1 1 1 1 1 1 1 1 1 1 1 1
1 1 1 AD13 BLM15BD121SN1D_0402
VDDCI#5 AD16
1
VDDCI#6 M15
RV215 RV202 VDDCI#7 M16 2 2 2 2 2 2 2 2 2 2 2 2
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
2 2 2 10_0402_1% 10_0402_1% VDDCI#8 M18
DIS@
DIS@
DIS@
VOLTAGE
DIS@ DIS@ SENESE
VDDCI#9 M23
VDDCI#10 N13
10mil VDDCI#11
2
VCCSENSE_VGA AF28 N15

<53> VCCSENSE_VGA FB_VDDC VDDCI#12 N17
VDDCI#13 N20
CV325
CV324
CV322
CV323
10mil
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
1U_0402_6.3V6K
VDDCI_SEN AG28 VDDCI#14 N22
<54> VDDCI_SEN FB_VDDCI 1 1 1 1
ISOLATED VDDCI#15 R12
CORE I/O VDDCI#16 R13
VSSSENSE_VGA AH29 VDDCI#17 R16
<53> VSSSENSE_VGA FB_GND VDDCI#18 2 2 2 2
T12
DIS@
DIS@
DIS@
DIS@
VDDCI#19
1
T15
RV204 VDDCI#20 V15
DIS@ 10_0402_1% VDDCI#21 Y13
VDDCI#22
VDDCI and VDDC should have seperate regulators with a merge option on PCB
2
A 216-0833000-A11-THAMES-XT-M2_FCBGA962~D A
THR1@
For Madison, Park, Capilano, Robson, Seymour and Whistler, VDDCI and VDDC can share one common regulator

Deciphered Date
ATI_ThamesXT_M2_Power
1.0
LA-9102P
5 4 3 2 1
5 4 3 2 1
UV1C MDA[0..63] UV1D MDB[0..63]

<30> MDA[0..63] <31> MDB[0..63]
DDR2 DDR2 DDR2 DDR2
GDDR3/GDDR5 GDDR5/GDDR3 GDDR3/GDDR5 GDDR5/GDDR3
DDR3 DDR3 MAA[14..0] DDR3 DDR3 MAB[14..0]
MAA[14..0] <30> MAB[14..0] <31>
MDA0 C37 G24 MAA0 MDB0 C5 P8 MAB0
MDA1 C35 DQA0_0/DQA_0 MAA0_0/MAA_0 J23 MAA1 A_BA[2..0] MDB1 C3 DQB0_0/DQB_0 MAB0_0/MAB_0 T9 MAB1 B_BA[2..0]
DQA0_1/DQA_1 MAA0_1/MAA_1 A_BA[2..0] <30> DQB0_1/DQB_1 MAB0_1/MAB_1 B_BA[2..0] <31>
MDA2 A35 H24 MAA2 MDB2 E3 P9 MAB2
MDA3 E34 DQA0_2/DQA_2 MAA0_2/MAA_2 J24 MAA3 MDB3 E1 DQB0_2/DQB_2 MAB0_2/MAB_2 N7 MAB3
MDA4 G32 DQA0_3/DQA_3 MAA0_3/MAA_3 H26 MAA4 MDB4 F1 DQB0_3/DQB_3 MAB0_3/MAB_3 N8 MAB4
MEMORY INTERFACE A
MDA5 D33 DQA0_4/DQA_4 MAA0_4/MAA_4 J26 MAA5 MDB5 F3 DQB0_4/DQB_4 MAB0_4/MAB_4 N9 MAB5
MEMORY INTERFACE B
MDA6 F32 DQA0_5/DQA_5 MAA0_5/MAA_5 H21 MAA6 MDB6 F5 DQB0_5/DQB_5 MAB0_5/MAB_5 U9 MAB6
MDA7 E32 DQA0_6/DQA_6 MAA0_6/MAA_6 G21 MAA7 MDB7 G4 DQB0_6/DQB_6 MAB0_6/MAB_6 U8 MAB7
MDA8 D31 DQA0_7/DQA_7 MAA0_7/MAA_7 H19 MAA8 MDB8 H5 DQB0_7/DQB_7 MAB0_7/MAB_7 Y9 MAB8
MDA9 F30 DQA0_8/DQA_8 MAA1_0/MAA_8 H20 MAA9 MDB9 H6 DQB0_8/DQB_8 MAB1_0/MAB_8 W9 MAB9
MDA10 C30 DQA0_9/DQA_9 MAA1_1/MAA_9 L13 MAA10 MDB10 J4 DQB0_9/DQB_9 MAB1_1/MAB_9 AC8 MAB10
D D
MDA11 A30 DQA0_10/DQA_10 MAA1_2/MAA_10 G16 MAA11 MDB11 K6 DQB0_10/DQB_10 MAB1_2/MAB_10 AC9 MAB11
MDA12 F28 DQA0_11/DQA_11 MAA1_3/MAA_11 J16 MAA12 MDB12 K5 DQB0_11/DQB_11 MAB1_3/MAB_11 AA7 MAB12
MDA13 C28 DQA0_12/DQA_12 MAA1_4/MAA_12 H16 A_BA2 MDB13 L4 DQB0_12/DQB_12 MAB1_4/MAB_12 AA8 B_BA2
MDA14 A28 DQA0_13/DQA_13 MAA1_5/MAA_13_BA2 J17 A_BA0 MDB14 M6 DQB0_13/DQB_13 MAB1_5/BA2 Y8 B_BA0
MDA15 E28 DQA0_14/DQA_14 MAA1_6/MAA_14_BA0 H17 A_BA1 MDB15 M1 DQB0_14/DQB_14 MAB1_6/BA0 AA9 B_BA1
MDA16 D27 DQA0_15/DQA_15 MAA1_7/MAA_A15_BA1 MDB16 M3 DQB0_15/DQB_15 MAB1_7/BA1
DQA0_16/DQA_16 DQMA#[7..0] <30> DQB0_16/DQB_16 DQMB#[7..0] <31>
MDA17 F26 A32 DQMA#0 MDB17 M5 H3 DQMB#0
MDA18 C26 DQA0_17/DQA_17 WCKA0_0/DQMA_0 C32 DQMA#1 MDB18 N4 DQB0_17/DQB_17 WCKB0_0/DQMB_0 H1 DQMB#1
MDA19 A26 DQA0_18/DQA_18 WCKA0B_0/DQMA_1 D23 DQMA#2 MDB19 P6 DQB0_18/DQB_18 WCKB0B_0/DQMB_1 T3 DQMB#2
MDA20 F24 DQA0_19/DQA_19 WCKA0_1/DQMA_2 E22 DQMA#3 MDB20 P5 DQB0_19/DQB_19 WCKB0_1/DQMB_2 T5 DQMB#3
MDA21 C24 DQA0_20/DQA_20 WCKA0B_1/DQMA_3 C14 DQMA#4 MDB21 R4 DQB0_20/DQB_20 WCKB0B_1/DQMB_3 AE4 DQMB#4
MDA22 A24 DQA0_21/DQA_21 WCKA1_0/DQMA_4 A14 DQMA#5 MDB22 T6 DQB0_21/DQB_21 WCKB1_0/DQMB_4 AF5 DQMB#5
MDA23 E24 DQA0_22/DQA_22 WCKA1B_0/DQMA_5 E10 DQMA#6 MDB23 T1 DQB0_22/DQB_22 WCKB1B_0/DQMB_5 AK6 DQMB#6
MDA24 C22 DQA0_23/DQA_23 WCKA1_1/DQMA_6 D9 DQMA#7 MDB24 U4 DQB0_23/DQB_23 WCKB1_1/DQMB_6 AK5 DQMB#7
MDA25 A22 DQA0_24/DQA_24 WCKA1B_1/DQMA_7 MDB25 V6 DQB0_24/DQB_24 WCKB1B_1/DQMB_7
DQA0_25/DQA_25 GDDR5/DDR2/GDDR3 QSA[7..0] <30> DQB0_25/DQB_25 GDDR5/DDR2/GDDR3 QSB[7..0] <31>
MDA26 F22 C34 QSA0 MDB26 V1 F6 QSB0
MDA27 D21 DQA0_26/DQA_26 EDCA0_0/QSA_0/RDQSA_0 D29 QSA1 MDB27 V3 DQB0_26/DQB_26 EDCB0_0/QSB_0/RDQSB_0 K3 QSB1
MDA28 A20 DQA0_27/DQA_27 EDCA0_1/QSA_1/RDQSA_1 D25 QSA2 MDB28 Y6 DQB0_27/DQB_27 EDCB0_1/QSB_1/RDQSB_1 P3 QSB2
MDA29 F20 DQA0_28/DQA_28 EDCA0_2/QSA_2/RDQSA_2 E20 QSA3 MDB29 Y1 DQB0_28/DQB_28 EDCB0_2/QSB_2/RDQSB_2 V5 QSB3
MDA30 D19 DQA0_29/DQA_29 EDCA0_3/QSA_3/RDQSA_3 E16 QSA4 MDB30 Y3 DQB0_29/DQB_29 EDCB0_3/QSB_3/RDQSB_3 AB5 QSB4
MDA31 E18 DQA0_30/DQA_30 EDCA1_0/QSA_4/RDQSA_4 E12 QSA5 MDB31 Y5 DQB0_30/DQB_30 EDCB1_0/QSB_4/RDQSB_4 AH1 QSB5
MDA32 C18 DQA0_31/DQA_31 EDCA1_1/QSA_5/RDQSA_5 J10 QSA6 MDB32 AA4 DQB0_31/DQB_31 EDCB1_1/QSB_5/RDQSB_5 AJ9 QSB6
MDA33 A18 DQA1_0/DQA_32 EDCA1_2/QSA_6/RDQSA_6 D7 QSA7 MDB33 AB6 DQB1_0/DQB_32 EDCB1_2/QSB_6/RDQSB_6 AM5 QSB7
DQA1_1/DQA_33 EDCA1_3/QSA_7/RDQSA_7 QSA#[7..0] <30> DQB1_1/DQB_33 EDCB1_3/QSB_7/RDQSB_7 QSB#[7..0] <31>
MDA34 F18 MDB34 AB1
MDA35 D17 DQA1_2/DQA_34 A34 QSA#0 MDB35 AB3 DQB1_2/DQB_34 G7 QSB#0
MDA36 A16 DQA1_3/DQA_35 DDBIA0_0/QSA_0B/WDQSA_0 E30 QSA#1 MDB36 AD6 DQB1_3/DQB_35 DDBIB0_0/QSB_0B/WDQSB_0 K1 QSB#1
MDA37 F16 DQA1_4/DQA_36 DDBIA0_1/QSA_1B/WDQSA_1 E26 QSA#2 MDB37 AD1 DQB1_4/DQB_36 DDBIB0_1/QSB_1B/WDQSB_1 P1 QSB#2
MDA38 D15 DQA1_5/DQA_37 DDBIA0_2/QSA_2B/WDQSA_2 C20 QSA#3 MDB38 AD3 DQB1_5/DQB_37 DDBIB0_2/QSB_2B/WDQSB_2 W4 QSB#3
MDA39 E14 DQA1_6/DQA_38 DDBIA0_3/QSA_3B/WDQSA_3 C16 QSA#4 MDB39 AD5 DQB1_6/DQB_38 DDBIB0_3/QSB_3B/WDQSB_3 AC4 QSB#4
MDA40 F14 DQA1_7/DQA_39 DDBIA1_0/QSA_4B/WDQSA_4 C12 QSA#5 MDB40 AF1 DQB1_7/DQB_39 DDBIB1_0/QSB_4B/WDQSB_4 AH3 QSB#5
MDA41 D13 DQA1_8/DQA_40 DDBIA1_1/QSA_5B/WDQSA_5 J11 QSA#6 MDB41 AF3 DQB1_8/DQB_40 DDBIB1_1/QSB_5B/WDQSB_5 AJ8 QSB#6
MDA42 F12 DQA1_9/DQA_41 DDBIA1_2/QSA_6B/WDQSA_6 F8 QSA#7 MDB42 AF6 DQB1_9/DQB_41 DDBIB1_2/QSB_6B/WDQSB_6 AM3 QSB#7
MDA43 A12 DQA1_10/DQA_42 DDBIA1_3/QSA_7B/WDQSA_7 MDB43 AG4 DQB1_10/DQB_42 DDBIB1_3/QSB_7B/WDQSB_7
MDA44 D11 DQA1_11/DQA_43 J21 ODTA0 MDB44 AH5 DQB1_11/DQB_43 T7 ODTB0
DQA1_12/DQA_44 ADBIA0/ODTA0 ODTA0 <30> DQB1_12/DQB_44 ADBIB0/ODTB0 ODTB0 <31>
MDA45 F10 G19 ODTA1 MDB45 AH6 W7 ODTB1
DQA1_13/DQA_45 ADBIA1/ODTA1 ODTA1 <30> DQB1_13/DQB_45 ADBIB1/ODTB1 ODTB1 <31>
MDA46 A10 MDB46 AJ4
MDA47 C10 DQA1_14/DQA_46 H27 CLKA0 MDB47 AK3 DQB1_14/DQB_46 L9 CLKB0
C CLKA0 <30> CLKB0 <31> C
MDA48 G13 DQA1_15/DQA_47 CLKA0 G27 CLKA0# MDB48 AF8 DQB1_15/DQB_47 CLKB0 L8 CLKB0#
DQA1_16/DQA_48 CLKA0B CLKA0# <30> DQB1_16/DQB_48 CLKB0B CLKB0# <31>
MDA49 H13 MDB49 AF9
MDA50 J13 DQA1_17/DQA_49 J14 CLKA1 MDB50 AG8 DQB1_17/DQB_49 AD8 CLKB1
DQA1_18/DQA_50 CLKA1 CLKA1 <30> DQB1_18/DQB_50 CLKB1 CLKB1 <31>
MDA51 H11 H14 CLKA1# MDB51 AG7 AD7 CLKB1#
DQA1_19/DQA_51 CLKA1B CLKA1# <30> DQB1_19/DQB_51 CLKB1B CLKB1# <31>
MDA52 G10 MDB52 AK9
MDA53 G8 DQA1_20/DQA_52 K23 RASA0# MDB53 AL7 DQB1_20/DQB_52 T10 RASB0#
DQA1_21/DQA_53 RASA0B RASA0# <30> DQB1_21/DQB_53 RASB0B RASB0# <31>
MDA54 K9 K19 RASA1# MDB54 AM8 Y10 RASB1#
DQA1_22/DQA_54 RASA1B RASA1# <30> DQB1_22/DQB_54 RASB1B RASB1# <31>
MDA55 K10 MDB55 AM7
MDA56 G9 DQA1_23/DQA_55 K20 CASA0# MDB56 AK1 DQB1_23/DQB_55 W10 CASB0#
DQA1_24/DQA_56 CASA0B CASA0# <30> DQB1_24/DQB_56 CASB0B CASB0# <31>
MDA57 A8 K17 CASA1# MDB57 AL4 AA10 CASB1#
DQA1_25/DQA_57 CASA1B CASA1# <30> DQB1_25/DQB_57 CASB1B CASB1# <31>
MDA58 C8 MDB58 AM6
MDA59 E8 DQA1_26/DQA_58 K24 CSA0#_0 MDB59 AM1 DQB1_26/DQB_58 P10 CSB0#_0
DQA1_27/DQA_59 CSA0B_0 CSA0#_0 <30> DQB1_27/DQB_59 CSB0B_0 CSB0#_0 <31>
MDA60 A6 K27 MDB60 AN4 L10
MDA61 C6 DQA1_28/DQA_60 CSA0B_1 MDB61 AP3 DQB1_28/DQB_60 CSB0B_1
MDA62 E6 DQA1_29/DQA_61 M13 CSA1#_0 MDB62 AP1 DQB1_29/DQB_61 AD10 CSB1#_0
DQA1_30/DQA_62 CSA1B_0 CSA1#_0 <30> DQB1_30/DQB_62 CSB1B_0 CSB1#_0 <31>
MDA63 A5 K16 MDB63 AP5 AC10
DQA1_31/DQA_63 CSA1B_1 DQB1_31/DQB_63 CSB1B_1
+VDD_MEM15_REFDA L18 K21 CKEA0 U10 CKEB0
+1.5VGS MVREFDA CKEA0 CKEA0 <30> CKEB0 CKEB0 <31>
+VDD_MEM15_REFSA L20 J20 CKEA1 +VDD_MEM15_REFDB Y12 AA11 CKEB1
MVREFSA CKEA1 CKEA1 <30> MVREFDB CKEB1 CKEB1 <31>
+VDD_MEM15_REFSB AA12
RV129 1 TH@ 2 240_0402_1% L27 K26 WEA0# MVREFSB N10 WEB0#
MEM_CALRN0 WEA0B WEA0# <30> WEB0B WEB0# <31>
RV130 1 SE@ 2 240_0402_1% N12 L15 WEA1# AB11 WEB1#
MEM_CALRN1 WEA1B WEA1# <30> WEB1B WEB1# <31>
RV131 1 TH@ 2 240_0402_1% AG12
MEM_CALRN2 DIS@
RV132 1 SE@ 2 240_0402_1% M12 H23 MAA13 RV133 1 2 TESTEN AD28 T8 MAB13
MEM_CALRP1 MAA0_8 MAA13 <29,30> TESTEN MAB0_8 MAB13 <29,31>
RV134 1 TH@ 2 240_0402_1% M27 J19 MAA14 5.11K_0402_1% W8 MAB14
MEM_CALRP0 MAA1_8 MAA14 <29,30> MAB1_8 MAB14 <29,31>
RV135 1 TH@ 2 240_0402_1% AH12 AK10
GDDR5
MEM_CALRP2 AL10 CLKTESTA AH11
GDDR5
DRAM_RST#_R
RV206 1 MS@ 2 120_0402_5% CLKTESTB DRAM_RST
RV205 1 @ 2 120_0402_5%
216-0833000-A11-THAMES-XT-M2_FCBGA962~D 216-0833000-A11-THAMES-XT-M2_FCBGA962~D
THR1@ THR1@
B B
1
@ @
CV218 CV219
0.1U_0402_16V7K 0.1U_0402_16V7K
2
Co-lay Thames/Seymour/Mars Pro route 50ohms single-ended/100ohms diff
This basic topology should be used for DRAM_RST for DDR3/GDDR5.These and keep short
Thames M2 Seymour M2 Mars Pro Capacitors and Resistor values are an example only. The Series R and
1
|| Cap values will depend on the DRAM load and will have to be Debug only, for clock observation, if not needed, DNI
RV129 TH@ @ @ @ @ 5mil 5mil
calculated for different Memory ,DRAM Load and board to pass Reset RV136 RV137
RV130 @ SE@ @ Signal Spec. 51.1_0402_1% 51.1_0402_1%
Place all these components very close to GPU (Within
2
RV131 TH@ @ @ 25mm) and keep all component close to each Other (within
5mm) except Rser2
RV132 @ SE@ @
RV134 TH@ @ @ +1.5VGS
RV135 TH@ @ @
1
RV206 @ @ MS@
RV138
RV205 @ @ @ 4.7K_0402_5% +1.5VGS +1.5VGS
@
2
1
RV141 RV142
40.2_0402_1% 40.2_0402_1%
+1.5VGS +1.5VGS 1 RV143 2 1 RV144 2 DRAM_RST#_R DIS@ DIS@
<30,31> DRAM_RST# 51.1_0402_1% 10_0402_1%
2
DIS@ DIS@
1
+VDD_MEM15_REFDB +VDD_MEM15_REFSB
2
RV139 RV140
1
40.2_0402_1% 40.2_0402_1% DIS@ DIS@
1
DIS@ DIS@ CV222 RV145 CV223 CV224
120P_0402_50V9 4.99K_0402_1% RV148 0.1U_0402_16V7K RV149 0.1U_0402_16V7K
2
100_0402_1% DIS@ 100_0402_1% DIS@

1
2
A +VDD_MEM15_REFDA +VDD_MEM15_REFSA DIS@ A
DIS@
2
1
CV220 CV221
RV146 0.1U_0402_16V7K RV147 0.1U_0402_16V7K
100_0402_1% DIS@ 100_0402_1% DIS@
2
DIS@ DIS@
2

Deciphered Date
ATI_ThamesXT_M2_MEM IF
1.0
LA-9102P
5 4 3 2 1
5 4 3 2 1
CHANNEL A: 256MB/512MB DDR3

UV18 UV19 UV20 UV21
VREFC_A1 M8 E3 MDA29 VREFC_A2 M8 E3 MDA18 VREFC_A3 M8 E3 MDA38 VREFC_A4 M8 E3 MDA55

VREFD_Q1 H1 VREFCA DQL0 F7 MDA27 VREFD_Q2 H1 VREFCA DQL0 F7 MDA23 VREFD_Q3 H1 VREFCA DQL0 F7 MDA36 VREFD_Q4 H1 VREFCA DQL0 F7 MDA51
VREFDQ DQL1 F2 MDA30 VREFDQ DQL1 F2 MDA19 VREFDQ DQL1 F2 MDA39 VREFDQ DQL1 F2 MDA50
MAA0 N3 DQL2 F8 MDA26 MAA0 N3 DQL2 F8 MDA20 MAA0 N3 DQL2 F8 MDA34 MAA0 N3 DQL2 F8 MDA52
MAA1 P7 A0 DQL3 H3 MDA28 MAA1 P7 A0 DQL3 H3 MDA17 MAA1 P7 A0 DQL3 H3 MDA35 MAA1 P7 A0 DQL3 H3 MDA48
D D
MAA3 N2 A2 DQL5 G2 MDA31 MAA3 N2 A2 DQL5 G2 MDA16 MAA3 N2 A2 DQL5 G2 MDA37 MAA3 N2 A2 DQL5 G2 MDA49
MAA5 P2 A4 DQL7 MAA5 P2 A4 DQL7 MAA5 P2 A4 DQL7 MAA5 P2 A4 DQL7
MAA6 R8 A5 MAA6 R8 A5 MAA6 R8 A5 MAA6 R8 A5
MDA[0..63] MAA7 R2 A6 D7 MDA0 MAA7 R2 A6 D7 MDA15 MAA7 R2 A6 D7 MDA42 MAA7 R2 A6 D7 MDA60
<29> MDA[0..63] A7 DQU0 A7 DQU0 A7 DQU0 A7 DQU0
MAA8 T8 C3 MDA5 MAA8 T8 C3 MDA10 MAA8 T8 C3 MDA44 MAA8 T8 C3 MDA58
MAA9 R3 A8 DQU1 C8 MDA1 MAA9 R3 A8 DQU1 C8 MDA14 MAA9 R3 A8 DQU1 C8 MDA40 MAA9 R3 A8 DQU1 C8 MDA63
MAA10 L7 A9 DQU2 C2 MDA6 MAA10 L7 A9 DQU2 C2 MDA11 MAA10 L7 A9 DQU2 C2 MDA46 MAA10 L7 A9 DQU2 C2 MDA56
MAA11 R7 A10/AP DQU3 A7 MDA3 MAA11 R7 A10/AP DQU3 A7 MDA13 MAA11 R7 A10/AP DQU3 A7 MDA43 MAA11 R7 A10/AP DQU3 A7 MDA61
MAA12 N7 A11 DQU4 A2 MDA4 MAA12 N7 A11 DQU4 A2 MDA9 MAA12 N7 A11 DQU4 A2 MDA45 MAA12 N7 A11 DQU4 A2 MDA59
MAA[14..0] MAA13 T3 A12/BC DQU5 B8 MDA2 MAA13 T3 A12/BC DQU5 B8 MDA12 MAA13 T3 A12/BC DQU5 B8 MDA41 MAA13 T3 A12/BC DQU5 B8 MDA62
<29> MAA[14..0] A13 DQU6 A13 DQU6 A13 DQU6 A13 DQU6
MAA14 T7 A3 MDA7 MAA14 T7 A3 MDA8 MAA14 T7 A3 MDA47 MAA14 T7 A3 MDA57
A14 DQU7 A14 DQU7 A14 DQU7 A14 DQU7
+1.5VGS +1.5VGS +1.5VGS +1.5VGS
M2 B2 A_BA0 M2 B2 A_BA0 M2 B2 A_BA0 M2 B2

<29> A_BA0 BA0 VDD BA0 VDD BA0 VDD BA0 VDD
N8 D9 A_BA1 N8 D9 A_BA1 N8 D9 A_BA1 N8 D9
<29> A_BA1 BA1 VDD BA1 VDD BA1 VDD BA1 VDD
DQMA#[7..0] M3 G7 A_BA2 M3 G7 A_BA2 M3 G7 A_BA2 M3 G7
<29> DQMA#[7..0] <29> A_BA2 BA2 VDD BA2 VDD BA2 VDD BA2 VDD
K2 K2 K2 K2
VDD K8 VDD K8 VDD K8 VDD K8
VDD N1 VDD N1 VDD N1 VDD N1
J7 VDD N9 CLKA0 J7 VDD N9 J7 VDD N9 CLKA1 J7 VDD N9
<29> CLKA0 CK VDD CK VDD <29> CLKA1 CK VDD CK VDD
K7 R1 CLKA0# K7 R1 K7 R1 CLKA1# K7 R1
<29> CLKA0# CK VDD CK VDD <29> CLKA1# CK VDD CK VDD
QSA[7..0] K9 R9 CKEA0 K9 R9 K9 R9 CKEA1 K9 R9
<29> QSA[7..0] <29> CKEA0 CKE VDD +1.5VGS CKE VDD +1.5VGS <29> CKEA1 CKE VDD +1.5VGS CKE VDD +1.5VGS
K1 A1 ODTA0 K1 A1 K1 A1 ODTA1 K1 A1
<29> ODTA0 ODT VDDQ ODT VDDQ <29> ODTA1 ODT VDDQ ODT VDDQ
L2 A8 CSA0#_0 L2 A8 L2 A8 CSA1#_0 L2 A8
<29> CSA0#_0 CS VDDQ CS VDDQ <29> CSA1#_0 CS VDDQ CS VDDQ
J3 C1 RASA0# J3 C1 J3 C1 RASA1# J3 C1
<29> RASA0# RAS VDDQ RAS VDDQ <29> RASA1# RAS VDDQ RAS VDDQ
K3 C9 CASA0# K3 C9 K3 C9 CASA1# K3 C9
<29> CASA0# CAS VDDQ CAS VDDQ <29> CASA1# CAS VDDQ CAS VDDQ
QSA#[7..0] L3 D2 WEA0# L3 D2 L3 D2 WEA1# L3 D2
<29> QSA#[7..0] <29> WEA0# WE VDDQ WE VDDQ <29> WEA1# WE VDDQ WE VDDQ
E9 E9 E9 E9
VDDQ F1 VDDQ F1 VDDQ F1 VDDQ F1
QSA3 F3 VDDQ H2 QSA2 F3 VDDQ H2 QSA4 F3 VDDQ H2 QSA6 F3 VDDQ H2
QSA0 C7 DQSL VDDQ H9 QSA1 C7 DQSL VDDQ H9 QSA5 C7 DQSL VDDQ H9 QSA7 C7 DQSL VDDQ H9
DQSU VDDQ DQSU VDDQ DQSU VDDQ DQSU VDDQ
C C
DQMA#3 E7 A9 DQMA#2 E7 A9 DQMA#4 E7 A9 DQMA#6 E7 A9
DQMA#0 D3 DML VSS B3 DQMA#1 D3 DML VSS B3 DQMA#5 D3 DML VSS B3 DQMA#7 D3 DML VSS B3
DMU VSS E1 DMU VSS E1 DMU VSS E1 DMU VSS E1
VSS G8 VSS G8 VSS G8 VSS G8
QSA#3 G3 VSS J2 QSA#2 G3 VSS J2 QSA#4 G3 VSS J2 QSA#6 G3 VSS J2
QSA#0 B7 DQSL VSS J8 QSA#1 B7 DQSL VSS J8 QSA#5 B7 DQSL VSS J8 QSA#7 B7 DQSL VSS J8
DQSU VSS M1 DQSU VSS M1 DQSU VSS M1 DQSU VSS M1
VSS M9 VSS M9 VSS M9 VSS M9
VSS P1 VSS P1 VSS P1 VSS P1
T2 VSS P9 DRAM_RST# T2 VSS P9 DRAM_RST# T2 VSS P9 DRAM_RST# T2 VSS P9
<29,31> DRAM_RST# RESET VSS RESET VSS RESET VSS RESET VSS
T1 T1 T1 T1
L8 VSS T9 L8 VSS T9 L8 VSS T9 L8 VSS T9
ZQ VSS ZQ VSS ZQ VSS ZQ VSS
1
1
J1 B1 J1 B1 J1 B1 J1 B1
RV150 L1 NC VSSQ B9 RV151 L1 NC VSSQ B9 RV152 L1 NC VSSQ B9 RV153 L1 NC VSSQ B9
J9 NC VSSQ D1 J9 NC VSSQ D1 J9 NC VSSQ D1 J9 NC VSSQ D1
240_0402_1% 240_0402_1% 240_0402_1% 240_0402_1%
DIS@ L9 NC VSSQ D8 DIS@ L9 NC VSSQ D8 DIS@ L9 NC VSSQ D8 DIS@ L9 NC VSSQ D8
M7 NC VSSQ E2 M7 NC VSSQ E2 M7 NC VSSQ E2 M7 NC VSSQ E2
2
2
NC VSSQ E8 NC VSSQ E8 NC VSSQ E8 NC VSSQ E8
VSSQ F9 VSSQ F9 VSSQ F9 VSSQ F9
VSSQ G1 VSSQ G1 VSSQ G1 VSSQ G1
VSSQ G9 VSSQ G9 VSSQ G9 VSSQ G9
VSSQ VSSQ VSSQ VSSQ
96-BALL 96-BALL 96-BALL 96-BALL
SDRAM DDR3L SDRAM DDR3L SDRAM DDR3L SDRAM DDR3L
DIS@ K4W2G1646E-BC11_FBGA96~D K4W2G1646E-BC11_FBGA96~D K4W2G1646E-BC11_FBGA96~D K4W2G1646E-BC11_FBGA96~D
CLKA0 1 2
RV154 56_0402_1%
DIS@
CLKA0# 1 2
RV155 56_0402_1%
1
CV225
0.01U_0402_16V7K
DIS@ +1.5VGS +1.5VGS +1.5VGS +1.5VGS +1.5VGS +1.5VGS +1.5VGS +1.5VGS
B B
2
1
RV156 RV157 RV158 RV159 RV160 RV161 RV162 RV163
4.99K_0402_1% 4.99K_0402_1% 4.99K_0402_1% 4.99K_0402_1% 4.99K_0402_1% 4.99K_0402_1% 4.99K_0402_1% 4.99K_0402_1%
DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@
DIS@
15mil 15mil 15mil 15mil 15mil 15mil 15mil 15mil
2
2
CLKA1 1 2
RV164 56_0402_1% VREFD_Q1 VREFC_A1 VREFC_A2 VREFD_Q2 VREFC_A3 VREFD_Q3 VREFC_A4 VREFD_Q4
1
1
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
DIS@
CV226
CV227
CV228
CV229
CV230
CV231
CV232
1
1
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
CLKA1# 1 2 RV166 RV167 RV168 RV169 RV170 RV171 RV172 RV173
CV233
RV165 56_0402_1% 4.99K_0402_1% 4.99K_0402_1% 4.99K_0402_1% 4.99K_0402_1% 4.99K_0402_1% 4.99K_0402_1% 4.99K_0402_1% 4.99K_0402_1%
1
CV234 DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@
2
2
0.01U_0402_16V7K DIS@ DIS@ DIS@
2
2
DIS@
2
+1.5VGS
+1.5VGS
+1.5VGS +1.5VGS
CV235
CV236
CV237
CV238
CV239
CV240
CV241
CV242
CV243
CV244
CV245
CV246
CV247
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
CV248
CV249
CV250
CV251
CV252
CV253
CV254
CV255
CV256
CV257
CV258
CV259
CV260
CV261
CV262
CV263
CV264
CV265
CV266
CV267
CV268
CV269
CV270
CV271
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1 1 1 1 1 1 1 1 1 1 1 1 1
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
2 2 2 2 2 2 2 2 2 2 2 2 2
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
A A

Deciphered Date
ATI_ThamesXT_M2_VRAM_A
1.0
5 4 3 2 1
5 4 3 2 1
CHANNEL B: 256MB/512MB DDR3

UV22 UV23 UV24 UV25
VREFC_A1_B M8 E3 MDB29 VREFC_A2_B M8 E3 MDB16 VREFC_A3_B M8 E3 MDB33 VREFC_A4_B M8 E3 MDB55

VREFD_Q1_B H1 VREFCA DQL0 F7 MDB26 VREFD_Q2_B H1 VREFCA DQL0 F7 MDB19 VREFD_Q3_B H1 VREFCA DQL0 F7 MDB37 VREFD_Q4_B H1 VREFCA DQL0 F7 MDB50
MDB[0..63] VREFDQ DQL1 F2 MDB30 VREFDQ DQL1 F2 MDB20 VREFDQ DQL1 F2 MDB35 VREFDQ DQL1 F2 MDB54
<29> MDB[0..63] DQL2 DQL2 DQL2 DQL2
MAB0 N3 F8 MDB27 MAB0 N3 F8 MDB22 MAB0 N3 F8 MDB39 MAB0 N3 F8 MDB51
MAB1 P7 A0 DQL3 H3 MDB31 MAB1 P7 A0 DQL3 H3 MDB17 MAB1 P7 A0 DQL3 H3 MDB32 MAB1 P7 A0 DQL3 H3 MDB53
D D
MAB3 N2 A2 DQL5 G2 MDB28 MAB3 N2 A2 DQL5 G2 MDB18 MAB3 N2 A2 DQL5 G2 MDB34 MAB3 N2 A2 DQL5 G2 MDB52
MAB[14..0] MAB5 P2 A4 DQL7 MAB5 P2 A4 DQL7 MAB5 P2 A4 DQL7 MAB5 P2 A4 DQL7
<29> MAB[14..0] A5 A5 A5 A5
MAB6 R8 MAB6 R8 MAB6 R8 MAB6 R8
MAB7 R2 A6 D7 MDB0 MAB7 R2 A6 D7 MDB15 MAB7 R2 A6 D7 MDB44 MAB7 R2 A6 D7 MDB56
MAB8 T8 A7 DQU0 C3 MDB4 MAB8 T8 A7 DQU0 C3 MDB10 MAB8 T8 A7 DQU0 C3 MDB41 MAB8 T8 A7 DQU0 C3 MDB59
MAB9 R3 A8 DQU1 C8 MDB1 MAB9 R3 A8 DQU1 C8 MDB14 MAB9 R3 A8 DQU1 C8 MDB47 MAB9 R3 A8 DQU1 C8 MDB63
MAB10 L7 A9 DQU2 C2 MDB6 MAB10 L7 A9 DQU2 C2 MDB11 MAB10 L7 A9 DQU2 C2 MDB43 MAB10 L7 A9 DQU2 C2 MDB62
MAB11 R7 A10/AP DQU3 A7 MDB3 MAB11 R7 A10/AP DQU3 A7 MDB12 MAB11 R7 A10/AP DQU3 A7 MDB45 MAB11 R7 A10/AP DQU3 A7 MDB57
DQMB#[7..0] MAB12 N7 A11 DQU4 A2 MDB7 MAB12 N7 A11 DQU4 A2 MDB9 MAB12 N7 A11 DQU4 A2 MDB40 MAB12 N7 A11 DQU4 A2 MDB61
<29> DQMB#[7..0] A12/BC DQU5 A12/BC DQU5 A12/BC DQU5 A12/BC DQU5
MAB13 T3 B8 MDB2 MAB13 T3 B8 MDB13 MAB13 T3 B8 MDB46 MAB13 T3 B8 MDB58
MAB14 T7 A13 DQU6 A3 MDB5 MAB14 T7 A13 DQU6 A3 MDB8 MAB14 T7 A13 DQU6 A3 MDB42 MAB14 T7 A13 DQU6 A3 MDB60
A14 DQU7 A14 DQU7 A14 DQU7 A14 DQU7
+1.5VGS +1.5VGS +1.5VGS +1.5VGS
QSB[7..0] M2 B2 B_BA0 M2 B2 B_BA0 M2 B2 B_BA0 M2 B2

<29> QSB[7..0] <29> B_BA0 BA0 VDD BA0 VDD BA0 VDD BA0 VDD
N8 D9 B_BA1 N8 D9 B_BA1 N8 D9 B_BA1 N8 D9
<29> B_BA1 BA1 VDD BA1 VDD BA1 VDD BA1 VDD
M3 G7 B_BA2 M3 G7 B_BA2 M3 G7 B_BA2 M3 G7
<29> B_BA2 BA2 VDD BA2 VDD BA2 VDD BA2 VDD
K2 K2 K2 K2
VDD K8 VDD K8 VDD K8 VDD K8
VDD N1 VDD N1 VDD N1 VDD N1
J7 VDD N9 CLKB0 J7 VDD N9 J7 VDD N9 CLKB1 J7 VDD N9
<29> CLKB0 CK VDD CK VDD <29> CLKB1 CK VDD CK VDD
QSB#[7..0] K7 R1 CLKB0# K7 R1 K7 R1 CLKB1# K7 R1
<29> QSB#[7..0] <29> CLKB0# CK VDD CK VDD <29> CLKB1# CK VDD CK VDD
K9 R9 CKEB0 K9 R9 K9 R9 CKEB1 K9 R9
<29> CKEB0 CKE VDD +1.5VGS CKE VDD +1.5VGS <29> CKEB1 CKE VDD +1.5VGS CKE VDD +1.5VGS
K1 A1 ODTB0 K1 A1 K1 A1 ODTB1 K1 A1
<29> ODTB0 ODT VDDQ ODT VDDQ <29> ODTB1 ODT VDDQ ODT VDDQ
L2 A8 CSB0#_0 L2 A8 L2 A8 CSB1#_0 L2 A8
<29> CSB0#_0 CS VDDQ CS VDDQ <29> CSB1#_0 CS VDDQ CS VDDQ
J3 C1 RASB0# J3 C1 J3 C1 RASB1# J3 C1
<29> RASB0# RAS VDDQ RAS VDDQ <29> RASB1# RAS VDDQ RAS VDDQ
K3 C9 CASB0# K3 C9 K3 C9 CASB1# K3 C9
<29> CASB0# CAS VDDQ CAS VDDQ <29> CASB1# CAS VDDQ CAS VDDQ
L3 D2 WEB0# L3 D2 L3 D2 WEB1# L3 D2
<29> WEB0# WE VDDQ WE VDDQ <29> WEB1# WE VDDQ WE VDDQ
E9 E9 E9 E9
VDDQ F1 VDDQ F1 VDDQ F1 VDDQ F1
DIS@ QSB3 F3 VDDQ H2 QSB2 F3 VDDQ H2 QSB4 F3 VDDQ H2 QSB6 F3 VDDQ H2
CLKB0 1 2 QSB0 C7 DQSL VDDQ H9 QSB1 C7 DQSL VDDQ H9 QSB5 C7 DQSL VDDQ H9 QSB7 C7 DQSL VDDQ H9
RV174 56_0402_1% DQSU VDDQ DQSU VDDQ DQSU VDDQ DQSU VDDQ
C C
DIS@ DQMB#3 E7 A9 DQMB#2 E7 A9 DQMB#4 E7 A9 DQMB#6 E7 A9
CLKB0# 1 2 DQMB#0 D3 DML VSS B3 DQMB#1 D3 DML VSS B3 DQMB#5 D3 DML VSS B3 DQMB#7 D3 DML VSS B3
RV175 56_0402_1% DMU VSS E1 DMU VSS E1 DMU VSS E1 DMU VSS E1
VSS G8 VSS G8 VSS G8 VSS G8
VSS VSS VSS VSS
1
CV272 QSB#3 G3 J2 QSB#2 G3 J2 QSB#4 G3 J2 QSB#6 G3 J2

0.01U_0402_16V7K QSB#0 B7 DQSL VSS J8 QSB#1 B7 DQSL VSS J8 QSB#5 B7 DQSL VSS J8 QSB#7 B7 DQSL VSS J8
DIS@ DQSU VSS M1 DQSU VSS M1 DQSU VSS M1 DQSU VSS M1
2
VSS M9 VSS M9 VSS M9 VSS M9

VSS P1 VSS P1 VSS P1 VSS P1
T2 VSS P9 DRAM_RST# T2 VSS P9 DRAM_RST# T2 VSS P9 DRAM_RST# T2 VSS P9
<29,30> DRAM_RST# RESET VSS RESET VSS RESET VSS RESET VSS
T1 T1 T1 T1
L8 VSS T9 L8 VSS T9 L8 VSS T9 L8 VSS T9
ZQ VSS ZQ VSS ZQ VSS ZQ VSS
DIS@
1
1
CLKB1 1 2 J1 B1 J1 B1 J1 B1 J1 B1
RV180 56_0402_1% RV176 L1 NC VSSQ B9 RV177 L1 NC VSSQ B9 RV178 L1 NC VSSQ B9 RV179 L1 NC VSSQ B9
J9 NC VSSQ D1 J9 NC VSSQ D1 J9 NC VSSQ D1 J9 NC VSSQ D1
240_0402_1% 240_0402_1% 240_0402_1% 240_0402_1%
DIS@ DIS@ L9 NC VSSQ D8 DIS@ L9 NC VSSQ D8 DIS@ L9 NC VSSQ D8 DIS@ L9 NC VSSQ D8
CLKB1# 1 2 M7 NC VSSQ E2 M7 NC VSSQ E2 M7 NC VSSQ E2 M7 NC VSSQ E2
2
2
RV181 56_0402_1% NC VSSQ E8 NC VSSQ E8 NC VSSQ E8 NC VSSQ E8
VSSQ VSSQ VSSQ VSSQ
1
CV273 F9 F9 F9 F9
0.01U_0402_16V7K VSSQ G1 VSSQ G1 VSSQ G1 VSSQ G1
DIS@ VSSQ G9 VSSQ G9 VSSQ G9 VSSQ G9
2
VSSQ VSSQ VSSQ VSSQ

96-BALL 96-BALL 96-BALL 96-BALL
SDRAM DDR3L SDRAM DDR3L SDRAM DDR3L SDRAM DDR3L
K4W2G1646E-BC11_FBGA96~D K4W2G1646E-BC11_FBGA96~D K4W2G1646E-BC11_FBGA96~D K4W2G1646E-BC11_FBGA96~D
+1.5VGS +1.5VGS +1.5VGS +1.5VGS +1.5VGS +1.5VGS +1.5VGS +1.5VGS

B B
1
1
4.99K_0402_1% 4.99K_0402_1% 4.99K_0402_1% 4.99K_0402_1% 4.99K_0402_1% 4.99K_0402_1% 4.99K_0402_1% 4.99K_0402_1%
15mil 15mil 15mil 15mil 15mil 15mil 15mil 15mil
2
2
VREFD_Q1_B VREFC_A1_B VREFC_A2_B VREFD_Q2_B VREFC_A3_B VREFD_Q3_B VREFC_A4_B VREFD_Q4_B
CV274
CV275
CV276
CV277
CV278
CV279
CV280
CV281
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
1
1
1 1 1 1 1 1 1 1
4.99K_0402_1% 4.99K_0402_1% 4.99K_0402_1% 4.99K_0402_1% 4.99K_0402_1% 4.99K_0402_1% 4.99K_0402_1% 4.99K_0402_1%
2 2 2 2 2 2 2 2
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
2
2
+1.5VGS
+1.5VGS
+1.5VGS +1.5VGS
CV282
CV283
CV284
CV285
CV286
CV287
CV288
CV289
CV290
CV291
CV292
CV293
CV294
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
CV295
CV296
CV297
CV298
CV299
CV300
CV301
CV302
CV303
CV304
CV305
CV306
CV307
CV308
CV310
CV311
CV312
CV313
CV314
CV315
CV316
CV317
CV318
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1 1 1 1 1 1 1 1 1 1 1 1 1
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
2 2 2 2 2 2 2 2 2 2 2 2 2
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
A A

Deciphered Date
ATI_ThamesXT_M2_VRAM_B
1.0
5 4 3 2 1
5 4 3 2 1
W=40mils
+3VALW
JP3 @
2 1 +LAN_IO rising time : >1ms and <100ms
W=40mils
2MM
QL1
W=40mils +LAN_IO 1.5A
D
6
S
1 5 4
2
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
CL38
1U_0402_6.3V6K 1 1 1 1 1 1 1
SI3456DDV-T1-GE3_TSOP6~D
G
D B+_BIAS 2 CL15 CL19 CL16 CL17 CL18 CL27 D
3
+3VALW @ @
2 2 2 2 2 2
2
MCT0 1 RL19 2 75_0603_5%
RL18
2
470K_0402_5%
RL28 MCT1 1 RL20 2 75_0603_5%
10K_0402_5% These caps close to Pin 12,27,39,42,47,48
1
EN_WOL 1
2
For 8105E-VD pop the capacitor close pin 27,39,47,48
0.1U_0603_50V_X7R
Place close to TCT pin
1
2
D CL33
1
WOL_EN# 2 QL2 RL27 100P_1206_2KV8J @
<40> WOL_EN# 2
CL39
G 2N7002BKW_SOT323-3~D 1.5M_0402_5%
S DL11
3
1
PESD5V0U2BT_SOT23-3~D
+LAN_VDD
1
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
1 1 1 1 1 1 1 TL1
CL20 CL21 CL22 CL23 CL24 CL25 CL26 MDI1- 1 16 MDO1-

2
@
2 2
@
2
@
2
@
2 2
MDI1+ 2 RD+
RD-
RX+
RX-
15 MDO1+ DL11 as close as
3 14 MCT0
4
5
CT
NC
CT
NC
13
12
possible to C27
NC NC
MDI0-
6
7 CT CT
11
10
MCT1
MDO0-
and C32
MDI0+ 8 TD+ TX+ 9 MDO0+
TD- TX-
2
X'FORM_ NS0014
C C
CL41
CL28,C30 Close UL1 1
0.01U_0402_16V7K
UL1 These caps close to Pin 3,6,9,13,29,41,45
<14> PCIE_PRX_LANTX_P1
CL28 1 2 0.1U_0402_16V7K PCIE_CRX_C_DTX_P0 22
HSOP LED3/EEDO
31 For 8105E-VD pop capacitor close to pin 13,29,45
37
CL30 1 2 0.1U_0402_16V7K PCIE_CRX_C_DTX_N0 23 LED1/EESK 40
<14> PCIE_PRX_LANTX_N1 HSON LED0
17 30 RL23 1 @ 2 10K_0402_5%
<14> PCIE_PTX_LANRX_P1 HSIP EECS/SCL
18 32 RL24 1 2 10K_0402_5%
<14> PCIE_PTX_LANRX_N1 HSIN EEDI/SDA @
16 1 MDI0+
<14> LAN_CLKREQ# CLKREQB MDIP0 2 MDI0-
25 MDIN0 4 MDI1+
<16,38,40,6> PLT_RST# PERSTB MDIP1 5 MDI1-
19 MDIN1 7
<14> CLK_PCIE_LAN REFCLK_P NC/MDIP2
20 8
<14> CLK_PCIE_LAN# REFCLK_N NC/MDIN2 10 XTAL@
NC/MDIP3 11 CL36 RL30 0_0402_5%
XTLO 43 NC/MDIN3 1 2 2 1 XTLI
CKXTAL1
XTLI 44 13 12P_0402_50V8J YL2 XTAL@
CKXTAL2 DVDD10 +LAN_VDD
29 XTAL@ 1 2
+LAN_IO DVDD10 41 OSC GND
PCIE_WAKE# 28 DVDD10 3 4
<15,40> PCIE_WAKE# LANWAKEB OSC GND
10K_0402_5% ISOLATEB 26 27 CL37 25MHZ_10PF_7V25000014
RL34 1 2 PCIE_WAKE# ISOLATEB DVDD33 39 1 2 XTLO
DVDD33
14 12 +LAN_IO 12P_0402_50V8J
15 NC/SMBCLK AVDD33 42
NC/SMBDATA AVDD33
W=20mils XTAL@
38 47 +LAN_VDD
GPO/SMBALERT AVDD33 48 RL26
AVDD33 1 @ 2 +LAN_EVDD10
B B
ENSWREG 33
ENSWREG 21 +LAN_EVDD10 0_0603_1%
0.1U_0402_16V7K
1U_0402_6.3V6K
34 EVDD10
VDDREG 1 1
+LAN_VDDREG 35 3 +LAN_VDD
VDDREG AVDD10 6 CL34 CL35
AVDD10 9
1 RL31 2 2.49K_0402_1% 46 AVDD10 45 2 2
RSET AVDD10
24 36
49 GND
PGND
REGOUT
JLAN
RJ45 Conn. CLK_LAN_25M 2 1 XTLI
<14> CLK_LAN_25M
+3VS S IC RTL8105E-VD-CGT QFN 48P LAN CTRL 8 RL21 GCLK@
PR4- 0_0402_5%
1
7
PR4+
1
RL39 @
RL33 MDO1- 6 22_0402_5%
1K_0402_5% PR2-
5
2
PR3-
2
4
ENSWREG ISOLATEB PR3+
MDO1+ 3
PR2+
1
+LAN_IO MDO0- 2
PR1-
2
RL36
@ RL35 MDO0+ 1
0_0402_1% 15K_0402_5% PR1+
@ 9
SHLD1
2
RL37 10K_0402_5%
1
LAN_CLKREQ# 1 2 10
SHLD2
RL38 10K_0402_5%
WOL_EN# 1 2 SANTA_130456-311
A A
@ CONN@
3.3V : Enable switching regulator SP011207090
0V : Disable switching regulator
Reserve 10K pull LAN_IO DC234004V00 (OLD)
10/100：100@ (LDO mode used)
Issued Date 2012/09/25 Deciphered Date 2013/09/30 Title
LAN RTL8105E
1.0
LA-9102P
5 4 3 2 1
WWW.MANUALS.CLAN.SU
5 4 3 2 1
JACK_PLUG Delay cricutis
+3VS +3VS
+5V_PVDD +5VS
+5V_PVDD +5V_PVDD +5VA RA203
1
2 @ 1 JACK_SENSE#
1 1 1 1 1 RA1 @ RA2 @
+5VA +5VS
0.1U_0402_16V7K
CA56
10U_0603_6.3V6M
CA55
0.1U_0402_16V7K
CA54
10U_0603_6.3V6M
CA53
0.1U_0402_16V7K
CA51
4.7U_0603_6.3V6K
CA71
1 0_0603_1% 100K_0402_5%
10K_0402_5%
3
D RA204 D
2
2 2 2 2 2 2 @ 1 QA4B @
2
0_0603_1% QA4A @ 5 DMN66D0LDW-7_SOT363-6
6
4
+3VS
1
JACK_PLUG# 1 2 2 CA2 @
UA1
CA58 1 1 RA3 @ 10U_0603_6.3V6M
1
12 CA65 1 2 1 2 PC_BEEP 100K_0402_5% 2
PCBEEP 1
0.1U_0402_16V7K
4.7U_0603_6.3V6K
26 0.1U_0402_16V7K RA79 1K_0402_1%

CA57 41 AVDD1 16 CA1 @
2 2 +3VS PVDD1 MONO-OUT
CA59 1 CA60 1 46 @ CA365 1 2 100P_0402_50V8J 10U_0603_6.3V6M
PVDD2 24 2
CA59, CA60 4.7U_0603_6.3V6K 0.1U_0402_16V7K 1 LINE2-L(PORT-E-L) 23
DVDD LINE2-R(PORT-E-R)
Close to UA1 2 2
36
CPVDD 22
@ RA81 2 1 10K_0402_5%
Pin36 9 LINE1-L(PORT-C-L) 21
RA9 1 @ 2 0_0402_1% 40 DVDD-IO LINE1-R(PORT-C-R)
+1.5VS 1 AVDD2
+3VS RA10 1 2 0_0402_5%
@ CA61 20 JACK_PLUG# 1 @ 2 JACK_SENSE#
4.7U_0603_6.3V6K MIC1-R(PORT-B-R) 19 RA4 0_0402_1%
RA130 1 2 22_0402_5% 2 8 MIC1-L(PORT-B-L) @
<13> HDA_SDIN0 SDATA-IN Reserve for cancel Delay cricutis
<13> HDA_SDOUT_AUDIO
5 18 CA67 1 2 4.7U_0603_6.3V6K
RA129 1 2 22_0402_5% HDA_BITCLK 6 SDATA-OUT MIC2-R(PORT-F-R) 17 CA66 1 2 4.7U_0603_6.3V6K RA23 2 1 1K_0402_1% MIC_IN
<13> HDA_BITCLK_AUDIO BCLK MIC2-L(PORT-F-L)
<13> HDA_SYNC_AUDIO
10
11 SYNC
<13> HDA_RST_AUDIO# RESETB
14
HDA_RST_AUDIO# CA23 1 2 2.2U_0603_6.3V6K 28 SENSE B 13 RA51 1 2 39.2K_0402_1% JACK_SENSE#
RA153 1 2 20K_0402_1% 15 VREF SENSE A
1 JDREF
CA68
37 45 INT-SPK-R+ +MIC2-VREFO
0.1U_0402_16V7K CA24 1 2 1U_0402_6.3V6K 35 CBP SPK-OUT-R+ 44 INT-SPK-R-
2 CA25 1 2 1U_0402_6.3V6K 34 CBN SPK-OUT-R- 43 INT-SPK-L- RA25 1 @ 2 0_0603_1%
CPVEE SPK-OUT-L- 42 INT-SPK-L+
2
RA49 1 @ 2 0_0402_5% 31 SPK-OUT-L+ RA28 1 @ 2 0_0603_1%
C C
30 MIC1-VREFO-L RA53
Place close to UA1.11
+MIC2-VREFO RA50 1 @ 2 0_0402_1% 29 MIC1-VREFO-R 33 HPOUT-R RA29 1 @ 2 0_0603_1%
+MIC2-VREFO 2.2K_0402_5%
MIC2-VREFO HPOUT-R(PORT-I-R) 32 HPOUT-L
HPOUT-L(PORT-I-L) RA1107 RA30 1 @ 2 0_0603_1%
1
CA62 1 2 10U_0603_6.3V6M 27 22K_0402_1%
CA63 1 2 10U_0603_6.3V6M 39 LDO1-CAP 48 1 2 MIC_IN MIC_IN RA31 1 @ 2 0_0603_1%
CA64 1 2 10U_0603_6.3V6M 7 LDO2-CAP SPDIF-OUT/GPIO2
2
LDO3-CAP 2 MIC_DATA RA32 1 @ 2 0_0603_1%
GPIO0/DMIC-DATA MIC_DATA <21> 1
10U_0603_6.3V6M
CA70
HDA_BITCLK_AUDIO 4 3 MIC_CLK_C RA1108
25 DVSS GPIO1/DMIC-CLK
22K_0402_1%
38 AVSS1 47 EC_MUTE#
1 AVSS2 PDB EC_MUTE# <40>
CA21 2
1
49
22P_0402_50V8J Thermal PAD GNDA GND
2
Place on the moat between GND & GNDA.
ALC3221-CG_MQFN48_6X6~D
MIC_CLK_C 2 1 MIC_CLK MIC_CLK <21>

RA131
22_0402_5% 1
CA22 @
22P_0402_50V8J DA8
2 2
EC Beep <40> BEEP#
CA41
1 1 2 PC_BEEP
3 0.1U_0402_16V7K
ICH Beep <13> HDA_SPKR
1
BAT54C-7-F_SOT23-3
@ RA19
10K_0402_5%
PC Beep
2
B B
Close to UA1
Pin11,13,14,16
close to Codec JSPK
INT-SPK-R- LA3 1 2 0_0603_5%~D SPK_R1-_CONN 1
INT-SPK-R+ LA4 1 2 0_0603_5%~D SPK_R2+_CONN 2 1
iPhone type Combo Jack INT-SPK-L-

INT-SPK-L+
LA5
LA6
1
1
2
2
0_0603_5%~D
0_0603_5%~D
SPK_L1-_CONN
SPK_L2+_CONN
3
4
2
3 GND
4 GND
5
6
2
LA7 E&T_3703-Q04N-11R
Trace width for SPK-L+/SPK-L-/SPK-R+/SPK-R-
AZ5125-02S.R7G_SOT23-3
DA5
AZ5125-02S.R7G_SOT23-3
DA6
FBMA-L10-160808-800LMT_2P CONN@
1000P_0402_50V7K
1000P_0402_50V7K
1000P_0402_50V7K
1000P_0402_50V7K
JHP CONN@ 1 1 1 1
2 1 3
CA29
CA30
CA31
CA32
MIC_IN
SP02000H300
6 Speaker 4 ohm : 40mil
18_0402_5% LA8 FBMA-L10-160808-800LMT_2P 2 2 2 2
HPOUT-L RA55 1 2 AUD_HP_OUT_LL 2 1 AUD_HP_OUT_L_CN 1 Speaker 8 ohm : 20mil
18_0402_5% LA9 FBMA-L10-160808-800LMT_2P
1
HPOUT-R RA56 1 2 AUD_HP_OUT_RL 2 1 AUD_HP_OUT_R_CN 2
JACK_PLUG# 2 @ 1 AUD_HP_NB_SENSE_R 4 EMC@ EMC@
RA21 0_0402_1%
SINGA_2SJ-E960-001F
A A
3
DC230007Y00
AZ5125-02S.R7G_SOT23-3
DA10
AZ5125-02S.R7G_SOT23-3
DA12
1 1 1 DC021103300 (OLD)
100P_0402_50V8J
CA39
100P_0402_50V8J
CA33
100P_0402_50V8J
CA38
2 2 2
1

Deciphered Date
Audio Codec ALC3221
EMC@ EMC@ Size Document Number Rev
1.0
LA-9102P
5 4 3 2 1
5 4 3 2 1
D D
SD_CD# MS_INS#
1 1
CR9 CR10
0.1U_0402_16V7K 0.1U_0402_16V7K
+3VS +VCC_3IN1 2 2
WCM-2012HS-900T_4P
Trace width:40mil For ESD request.
USB20_CR_P10 1 2 USB20_CR_P10_R
<16> USB20_CR_P10 1 2 Place close to UR1
5
USB20_CR_N10 4 3 USB20_CR_N10_R UR1
<16> USB20_CR_N10 4 3
3V3_IN
CARD_3V3
LR2 EMC@ RR1 2 1 6.19K_0402_1% RREF 1 22 MS_BS
1 2 RREF SP14 21 SD_D2
RR8 @ 0_0402_5% SP13 20 MS_D1_SD_D3
USB20_CR_N10_R 2
DM
SP12
SP11
19 close to chip side
1 2 USB20_CR_P10_R 3 18 SD_CMD
RR7 @ 0_0402_5% DP SP10 16 MS_D0
SP9
SP8
15 MS_D2_SD_CLK_R RR2 1 2 0_0402_5% MS_D2_SD_CLK 拉MS_D2_SD_CLK到Conn pin 13 SD_CLK
RTS5179-GR_QFN24
再打Via拉到pin 10 MS_D2
14
7 SP7 13 SD_CD#
23 XD_CD# SP6 12 MS_D3
17 XD_D7 SP5 11 SD_D0
GPIO0 SP4
Thermal pad
10 SD_D1
6 SP3 9 MS_INS#
V18 24 SDREG SP2 8 MS_CLK_SD_WP_R RR3 1 2 0_0402_5% MS_CLK_SD_WP
V18 SP1 拉MS_CLK_SD_WP到Conn pin 5 MS_CLK
CR5
CR6
CR3
CR4
1 1
C 2 2 再打Via拉到pin 20 SD_W C
5P_0402_50V8C
5P_0402_50V8C
25
RTS5179-GR_QFN24_4X4
2 2
1 1
1U_0402_6.3V6K
1U_0402_6.3V6K
+3VS
1 1
CR1 CR2
+VCC_3IN1
0.1U_0402_16V7K 4.7U_0603_6.3V6K
2 2
+VCC_3IN1
JREAD
SD_D2 1
2 SD-DAT2
MS_D1_SD_D3 3 MS-VSS1
4 SD-CD/DAT3 MMC-RSV
MS_CLK_SD_WP 5 MS-VCC
MS-SCLK
2
1 1 SD_CMD 6
CR8 CR7 @ RR4 MS_D3 7 SD-CMD MMC-CMD
MS_INS# 8 MS-DATA3
4.7U_0603_6.3V6K 0.1U_0402_16V7K 10K_0402_5% 9 MS-INS
2 2 MS_D2_SD_CLK 10 SD-VSS MMC-VSS1
1
11 MS-DATA2
MS_D0 12 SD-VDD MMC-VDD
MS_D1_SD_D3 13 MS-DATA0
MS_D2_SD_CLK 14 MS-DATA1
B B
MS_BS 15 SD-CLK MMC-CLK
16 MS-BS
17 MS-VSS2
Close to JREAD1 SD_D0 18 SD-VSS MMC-VSS2
SD-DAT0 MMC-DAT
SD_D1 19
SD_CD# 20 SD-DAT1
21 SD-CD 23
MS_CLK_SD_WP 22 SD-GND GND1 24
SD-WP(SW) GND2
T-SOL_143-2300302602_RV
CONN@
SD_CMD
SP071204100
1
CR11
10P_0402_50V8J
LTCX004AK00
2
For ESD request.
Place close to JREAD
A A

Deciphered Date
Card Reader RTS5179
1.0
LA-9102P
5 4 3 2 1
A B C D E
+5VALW to +5VS
+3VALW to +3V_PCH
+5VALW QZ1 +5VS
1 SI4128DY-T1-GE3_SO8 1
+3VALW
8 1
7 2 JP2 @
2
10U_0805_10V6K
1U_0603_10V6K
1 1 6 3 1 1 1 2
5 CZ3 CZ4 1 2 +1.5V_CPU_VDDQ +0.75VS
CZ1 CZ2 RZ1 JUMP_43X79
10U_0805_10V6K 10U_0805_10V6K 470_0603_5% QZ3 +3V_PCH
1
2 2 2 2 SI4128DY-T1-GE3_SO8
1
8 1
40mil RZ3 RZ2
+5VS_D
7 2 220_0402_5% 22_0603_5%~D
RZ4 1 1 6 3 1 1
2
B+_BIAS
1 2 1 @ 2 5
2
0.1U_0603_50V_X7R
RZ5 0_0402_1% CZ5 CZ6 CZ7 CZ8
+1.5V_CPU_VDDQ_CHG
+DDR_CHG
56K_0402_5% 1 QZ2A 10U_0805_10V6K 10U_0805_10V6K 10U_0805_10V6K 1U_0603_10V6K
3
4
@ 2 SUSP 2 2 2 2
CZ9
RZ6
QZ2B 1.5M_0402_5% DMN66D0LDW-7_SOT363-6
1
SUSP 5 2
1
DMN66D0LDW-7_SOT363-6 B+_BIAS
1 2 1 @ 2
4
0.1U_0603_50V_X7R
RZ7 RZ8 0_0402_1%
2M_0402_5%~D
470K_0402_5% 1 QZ5 QZ6
1
2N7002BKW_SOT323-3~D D D 2N7002BKW_SOT323-3~D
CZ10
D 2 2
<10,6> RUN_ON_CPU1.5VS3#
PCH_PWR_EN# 2 G G
G 2 RZ9
S S
3
QZ4 S
1
2N7002K_SOT23-3
3
+3VALW to +3VS
+3VALW QZ7 +3VS
SI4128DY-T1-GE3_SO8 +5VALW
2 8 1 2
7 2
1 1 6 3 1 1
1
5 +5VALW
CZ11 CZ12 CZ13 CZ14 +3VALW
10U_0805_10V6K 10U_0805_10V6K 10U_0805_10V6K 1U_0603_10V6K RZ10
4
2 2 2 2 100K_0402_5%
1
SUSP
2
RZ14
1
RZ13 39.2K_0402_1% RZ11 RZ12
B+_BIAS
1 2 D 10K_0402_5% 100K_0402_5%
0.1U_0603_50V_X7R
2 QZ8 @
2M_0402_5%~D
<10,40,48,49,50> SUSP#
2
56K_0402_5% 1 G 2N7002K_SOT23-3 PCH_PWR_EN#
<19> PCH_PWR_EN#
1
1
0.1U_0603_50V_X7R
S
1
CZ15
D @ 1
3
Reserve for ESD SUSP 2 RZ16 @ D
2 RZ15
CZ16
G 100K_0402_5% 2 QZ10
<40> PCH_PWR_EN
CZ23 QZ9 S G 2N7002K_SOT23-3
1
0.1U_0603_50V_X7R
2 1 SUSP 2N7002K_SOT23-3 S
3
1
1
3
0.1U_0402_16V7K RZ17
CZ17
100K_0402_5%
Please close to QZ9
2
2
+1.5V To +1.5VS
B+_BIAS UZ1
+1.5V +1.5VS
SI4634DY-T1-E3_SO8~D
1
8 1 +5VALW
10U_0805_10V6K
0.1U_0402_16V7K
7 2
RZ18 6 3 1 1
CZ18
CZ19
470K_0402_5% 5
2
1
3 3
4
1 @ 2 2 2
RZ20 0_0402_1% RZ19
1
D
0.1U_0603_50V_X7R
100K_0402_5%
2M_0402_5%~D
1
SUSP 2 QZ11 RZ21
2
CZ20
G 2N7002BKW_SOT323-3~D SYSON#
S
3
2
1
2
CZ22
+1.5VS +VCCP +3V_PCH +3VS 0.1U_0402_25V6K
+1.5V 2
1
1
RZ23 RZ24 RZ25 RZ26 D
1
+5VALW 2 QZ12
<40,50> SYSON
470_0402_5% 470_0402_5% 470_0402_5% 470_0402_5% RZ27 G 2N7002K_SOT23-3
0.1U_0603_50V_X7R
1 2 1 S
2
1
470_0402_5% @
3
CZ21
CZ24 @ RZ22
2
0.1U_0402_16V7K
+1.5VS_D
+VCCP_D
+1.5V_D
100K_0402_5%
1 2 2
+3V_D
+3VS_D
2N7002DW-7-F_SOT363-6
2N7002DW-7-F_SOT363-6
2N7002DW-7-F_SOT363-6
2N7002DW-7-F_SOT363-6
2
CZ25 @
0.1U_0402_16V7K
6
1
+3VS +5VALW D
QZ13A QZ13B QZ14A QZ14B SYSON# 2 QZ15
1 2 G 2N7002BKW_SOT323-3~D
SUSP 2 SUSP 5 PCH_PWR_EN# 2 SUSP 5 S
3
CZ26 @
0.1U_0402_16V7K
1
1 2
CZ27 @
0.1U_0402_16V7K
+3VS
4 1 2 4
CZ28 @
0.1U_0402_16V7K
+3VS +1.05VS
1 2
CZ29 @
0.1U_0402_16V7K
Deciphered Date
Reserve for ESD
DC/DC Interface
1.0
LA-9102P
A B C D E
5 4 3 2 1
SM070001U00
(CPN change only)
WCM-2012HS-900T_4P +5VALW
USB3RN2_JUSB1 4 3 USB3RN2_JUSB1_R
<16> USB3RN2_JUSB1 4 3
D D
USB3RP2_JUSB1 1 2 USB3RP2_JUSB1_R 1 1
<16> USB3RP2_JUSB1 1 2 CI12 CI14
LI1
1
EMC@
2 4.7U_0805_10V4Z
2 2
0.1U_0402_16V7K 2.0A +5V_USB_PWR1
USB conn.1
@ RI1 0_0402_5%
1 2 UI3
@ RI2 0_0402_5% 1 8 +5V_USB_PWR1
2 GND VOUT 7
80mil JUSB1
3 VIN VOUT 6 0_0402_1% USB3TP2_JUSB1_R 9
VIN VOUT SSTX+
EPAD
SM070001U00 USB_EN# 4 5 1 2 1
<37,40> USB_EN# EN FLG USB_OC1# <16> VBUS
0.1U_0402_25V6K
(CPN change only) USB3TN2_JUSB1_R 8
RI19 @ USB20_JUSB1_P1_R 3 SSTX-
1 1 1 D+
CI13 CI15 1 7
GND
9
WCM-2012HS-900T_4P AP2301MPG-13_MSOP8 CI1 + USB20_JUSB1_N1_R 2 10
D- GND
0.1U_0402_16V7K
CI2
<16> USB3TN2_JUSB1 USB3TN2_JUSB1 2 1 USB3TN2_JUSB1_C 4 3 USB3TN2_JUSB1_R 0.1U_0402_16V7K USB3RP2_JUSB1_R 6 11
4 3 SSRX+ GND
2
CI3 0.1U_0402_16V7K 2 2 220U_6.3V_M 4 12
2 2 GND GND
DI2
USB3RN2_JUSB1_R 5 13
USB3TP2_JUSB1 2 1 USB3TP2_JUSB1_C 1 2 USB3TP2_JUSB1_R
SSRX- GND
<16> USB3TP2_JUSB1 1 2
CI4 0.1U_0402_16V7K ACON_TARA4-9K1311
LI3 EMC@ CONN@
1 2
@ RI4 0_0402_5% USB 2.0 Port 1
USB 3.0 Port 2
1 2 DI1 EMC@
1
@ RI6 0_0402_5% USB3RN2_JUSB1_R 1 10 USB3RN2_JUSB1_R
DC233007O10
USB3RP2_JUSB1_R 2 9 USB3RP2_JUSB1_R
DC231204030 (OLD)
USB3TN2_JUSB1_R 4 7 USB3TN2_JUSB1_R
EMC@
USB3TP2_JUSB1_R 5 6 USB3TP2_JUSB1_R
WCM-2012HS-900T_4P
USB20_JUSB1_N1 4 3 USB20_JUSB1_N1_R 3
<16> USB20_JUSB1_N1 4 3
C 8 C
USB20_JUSB1_P1 1 2 USB20_JUSB1_P1_R
<16> USB20_JUSB1_P1 1 2 IP4292CZ10-TBR_XSON10_2.5X1~D
LI2 EMC@
1 2
@ RI3 0_0402_5%
1 2
@ RI5 0_0402_5%
SM070001U00
(CPN change only)
WCM-2012HS-900T_4P
+5VALW
USB3RN1_JUSB2 4 3 USB3RN1_JUSB2_R
<16> USB3RN1_JUSB2 4 3
USB3RP1_JUSB2 1 2 USB3RP1_JUSB2_R
<16> USB3RP1_JUSB2 1 2
1 1
LI4 EMC@ CI6 CI7
1 2
@ RI13 0_0402_5% 4.7U_0805_10V4Z
2 2
0.1U_0402_16V7K 2.0A +5V_USB_PWR2
1 2
@ RI14 0_0402_5% UI2
1 8 80mil
2 GND VOUT 7
B B
3 VIN VOUT 6 0_0402_1%
VIN VOUT
EPAD
USB_EN# 4 5 1 2
1
EN FLG
RI20 @ 1
USB_OC0# <16>
USB conn.2
CI26 CI17
9
AP2301MPG-13_MSOP8
0.1U_0402_16V7K
0.1U_0402_16V7K
2 2
+5V_USB_PWR2
JUSB2 CONN@
SM070001U00 USB3TP1_JUSB2_R 9
1 SSTX+
(CPN change only) VBUS
0.1U_0402_25V6K
USB3TN1_JUSB2_R 8
USB20_JUSB2_P0_R 3 SSTX-
1 D+
WCM-2012HS-900T_4P 1 7
USB3TN1_JUSB2 2 1 USB3TN1_JUSB2_C 4 3 USB3TN1_JUSB2_R CI8 + USB20_JUSB2_N0_R 2 GND 10
<16> USB3TN1_JUSB2 4 3 D- GND
CI9
CI10 0.1U_0402_16V7K USB3RP1_JUSB2_R 6 11
SSRX+ GND
2
220U_6.3V_M 4 12
2 2 GND GND
DI5
<16> USB3TP1_JUSB2 USB3TP1_JUSB2 2 1 USB3TP1_JUSB2_C 1 2 USB3TP1_JUSB2_R USB3RN1_JUSB2_R 5 13
CI11 0.1U_0402_16V7K 1 2 SSRX- GND
LI6 EMC@ DI4 EMC@ ACON_TARA4-9K1311
1 2 USB3RN1_JUSB2_R 1 10 USB3RN1_JUSB2_R
@ RI17 0_0402_5%
USB3RP1_JUSB2_R 2 9 USB3RP1_JUSB2_R USB 2.0 Port 0
1 2 USB 3.0 Port 1
@ RI18 0_0402_5% USB3TN1_JUSB2_R 4 7 USB3TN1_JUSB2_R
1
USB3TP1_JUSB2_R 5 6 USB3TP1_JUSB2_R
DC233007O10
3 DC231204030 (OLD)
EMC@
WCM-2012HS-900T_4P 8
USB20_JUSB2_N0 4 3 USB20_JUSB2_N0_R
<16> USB20_JUSB2_N0 4 3 IP4292CZ10-TBR_XSON10_2.5X1~D
USB20_JUSB2_P0 1 2 USB20_JUSB2_P0_R
<16> USB20_JUSB2_P0 1 2
A A
LI5 EMC@
1 2
@ RI15 0_0402_5%
1 2
@ RI16 0_0402_5%

Deciphered Date
USB3.0
1.0
LA-9102P
Date: Wednesday, September 26, 2012 Sheet 36 of 57
5 4 3 2 1
5 4 3 2 1
+5VALW
1 1
D CI23 CI22 D
4.7U_0805_10V4Z
2 2
0.1U_0402_16V7K 2.0A +5V_USB_PWR3
UI4
1 8 80mil
2 GND VOUT 7
3 VIN VOUT 6 0_0402_1%
VIN VOUT
USB conn.3
EPAD
USB_EN# 4 5 1 2
<36,40> USB_EN# EN FLG USB_OC2# <16>
1 RI24 @ 1
CI16 CI24
9
AP2301MPG-13_MSOP8
0.1U_0402_16V7K
0.1U_0402_16V7K
2 2
+5V_USB_PWR3
+5V_USB_PWR3
JUSB3
1
USB20_JUSB3_N2_R 2 VBUS
D-
0.1U_0402_25V6K
USB20_JUSB3_P2_R 3
4 D+
GND 1
5 1
GND
2
6 CI20 +
GND
DI7
CI19
7
8 GND 220U_6.3V_M
GND 2 2
ACON_UARBG-4K1926
EMC@ CONN@
WCM-2012HS-900T_4P
USB20_JUSB3_P2 4 3 USB20_JUSB3_P2_R USB 2.0 Port 2
<16> USB20_JUSB3_P2 4 3
Place close to JUSB3
1
USB20_JUSB3_N2 1 2 USB20_JUSB3_N2_R
DC233007P00
<16> USB20_JUSB3_N2 1 2
LI7 EMC@ DC233007P00(OLD)
C 1 2 C
@ RI25 0_0402_5%
1 2
@ RI21 0_0402_5%
+5VALW
1 1
CI31 CI30
4.7U_0805_10V4Z
2 2
0.1U_0402_16V7K 2.0A +5V_USB_PWR4
B B
UI5
1 8 80mil
WCM-2012HS-900T_4P 2 GND VOUT 7
<16> USB20_USBDB_P3
USB20_USBDB_P3 4
4 3
3 USB20_USBDB_P3_R
USB_EN#
3
4
VIN
VIN
EN
EPAD
VOUT
VOUT
FLG
6
5
0_0402_1%
1 2
USB_OC3# <16>
USB conn.4
USB20_USBDB_N3 1 2 USB20_USBDB_N3_R 1 RI31 @ 1
<16> USB20_USBDB_N3 1 2 CI25 CI32
9
LI10 EMC@ AP2301MPG-13_MSOP8

0.1U_0402_16V7K
1 2 0.1U_0402_16V7K
@ RI32 0_0402_5% 2 2 +5V_USB_PWR4
JDB
1 2 1
@ RI28 0_0402_5% 2 1
3 2
USB20_USBDB_P3_R 4 3
USB20_USBDB_N3_R 5 4
6 5 9
7 6 G1 10
8 7 G2
1
2
8
DI8
CI27 @ + ACES_51524-0080N-001
CONN@
220U_6.3V_M
@ 2 USB 2.0 Port 3
SP01001A900
1
A A

Deciphered Date
MB to USB2.0 DB
1.0
LA-9102P
5 4 3 2 1
5 4 3 2 1
Mini WLAN/WIMAX H=6.7
+3V_WLAN +3V_WLAN
D
WLAN_WAKE# 1
JMINI
2
+1.5VS
+3VS
Power Control for Mini card D
<40> WLAN_WAKE# 1 2
3 4
5 3 4 6 +3VS
1
WLAN_CLKREQ# 7 5 6 8
<14> WLAN_CLKREQ# 7 8
9 10 R110 +3VALW +3V_AOAC
CLK_PCIE_WLAN# 11 9 10 12 Q2 @
<14> CLK_PCIE_WLAN# 10K_0402_5%
CLK_PCIE_WLAN 13 11 12 14 +3VALW B+_BIAS SI3456DDV-T1-GE3_TSOP6~D
<14> CLK_PCIE_WLAN
2
15 13 14 16
G
15 16
D
100K_0402_5%
@ 17 18 6
S
1
17 18
100K_0402_5%
BT_ON# 2 1 19 20 WLAN_RADIO_DIS#_R 1 3 WL_OFF# WL_OFF# <16> 5 4
19 20
R19
R12 0_0402_5% C49 0.1U_0402_10V7K~D 21 22 2 @ 1 PLT_RST# @ 2
S
21 22 PLT_RST# <16,32,40,6>
R20
PCIE_PRX_WLANTX_N2 1 2 PCIE_PRX_WLANTX_N2_C 23 24 R16 0_0402_1% 1
<14> PCIE_PRX_WLANTX_N2 23 24
PCIE_PRX_WLANTX_P2 1 2 PCIE_PRX_WLANTX_P2_C 25 26 QV30
G
<14> PCIE_PRX_WLANTX_P2
1
C44 0.1U_0402_10V7K~D 27 25 26 28 2N7002_SOT23-3 @
27 28
3
29 30 PCH_SMBCLK @ R17
PCH_SMBCLK <11,12,14,6>
2
29 30
<14> PCIE_PTX_WLANRX_N2 PCIE_PTX_WLANRX_N2 31 32 PCH_SMBDATA 20K_0402_5%
31 32 PCH_SMBDATA <11,12,14,6>
4700P_0402_25V7K
<14> PCIE_PTX_WLANRX_P2 PCIE_PTX_WLANRX_P2 33 34
35 33 34 36 USB20_MINI1_N8
35 36 USB20_MINI1_N8 <16> 1
2
Q4B
1M_0402_5%
37 38 USB20_MINI1_P8 USB20_MINI1_P8 <16>
1
37 38
C13
39 40 5
39 40
R21
41 42 @
6
43 41 42 44 Q4A @ 2 @
43 44
4
45 46 DMN66D0LDW-7_SOT363-6 @
47 45 46 48
47 48
2
EC_TX R14 1 @ 2 0_0402_1% 49 50 <40> WLAN_ON WLAN_ON 2
<40> EC_TX 49 50
EC_RX R15 1 @ 2 0_0402_1% 51 52
<40> EC_RX 51 52
1
BT_ON# R13 2 1 1K_0402_1% 53 54
<17> BT_ON# GND1 GND2
2
R18
R11 100K_0402_5%
CONCR_525B01BE17A @
2
100K_0402_5% CONN@
1
DC040009U00
C C
+1.5VS +3V_WLAN CC47靠近wlan connector

0.047U_0402_16V4Z
0.047U_0402_16V4Z
0.047U_0402_16V4Z
0.047U_0402_16V4Z
0.1U_0402_25V6K
0.1U_0402_25V6K
4.7U_0603_6.3V6K
0.1U_0402_25V6K
CC47 330U_D2_2VM_R6M~D
1
@ C47
1 1 1 1 1 1 2 2 1 1 +3VS
1 2 +3V_WLAN
@ + @
C50
C45
C40
C42
C46
C48
C43
C87 C88 R25
47P_0402_50V8J @ 47P_0402_50V8J 0_1206_5%~D
2 2 2 2 2 2 1 1 2 2 2
+3V_AOAC
1 2
R22
0_1206_5%~D
@
HDD LED Battery LED

LED2
B 12-21C-T3D-CM2P1B18X-2C_WHITE White B
R2 R3
<13> PCH_SATALED# PCH_SATALED# 1 2 1 2 +5VS <40> BATT_CHG_LED# BATT_CHG_LED# 1 2 2
680_0402_1%
390_0402_5% R4 1 +5VALW
3
<40> BATT_LOW_LED# BATT_LOW_LED# 1 2 3

390_0402_5%
Amber
LED3
HT-210UD5-BP5_AMBER-WHITE
Power LED
10mils, All pins LED1 Wireless LED
12-21C-T3D-CM2P1B18X-2C_WHITE
R1
PWR_LED# 1 2 1 2 +5VALW
390_0402_5% LED4
3
12-21C-T3D-CM2P1B18X-2C_WHITE
R9
<40> WL_BT_LED# WL_BT_LED# 1 2 1 2 +5VALW
680_0402_1%
1
3
<40> PWR_PWM_LED#
2 Q1
G
S 2N7002_SOT23-3
1
R786
100K_0402_5%
2
A A

Deciphered Date
Mini Card/LED
1.0
LA-9102P
5 4 3 2 1
5 4 3 2 1
+FAN_POWER
D D
Power ON Circuit +3VLP

40mil
FAN Control circuit
2.2U_0603_6.3V6K
1000P_0402_50V7K
1 1
2
ON/OFF switch RE49 CE22 CE23
100K_0402_5% +5VS
KB9012@ 2 2 CE25
TOP Side 2.2U_0603_6.3V6K
1
@ SW1 DE1 1 2
SMT1-05-A_4P 2
ON/OFF <40>
1 3 ON/OFFBTN# 1
3 UE3
2 4 1 1 8
BAV70W_SOT323-3 2 VEN GND 7
CE20 3 VIN GND 6
6
5
0.1U_0402_25V6K EN_DFAN1 4 VO GND 5

2 <40> EN_DFAN1 VSET GND
1
APE8873M SOP 8P
D
2 QE1 @
<40,47> EC_ON
G 2N7002K_SOT23-3
2
S
@ RE51
Bottom Side
3
10K_0402_5%
@ SW2 +3VS
SMT1-05-A_4P +FAN_POWER
1
1 3
1
2 4 RE50 40mil JFAN
10K_0402_5% 1
2 1
6
5
3 2
3
2
C 4 C
<40> FAN_SPEED1 GND
5
GND
1 ACES_85204-0300N
Pop only CONN@
CE24
before MP 0.01U_0402_16V7K
2 SP02000JR00
POWER/B
INT_KBD Conn.
+3VALW
KSI[0..7]
<40> KSI[0..7]
JPWR
1 KSO[0..16]
1 <40> KSO[0..16]
LID_SW# 2
<40> LID_SW# 2
ON/OFFBTN# 3
4 3 JKB CONN@
4 HB_A823020-SBHR21
5
3
GND 6 30 32
DE5 GND KSI7 29 30 GND 31
PESD24VS2UT_SOT23-3~D HB_A090420-SAHR21 KSI6 28 29 GND
EMC@ CONN@ KSI4 27 28
B B
KSI2 26 27
KSI5 25 26
SP01001G200
1
KSI1 24 25
KSI3 23 24
SP01000Z300 (OLD) KSI0 22 23
KSO5 21 22
KSO4 20 21
KSO7 19 20
KSO6 18 19
KSO8 17 18
KSO3 16 17
KSO1 15 16
Touch pad KSO2

KSO0
14
13
15
14
13
KSO12 12
KSO16 11 12
+3VS KSO15 10 11
KSO13 9 10
JTP KSO14 8 9
1 KSO9 7 8
TP_CLK 2 1 +5VS KSO11 6 7
<40> TP_CLK 2 6
TP_DATA 3 RE60 KSO10 5
<40> TP_DATA 3 5
4 1 2 KB_CAPS_PWR 4
TP_SMBCLK 5 4 7 3 4
<14> TP_SMBCLK 5 G1 3
TP_SMBDATA 6 8 240_0402_1% 2
<14> TP_SMBDATA 6 G2 2
KB_CAPS_PWR- 1
ACES_51524-0060N-001 1
CONN@
SP01001H500
SP010014M10
3
1
D
DE3
2 QE3
<40> CAPS_LED
G 2N7002BKW_SOT323-3~D
3 S
EMC@
A A
1

Deciphered Date
FAN/TP/KB/PWR SW
1.0
LA-9102P
5 4 3 2 1
5 4 3 2 1
Board ID Project ID
+3VALW +3VALW
2
RE3
MS@ RE19
+EC_VCCA Ra 100K_0402_5% Rb => NC Ra 100K_0402_5%
+3VALW LE1
1
@ FBMA-L11-160808-800LMT_0603 AD_BID0 AD_PID0
1 2 0.1U_0402_16V7K 0.1U_0402_16V7K +3VALW_EC 1 2 +EC_VCCA RE5 UMA@ RE12 TH@
2
RE1 0_0805_1%1 1 1 1 2 2 1 1
CE1 CE2 CE3 CE4 CE5 CE6 1 CE7 DIS@ CE8 UMA@ CE21
D 0.1U_0402_16V7K Rb RE5 Rb RE12 D
1000P_0402_50V7K 100K_0402_5% 0.1U_0402_16V7K 100K_0402_5% 0.1U_0402_16V7K
2 2 2 2 1 1 ECAGND 2 2
ECAGND <45>
1
0.1U_0402_16V7K 0.1U_0402_16V7K 1000P_0402_50V7K 2
56K_0402_5% 200K_0402_5%
1 @ 2 +3VLP
RE4 0_0402_1% Analog Board ID definition, Analog Project ID definition,
111
125
Please see page 4. Please see page 4.
22
33
96
67
Reserved for KB9012
9
UE1
+3VS
EC_VDD/VCC
EC_VDD/VCC
EC_VDD/VCC
EC_VDD/VCC
EC_VDD/VCC
EC_VDD/AVCC
EC_VDD0
@
1 2 EC_SCI# GATEA20 1 21 KB_LED_PWM
<17> GATEA20 GATEA20/GPIO00 GPIO0F KB_LED_PWM
RE32 10K_0402_5% KB_RST# 2 23 BEEP#
<17> KB_RST# KBRST#/GPIO01 BEEP#/GPIO10 BEEP# <33>
1 @ 2 PCH_HOT# SERIRQ 3 26 43_0402_1% 2 RE36 1 PCH_PWR_EN
<13> SERIRQ SERIRQ GPIO12 PCH_PWR_EN <35>
RE35 10K_0402_5% LPC_FRAME# 4 27 ACOFF
<13>
LPC_FRAME# LPC_FRAME# ACOFF/GPIO13 ACOFF <46>
CE10 LPC_AD3 5 2 1 ECAGND
<13> LPC_AD3 LPC_AD3
@ 22P_0402_50V8J LPC_AD2 7 PWM Output CE9 100P_0402_50V8J
<13> LPC_AD2 LPC_AD2
2 1 RE6 2 1 @ 33_0402_5% LPC_AD1 8 63 BATT_TEMP
+3VALW <13> LPC_AD1 LPC_AD1 BATT_TEMP/GPIO38 BATT_TEMP <45,46>
LPC_AD0 10 LPC & MISC 64 VCIN0_PH_R RE17 2 1 VCIN0_PH
<13> LPC_AD0 LPC_AD0 GPIO39 65 ADP_I 0_0402_5% @
ADP_I/GPIO3A ADP_I <45,46>
1 2 EC_SMB_CK1_R 12 AD Input 66 AD_BID0
<16> CLK_PCI_LPC CLK_PCI_EC GPIO3B
RE11 2.2K_0402_5% 13 75 PCH_HOT#_R 2 @ 1 PCH_HOT#
<16,32,38,6> PLT_RST# PCIRST#/GPIO05 GPIO42 RE7 0_0402_5% PCH_HOT# <14>
1 2 EC_SMB_DA1_R +3VALW RE8 2 1 47K_0402_5% EC_RST# 37 76 AD_PID0
RE13 2.2K_0402_5% EC_SCI# 20 EC_RST# IMON/GPIO43
<17> EC_SCI# EC_SCII#/GPIO0E
1 2 KSO1 CE11 2 1 0.1U_0402_16V7K 38 +5VS
<38> WLAN_ON GPIO1D
RE62 @ 47K_0402_5% 68
DAC_BRIG/GPIO3C EN_INVPWR <21>
1 2 KSO2 70 EN_DFAN1
EN_DFAN1/GPIO3D EN_DFAN1 <39>
RE63 @ 47K_0402_5% DA Output 71 TP_CLK 2 1
IREF/GPIO3E EC_ENVDD <21>
KSI0 55 72 4.7K_0402_5% RE9
KSI0/GPIO30 CHGVADJ/GPIO3F LCD_TEST <21>
1 2 LID_SW# KSI1 56 TP_DATA 2 1
RE71 10K_0402_5% KSI2 57 KSI1/GPIO31 4.7K_0402_5% RE10
KSI3 58 KSI2/GPIO32 83 EC_MUTE#
KSI3/GPIO33 EC_MUTE#/GPIO4A EC_MUTE# <33>
KSI4 59 84 USB_EN#
KSI4/GPIO34 USB_EN#/GPIO4B USB_EN# <36,37>
1 2 WLAN_WAKE# KSI5 60 85
KSI5/GPIO35 CAP_INT#/GPIO4C IMVP_PWRGD <52>
RE70 10K_0402_5% KSI[0..7] KSI6 61 86
C <39> KSI[0..7] KSI6/GPIO36 PS2 Interface EAPD/GPIO4D C
KSI7 62 87 TP_CLK_R 2 @ 1 TP_CLK
KSO[0..16] KSI7/GPIO37 TP_CLK/GPIO4E TP_CLK <39>
KSO0 39 88 TP_DATA_R RE23 2 @ 1 0_0402_1% TP_DATA
<39> KSO[0..16] KSO0/GPIO20 TP_DATA/GPIO4F TP_DATA <39>
1 @ 2 EC_SMI# KSO1 40 RE38 0_0402_1% WL_BT_LED#_R
RE16 1K_0402_1% KSO2 41 KSO1/GPIO21
1 @ 2 EC_PME# KSO3 42 KSO2/GPIO22 97 CPU1.5V_S3_GATE
KSO3/GPIO23 CPU1.5V_S3_GATE/GPXIOA00 CPU1.5V_S3_GATE <10> 1
RE21 10K_0402_5% KSO4 43 98 WOL_EN#
KSO4/GPIO24 WOL_EN/GPXIOA01 WOL_EN# <32>
1 2 EC_SMB_CK2 KSO5 44 99 ME_EN CE30
RE24 2.2K_0402_5%
EC_SMB_CK2 <25>
KSO6 45 KSO5/GPIO25 Int. K/B ME_EN/GPXIOA02 109 1 @ 2
ME_EN <13>
0.1U_0402_16V7K
1 2 EC_SMB_DA2 KSO7 46 KSO6/GPIO26 Matrix VCIN0_PH/GPXIOD00 RE15 0_0402_1%
VCIN0_PH <45> 2
EC_SMB_DA2 <25> KSO7/GPIO27 SPI Device Interface
RE25 2.2K_0402_5% KSO8 47
KSO9 48 KSO8/GPIO28 119 HDD_S3.5
KSO9/GPIO29 SPIDI/GPIO5B HDD_S3.5 <41>
1 2 ODD_EC_EN# KSO10 49 120 ODD_EC_EN#
KSO10/GPIO2A SPIDO/GPIO5C ODD_EC_EN# <41>
RE72 10K_0402_5% KSO11 50 SPI Flash ROM 126 Reserve for ESD
KSO12 51 KSO11/GPIO2B SPICLK/GPIO58 128 WL_BT_LED#_R 1 @ 2 WL_BT_LED# Place close to UE1.128
KSO12/GPIO2C SPICS#/GPIO5A WL_BT_LED# <38>
KSO13 52 RE67 0_0402_1%
KSO14 53 KSO13/GPIO2D
KSO15 54 KSO14/GPIO2E 73 RE22 1 @ 2 0_0402_1% ENBKL
KSO15/GPIO2F ENBKL/GPIO40 ENBKL <15>
KSO16 81 74 PECI_KB930 PECI_KB930 1 @ 2
KSO16/GPIO48 PECI_KB930/GPIO41 WLAN_WAKE# <38>
TOUCH_ON# 82 89 RE69 0_0402_1%
<41> TOUCH_ON# KSO17/GPIO49 FSTCHG/GPIO50 PX_MODE <26,53,54>
90 BATT_CHG_LED#
BATT_CHG_LED#/GPIO52 BATT_CHG_LED# <38> +3VLP
91 CAPS_LED
CAPS_LED#/GPIO53 CAPS_LED <39>
EC_SMB_CK1 RE26 1 @2 0_0402_1% EC_SMB_CK1_R 77 GPIO 92 PWR_PWM_LED# reserve for KB9012 Rev.A2
<45,46> EC_SMB_CK1 EC_SMB_CK1/GPIO44 PWR_LED#/GPIO54 PWR_PWM_LED# <38>
EC_SMB_DA1 RE27 1 @2 0_0402_1% EC_SMB_DA1_R 78 93 BATT_LOW_LED#
<45,46> EC_SMB_DA1 EC_SMB_DA1/GPIO45 BATT_LOW_LED#/GPIO55 BATT_LOW_LED# <38>
RE28 @1 2 0_0402_1% EC_SMB_CK2 79 SM Bus 95 SYSON SYSON
<14> PCH_SMLCLK EC_SMB_CK2/GPIO46 SYSON/GPIO56 SYSON <35,50>
1
Reserve for ESD RE29 @1 2 0_0402_1% EC_SMB_DA2 80 121 VR_ON
<14> PCH_SMLDATA EC_SMB_DA2/GPIO47 VR_ON/GPIO57 VR_ON <52>
127 PM_SLP_S4#_R RE30 1
CE27 PM_SLP_S4#/GPIO59 @ 47K_0402_5% PM_SLP_S4#_R 1 @ 2 PM_SLP_S4#
PM_SLP_S4# <15>
2 1 PM_SLP_S3#_R RE39 0_0402_1% CE26
RE31 1 @2 0_0402_1% PM_SLP_S3#_R 6 100 EC_RSMRST# 0.1U_0402_16V7K
<15> PM_SLP_S3# EC_RSMRST# <15>
2
0.1U_0402_16V7K RE33 1 @2 0_0402_1% PM_SLP_S5#_R 14 PM_SLP_S3#/GPIO04 EC_RSMRST#/GPXIOA03 101 EC_LID_OUT# 2
<15> PM_SLP_S5# PM_SLP_S5#/GPIO07 EC_LID_OUT#/GPXIOA04 EC_LID_OUT# <17>
EC_SMI# 15 102 2 @ 1
<17> EC_SMI# EC_SMI#/GPIO08 PROCHOT_IN/GPXIOA05 VCIN1_PH <45>
CE28 16 103 RE34 0_0402_1% VCOUT1_PH
<45> PS_ID GPIO0A H_PROCHOT#_EC/GPXIOA06
2 1 PM_SLP_S5#_R CE_EN 17 104 VCOUT0 2 @ 1
<21> CE_EN GPIO0B VCOUT0_PH/GPXIOA07 VCOUT0_PH <47>
18 GPO 105 BKOFF# RE37 0_0402_1% Place close to UE1.95
<21> CMOS_ON# GPIO0C BKOFF#/GPXIOA08 BKOFF# <21>
0.1U_0402_16V7K 19 GPIO 106 PBTN_OUT#
<45> 130W/90W# GPIO0D PBTN_OUT#/GPXIOA09 PBTN_OUT# <15,6>
DBC_EN 25 107 ACIN_65W_R ACIN_65W_R 1 @ 2
<21> DBC_EN EC_INVT_PWM/GPIO11 PCH_APWROK/GPXIOA10 ACIN_65W <25>
B Please close to EC FAN_SPEED1 28 108 SA_PGOOD RE80 0_0402_1% B
<39> FAN_SPEED1 FAN_SPEED1/GPIO14 SA_PGOOD/GPXIOA11 SA_PGOOD <51>
EC_PME# 29
EC_TX 30 EC_PME#/GPIO15
<38> EC_TX EC_TX/GPIO16
RE18 EC_RX 31 110 ACIN_D RE14 1 @ 2 0_0402_1%
<38> EC_RX EC_RX/GPIO17 AC_IN/GPXIOD01 ACIN <15,25,45,46>
2 1 PCH_PWROK PCH_PWROK 1 @ 2 32 112 EC_ON_R RE41 1 @ 2 0_0402_1%
<15,6> PCH_PWROK PCH_PWROK/GPIO18 EC_ON/GPXIOD02 EC_ON <39,47>
RE40 0_0402_1% 34 114 ON/OFF_R RE42 1 @ 2 0_0402_1%
SUSP_LED#/GPIO19 ON/OFF/GPXIOD03 ON/OFF <39>
10K_0402_5% 36 GPI 115 LID_SW#_R
NUM_LED#/GPIO1A LID_SW#/GPXIOD04 116 SUSP#
SUSP#/GPXIOD05 SUSP# <10,35,48,49,50>
1 @ 2 EC_PME# 117
<15,32> PCIE_WAKE# GPXIOD06 65W/90W# <45>
RE61 0_0402_1% RE82 118 PECI_KB9012 RE43 1 2 H_PECI
PECI_KB9012/GPXIOD07
AGND/AGND H_PECI <17,6>
0_0402_5% EC_CRY1 122 KB9012@ 43_0402_1%
1 2 123 XCLKI/GPIO5D 124
GND/GND
GND/GND
GND/GND
GND/GND
EC_CRY2 +V18R
<15> SUSCLK_R XCLKO/GPIO5E V18R
1
GND0
FAN_SPEED1 2 RE45 1 100K_0402_5% CE16
1 4.7U_0805_10V4Z
CE29 RE82 please close to EC KB9012@ KB9012QF-A3_LQFP128_14X14 2
11
24
35
94
113
69
1 2 20mil LID_SW#_R 1 @ 2 LID_SW#

LID_SW# <39>
220P_0402_50V8J CE17 20P_0402_50V8 LE2 RE81 0_0402_1%
2 ECAGND 2 1
FBMA-L11-160808-800LMT_0603 For LID SW debug & test
Place close to UE1.115
Please close to EC VR_HOT# EC_CRY1 EC_CRY2
<52> VR_HOT#
+3VS
0.1U_0402_16V7K
@ 1 1@
CE12 CE13
1
@ 1
CE15
22P_0402_50V8J 22P_0402_50V8J
OSC
OSC
0_0402_1% 2 2
RE44
2
2
NC
NC
CE14
5
UE2 SA_PGOOD 1 2 0.1U_0402_16V7K

P
<46,6> H_PROCHOT# H_PROCHOT# 4 2 VCOUT1_PH @

Y A
NC
YE1
2
G
32.768KHZ_12.5PF_Q13MC14610002
A SN74LVC1G06DCKR_SC70-5
1 RE47 CE18 100P_0402_50V8J A
1
100K_0402_5% ACIN 2 1
CE19
47P_0402_50V8J
1

Deciphered Date
EC ENE-KB9012
1.0
LA-9102P
5 4 3 2 1
A B C D E F G H
SATA HDD Conn.

JHDD
1
SATA_PTX_DRX_P0_C 2 GND
1 <13> SATA_PTX_DRX_P0_C 1
SATA_PTX_DRX_N0_C 3 A+
<13> SATA_PTX_DRX_N0_C A-
4
CN3 1 2 0.01U_0402_16V7K SATA_PRX_DTX_N0_C 5 GND
<13> SATA_PRX_DTX_N0 B-
CN4 1 2 0.01U_0402_16V7K SATA_PRX_DTX_P0_C 6
<13> SATA_PRX_DTX_P0 B+
7
GND
8
+5V_HDD Source +3VS
9
10
V33
V33
V33
11
HDD_DET# 12 GND
<13> HDD_DET# 13 GND
+5VALW 14 GND
B+_BIAS 15 V5
+5V_HDD V5
16
17 V5
+3VALW 18 GND
1
19 Reserved
RN9 @ 20 GND
1
2
5
6
@ 100K_0402_5% 21 V12 24
V12 GND
1
D QN4 22 23
RN10 G V12 GND
@ 100K_0402_5% 2 HDD_EN_5V 3 SI3456DDV-T1-GE3_TSOP6~D
S SANTA_194301-1
DMN66D0LDW-7_SOT363-6 +5V_HDD +5VS CONN@
2
4
@ JP13
0.1U_0603_50V_X7R
1 2
1 2 DC010003V00
QN5B
10U_0805_10V6K
5 JUMP_43X79
1 1 DC010003Y00 (OLD)
1
CN17
@ @ SHORT DEFAULT
6
CN18
@
4
@ @ RN11
2 2
QN5A
100K_0402_5% +3VS +5V_HDD

2
<40> HDD_S3.5
0.1U_0402_25V6K
0.1U_0402_25V6K
1000P_0402_50V7K
0.1U_0402_25V6K
2 2
1
10U_0805_10V6K
@ RN12 1 1 1 1 1
100K_0402_5%
CN8 CN9 CN5 CN6 CN7
2
2 2 2 2 2
ODD Power Control * Key Board Back Light

@ JP7
1 2
1 2
JUMP_43X79 ODD_EN
+5VS +5VS FE1 KBBL@ +5VS_KBL
QN2 +5VS_ODD
0.75A_24V_1812L075-24DR~OK
1
D
6 D
S
5 4 2 QN6 @ 2 1
1U_0402_6.3V6K
3 <40> ODD_EC_EN# 3
10U_0603_6.3V6M
1 2 G 2N7002BKW_SOT323-3~D 20mil
1U_0603_10V6K
1 S 1 2
1
CN13 SI3456BDV-T1-E3 1N TSOP6 1 RE59 1

G
CE56
@ RN15 Place near JBTB1 CONN. 0_0805_5%
3
CE57
B+_BIAS 100K_0402_5% KBBL@ @ KBBL@
+5VS_ODD 2 2
2
RN6
470K_0402_5%
1000P_0402_50V7K
0.1U_0402_25V6K
10U_0805_10V6K
1 1 1
1
ODD_EN
CN10
CN11
CN12
+3VS
2 2 2
0.1U_0603_50V_X7R
ODD BTB Conn.

1
D RE68
1
2 QN3 RN7 <17> KB_DET# 1 2
<17> ODD_EN#
CN16
G 2N7002BKW_SOT323-3~D @ 1.5M_0402_5%
S 10K_0402_5% +5VS_KBL
3
2 +5VS_ODD
1
JKBBL
1
D 1
2 2 1
G 3 2
JBTB1 QE4 KB_BL_PWM 4 3
S
1
1 2 2N7002BKW_SOT323-3~D 4
@ 3 1 2 4 ODD_DETECT# KBBL@ RE58 5
RN8 1 2 0_0402_1% ODD_DA#_R 5 3 4 6 ODD_DETECT# <17> 100K_0402_5%
20mil GND 6
<16> ODD_DA# 5 6 GND
RN13 1 2 0_0402_5% SATA_PRX_DTX_N2_C 7 8 SATA_PTX_DRX_P2_C RH43 2 1 0_0402_5% KBBL@
<13> SATA_PRX_DTX_N2 7 8 SATA_PTX_DRX_P2 <13>
RN14 1 2 0_0402_5% SATA_PRX_DTX_P2_C 9 10 SATA_PTX_DRX_N2_C RH42 2 1 0_0402_5% SATA_PTX_DRX_N2 <13> HB_A090420-SAHR21
<13> SATA_PRX_DTX_P2 9 10
1
2
5
6
11 12 CONN@
11 12 D QE5
13 16 G SI3456BDV-T1-E3 1N TSOP6
14 GND GND 17 3
GND GND <40> KB_LED_PWM
15 18 S KBBL@
+5VS_ODD GND GND
4 4
4
E&T_1133-Q12C-01R
ACES_50100-0127N-001
JBTB @
1 2
SATA_PRX_DTX_P2_C 3 1 2 4 SATA_PTX_DRX_N2_C
SATA_PRX_DTX_N2_C 5 3 4 6 SATA_PTX_DRX_P2_C
SP02000WP00
ODD_DA#_R 7 5 6 8 ( 2nd connector SP02000MJ00
9 7 8 10 ODD_DETECT#
11 9 10 12 co-layout with SP02000G800 (OLD)
11 12
13 14 JBTB1 Main ) Security Classification Compal Secret Data Compal Electronics, Inc.
WWW.MANUALS.CLAN.SU
15 G1 G2 16 Title
G3 G4 Issued Date 2012/09/25 Deciphered Date 2013/09/30
17 18
G5 G6
HDD/ ODD
1.0
LA-9102P
A B C D E F G H
5 4 3 2 1
D D
Screw Hole
C H1 H2 H4 H5 H6 H7 H8 H9 H10 C
H_2P8 H_2P8 H_5P0N H_2P8 H_3P3 H_3P3 H_2P8 H_2P8 H_3P3
@ @ @ @ @ @ @ @ @
1
H11 H12 H16 H17 H18 H19 H20
H_2P8 H_2P8 H_2P8 H_2P8 H_5P0X3P0N H_3P5 H_3P5
@ @ @ @ @ @ @
1
1
H31 H32 H33 H34 H35
H_3P7 H_3P7 H_3P7 H_3P7 H_3P0
@ @ @ @ @
1
1
FD1 FD2 FD3 FD4
@ FIDUCAL @ FIDUCIAL @ FIDUCAL @ FIDUCIAL
1
B B
A A

Deciphered Date
Screw Hole
1.0
LA-9102P
5 4 3 2 1
5 4 3 2 1
Version Change List ( P. I. R. List ) Page 1

Request
Item Page# Title Date Owner Issue Description Solution Description Rev.
1 21,39 LVDS 2012/05/17 SED Add FHD Panel CE_ENABLE, DBC_ENABLE function from SED request Add CE_EN, DBC_EN control pin to EC 0.2
2 21 LVDS 2012/05/22 SED Follow SED team request disable CE_EN function Change RV62 to DE-POP and RV100 to POP for disable CE_EN function 0.2
D Add AUDIO JACK PLUG delay circuit, Spearate NET JACK_PLUG to D
3 33 Audio codec 2012/05/23 CODEC Follow CODEC vendor suggestion => JACK_SENSE# & => JACK_PLUG# 0.2
Add RV217, RV218, RV219, RV249, CV59, CV60, CV328,
4 16,21 Touch Screen 2012/05/29 HW Add touch screen function DV13, QV16, JTOUCH 0.2
5 39 Board ID 2012/05/30 HW Board ID change for PT Change RE5 from 8.2k_0402(SD028820180) to 33k_0402(SD028330280) 0.2
Add NET "TOUCH_ON#" from JTOUCH to UE1.82(KB9012) for
6 21,39 Touch Screen 2012/05/30 HW Add touch screen function power control TOUCH SCREEN PANEL power control 0.2
7 33 Audio codec 2012/05/30 HW Follow RealTek suggestion remove, delete reserve MUTE circuit Delete D1,QA1,QA2,QA3,RA24,RA26,RA60,RA62,RA68,RA109,CA72,CA73 0.2
15,16,
8 39,41 ESD 2012/05/30 ESD ESD ask CAP for reserve Reserve 0.1u/0402 CH104,CZ23,CH105,CE27,CE29 0.2
Change RH31,RH41,RV232 0ohm form "GCLK@" to "@"
9 14 Green CLK 2012/05/30 HW For Green CLK test for break the clock signal to device 0.2
Change RC150 330K/0402 to 2M/0402, RC151 100K/0402 to 470K/0402,
10 10,26,41 DC/DC 2012/05/31 HW Change "+1.5V_CPU_VDDQ", "+1.5VS", "+1.5VGS" derating RZ18 100K/0402 to 470K/0402, RV115 0/0402 to 2M/0403 0.2
11 41 DC/DC 2012/05/31 HW For power sequence trunning Change RZ15 to DE-POP 0.2
06,15,16,
12 39,41 ESD 2012/05/31 ESD Follow ESD team request Change 0.1u/0402 from "@" to POP 0.2
13 32 Green CLK 2012/06/15 HW Change for Green CLK bom control Change RL21,RL30 from "@" to "GCLK@" 0.2
14 41 DC/DC 2012/06/15 HW For WLAN card power sequence issue Change RZ4,RZ13 from 470K/0402 56K/0403 0.2
C 15 35,41 Schematic page modify 2012/06/18 HW Schematic page modify for easily maintain. Swap Page. 35 & Page 41. 0.2 C
16 41 ODD 2012/06/18 HW Change component location for easily maintain. Move CH9,CH10 from Page.13 to Page.41 0.2
17 39 FAN 2012/06/29 HW Fan speed noise issue Reserve 220p/0402 CE24 0.2
18 6 CPU 2012/06/29 ESD System boot-up shot down issue. Change CC151 from POP to "@" 0.2
21,35, 1. Swap P.35 & P.41and move touch screen circuit from P.21 to P.41.
19 39,40,41 Circuit adjuest 2012/07/01 HW Circuit & page adjust for OAK 15" & OAK 17" 2. Swap P.39 & P.40 page no 0.2
20 40 LID SW 2012/07/01 HW LID SW need a trace for debug and switch. Add RE81 for LID SW. 0.2
21 25 GPU 2012/07/01 HW Follow AMD request, MarsPro will used MPLs. Change RV75,RV76,RV81 from "DIS@" to "TH@" 0.2
22 29 GPU 2012/07/01 HW Follow AMD request, MEM_CALRP2 is not need for Mars ASIC now. Change RV205 from "MS@" to "@" 0.2
23 38 MINI card 2012/07/03 HW Power Control for Mini card didn't need Change R17 to "@" 0.2
24 6 XDP 2012/07/06 HW S3 return hang issue Change RC89 from "@" to POP 0.2
1. Change UG1.2(+3VLP) & UG1.8(+3VALW) connect to +LAN_IO
2. Add R787 connect from +RTCBATT to C5.2 & UG1.10
25 23 GREEN CLK 2012/07/09 HW Follow Green CLK FAE suggestion 3. Change C14 from 0.1u to 5p/0402 0.2
4. Change C8 connect from +3V_ALW to +LAN_IO
5. Add R788 0ohm/0402 from +RTCVCC to UG1 for GCLK & DH1 select
26 35 MOAT 2012/07/09 ESD For ESD request reserve CAP. Reserve those CAP for ESD MOAT. 0.2
B B
27 18 LVDS 2012/07/10 HW Change RES and reserve CAP for LVDS issue Change RH185 from 0ohm-short to 0ohm/0805, and reserve CH106 1U/0402 0.2
28 41 Connector 2012/07/10 ME For ME request Change JBTB1 footprint from SP02000G800 (OLD) to SP02000MJ00 0.2
Add RH44,RH48,RH70 & NET PCH_JTAG_TMS_R, PCH_JTAG_TDI_R,
29 13 PCH 2012/07/11 ESD Follow ESD team request PCH_JTAG_TDO_R for break signal trace 0.2
1.Change NET NAME "N59110727" to "WL_BT_LED#_R"
30 40 PCH 2012/07/11 ESD Follow ESD team request 2. Reserve 0.1u/0402 on "WL_BT_LED#_R" for ESD 0.2
31 21 LVDS 2012/07/11 HW Reserve for CE function for LVDS connector Change CE_EN_R from dummy to JLVDS.18 0.2
32 32 Connector 2012/07/12 ME For ME request Change JLAN CPN from "DC234004V00" to "SP011207090" 0.2
33 40 FAN 2012/07/16 HW For FAN_SPEED1 noise issue Change CE29 from "@" to POP 0.2
34 14 Touch PAD 2012/07/17 SED Change Touch PAD SMBUS port for SMBUS issue Change Touch PAD SMBUS port for SMB0 to SMB 0.3
35 32 GREEN CLK 2012/07/19 HW Follow Silego FAE request Change RL21 from 510 ohm to 0 ohm/0402 0.3
36 41 Touch Screen 2012/08/07 SED Follow SED team request change JTOUCH USB signal conatct. Change JTOUCH Pin define. 0.3
37 34 Card Reader 2012/08/14 ESD Follow ESD team request Reserve CR11 100p/0402 close to JREAD 0.3
38 23 GREEN CLK 2012/08/16 HW Fixed GCLK output abnormal issue Change UG1.2(UG1/VDD) from +LAN_IO to+3VALW 0.3
A A
39 33 CODEC 2012/08/16 HW The issue already fixed by new CODEC. Remove delay circuit and POP RA4 0.3

Deciphered Date
HW-PIR
1.0
LA-9102P
5 4 3 2 1
5 4 3 2 1

Request
Item Page# Title Date Owner Issue Description Solution Description Rev.
D D
C C
B B
A A

Deciphered Date
HW-PIR
1.0
LA-9102P
5 4 3 2 1
A B C D
1 PL901
VIN +5VALW +3VALW
1
BAV99W-7-F_SOT-323-3~D
SMB3025500YA_2P
ADPIN 1 2
PR901
1000P_0402_50V7K
1000P_0402_50V7K
2
PJPDC @ 0_0402_5%
PD901
2.2K_0402_5%
100P_0402_50V8J
100P_0402_50V8J
1
1
1 1 2
1
2
2
PC901
PC902
PC903
PC904
2 3
3
2
4
PR902
4 5 PR903
5
1
33_0402_5%
Erp lot6 CircuitVIN
1
6 1 3 PSID-3 1 2
S
GND 7 PQ901 PS_ID <40>
GND FDV301N_NL_SOT23-3~D
ACES_50299-00501-003
3.3K_1206_5%~D
G
2
CONN@ +5VALW
100K_0402_1%
1
2
PL902 +5VALW
BLM18BD102SN1D_0603~D
PR931
PR904
DA204U_SOT323~D
PSID 2 1 PR929 PSID-2
ACIN <15,25,40,46>
10K_0402_1%
1
2
1M_0402_1%
PD900
2
6
PR905
C
PSID-1 2 PQ900
L2N7002DW1T1G_SC88-6
MMST3904-7-F_SOT323~D @
PQ904A
15K_0402_1%
B
2
2 E
2
PR928
PR900
3
1
@
1
200K_0402_1% PD902 PR906
PQ904B
PR930 SM24_SOT23 1 2 PSID-5
1
5
BATT+ BATT++ 1M_0402_1% 10K_0402_1%
1
PC916
4
0.1U_0402_25V6
BATT+
2
PL900
2
SMB3025500YA_2P 2
1 2 BATT++
100P_0402_50V8J
1
1
1000P_0402_50V7K
100P_0402_50V8J
0.01U_0402_25V7K
1
PC900
PC907
PC905
PC906
2
2
2 1
- + +RTCBATT
1
3 1
PD904 PD903 B+ B+_BIAS
@
100K_0402_1%
PESD24VS2UT_SOT23-3~D PESD24VS2UT_SOT23-3~D
0.1U_0402_25V6
0.22U_0603_25V7K
1
PD905
1
RB751V-40_SOD323-2
PR907
PC908
PC909
JRTC 1 2
+3VLP
2
LOTES_AAA-BAT-054-K01
2
CONN@
2
+5VALW PR908
PQ902
TP0610K-T1-E3_SOT23-3
22K_0402_1%
BATT_TEMP <40,46>
PBATT 1 2 VSB_N_001
2
1
1VSB_N_003
1 2 PR909
2 3 BAT_ALERT PR910 PR911 100K_0402_1%
3 4 SYS_PRES 100_0402_5% 10K_0402_1%
4 5 BATT_PRS 1 2 1 2
+3VALW
1
5 6 DAT_SMB PR912 @ D
6 7 CLK_SMB 2 1VSB_N_002 2 PQ903
7 <47> POK
8 PR914 G 2N7002KW_SOT323-3
8 9 100_0402_5%
.1U_0402_16V7K
S
3
9 10 1 2 0_0402_5%~D
PC910
GND 11 EC_SMB_CK1 <40,46>
0_0402_5%~D
2
GND PR913
PR919
2
SUYIN_200028MR009G502ZL 100_0402_5%
CONN@ 1 2
@ EC_SMB_DA1 <40,46>
1
3 PBATT battery connector 3
SMART
Battery:
01.GND1 ADP_I <40,46> PH900 under CPU botten side :
02.GND2 CPU thermal protection at 96 +/- 3 degree C
03.BAT_ALERT
04.SYS_PRES
05.BATT_PRS
2
06.DAT_SMB PR918 PR926 @
07.CLK_SMB 90.9K_0402_1% 6.81K_0402_1% +EC_VCCA +3VLP
2N7002KW_SOT323-3
2N7002KW_SOT323-3
2
08.BATT1+ PR915
1 1
1 1
2
332K_0402_1% @
09.BATT2+ D D PR927 PR916 @
2 2
PQ905
PQ906
11K_0402_1% 11K_0402_1%
1
G G
S 65W/90W# <40> S 130W/90W# <40>
3
<40> VCIN0_PH
1
<40> VCIN1_PH
1
65W 90W 130W
2
PR917 PC915 @
65W/90W# High Low PH900
2
499K_0402_1% .1U_0402_16V7K 100K_0402_1%_TSM0B104F4251RZ
1
1
130W/90W# Low High

ECAGND <40>
4 4

WWW.MANUALS.CLAN.SU Issued Date 2012/09/25
Deciphered Date 2013/09/30 Title
PWR_DCIN/BATT CONN/OTP
1.0
LA-9102P
A B C D
A B C D
Iada=0~3.34A(65W)
VIN
PQ101 Iada=0~4.62A(90W)
PQ100 AO4409L_SO8 P3
AO4407AL_SO8 P2
8 1 1 8 ADP_I = 19.9*Iadapter*Rsense
7 2 2 7
6 3 3 6 3S2P : CV = 13.3V CC: 1.54A
5 5
1 PR102 B+ PQ102 4S1P: CV = 17.7V CC: 1.1A 1
0.01_1206_1% AO4407AL_SO8
4
1 8
1
1 4 2 7
3 6
3.3_1210_5%
200K_0402_1%
0.1U_0603_25V7K
3
1
PQ103 2 3 CSIN 5
PR101
1
PDTA144EU PNP_SOT323
PC101
5600P_0402_25V7K~D
1
CSIP
PR100
4
2
200K_0402_1%
PL101 CHG_B+
PR103
1UH_NRS4018T1R0NDGJ_3.2A_30%
2
1
1 2 PR108
2
200K_0402_1%
3.3_1210_5%
1
1 2
PC102
2200P_0402_25V7K
0.1U_0603_25V7K
VIN
1
1
PQ104
4.7U_0805_25V6-K
4.7U_0805_25V6-K
DDTC115EUA-7-F_SOT323
PR104
PC103
PC104
1
2
V1 2 100K_0402_1%
10_0402_5%
10_0402_5%
VIN
1
PR110
PR127
PR107
PC106
PC105
PR118
2 2
PR105 47K_0402_1%
0.1U_0603_25V7K
2
150K_0402_1% 1 2 V1
PC100
2.2U_0805_25V6K
0.1U_0603_25V7K
3
1
731@
731@
1
2
2
PR109
PQ113A
1
BATT_TEMP 2 10_1206_1% 731@
PC107
731@ PC108
6
2
1 2 PC123
0.1U_0402_10V7K
1
PQ114B 0.047U_0603_25V7M PC110 731@
PQ114A
PC109
3
5 1 2 1U_0603_10V6K
PQ107
L2N7002DW1T1G_SC88-6 @
1
2 PC111 2
2
1MAX8731_REF
@ 1U_0603_25V6K~D PR111 731@
PQ112B
4
2
4.7_0603_5% 5
1VDDP_LDO
1
VIN 2 1
PC136 PR138
232K_0402_1%
4
PC113 PR114 VDDP_LDO 1 2
2
1000P_0402_50V7K 731@ 2.2_0603_5% 0.1U_0603_25V7K
28
27
1
1 2 1 2BST_CHGA 1 2
731@
PU100 10K_0402_5%
PR142
100K_0402_1%
100K_0402_1%
6
731@
747@
PR112
PR137
CSSN
ICREF
CSSP
2 2
DCIN 22 26
DCIN ICOUT PD101 747@ PC115
1
1 2
PR116 ACSETIN 2 BAT54HT1G_SOD323-2~D ACOFF 2
ACIN <15,25,40,45>
2
5
6
7
8
PR139 49.9K_0402_1% ACIN 25 BST 1 2 1 2 PQ112A
13 BOOT
PQ108
200K_0402_5% ACIN
AO4466L_SO8~D
1
ACIN 1 2 +5VALW ACOK 1U_0603_10V6K L2N7002DW1T1G_SC88-6
1
11
158K_0402_1%
0_0402_5%~D VDDSMB
0.1U_0402_10V7K
10 4
731@
PR119 @
PR117
1
<40,45> EC_SMB_CK1 1 2 SCL

PC116
9 21 VDDP_LDO
2
0_0402_5%~D SDA VDDP

2
PR133 PR120 @ 14 PR121

<40,45> EC_SMB_DA1
3
2
1
ACOFF 1 2 2 1 2 NC 24
PQ109
DH_CHG PL100 0.01_1206_1%

<40> ACOFF UGATE
8
VICM
10UH_PCMB063T-100MS_4A_20% BATT+
10K_0402_5% 23 LX_CHG 1 2 1
CHG 4
6 PHASE
4.7_1206_5%
FBO 2 3
1
1 2 5
3
5
6
7
8
747@ PC117 PR123 747@ EAI
PR141
2 1 1 2 4 20
PQ110
747@ PR122
PQ1111B
DL_CHG
4.7K_0402_5%
AO4712L_SO8~D
200K_0402_5% EAO LGATE
10U_0805_25V5K~D
10U_0805_25V5K~D
10U_0805_25V5K~D
10U_0805_25V5K~D
2
5 2200P_0402_50V7K 7.5K_0402_5%
731@ 10_0402_5%
0_0402_5%
BATT_TEMP
1000P_0402_50V7K
<40,45> BATT_TEMP
1 2
1
PR125
PR126
PC122
PC118
PC119
PC120
100_0402_1% MAX8731_REF 3 19 4
680P_0402_50V7K
4
VREF PGND 18
PC121
PR132
PR128
CSOP
2
747@ PR129 @ @
56P_0402_50V8~D
1
2
1 2 7 17
PC124
PC112
CE CSON
2
747@ PC126
2
3
2
1
1 2 10K_0402_5% 15 VFB 1 PR130 2 BATT+
12 VFB
<40,45> ADP_I GND 16
747@
120P_0402_50VNPO~D 100_0402_5%
0.1U_0402_10V7K
NC
1
29 731@ PC139
<40,6> H_PROCHOT# MAX8731_REF TP 1 2
1U_0603_10V6K
2
1
0_0402_5%
747@ PC125
PC128
ISL88731CHRTZ-T_QFN28_5X5~D 747@ PC129 0.22U_0603_25V7K

PR134
1
0.1U_0603_25V7K @ PC130
2
3
@ PC127 731@ @ 1 2 1 2 3
2
1U_0603_25V6K~D @
0.01U_0402_25V7K
0.01U_0402_25V7K
0.01U_0402_25V7K
2
2 1
PC135 0.1U_0603_25V7K
1
.1U_0402_16V7K
0_0402_5%
731@ PC132
PC138
731@ PC134
1
PR135
2
2
@
@
ISL88731C BQ24747 ISL88731C BQ24747 ISL88731C BQ24747 ISL88731C BQ24747
1
D
BATT_TEMP2 PQ111 @
G SSM3K7002FU_SC70-3
S
PU100 ISL88731C BQ24747 PR122 @ 200k PC134 0.01u @ PC108 0.1u @
3
For DT Mode PR137 @ 100k PR123 @ 7.5k PC129 @ 0.1u PR127 10 0

PU100 747@ PR142 747@ PC135 747@ PC139 747@ PR132 747@
PR112 100k @ PR129 @ 10k PC139 0.22u 0.1u PR107 10 0
VIN
3.3K_1206_5%~D
PR117 158k @ PC117 @ 2200p PR132 10 0 PC123 0.047u 0.1u

1
PR136
BQ24747 324K/0402 0.1U/0402 0.1U/0603 0/0402

PR142 232k 324k PC124 @ 56p PR111 4.7 @
PR107 747@ PC123 747@
731@ for ISL88731C
2
V1
PC135 0.1u 220p PC126 @ 120p PC110 1u @
747@ for BQ24747
PC132 0.01u @ PC125 @ 1u PD101 @ BAT54HT1G
6
@ 0/0402 0.1U/0603
PQ1111A
PQ113B
ACOFF 2 BATT_TEMP 5
PR127 747@
1
4 4
0/0402

WWW.MANUALS.CLAN.SU Issued Date 2012/09/25
Deciphered Date 2013/09/30 Title
PWR_CHARGER
1.0
LA-9102P
A B C D
A B C D E
1 1
2VREF_6182
1U_0603_16V6K
1
PC201
2
0.1U_0402_25V6
0.1U_0402_25V6
@ @ PC200
PC202
1 2 1 2
PR201 PR202
13.7K_0402_1% 30.9K_0402_1%
1 2 1 2
B+ B++ PR203 PR204

20K_0402_1% 20K_0402_1% B++
PL202 1 2 FB_3V FB_5V 1 2
1UH_PCMB053T-1R0MS_7A_20%
1 2
+3VLP
ENTRIP2
ENTRIP1
0.1U_0402_25V6
0.1U_0402_25V6
0.1U_0402_25V6
0.1U_0402_25V6
0.1U_0402_25V6
0.1U_0402_25V6
PR205 PR206
133K_0402_1% 130K_0402_1%
2200P_0402_50V7K
4.7U_0805_25V6-K
1 2 1 2
2200P_0402_50V7K
0.1U_0402_25V6
0.1U_0402_25V6
4.7U_0805_25V6-K
1
1
PC208
PQ202
PC203
PC204
PC205
PC207
PC209
6
1
AON7408L_DFN8-5 PU200
2
5
ENTRIP2
FB2
TONSEL
FB1
ENTRIP1
REF
2 2
1
PC206 PQ203
PC220
PC221
PC222
PC223
PC224
PC225
4 10U_0805_6.3V6M 25 AON7408L_DFN8-5
P PAD
2
@ @ @ @ @ @
7 24 4
VO2 VO1
1
2
3
PC210 8 23 PC211
VREG3 PGOOD
0.22U_0603_10V7K
PR207 PR208 POK <45>
0.22U_0603_10V7K
2 1 BST1_3V 1 2 BST_3V 9 22 BST_5V 1 2 BST1_5V 2 1
3
2
1
BOOT2 BOOT1
reserve from ESD requirement 2.2_0603_5% 2.2_0603_5%
PL200 UG_3V 10 21 UG_5V PL201
3.3UH_PCMB063T-3R3MS_6.5A_20% UGATE2 UGATE1 3.3UH_PCMB063T-3R3MS_6.5A_20%
1 2 LX_3V 11 20 LX_5V 1 2
+3VALWP PHASE2 PHASE1 +5VALWP
1
1
LG_3V 12 19 LG_5V
4.7_1206_5%
4.7_1206_5%
@ LGATE2 LGATE1
PR209
PR210
SKIPSEL
@ PD200 @ PR200 @
VREG5
1000P_0402_50V7K
1000P_0402_50V7K
1
499K_0402_1%
PC229
GND
1
B++
VIN
+ 1 2 1 2
EN
NC
PC212
2
2
330U_6.3V_M 4 4 + PC213
@ BZV55-B5V1_SOD80C2 PR211 330U_6.3V_M
PC230
13
14
15
16
17
18
2
SNUB_3V
SNUB_5V
@ 0_0402_5%
1
1
VCOUT0_PH 1 2 RT8205LZQW(2) WQFN 24P PWM 2
@
1
2
3
3
2
1
PQ204 PQ205
VL
2
2
AON7702A_DFN8-5 AON7702A_DFN8-5
1
680P_0402_50V7K
1
PC214
680P_0402_50V7K
3.3VALWP
PC215
2
TDC 5.4A
2
@ @
200K_0402_1%
1U_0603_10V6K
1
Peak Current 7.7A PC216 @
PC217
PR212 4.7U_0805_10V6K
2
OCP current 9.2A
ENTRIP1
ENTRIP2
1
TYP MAX 2 @ B++ PC218
3
H/S Rds(on) :27mohm , 34mohm 3
2
0.1U_0402_25V6
3
L/S Rds(on) :11mohm , 14mohm 2VREF_6182

PQ206B PQ206A
0.1U_0402_10V7K
0.1U_0402_10V7K
5 N_3_5V_001 2
PC227
PC228
1
4
@ L2N7002DW1T1G_SC88-6 @
2
5VALWP
TDC 5.6A
reserve from ESD requirement PJP202 PJP203
Peak Current 8A
1 2 +5VALW
1 2 +3VALW
+5VALWP +3VALWP
PR213 2.2K_0402_5% OCP current 9.6A
1 2 1 2
<39,40> EC_ON VL PAD-OPEN 4x4m
PJP204
PAD-OPEN 4x4m
PJP200
TYP MAX
PR215 @ PR214
H/S Rds(on) :27mohm , 34mohm
1
VCOUT0_PH 1 2 3/5V_EN-2 100K_0402_5% 1 2 1 2

<40> VCOUT0_PH
0_0402_5%~D PQ201
L/S Rds(on) :11mohm , 14mohm
PAD-OPEN 4x4m PAD-OPEN 4x4m
DDTC115EUA-7-F_SOT-323
0.1U_0402_10V7K
2
PC226
@
2
4.7U_0603_10V6K
3
1
PC219
2
reserve from ESD requirement
4 4

Deciphered Date
PWR_3.3VALWP/5VALWP
1.0
LA-9102P
A B C D E
A B C D
1 1
<Vo=1.8V> VFB=0.6V
Vo=VFB*(1+PR403/PR400)=0.6*(1+20K/10K)=1.8V
PU400 PL400
4
2 2
PJP400 @ 1UH_NRS4018T1R0NDGJ_3.2A_30%
+3VALW 1 2 1.8VSP_VIN 10 2 1.8VSP_LX 1 2
PG
PVIN LX +1.8VSP
9 3
22P_0402_50V8J
PVIN LX
1
PAD-OPEN 3x3m
PC402
4.7_1206_5%
+1.8VSP
1
1
PC403 8
SVIN
22U_0805_6.3VAM PR403 TDC 2.6A
PR404
6 1.8VSP_FB 20K_0402_1%
FB
2
2
5 Peak Current 3.8A
22U_0805_6.3V6M
22U_0805_6.3V6M
1SNUB_1.8VSP 2
1
EN
NC
NC
TP
OCP current 4.5A
PC400
PC404
11
2
1 2 EN_1.8VSP
<10,35,40,49,50> SUSP#
1
PR402 100K_0402_5% 1
0.22U_0402_16V7K
SY8033BDBC_DFN10_3X3 PR400
PC405
1
@ PR401 10K_0402_1%
680P_0402_50V7K
47K_0402_5%
PC401
2
2
2
PJP401 @
1 2
+1.8VSP +1.8VS
PAD-OPEN 3x3m
3 3
4 4

WWW.MANUALS.CLAN.SU Issued Date 2012/09/25 Deciphered Date
2013/09/30 Title
PWR_1.8VSP
1.0
LA-9102P
A B C D
5 4 3 2 1
D D
@ PJP500
+V1.05S_VCCPP_B+ 2 1
2 1 B+
JUMP_43X118
+3VS
SIR472DP-T1-GE3_POWERPAK8-5~D
2200P_0402_50V7K
4.7U_0805_25V6-K
4.7U_0805_25V6-K
0.1U_0402_25V6
1
1
PC501
PC502
PC503
PC504
2
2
PR501
PQ500
100K_0402_5%
1
4
<51> +V1.05S_VCCP_PWRGOOD
PC505
PU500 .1U_0603_25V7K
PR500
1 10 BST_+V1.05S_VCCPP 1 2 2 1
PGOOD VBST
3
2
1
PR502 2.2_0603_5%
1 2 TRIP_+V1.05S_VCCPP 2 9 UG_+V1.05S_VCCPP PL500
TRIP DRVH 1UH_PCMB063T-1R0MS_12A_20%
53.6K_0402_1%
PR503 EN_+V1.05S_VCCPP 3 8 SW_+V1.05S_VCCPP 1 2
150K_0402_5% EN SW +VCCP
SIR818DP-T1_POWERPAK-SO8-5~D
1 2 FB_+V1.05S_VCCPP 4 7
<10,35,40,48,50> SUSP# VFB V5IN +5VALW
RF_+V1.05S_VCCPP 5 6 LG_+V1.05S_VCCPP PC500
TST DRVL
1
1
1 2
11
PQ501
C PC506 C
0.22U_0402_16V7K TP 1U_0603_10V6K PR505
2
TPS51212DSCR_SON10_3X3 @4.7_1206_5%
0.1U_0402_10V7K
2
2
PR504 4
PC507
470K_0402_1%
1
1000P_0402_50V7K
680P_0402_50V7K
2
1
PC508
1
PC510
3
2
1
2
@
2
@
2 1 2 1
+VCCP
PC509 PR506
PR507 @ 1000P_0402_50V7K @ 1.2K_0402_1% PR508
100_0402_5%
4.99K_0402_1%
2 1 1 2
VCCIO_SENSE <9>
PR511 @
1 2
VSSIO_SENSE_R <9>
2
0_0402_5%~D
PR509
10K_0402_1%
1
B B
+V1.05S_VCCP
TDC 11A
Peak Current 16A
OCP current 19A
TYP MAX
H/S Rds(on) 10mohm , 14.5mohm
2
@ PJP501
PR510 1 2
@ 10_0402_1% +VCCP +1.05VS L/S Rds(on) :3mohm , 3.6mohm
PAD-OPEN 4x4m
1
A A

Deciphered Date
PWR_+VCCIO
1.0
LA-9102P
5 4 3 2 1
5 4 3 2 1
PJP301
VLDOIN_1.5V 2 1 +1.5VP
B+ @ PJP302
PR301
PAD-OPEN1x1m
2 1 1.5V_B+ 1 2 BOOT_1.5V
2 1
2.2_0603_5%
JUMP_43X118
DH_1.5V
2200P_0402_50V7K
0.1U_0402_25V6
4.7U_0805_25V6-K
4.7U_0805_25V6-K
+0.75VSP
10U_0805_6.3V6M
10U_0805_6.3V6M
1
1
PC304 SW_1.5V
PC301
PC302
PC303
PC305
0.22U_0603_10V7K
1
2
1
16
17
18
19
20
PC306
PC307
D DL_1.5V D
PQ300
PU300 @
AON7408L_DFN8-5
PJP300
VLDOIN
BOOT
VTT
PHASE
UGATE
+0.75VS
2
PAD
21 +0.75VSP 1 2
4 15 1
LGATE VTTGND PAD-OPEN 3x3m
PR302 14 2
PL300 8.66K_0402_1% PGND VTTSNS
1
2
3
1UH_PCMB063T-1R0MS_12A_20% 1 2 CS_1.5V
1 2 13 3 0.75Volt +/- 5%
+1.5VP CS RT8207MZQW_WQFN20_3X3 GND
TDC 0.7A
5
@
4.7_1206_5%
1 2 PC309 12 4 Peak Current 1A
PQ301
PR304 VTTREF_1.5V
AON7702A_DFN8-5
5.1_0603_5% 1U_0603_10V6K VDDP VTTREF
PR303
1
OCP Current 1.2A
1.5VP + PC308 +5VALW 1 2 VDD_1.5V 11
VDD VDDQ
5
+1.5VP PC310
PGOOD
330U_2.5V_M 4 0.033U_0402_16V7K
1
TDC 6A
SNUB_1.5V
1000P_0402_50V7K
TON
2 PC311
FB
S5
S3
Peak Current 8A 1U_0603_10V6K
2
PC314 220P_0402_50V8J~D
1
2
3
10
6
OCP current 10A 1 2
PC316
+5VALW
2
680P_0402_50V7K
PR305
PC312
10K_0402_1%
2
1.5V_FB 2 1
@ PJP303 @
2 1 PR300
2 1 1M_0402_1%
+1.5VP +1.5V
2
JUMP_43X118 PR306 1.5V_B+ 1 2
1
200K_0402_5% PR307
@ PJP304 1 2 S5_1.5V 10K_0402_1% PC313
2
2 1
1 <35,40> SYSON @.1U_0402_16V7K
2
PC300 PR308
1
C JUMP_43X118 100K_0402_5% C
1U_0402_6.3VX5R SUSP# 1 2 S3_1.5V
0.1U_0402_10V7K
PC315
1
2
+1.5VP
PJP1100
@
+V1.05SP_B+ 2 1
2 1 B+
JUMP_43X118
PC1101 VGA@
VGA@
PC1100 VGA@
PC1102 VGA@
2200P_0402_50V7K
4.7U_0805_25V6-K
4.7U_0805_25V6-K
0.1U_0402_25V6
1
1
5
PC1105
PQ1100
VGA@
AON7408L_DFN8-5
2
VGA@
PC1108 4
VGA@ 0.1U_0603_25V7K
PR1100
1 2 1 2
VGA@ 2.2_0603_5%
3
2
1
VGA@ PU1100
1 10 BST_+1.5VGPU
PGOOD VBST
B PR1104 B
1 2 TRIP_+1.5VGPU 2 9 UG_+1.5VGPU PL1100 VGA@
TRIP DRVH 1UH_PCMB053T-1R0MS_7A_20%
62K_0402_1%
EN_+1.5VGPU 3
EN SW
8 SW_+1.5VGPU 1 2 +1.5VGPUP
5
VGA@ PR1101 FB_+1.5VGPU 4 7
1 2 VFB V5IN +5VALW
PQ1101
VGA@
SUSP#
AON7702A_DFN8-5
RF_+1.5VGPU 5 6 LG_+1.5VGPU 1
RF DRVL
1
0_0402_5% @ VGA@
1
<10,35,40,48,49> SUSP# TP
11 VGA@ + PC1103
1
@ PC1107 4 PR1102 330U_2.5V_M

1
PC1104 TPS51212DSCR_SON10_3X3 1U_0603_10V6K 4.7_1206_5%

2
0.1U_0402_16V7K VGA@ 2
2
2
PR1106
1000P_0402_50V7K
@ PR1107 470K_0402_1%
1
3
2
1
1
1 2
@ PC1109
680P_0402_50V7K
2
<26,40,53> PX_MODE
PC1106
0_0402_5%
2
2
@
VGA@
PR1105
11.5K_0402_1%
2 1
+1.5VGPU
2
VGA@
PR1103
TDC 4.2A
10K_0402_1% Peak Current 6A
A OCP current 7.2A A
1
PJP1102
+1.5VGPUP 2
2 1
1 +1.5VGPU
@ JUMP_43X118

Deciphered Date
PWR_+1.5VP/+1.5VGPUP/0.75VSP
1.0
LA-9102P
5 4 3 2 1
5 4 3 2 1
D D
VID [0] VID[1] VCCSA Vout

0 0 0.9V
0 1 0.85V
1 0 0.775V
1 1 0.75V
output voltage adjustable network
680P_0402_50V7K
PC600
2
+VCC_SAP
SNUB_+1.5VP
C TDC 4.2A C
Peak Current 6A
OCP current 7.2A
2
PR600
4.7_1206_5%
PL601
PU600 PL600
1
HCB1608KF-121T30_0603 SY8037DDCC_DFN12_3X3 0.47UH_FDVE0630-H-R47M=P3_17.7A_20%
+3VALW 1 2 +VCCSA_PWR_SRC 12
PVIN LX
1 +VCCSA_PHASE 1 2 +VCCSAP
11 2
10U_0805_6.3V6M
10U_0805_6.3V6M
22U_0805_6.3VAM
PVIN LX SA_PGOOD <40>
22U_0805_6.3VAM
22U_0805_6.3VAM
22U_0805_6.3VAM
2
2200P_0402_50V7K
0.1U_0603_25V7K
PC610 10 3 PR605
PC605
PC611
PC612
SVIN LX
2
68P_0402_50V8J 100K_0402_5%
PC603
PC604
PC606
PC607
PC609
+VCCSAP_FB 2 1 9 4 2 1
FB PG +3VS
2
1
8 5 +VCCSA_EN 1 2
VOUT EN +V1.05S_VCCP_PWRGOOD <49>
0.1U_0402_10V7K
7 GND 6 PR601 @
VID1 VID0
1
0_0402_5%~D
2
2
PR606
@ PC601
1K_0402_5%
1K_0402_5%
13
100_0402_5%
PR603
PR604
2
2 1
1
PR602 @
1 2
VCCSA_VID0 <10> VCCSA_SENSE <10>
0_0402_5%~D
VCCSA_VID1 <10>
B B
The 1k PD on the VCCSA VIDs are empty.

These should be stuffed to ensure that
VCCSA VID is 00 prior to VCCIO stability.
@
PJP601
+VCCSAP 1 2 +VCCSA
PAD-OPEN 4x4m
+VCCP 1 4 +VCCSA
2 3
@ PR607
0.004_2512_1%
A A
reserve for Pentium and Celeron only

Deciphered Date
PWR_+VCCSAP
1.0
LA-9102P
5 4 3 2 1
5 4 3 2 1
PR701 PC701
2K_0402_1% 330P_0402_50V7K
2 1 2 1
Local sense put on HW site
PR702 PR703 PC702
2 1 2 1 2 1
B+
@ PC703 2.61K_0402_1% 130K_0402_1% 150P_0402_50V8F~D
33.2K_0402_1%
1
2 1 @ PJP701
PR705
D PR704 PC704 PC705 +VCC_GFX_PWR_SRC 2 1 D
<10> VCC_AXG_SENSE 2 1
330P_0402_50V7K 2 1 2 1 1 2
JUMP_43X118
PC706 499_0402_1% 390P_0402_50V7K 68P_0402_50V8J
2200P_0402_25V7K
10U_0805_25V6K
10U_0805_25V6K
0.1U_0402_25V6
<10> VSS_AXG_SENSE
5
1 2
PQ700
1
0.01U_0402_50V7K
PC746
PC747
PC749
PC752
VCC_GFXCORE
TDC 21.5A
2
4
Peak Current 33A
VSUMG+
.1U_0402_16V7K
0.082U_0402_16V7K
OCP current 40A
2.61K_0402_1%
Load line -3.9mV/A

1
3
2
1
PC708
PC709
IMVP_PWRGD <40>
PL700
PR707
0.033U_0402_16V7K
0.22UH_FDUE0640J-H-R22M-P3_25A_20%
11K_0402_1%
1
2
+VCC_GFXCORE_AXG
1
@ 1 4
PR709
PC707
1 2
10KB_0402_5%_ERTJ0ER103J
IMVP_PWRGD
2
5
2 3 GP1_Vo
4.7_1206_5%
2
1
PQ702
PQ703
2
2
PR710
PH700
PR760
0_0402_5% PC750
3.65K_0603_1%
2
1
PR711 PR708 0.22U_0402_16V7K @
2
1 1
392_0402_1% @ 0_0402_5% 4 4
1_0402_5%
PR758
PR759
2
2
VSUMG- 1 2 UGATEG
1000P_0402_50V7K
1
PR763
680P_0402_50V7K
1
2
@ PR753 @ PC735 2.2_0603_5%
PC755
PC751
3
2
1
3
2
1
649_0402_1% 2200P_0402_50V7K
2
2 1 1 2 BOOTG
.1U_0402_16V7K
1
2
@ @ VSUMG+ VSUMG-
PC711
33
32
31
30
29
28
27
26
25
2 1
PAD
ISUMPG
ISUMNG
RTNG
FBG
COMPG
PGOODG
BOOTG
UGATEG
C C
PH701
470K_0402_5%_ TSM0B474J4702RE PR712
3.83K_0402_1%
2 PR715 1 1 2 NTCG 1 24 PHASEG
PR722 @ 27.4K_0402_1% NTCG PHASEG
1 2 VR_EN 2 23 LGATEG
<40> VR_ON VR_ON LGATEG
0_0402_5%~D
1 2 SCLK 3 22
<9> VR_SVID_CLK
PR723 @ 0_0402_5%~D SCLK VCCP +5VS
1 2 ALERT# 4 PU700 21 VDD 2 1
<9> VR_SVID_ALRT# ALERT# VDD
PR729 @ 0_0402_5%~D ISL95833HRTZ-T_TQFN32_4X4
<9> VR_SVID_DAT
1 2 SDA 5 20 PR720 B+
PR731 @ 0_0402_5%~D SDA PWM2 1_0603_5%
1 2 VR_HOT#_1 6 19 LGATE1 @ PJP700
<40> VR_HOT# VR_HOT# LGATE1
PR732 @ 0_0402_5%~D +VCC_PWR_SRC 2 1
1
PR725 NTC 7 18 PHASE1 2 1
3.83K_0402_1% NTC PHASE1 PC714 PC715 JUMP_43X118
PGOOD
PR724 @ 2 1 1 2 8 17 UGATE1 1U_0603_10V6K 1U_0603_10V6K
BOOT1
ISUMN
ISUMP
COMP
ISEN2 UGATE1
ISEN1
2
1 2 PH702
+VCCP
RTN
0_0402_5% 470K_0402_5%_ TSM0B474J4702RE
FB
2200P_0402_25V7K
10U_0805_25V6K
10U_0805_25V6K
100U_25V_M~D
100U_25V_M~D
0.1U_0402_25V6
1 1
5
43P_0402_50V8J~D
PQ701
PR727 PR733 @ + +
PC719
PC730
PC731
1
10
11
12
13
14
15
16
1
27.4K_0402_1% 1 2
PC733
PC734
PC736
PC754
2 1 +5VS
0_0402_5%~D BOOT1 2 2
PGOOD
2
2
UGATE1 4
PR726 @
1 2 VGATE <15,6> PL701
0.22UH_FDUE0640J-H-R22M-P3_25A_20%
3
2
1
0_0402_5%~D
0.22U_0402_16V7K
PR730 54.9_0402_1% 2 1 PHASE1 1 4

.1U_0402_16V7K
+3VS
VSUM+ PR728 +VCC_CORE
1
2 1 SCLK 1.91K_0402_1% 2 3
4.7_1206_5%
5
PR751
11K_0402_1%
2.61K_0402_1%
P1_Vo
0.033U_0402_16V7K
1
2 1 1 2
PQ704
@
PC738
PC739
@ PR735 75_0402_5% PR749 PC742

PR746
B B
10KB_0402_5%_ERTJ0ER103J
2 1 ALERT# 2.2_0603_5% 0.22U_0402_16V7K

PC740
1
1 2
LGATE1 4 P1_SW VCC_core
1000P_0402_50V7K
680P_0402_50V7K
2
1
PR737 130_0402_1% PR713 @ TDC 16A
PC745
2
2 1 SDA 0_0402_5%
PR747
2
Peak Current 33A
PH703
PC756
2
PR750 PC722 @ PR755

.1U_0402_16V7K
3
2
1
@ 365_0402_1% PR736 390P_0402_50V7K PC723 1
VSUM+ 2 OCP current 40A
2
2
VSUM- 2 1 2 1 2 1 2 1 @ 3.65K_0603_1%
Load line -2.9mV/A
1
PC710
499_0402_1% 47P_0402_50V8J
2
@ PR752 @ PC732 PR757

649_0402_1% 2200P_0402_50V7K PR742 VSUM- 2 1
2 1 1 2 PR740 PR741 PC727 42.2K_0402_1% 1_0402_5%
2 1 2 1 2 1 1 2
.1U_0402_16V7K
1
1.78K_0402_1% 130K_0402_1% 150P_0402_50V8F~D

PC743
PR744 PC729
1 2 1 2
2K_0402_1% 330P_0402_50V7K
@
PC737
1 2 VCCSENSE <9>
330P_0402_50V7K
PC741
1 2 VSSSENSE <9>
0.01U_0402_50V7K
A A
Local sense put on HW site

Deciphered Date
PWR_VCORE
1.0
LA-9102P
5 4 3 2 1
5 4 3 2 1
+3VS
@ PJP800
@ PR824 10K_0402_5% VGA_CORE_B+ 2 1
B+
<25>
<25>
<25>
<25>
<25>
2 1
GPU_VID1
GPU_VID2
GPU_VID3
GPU_VID4
GPU_VID5
2 1
PX_MODE
<26,40,54>
GPU_VID1
JUMP_43X118
VGA@ PR819 10K_0402_5%
2 1
PC846 VGA@
PC847 VGA@
PC848 VGA@
VGA@
2200P_0402_50V7K
0.1U_0402_25V6
4.7U_0805_25V6-K
4.7U_0805_25V6-K
VGA@ PR829 10K_0402_5%
1
2 1 GPU_VID2
PC816
@ PR811 10K_0402_5%
2
2 1
0_0402_5%~D
0_0402_5%~D
VGA@ PQ800
@ PR835 10K_0402_5% +5VS
2 1 GPU_VID3
PR833
0.1U_0402_16V7K
D D
2
VGA@ PR807 10K_0402_5% 4
80.6K_0402_1%
0_0402_5%~D
2
2
2 1
PC800
VGA@
PR823
PR818
PR805
VGA@ PR837 10K_0402_5% @ PR813
1
2 1 GPU_VID4 @ 10_0603_1%
3
2
1
@ VGA@ PL800
1
1
1
@ PR827 10K_0402_5% @ @ 0.36UH_FDUM0640J-H-R36M-P3_22A_20%
2 1
VGA_EN
1 4 +VGA_CORE
VID1
VID2
VID3
VID4
VID5
VGA@ PR804 10K_0402_5% +3VS
1
2 1 GPU_VID5 VGA@ VGA@ 2 3
VGA_VCC
PU800 PC802
1
@ PR820 10K_0402_5% VGA@ 1U_0603_10V6K
32
31
30
29
28
27
26
25
PC817 VGA@
PC850 VGA@
PC815 VGA@
1 1
470U_D2_2VM_R4.5M
470U_D2_2VM_R4.5M
2
1
2 1 PR815
10U_0805_6.3V6M
10U_0805_6.3V6M
10U_0805_6.3V6M
PQ802
PQ801
+ +
VGA@ PC843
VGA@ PC849
1K_0402_1%
EN
VID0
VID1
VID2
VID3
VID4
VID5
VID6
1
PR817 VGA@ PC839 VGA@ PR821 @
24 2.2_0603_5% 0.1U_0603_25V7K 4.7_1206_5%
VCC
2
1 2 2
<17> VGA_PWRGD
2
VGA@ PC801 PWRGD 23 VGA_BOOST 2 1VGA_BOOST-11 2 4 4
VGA@
VGA@
BST
1
1000P_0402_50V7K VGA@ PR806 2
1
100K_0402_1% IMON 22 UG_VGA_CORE PC841 @
1000P_0402_50V7K
1 2 3 DRVH
2
1
PR830 @ CLKEN# 21 SW_VGA_CORE 1000P_0603_50V7K
@ PC853
SW
3
2
1
3
2
1
2
<28> VSSSENSE_VGA
1 2 4
FBRTN ADP3211AMNR2G_QFN32_5X5 20
PVCC +5VS
2
0_0402_5%~D 1 2 VGA_FB 5
FB 19 LG_VGA_CORE PC803 VGA@
DRVL
1
VGA@ PC810 VGA@ PC809 VGA_COMP 6 2.2U_0603_10V6K
220P_0402_50V7K 47P_0402_50V8J COMP 18 1 2
PR834 @ VGA_VCC 7
PGND
2
1 2 1 2 1 2VGA_COMP-1
1 2 GPU 17
<28> VCCSENSE_VGA AGND
VGA_ILIM 8
CSCOMP
0_0402_5%~D VGA@ PR812 VGA@ PC804 VGA@ PR816 ILIM 33
CSREF
AGND
RAMP
LLINE
CSFB
1K_0402_1% 470P_0402_50V8J 20K_0402_1%
IREF
RPM
RT
C C
10
11
12
13
14
15
16
VGA@ PR800
2.05K_0402_1%
VGA_IREF
VGA_RAMP
VGA_CSFB
VGA_CSCOMP
VGA_RT
VGA_RPM
VGA_CSCOMP 1
PR825 422K_0402_1% VGA@

2
2
VGA@ PR836
VGA@ PR828
VGA@ PR808
237K_0402_1%
301K_0402_1%
80.6K_0402_1%
1
1
1
1
1
@ VGA@
VGA@ PR809
2
PC805 PC806 220K_0402_1%
2
1500P_0402_50V7K 1200P_0402_50V7K
2
VGA@ PR814 2 1
1K_0402_1%
VGA_CORE_B+
2 1 VGA_RAMP-1 PR810 VGA@
243K_0402_1%
Mars Pro
1
GPU_VID5 GPU_VID4 GPU_VID3 GPU_VID2 GPU_VID1 VGA@ PC807 1 VGA@ PC808

(GPIO_10) (GPIO_14) (GPIO_15) (GPIO_16) (GPIO_20) Core Voltage Level 1000P_0402_50V7K 1000P_0402_50V7K
2
0 1 1 1 1 1.125V +VGA_PCIE
1 2
TDC 3.6A
B 1 0 0 0 0 1.1V B
Peak Current 5.2A
0_0402_5%~D
2
@ PR822
0_0402_5% OCP current 6A
PR826
1 0 0 0 1 1.075V
VGA@
@ VGA@ PL803
PJP807 +VGA_PCIEP
4
1 0 0 1 0 1.05V @ PU801 0.47UH_FDVE0630-H-R47M=P3_17.7A_20%
+3VALW
1
2 1 PCIE_B+ 10 2 LX_PCIE 1 2
PG
VGA_CSCOMP
2 1 PVIN LX
1 0 0 1 1 1.025V 9 3
JUMP_43X79 PVIN LX
1
VGA@
4.7_1206_5%
1
PC833 8
22U_0805_6.3VAM SVIN
VGA@ PR841
1 0 1 0 0 1V
6 FB_PCIE
FB
2
5
22U_0805_6.3VAM
22U_0805_6.3VAM
22U_0805_6.3VAM
22U_0805_6.3VAM
2
1
EN
SS
1 0 1 0 1 0.975V
TP
LX
VGA@ PR843 SY8036LDBC_DFN10_3x3
PC835
PC852
PC837
PC851
<16,26> PXS_PWREN
11
2
1 0 1 1 0 0.95V 1 2EN_PCIE
SNUB_PCIE
VGA@
PC832
0.1U_0402_10V7K
1
1
200K_0402_5% PR832 VGA@
VGA@
VGA@
VGA@
VGA@
0.1U_0402_10V7K
Thames XT
PC842
1 0 1 1 1 0.925V
1
@ PR844 5.9K_0402_1%
2
47K_0402_5% 2 1
VGA@
GPU_VID5 GPU_VID4 GPU_VID3 GPU_VID2 GPU_VID1
1 1 0 0 0 0.9V (GPIO_10) (GPIO_14) (GPIO_15) (GPIO_16) (GPIO_20) Core Voltage Level
680P_0402_50V7K
VGA@ PC834
1 1 0 0 1 0.875V 1 0 0 1 0 1.05V PC840
VGA@
2
2 1
1 1 0 1 0 0.85V 1 0 1 0 0 1V Thames XT Mars Pro
VGA@ PR831
+VGA_PCIEP
22P_0402_50V8J
10K_0402_1%
1 1 0 1 1 0.825V 1 0 1 1 0 0.95V
2
VGA_PCIE 1.0V 0.95V
1 1 1 0 0 0.8V 1 1 0 0 0 0.9V @
PJP806
A A
2 1 PR832 6.81K 5.9K
+VGA_PCIEP 2 1 +1.0VGS
+VGA_CORE +VGA_CORE
JUMP_43X79
TDC 22A TDC 20A
Peak Current 30A Peak Current 30A
OCP current 36A OCP current 36A
FSW=350kHz FSW=350kHz
DCR 1.1mohm +/-5% DCR 1.1mohm +/-5%
Deciphered Date
Loadline = 1.5mohm PWR_VGA_CORE/VGA_PCIE
1.0
LA-9102P
5 4 3 2 1
5 4 3 2 1
D D
+VDDCI
TDC 2.2A
Peak Current 2.2A
@ OCP current 4A
PU1000 PL1000 @
PJP1002
4
@ SY8033BDBC_DFN10_3X3 1UH_NRS4018T1R0NDGJ_3.2A_30%
+3VALW 1 2 10 2 LX_VDDCIP 1 2
PG
1 2 PVIN LX +VDDCIP
@
JUMP_43X79 9 3
22P_0402_50V8J
PVIN LX
2
4.7_1206_5%
22U_0805_6.3V6M
1
1
PC1009 @ 8 PR1011 @
@ PC1007
22U_0805_6.3V6M
SVIN
1
22U_0805_6.3V6M
PR1012
10_0402_5%
6 FB_VDDCIP
@ PC1010
@ PC1012
FB
2
2
EN_VDDCIP 5
2
EN
NC
NC
TP
C C
1 2
FB=0.6Volt
11
1
1 2 @ PR1013
<26,40,53> PX_MODE
1
PR1020 10K_0402_5% 4.99K_0402_1%
680P_0402_50V7K
0.1U_0402_10V7K
2
@
PC1008
@ PC1011
@
1
PR1021 PR1014 @
2
1M_0402_5% 1 2 VDDCI_SEN <28>
@
2
0_0402_5%~D
1
+3VGS
1
@
1
PR1015
1
29.4K_0402_1% PR1016 @
@ 10K_0402_5%
2
PR1018
10K_0402_1% PR1017 @
2
D 10K_0402_5%
2
2 2 1
G VDDCI_VID <25>
1
S
1
PQ1006 @
2N7002W-T/R7_SOT323-3 @ PC1013 PR1019 @
4700P_0402_25V7K 100K_0402_5%
2
VDDCI_VID (GPIO_6)
High 1V
B B
Low 0.9V
PJP1003
@
+VDDCIP 1
1 2
2 +VDDCI
JUMP_43X79
A A

Deciphered Date
PWR_+VDDCIP
1.0
LA-9102P
5 4 3 2 1
A
B
C
D
5
5
+VCC_CORE
+VCC_CORE
+VCC_CORE
2 1 2 1
2
1
2
1
2
1
22U_0805_6.3V6M 22U_0805_6.3V6M 2.2U_0402_6.3V6M 2.2U_0402_6.3V6M
PC1222 PC1216 PC1208 PC1200
PC1228
2
1
2
1
2 1 2 1
330U_D2_2V_Y
22U_0805_6.3V6M 22U_0805_6.3V6M
PC1223 PC1217 2.2U_0402_6.3V6M 2.2U_0402_6.3V6M
PC1209 PC1201
2
1
2
1
2
1
2 1 2 1
2 1 2 1 22U_0805_6.3V6M 22U_0805_6.3V6M
+VCCP
PC1229
PC1224 PC1218 2.2U_0402_6.3V6M 2.2U_0402_6.3V6M
For TOP side
PC1270 PC1257 PC1210 PC1202

For BOT side
WWW.MANUALS.CLAN.SU
1U_0402_6.3V6K 1U_0402_6.3V6K
330U_D2_2V_Y
2
1
2
1
2 1 2 1 2 1 2 1
4
4
2
1
+
22U_0805_6.3V6M 22U_0805_6.3V6M
PC1271 PC1258
PC1225 PC1219 2.2U_0402_6.3V6M 2.2U_0402_6.3V6M
1U_0402_6.3V6K 1U_0402_6.3V6K PC1211 PC1203
PC1230
2 1 2 1
2
1
2
1
2 1 2 1
PC1272 PC1259 22U_0805_6.3V6M 22U_0805_6.3V6M
1U_0402_6.3V6K 1U_0402_6.3V6K
330U_D2_2V_Y
PC1226 PC1220 2.2U_0402_6.3V6M 2.2U_0402_6.3V6M
PC1212 PC1204
2 1 2 1 2 1
2
1
2
1
PC1283 PC1273 PC1260 2 1 2 1

10U_0603_6.3V6M 1U_0402_6.3V6K 1U_0402_6.3V6K 22U_0805_6.3V6M 22U_0805_6.3V6M
PC1227 PC1221 2.2U_0402_6.3V6M 2.2U_0402_6.3V6M
2 1 2 1 2 1 PC1213 PC1205
PC1284 PC1274 PC1261 2 1 2 1

10U_0603_6.3V6M 1U_0402_6.3V6K 1U_0402_6.3V6K
2.2U_0402_6.3V6M 2.2U_0402_6.3V6M
2 1 2 1 2 1 PC1214 PC1206
PC1285 PC1275 PC1262 2 1 2 1

10U_0603_6.3V6M 1U_0402_6.3V6K 1U_0402_6.3V6K
2.2U_0402_6.3V6M 2.2U_0402_6.3V6M
2 1 2 1 2 1 PC1215 PC1207
PC1286 PC1276 PC1263

10U_0603_6.3V6M 1U_0402_6.3V6K 1U_0402_6.3V6K
2 1 2 1 2 1
PC1287 PC1277 PC1264

10U_0603_6.3V6M 1U_0402_6.3V6K 1U_0402_6.3V6K
+VCC_GFXCORE_AXG
2 1 2 1 2 1 PC1254
330U_D2_2V_Y
PC1288 PC1278 PC1265
+
10U_0603_6.3V6M 1U_0402_6.3V6K 1U_0402_6.3V6K

2
1
2 1 2 1 2 1
PC1289 PC1279 PC1266
3
3
10U_0603_6.3V6M 1U_0402_6.3V6K 1U_0402_6.3V6K

Vaxg
2
1
+
2 1 2 1 2 1 2 1 2 1
2
1
PC1255
PC1290 PC1280 PC1267 330U_D2_2V_Y 22U_0805_6.3V6M PC1242 PC1231
10U_0603_6.3V6M 1U_0402_6.3V6K 1U_0402_6.3V6K PC1248 10U_0603_6.3V6M 1U_0402_6.3V6K
2 1 2 1 2 1 2 1 2 1
2
1
PC1291 PC1281 PC1268 22U_0805_6.3V6M PC1243 PC1232

PC1294 10U_0603_6.3V6M 1U_0402_6.3V6K 1U_0402_6.3V6K PC1249 10U_0603_6.3V6M 1U_0402_6.3V6K
330U_D2_2V_Y
2 1 2 1 2 1 2 1 2 1
2
1
2
1
floating) if the VR is stuffed
PC1292 PC1282 PC1269 22U_0805_6.3V6M PC1244 PC1233

10U_0603_6.3V6M 1U_0402_6.3V6K 1U_0402_6.3V6K PC1250 10U_0603_6.3V6M 1U_0402_6.3V6K
Issued Date
2 1 2 1
2
1
2
1
Security Classification
PC1293 22U_0805_6.3V6M PC1245 PC1234
330U_D2_2V_Y PC1251 10U_0603_6.3V6M 1U_0402_6.3V6K
2 1 2 1
‧ VAXG can be left floating in a common
stuffed in a common motherboard design,
2
1
PC1246 PC1235
‧ Can connect to GND if motherboard only
22U_0805_6.3V6M
PC1252 10U_0603_6.3V6M 1U_0402_6.3V6K
motherboard design (Gfx VR keeps VAXG from
supports external graphics and if GFX VR is not
2 1 2 1
2
1
22U_0805_6.3V6M PC1247 PC1236
2012/09/25
PC1253 10U_0603_6.3V6M 1U_0402_6.3V6K
2 1
PC1237
1U_0402_6.3V6K
2 1
PC1238
1U_0402_6.3V6K
2
2
2 1
PC1239
1U_0402_6.3V6K
Compal Secret Data
Deciphered Date
2 1
PC1240
1U_0402_6.3V6K
2 1
PC1241
1U_0402_6.3V6K
2013/09/30
Size
Title
Date:
Document Number
LA-9102P
1
1
Tuesday, September 25, 2012

Sheet
55
Compal Electronics, Inc.
of
57
PWR_PROCESSOR DECOUPLING
Rev
1.0
A
B
C
D
5 4 3 2 1
D Power block D
CPU OTP
Page 44
Turn Off
Input B+
DC IN +3VALWP: TDC:5.4A
Switch Page 45 +5VALWP: TDC:5.6A Always
RT8205LZQW(2) WQFN Page 46
CHARGER
CC:0A~1A(4cell) or 2.1A(6cell) +3VALW
CV:17.7V(4cell) / 13.3V(6cell)
ISL88731CHRTZ-T
C +1.8VSP: TDC:2.6A SUSP# C
Page 45 SY8033BDBC
Page 47
Battery
+VCCSAP: TDC:4.2A +V1.05S_VCCP_PWRGOOD
SY8037DDCC
Page 50
+VGA_PCIEP: TDC:3.6A PXS_PWREN

SY8036LDBC
Page 52
+VDDCIP: TDC:2.2A PX_MODE

+VGA_CORE SY8033BDBC
PX_MODE
B TDC: 22A Page 53 B
ADP3211AMNR2G_QFN32
Page 52
+VCCP: TDC:11A SUSP#

TPS51212DSCR Page 48
+VCC_CORE
VR_ON
TDC: 16A +1.5VP/+0.75VSP: TDC:6A/0.7A SYSON
ISL95833HRTZ-T_TQFN32 RT8207MZQW
Page 51
Page 49
+VCC_GFXCORE_AXG +1.5VGPUP: TDC:4.2A SUSP#

VR_ON
TDC: 12A TPS51212DSCR Page 49
ISL95833HRTZ-T_TQFN32
Page 51
A A

Deciphered Date
PWR_POWER BLOCK DIAGRAM
1.0
LA-9102P
5 4 3 2 1
5 4 3 2 1

Request
D
Item Page# Title Date Owner Issue Description Solution Description Rev. D
1 52 VCORE 12/05/11 Morris adjust VR parameter change PL700 and PL701 from 0.36u to 0.22u X00
change PC707 and PC740 from 0.047u to 0.033u
change PR750 from 649 to 365
change PR711 from 649 to 392
change PR740 from 1.91k to 1.78k
change PR705 from 150k to 33.2k
2 45 DCIN/BATT CONN/OTP 12/05/11 Morris follow SSI memo for part shortage issue change PQ112,PQ114,PQ1111,PQ206,PQ904 from SB00000CQ00 to SB00000PV00 X00
46 CHARGER
47 3.3VALWP/5VALWP
3 50 +1.5VP/1.5VDGPU/0.75VSP 12/05/15 Morris design change change PR302 from 12k to 8.66k X00
4 51 +VCCSAP 12/05/23 Morris for Pentium and Celeron special BOM add PR607 and reserve X00
5 50 +1.5VP/1.5VDGPU/0.75VSP 12/07/06 Morris design change to reduce low-side mosfet induce add PC316 1000pf X01
6 46 CHARGER 12/07/17 Morris from EMI request change PR114 from 0 to 2.2 X01
add PR141 and PC121
7 46 CHARGER 12/07/17 Morris design change to solve Battery LED change PR142 from 210k to 232k for ISL88731C (X76) X01
is still on after unplug AC when SUT in S3S4S5 issue change PR142 from 309k to 324k for BQ24747 (X76)
C C
8 45 DCIN/BATT CONN/OTP 12/07/17 Morris revise OTP setting to 96C from thermal request change PR927 from 12.1k to 11k X01
delete PR811,PR827
9 52 VCORE 12/08/27 Morris adjust initial output voltage from vendor recommend add PR829,PR837 X02
B B
A A

Deciphered Date
PWR-PIR
1.0
LA-9102P
5 4 3 2 1

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A B C D E

MODEL NAME : VAW11

DA40001G400 LS-9105P POWER BUTTON/B

Dell / Compal Confidential

Intel Chief River

46@ : for 46 level

Fan Control CPU XDP

VRAM * 4 AMD PEG 2.0 x8

Half P.38 P.32

RJ45 Port 9 Touch Screen

DC/DC Interface CKT. ENE KBC

Int.KBD Touch Pad

Security Classification Compal Secret Data Compal Electronics, Inc.

SW1 4 pin-Hot Bar JBTB2

JTP LS-9102P (USB/B)

JUSB1 USB Top Side JHDD

Board ID Table for AD channel

PCH_SML0CLK PCH Link 8 MINI CARD (WLAN)

MEM_SMBCLK PCH V V V V V V 10 Card Reader

CLKOUT_PCIE0 10/100 LAN CLKOUTFLEX0 None 13 NC

CLKOUT_PCIE1 MINI CARD WLAN CLKOUTFLEX1 None

CLKOUT_PCIE5 None SATA2 ODD Lane 3 None

: means Analog Ground

UC1 i3R1@ UC1 i3R3@ UC1 i3VOSR1@ UC1 i3VOSR3@

SA00005L52L SA00005L53L SA00005UH1L SA00005UH2L

AV8063801058401-SR0N9-L1-1.8G_BGA1023~D AV8063801058401-SR0N9-L1-1.8G_BGA1023~D AV8062701313000-SR0U3-J1-1.4G_BGA1023~D AV8062701313000-SR0U3-J1-1.4G_BGA1023~D

SA00005K62L SA00005K53L SA00005K52L

PEG_RCOMPO (G4) R_COMP place close to CPU SA00006021L SA00006022L

SA00005K63L UC1I i5R1@

FDI_CTX_PRX_N6 Y2 FDI1_TX#[1] PEG_RX[8] C9 PEG_GTX_C_HRX_P6 E29 VSS[209] VSS[278] T1

C8 PEG_GTX_C_HRX_P4 PEG_GTX_C_HRX_P4 <24> E35 T50

G17 L30 BE4

Security Classification Compal Secret Data Compal Electronics, Inc.

signal to determine if the processor is present XDP_TDI_R 51_0402_5% 1 2 RC46

A48 AT30 H_DRAMRST# H_DRAMRST# XDP_PREQ# 51_0402_5% 1 @ 2 RC48

B 1 2 H_PROCHOT#_R C45 BE43 SM_RCOMP1 25.5_0402_1%1 2 RC83 0.1U_0402_25V6K B

J58 XDP_TRST# RC126 1 @ 2 0_0402_5% XDP_TRST#_R

<15> H_PM_SYNC H_PM_SYNC C48 M60 XDP_TDI_R RC50 1 @ 2 0_0402_5% XDP_TDI

Security Classification Compal Secret Data Compal Electronics, Inc.

UC1C i5R1@ UC1D i5R1@

DDR SYSTEM MEMORY B

<6> H_DRAMRST# H_DRAMRST# 3 1 DDR3_DRAMRST#_R 1 2 1

Security Classification Compal Secret Data Compal Electronics, Inc.

CFG Straps for Processor

PEG Static Lane Reversal - CFG2 is for the 16x

+VCC_GFXCORE_AXG @ CFG13 G53 CFG[12] RSVD36 W14 @ T20 PAD~D @ 1K_0402_1%

@ PAD~D T89 @ L53 CFG[16] AT49

RC119 K24 @ T23 PAD~D

@ AG13 @ T27 PAD~D Display Port Presence Strap

@ PAD~D T46 @ H48

PAD~D T32 @ AV19 D1 TP_DC_TEST_D1 @ T118 PAD~D

0: PEG Wait for BIOS for training

Security Classification Compal Secret Data Compal Electronics, Inc.

UC1F i5R1@ POWER +VCCP

PEG IO AND DDR IO

VCC[74] VCCPQE[1] RC145 close to CPU 300~1500mils

N38 RC147 close to CPU

C44 H_CPU_SVIDDAT RC144 1 @ 2 0_0402_1%

G43 VSSSENSE_R RC122 1 @ 2 0_0402_1%

A AV8063801058002-SR0N8-L1-1.7G_BGA1023~D Place RC98 close to CPU A

Security Classification Compal Secret Data Compal Electronics, Inc.

AM28 AJ30 BA1

VCCDQ[1] VSS[64] VSS[154]

AK52 VSS[71] VSS[161] BB53