IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 41, NO.
9, SEPTEMBER 2006
A 110 nA Voltage Regulator System With Dynamic
Bandwidth Boosting for RFID Systems
Ganesh K. Balachandran and Raymond E. Barnett
Abstract—This paper describes a voltage regulator system for
ultra-low-power RFID tags (also called passive tags) in a 0.15 m
analog CMOS technology. These tags derive their power supply
from the incoming RF energy through rectification instead of from
a battery. The regulator is functional with just 110 nA current.
Owing to the huge variation of the rectified voltage (by as much as
tens of volts), voltage limiters and clamps are employed at various
points along the regulation path. A limiter at the rectifier output
clamps the rectifier voltage to a narrower range of 1.4 V. A fine-reg-
ulator, then, regulates the supply voltage close to a bandgap refer-
ence value of 1.25 V. The key aspect of this regulator is the dynamic
bandwidth boosting that takes place in the regulator by sensing
the excess current that is bypassed in the limter (during periods
of excess energy) and increasing its bias current and hence band-
width, accordingly. A higher bandwidth is necessary for quick re-
covery from line transients due to the burst nature of RF transmis-
sion, with a larger energy burst requiring a higher bandwidth to
settle quickly without large line transients. The challenge of com-
pensating such a regulator across various load currents and RF
energy levels is described in this paper.
Index Terms—Frequency compensation, passive tags, power
management, RFID, voltage regulator.
I. INTRODUCTION
T HERE is great interest in the area of radio frequency identi-
fication (RFID) tags [1], [2] due to a large number of appli-
cations where they could be used to collect information about a
large number of assets quickly, easily and without human error.
RFID tags can be read from and written to without the need
for direct line-of-sight. Tags fall into two categories—active and
passive. Active tags use a battery to power the circuits. Passive
tags, on the other hand, are used for high-volume commercial
applications. Due to cost reasons, the die area for passive tags
is small, usually well within 1 mm , and they do not use a bat-
tery or any other external components, but for the antenna. The
power management strategy for these two, thus, greatly differ.
The entire passive tag is powered by rectifying the incoming
energy to a DC voltage. This energy source can be a RF signal
obtained through an antenna or a low frequency (tens of kHz
to several tens of MHz) AC signal introduced by a coupling
mechanism, like a magnetic coupler. This paper focuses on a
passive tag operating in the ultra-high-frequency (UHF) range
around 900 MHz, using an antenna to pick up RF signals. The
next paragraph describes the method of communication to and
Manuscript received October 9, 2005; revised March 20, 2006.
The authors are with Texas Instruments Incorporated, Dallas, TX 75243 USA
(e-mail: ganesh2@ti.com; raybarnett@ti.com).
Digital Object Identifier 10.1109/JSSC.2006.881015
0018-9200/$20.00 © 2006 IEEE
2019
from the tag and the various constraints it poses on the power
management scheme.
UHF RFID tags [3]–[5] communicate with a central base unit
called the reader by pulsed RF communication. For the for-
ward link (reader to tag communication), the presence of RF
energy denotes a bit “1” and a lower level or complete absence
of RF energy denotes a bit “0”.1 For the reverse link (tag to
reader communication), the reader puts out a constant RF signal
(without pulsing) and the tag signals a bit “1” by changing its
input impedance from its normal value that is closely matched2
to that of the antenna, to a lower value by connecting it through
a switch to ground (Fig. 1). This reflects a large amount of the
received RF power back to the reader. This process is called
backscattering. A bit “0” is signaled by retaining the impedance
match with the antenna thus reflecting very little power back to
the reader. Thus, during both forward and reverse communica-
tions, there are times when there is little RF power available to
the chip. During such times of very low RF power, the chip con-
tinues to work by drawing current from a large on-chip storage
capacitor which is charged by a voltage regulator during times
of RF power availability. For reasons of die area, the value of
the storage capacitor, , is limited to several hundereds of pF.
This value of along with the duration of absence of RF power
(typically a few s and set by the standard), sets the maximum
current consumption of the chip which is usually 1–3 A. Thus,
the Voltage regulator system itself should not consume much
more than a 100 nA of current.
Finally, the most severe constraint for the tag described in this
paper comes from the low supply voltage ( V)
requirement due to the use of a 0.15 m CMOS process where
the standard MOS devices are rated to operate off 1.5 V or less.
The use of thick oxide (3.3 V) devices is not an option for a
low-voltage and area sensitive chip like this with nearly 50% of
the area consisting of digital circuitry. This is because the thick
oxide devices have a longer minimum channel length (1 m)
and also the larger threshold voltages (as high as 1 V at 40 C).
The nominal value of the supply voltage is typically set a little
below this value (to 1.25 V in this case) of 1.5 V to give room
for certain kinds of data bursts at low chip currents which result
in a larger positive transition than the decay that happens during
the negative transition (Fig. 2). This is because the reverse path
from the supply voltage, , to the antenna is blocked by many
diodes, some of which are in the rectifier (Fig. 3) and others
1It has to be noted that the symbols are typically an encoded stream of bits
with a symbol-1, for example, being denoted by the bit pattern “1110” and the
symbol-0 by, say, “10” with the idea that there is a sufficient time during which
there is RF energy even when a series of symbol-0’s are transmitted.
2Due to nonlinearity of the chip input impedance, the impedance match is
provided only at a certain input power level which is the minimum input power.
2020 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 41, NO. 9, SEPTEMBER 2006

Fig. 1. Voltage regulation system for the RFID tag.

Fig. 2. Illustration of the necessity for tight V requirement.

in the limiter. The rectifier by its very nature allows current in

only one direction. This prevents leakage of the charge stored
on the storage capacitor from dissipating through the antenna
into the ground when there is no RF signal present. Due to this
uni-directional current path from the antenna to the node,
there is no negative jerk on the node to match the positive
jerk encountered during RF surges. The only droop on is
induced by the chip load current which consumes the charge on
the storage capacitor and decreases its voltage. Such a switching
operation can result in a larger value of the supply voltage than
set by the DC operating point as is shown in Fig. 2. On the
other extreme, the minimum ( ) that is reached at
the end of the droop period when there in no RF energy, should
be greater than 0.8 V so that the analog circuits in the chip can
still operate comfortably. From Fig. 2, using typical values of Fig. 3. Rectifier circuit.
0.2 V for and 0.2 V for , the range, , into
which the nominal , , should fall is given by
as is done in most RFID tags [4], [6]. Fig. 4 shows a circuit of
such a crude clamp used in [4]. When the voltage at node B
exceeds four times the MOS threshold voltage ( ), the bypass
V V V V device turns on and provides an alternate path for the excess rec-
V (1) tifier current, thereby clamping the voltage at B to nearly four
times . It can easily be seen that there is a significant vari-
Such a small allowable range for is not possible across ation in the clamped voltage due to dependence. Hence, a
process and temperature variations with the use of crude clamps bandgap-based reference is necessary. Even the ones that use
BALACHANDRAN AND BARNETT: A 110 nA VOLTAGE REGULATOR SYSTEM WITH DYNAMIC BANDWIDTH BOOSTING FOR RFID SYSTEMS 2021

Fig. 4. Voltage regulation using a crude clamp.

Fig. 5. Voltage regulation using a bandgap reference.

a bandgap reference, suffer from limited bandwidth and insta- potential instability at certain rectifier currents. This can be seen
bility problems, limiting their use to a narrow range of rectifier by breaking the loop at A and calculating the loop gain (LG).
currents (which translates to a small range for the tag). Fig. 5
shows one such reference reported in [4].When the rectifier puts
out a large amount of current, the increases beyond a cer- LG
tain fixed value (determined by the resistor divider ratio and (2)
the value of the reference) and this turns the bypass device on, where the different notations are shown in Fig. 5. Clearly, at high
thus regulating . The problem with this topology lies in the values of the rectifier current, is large and this can result in
2022
Fig. 6. Schematic of the limiter.
a large unity-gain frequency and a small secondary pole (due to
and ) if the nonlinear rectifier output resistance does
not drop at a rate faster than the increase of with increase
in rectifier current. This can lead to very low phase margin and
potential instability. On the other hand, if drops at a rate
much faster than the increase of with increasing rectifier
current, this will result in a stable system but with a very low
bandwidth.
Since the quiescent current of the regulator system needs to
be as low as 100 nA when the input RF signal is at its weakest,
the resulting bandwidth of the closed loop regulator will also be
low. But the bandwidth of the regulator needs to be large for it
to recover quickly from periods of no RF energy to a full blast
of RF energy. For this reason, a dynamic biasing scheme is em-
ployed in the regulator which senses and uses a small part of the
current wasted in the limiter when the input RF energy is high.
This boosts the bandwidth of the regulator and the regulator
output reaches the DC value fast and without much overshoot.
However, with the load varying over a wide range (0.1 to 25 A)
and the input RF signal varying from 0.25 V-peak to 1.8 V-peak,
stability of the regulator is challenging. This paper discusses
how the regulator is made unconditionally stable across the en-
tire range of load currents and RF signals.
II. GROSS REGULATION OF SUPPLY VOLTAGE
The antenna can be modeled as having a nearly constant
impedance in series with a Thevenin sinusoidal voltage source
whose peak voltage can range from 0.5 V to 40 V, depending
on the vicinity of the reader to the tag. In order to obtain the
final regulated of 1.25 V without wasting the RF energy
at low power levels, but strongly clamping at higher power
levels to protect devices, a progressive regulation scheme is
used as shown in Fig. 1. The rectifier consists of six stages
of the basic Schottky-diode-based voltage doubler as shown
in Fig. 3. The rectifier input is protected using an RF clamp
which limits the input swing in either direction to not more
than 1.8 V-peak. At high RF signal levels, if there is no bypass
path for the rectifier’s DC output current to flow through, the
voltage at the rectifier output can exceed 10 V and thus damage
several components. A DC limiter provides such a bypass path
and is shown in Fig. 6. The basic shunting path consists of two
p-n junction diodes, D0 and D1, and the MOS-diode, M0. The
IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 41, NO. 9, SEPTEMBER 2006
number of diodes in the limiting path and the size of the MOS
diode is chosen so that at low RF levels, the limiter does not
load the rectifier and almost all the current coming out of the
rectifier flows into the regulator and to various IC blocks. At
high levels, though, the shunt impedance offered by the limiter
to the rectifier is smaller than the output impedance of the
rectifier itself. Thus, it provides a bypass for the excess current.
A MOS diode (M0) is used and not another p-n junction diode,
because the MOS diode serves as a good current sensing ele-
ment which can then be used to dynamically bias the regulator.
The current through the MOS diode is also mirrored inside
the limiter to achieve better control of the slope of the limiter
output voltage as a function of the rectifier output current. This
can be seen as follows. For low values of the rectifier current,
( A), none of the mirror transistors, M1 through
MN ( for the current implementation), are in the linear
region due to the low voltage drops across resistors R1 through
RN. Hence, each of these transistors conducts the same current
as M0. The voltage at the output of the limiter, , is then
given by
(3)
where voltage drops of the regular diodes are represented by
and those of the Scottky diodes by . Both and change
very little with the load current, . Therefore, the derivative of
with respect to is given by
(4)
For low values of , the first term in the slope is dominant
resulting in a positive overall slope (Fig. 7). Clearly, has
a maximum value at a rectifier current , given by
(5)
BALACHANDRAN AND BARNETT: A 110 nA VOLTAGE REGULATOR SYSTEM WITH DYNAMIC BANDWIDTH BOOSTING FOR RFID SYSTEMS
Fig. 7. Sketch illustrating slope control to obtain a smooth I –V characteristic.
Fig. 8. Simulated limiter I –V characteristics for different number of mirrored
legs.
Fig. 8 shows the – characteristics of the limiter for two,
four, and six mirrored legs, respectively. Clearly, if only the
basic shunt path consisting of D0, D1, and M0 were used,
the output voltage will continue to rise as the rectifier current
increases and the voltage will exceed the maximum rated
voltage for the devices in the fine regulator. The use of multiple
mirror legs helps provide a dip in the output voltage of the
limiter making it as flat as possible. As the current through
M0 increases, the equally mirrored current in each of the
legs increases. This causes the voltage drops across the shunt
resistors, R1–RN, to increase. Ultimately, starting from M1,
the drain–source voltages of each of the transistors, M1–MN,
collapses successively below their respective saturation volt-
ages ( ) and the current in each leg will be clamped.
This results in the second term in (4) decreasing gradually and
preventing a plummeting down of the limiter voltage as shown
in the sketch of Fig. 7. More the number of legs, the flatter the
– curve. Fig. 8 shows the simulated result for the case with
six legs as compared to that for two and four legs. Region 1
is that part of the curve which is primarily by the square-law
2023
characteristics of M0. In region 2, the slope gradually decreases
as each leg of the mirror saturates on account of the transistors
going into linear region. Once the currents in all the legs have
saturated, the voltage rises again, giving rise to region 3, where
the shape of the curve is not just determined by the of
transistor M0 but also by the series parasitic resistances of the
p-n diodes D0 and D1 which are implemented with pMOS
bulk-source diffusions.
III. FINE REGULATION USING A VOLTAGE REGULATOR
The regulator circuit is shown in Fig. 9. The various aspects
of this regulator are outlined below.
A. Supply
The supply to the regulator (denoted as PRE-REG in Fig. 9)
comes from the output of the limiter and can be as high as 2.2 V
under the worst case process and temperature corner. Despite
this high a pre-regulated voltage, which exceeds the rated gate
voltage of 1.5 V for all the devices in the regulator, none of the
device gate-source voltages see the entire pre-regulated voltage
because there is a stack of at least two gate-source drops be-
tween the supply and ground. The MOS drain (or source) junc-
tion breakdown voltages ( V) are much higher than the gate
to drain (or source) breakdown voltage and hence is not a con-
cern here. At the other extreme, the output of the limiter can be
as low as 1 V at low RF levels. Under this case, the pass de-
vice of the regulator, Mpass, will operate in the linear region,
acting as a switch. The regulator feedback loop would have sat-
urated and the would then be the same as the Limiter output
voltage. The pass device will go into the saturation region and
the loop will regulate the output only when the limiter output
voltage exceeds the desired regulated voltage of 1.25 V.
B. Bandgap Reference
A bandgap reference is implicitly generated using resistors
R1, R2, R3, the substrate p-n-p Q1, and the error amplifier
shown inside the shaded box. The input devices, Min1 and
Min2, of the error amplifier have their sizes skewed to op-
erate with a deliberate offset when their currents are forced
by the mirrors Mp1 and Mp2. In subthreshold, their –
characteristics are exponential and therefore this offset is a pro-
portional-to-absolute-temperature (PTAT) voltage. This small
PTAT voltage is scaled using resistors R1 and R2 to generate a
larger PTAT voltage which is then summed with the of Q1
to produce a bandgap voltage of 1.25 V at the output denoted
by OUT. This voltage provides the for the entire chip. The
reason why the bandgap voltage of 1.25 V and not a higher
scaled voltage (like 1.4 V) is used as the is several fold.
First, this initial value of 1.25 V is amply sufficient even when
there is a 0.2 V droop during a period of RF absence in a data
burst. The resulting voltage of 1.05 V will be amply sufficient
to operate the analog circuits on the chip, which are operational
down to V. Secondly, if the voltage is increased
to, say, 1.4 V by scaling R1 and R2, the resulting voltage will
have a stronger PTAT component and hence more temperature
variation. The third reason is to give some room so that under
the data bursts mentioned in Section I, the voltage does not
gravitate towards the safe limit of 1.5 V. The absolute variation
2024
Fig. 9. Schematic of the regulator.
Fig. 10. Schematic of the unity-gain buffer.
of this regulated voltage of 1.25 V due to device non-idealities
(like offset, resistor mismatch) is just V as will be seen,
again, in the section on measurement results (Section VI).
C. Unity Gain Buffer
This unity-gain buffer isolates the larger of the pass de-
vice from node B and pushes the pole formed at node B further
away, increasing stability. It is a simple differential amplifier
with a current mirror load (Fig. 10). Its output is connected to
the negative input thus achieving unity gain.
IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 41, NO. 9, SEPTEMBER 2006
D. Dynamic Biasing
As discussed earlier, the purpose of dynamic biasing is to in-
crease the bandwidth and react fast to supply variations. Supply
variations are large only when there is a surge of RF energy.
During such times, a small part of the excess current, which
would otherwise be bypassed in the DC limiter, is used to in-
crease the bias. Fig. 9 shows the two types of current sinks used
in the regulator– the normal current sink and the variable current
sink. Both the normal current sinks in Fig. 9 have nominal values
of 25 nA. This provides just adequate bias during low RF power
for the regulator to be functional. The dynamic current sink con-
sists of a resistively degenerated transistor (Fig. 11). The gate of
the MOS device is connected to that of the MOS diode, M0, in
the limiter (Fig. 6). At low values of current in the MOS diode
(i.e., when the RF power is low), the voltage across the degener-
ating resistors is not significant and the mirroring is 1:1. How-
ever at high values of current in the MOS diode, the mirrored
current is limited to a certain maximum value by the degener-
ating resistor. This is done for stability as explained next.
E. Compensation of the Feedback Loop and Stability
Considerations
With the load current varying from 100 nA to 25 A
and the rectifier’s output current varying from 2 A to
BALACHANDRAN AND BARNETT: A 110 nA VOLTAGE REGULATOR SYSTEM WITH DYNAMIC BANDWIDTH BOOSTING FOR RFID SYSTEMS 2025

Fig. 11. Current sink used for dynamic bias.

Fig. 13. Simplified block diagram of the regulator feedback loop.

these poles is that formed by the resistor string comprising re-

sistors R1, R2, and R3 in Fig. 9 and the combination of their
self-capacitances and the input capacitance of the error am-
plifier. Hence, further increase of unity-gain frequency by in-
creasing the dynamic current will lead to a decreasing phase
margin. So the dynamic bias is limited to a certain maximum
value determined by stability considerations.
Node A is a virtual ground due to the low impedance of
transistor Mc2. Therefore, whatever current flows into node A
comes out of the drain of Mc2. Hence, the feedback loop can be
further simplified, as shown in Fig. 13, for ease of analysis.

IV. ANALYSIS OF THE LOOP GAIN

Fig. 12. Block diagram of the feedback loop of the regulator.
In this section, an analysis of the stability of the regulator is
done across a wide range of and . Though changes
3 mA, the stability of the regulator is challenging. The com- both the dynamic bias, , and the pre-regulated voltage
pensation scheme proposed by Ahuja [8], [9] provides stability (output of the limiter), , only is of concern in the
across a wide range of load currents. Fig. 12 is a simplified block stability analysis because it is and not that determines
diagram of the circuit of Fig. 9. It shows the different kinds the transconductances and output impedances as long as
of bias—fixed, dynamic or both—used for the various blocks. is large enough to keep various devices in the saturation region.
refers to the transconductance of the pass device, Mpass of Thus, the two variables that are of concern in the stability
Fig. 9. is the transconductance of the skewed differential analysis are and . The dynamic bias currents, which are
pair Min1 and Min2. denotes the small-signal division ratio zero at minimum RF power, saturate at 10 A for high rectifier
in the resistor string and has a value output currents because of the degenerating resistor shown in
Fig. 11. With so much variation, a brute-force simulation of
(6) loop gain across all corners is not a good idea. A better way
to study this circuit is by analyzing the generic expression for
(The of transistor Q1 is much smaller than the sum of the re- loop gain and studying how the poles move with and .
sistors in the string and is neglected). denotes the interstage The generic expression for the loop gain [7], after making
parasitic capacitance which is small and less than 50 fF. Cc is a a few valid assumptions like fF pF
2 pF compensation capacitor and is the load capacitor, which pF , is
is 250 pF. The dynamic current boosts the unity-gain frequency
LG
of the regulator by increasing . Increasing unity-gain fre-
quency without increasing the secondary poles will lead to a de-
creased phase margin and potential instability. So, the dynamic (7)
bias current pushes certain secondary poles to higher frequen- refers to the parallel combination of the output impedance
cies (most notably the buffer pole and the output pole formed by of the pass device and the load. is the output impedance of
with ) by increasing the transconductances of all tran- the first transconducance stage denoted by . The pole due to
sistors. However, there are certain parasitic poles which do not the unity-gain buffer is also neglected in this expression because
scale with transconductance and can decrease phase margin if it lies much beyond the unity-gain frequency ( ), scales along
the unity-gain frequency is very large. The most prominent of with (due to both of them scaling up with increased dynamic
2026 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 41, NO. 9, SEPTEMBER 2006

bias) and causes very little phase degradation at unity-gain. It

can be seen that the poles vary with the load current (because
changes both and ) and the dynamic bias (due
to change in , and ). Also, the DC loop gain varies
with both and . For the system to be stable, the poles
( and ) have to lie far apart, thereby making one of them
dominant. How far apart they should be is a function of the DC
loop gain, . With , the loop gain expression can
be simplified as shown in (8):

LG

(8)

For a phase margin greater than approximately 45 degrees, the

secondary pole has to be greater than the unity-gain frequency,
, with the phase margin approaching 90 degrees if . Fig. 14. Phase margin versus rectifier current for various load currents.
Thus, a term given by

(9) the current sources as seen in Fig. 11. The loop gain LG is then
given by
is defined as a figure of merit for stability with a larger value
indicating higher phase margin. LG
A quick and accurate way to analyze the stability of the loop
gain in (7) is by separating the characteristic polynomial into (13)
two extremities given by and
. For the case when , both
and need to be very small because is biased by the where the pole given by
sum of the currents and and has a maximum value
because the first transconductance stage is biased by the sum of (14)
a fixed current and . The loop gain LG is then given by
is the dominant pole formed by the Miller multiplication of the
LG compensation capacitor by the gain of the second stage. The
other pole is formed at the output. This indicates strong Miller
(10) effect and pole splitting [7]. The expression for becomes

The system reduces to a simple two-pole parallel compen- (15)

sated circuit with the dominant pole formed by and . As
and are decreased, the secondary pole formed by which can, again, be made larger than 1 by making small
and reaches a certain minimum value and decreases no fur- by using the unity-gain buffer in Fig. 13.
ther due to attaining a maximum value. The unity-gain fre- Thus it is clear that at low values of both and , the
quency, given by system is compensated by the load capacitor and exhibits excel-
lent stability. Similarly at high values of both , the system
(11) exhibits excellent stability due to the strong Miller effect. The
phase margin is the lowest at intermediate values of both and
however, decreases due to decrease in and the expression . If it is ensured that there is sufficient phase margin at these
for becomes intermediate values, the system is stable across the entire range
of and .The next section gives the simulation results for
(12) the loop gain.

which can be made much greater than 1 for small enough values V. SIMULATION RESULTS
of . Stability is thus very good at low values of both Fig. 14 shows the phase margin and Fig. 15 shows the unity-
and . gain frequency as functions of the rectifier current for var-
For the other extreme, i.e., , needs to ious . At low values of , the phase margin is very high
be large and not too large as to decrease considerably. due to the unity-gain frequency being very low. There is a dip
Limiting to a certain value is easily done by degenerating in the phase margin for intermediate values of . This dip is
BALACHANDRAN AND BARNETT: A 110 nA VOLTAGE REGULATOR SYSTEM WITH DYNAMIC BANDWIDTH BOOSTING FOR RFID SYSTEMS
Fig. 15. Bandwidth versus rectifier current for various load currents.
Fig. 16. Simulated regulator output voltage response to pulsed RF, with and
without bias boosting.
not prominent for a high load current of 50 A due to signifi-
cant Miller effect. It can also be seen that the phase margin for
large values of (i.e., when saturates) is a fixed value.
This can be seen from (15), where , which is a measure of
phase margin, is a constant and dependent only on the capacitor
values and resistor ratio which are all constant.
Fig. 16 shows the transient response of the regulator to pulsed
RF, as when happens during communication. The simulation
used a small load current of 500 nA and a large pulsed recti-
fier current from 0 to 3 mA at 40 kHz to model the worst case
jump in the regulated output. Two cases are shown—one with
the dynamic bias boost and the other without it. When there is
no bias boosting, the transient line regulation is bad and it re-
sults in a positive spike in the regulated output upon the rising
edge of the RF pulse. During the falling edge of the RF pulse,
though, the schottky diode S1 of Fig. 6 is reverse biased pre-
venting a downward spike. Thus, there is a net positive spike
in the regulator output and so it continues to rise during every
rising edge of an RF burst and reaches a equilibrium point far
2027
Fig. 17. Photograph of the power management section of the die.
Fig. 18. Measured voltage waveforms of rectifier, limiter and regulator outputs.
higher than the desired voltage as seen in Fig. 16. It can be seen
that under that condition, the quasi-regulated voltage is higher
than the rated voltage of 1.5 V for most components in this
process. This proves the necessity for dynamic biasing.
VI. MEASUREMENT RESULTS
Fig. 17 shows the photograph of the power management sec-
tion of the die with the rectifier, DC limiter, regulator, and load
capacitor. The regulated (i.e., the bandgap voltage) shows
a variation around 1.25 V of V across the wafer
and across temperature extremes ( 40 C to 65 C). Fig. 18
shows the measured waveforms at the rectifier output, the lim-
iter output and the regulator output (nodes B, C, and D, respec-
tively, in Fig. 1) for a equivalent antenna Thevenin voltage of
10 V-peak . The performance of the DC limiter and regulator
2028
shows little change beyond this value because the MOS tran-
sistor-based clamp at the input of the chip turns on heavily and
limits the peak voltage swing at the rectifier input to a fixed
value. After the positive going edge of the RF pulse is encoun-
tered, the regulator snaps up to its steady state value immedi-
ately. The regulated output droops during the absence of the RF
signal. It is to be noted that when the RF signal is absent, the rec-
tifier and limiter outputs fall steeply for a while and then decays
slowly. This is because of the reverse leakage of the Schottky
diodes S0 and S1 in Fig. 6. A current, of the order of several
tens of nano-amperes, flows from the load capacitor, through
the body diode of the pass device, back to the limiter and recti-
fier and pulls up the voltage of these nodes.
VII. CONCLUSION
A voltage regulation system for UHF RFID tags has been pre-
sented. It was shown how the RF energy, which could vary by
as much as 40 dB, is regulated successively, from gross to fine,
to a 1.25 V bandgap-based accurate value. The voltage regu-
lator system functions with just 110 nA of current, with extra
current used to increase bandwidth depending on availability of
power. It was shown that bandwidth boosting is critical for line
regulation and how the regulator is compensated amidst such
large variations in load current and RF power levels. Finally
measured waveforms of the system implemented in a 0.15 m
analog CMOS process are given.
ACKNOWLEDGMENT
The authors would like to thank B. Kramer, S. Lazar, and
K. Doddamane of Texas Instruments Incorporated for their help
during the course of this project.
REFERENCES
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Ganesh K. Balachandran received the B.Tech.
degree in electrical engineering from the Indian
Institute of Technology, Chennai, India, in 1997, and
the M.S. and Ph.D. degrees, also in electrical engi-
neering, from the Georgia Institute of Technology,
Atlanta, in 1999 and 2001, respectively.
He is currently with Texas Instruments Incorpo-
rated, Dallas, TX, where he has worked on precision
voltage regulation and measurement circuits, UHF
RFID circuits and other low-power RF circuits. His
current focus is on the design of high-performance
sigma-delta ADCs for cell phones. Prior to joining T.I. in 2004, he was with
Analog Devices, Inc. from 2002 to 2003, where he designed frequency syn-
thesizers and radio baseband circuits. He spent the summers of 1998 and 2000
at Conexant Systems, Newport Beach, CA, and IBM T. J. Watson Research
Center, Yorktown Heights, NY, respectively.
Raymond E. Barnett received the B.S. degree from
the University of Illinois at Urbana-Champaign
in 1992, the M.S. degree from the University of
Minnesota, Minneapolis, in 1997, and is currently
pursuing the Ph.D. degree at the University of Texas,
Dallas, all in electrical engineering.
From 1992 to 1997, he was an analog/mixed signal
IC design engineer with VTC Inc., Bloomington,
MN, where he worked on hard disk and tape drive
preamplifiers and read channels. He was a principle
mixed-signal Design Engineer at an Atmel startup
design center in Bloomington, MN, working on advanced DVD-RAM read
channels and preamplifiers from 1997 to 1999. From 1999 to 2000, he was a
Senior Design Engineer at VTC Inc. engaged in advanced MR preamplifier
design for disk drive applications. In 2000, he was a part of a start-up design
center located in Bloomington, MN, for Texas Instruments Storage Products
Group. Between 2000 and 2004, he worked on advanced MR preamplifiers
for Texas Instruments. In 2001, he was elected as a Senior Member of the
Technical Staff at Texas Instruments. Since 2004, he has been with the RF
division of the Custom Mixed Signal group at Texas Instruments in Dallas,
TX, working on various low power UHF band RF circuits, with a major focus
on radio frequency identification devices. He holds over 20 patents granted or
pending in integrated circuit design.