A ee, ve 7 :D ik Pe [2403, HBS Tse aks er ment of Computer Science & Engineering e epal — E Begum Rokeya University, Rangpur 999 2" Year I* Semester Final Examination ~ 2011 (Session. 2010-2011) a) Course Code: CSE 2101 Course Titl 3 ign“ Full Marks: $0 Time: 03:00 his | (Answer any Five, Figures in the right margin indicate fall marks.) { ' 1, (a) What is BCD? How many bytes are needed to represent the decimal value $46,569 BCD? (b) What is Parity Bir? Describe odd and even parity for error detestion with its 4 limitation (c) A small process-conttol computer uses hexadecimal codes to represent its 16-bit 3 memory addresses, i, Mow many hes digits are required, What is the range of addresses in hew How many memory focations ure there? 2 (a) Simplify the following Hootean function by sing Quine-MeClushy method 6 FAB.C.D)=S m(0.2.3.6.7.8.10 12,13) (by Why the Gray code used for cling the cells of K-mnap. 4 3. (4) Substantiste that four bas gates can cither enable or disable the passage af an 5 al, A. under euniral of the louie level at conteot input B —— "and describe parity generator and ckechee by using gate so 4. (a) Define the setup tune and the hold time requirements ofa clocked FF 2 (b) Describe parallel data transfer of binars Uata using D flip-top 3 (¢) How a D ip-flop is used ta synchronize the input signals and detecting an input 3 sequence? 5 (8) Desctabe a counter with MOD number where Nis the number oF PL 33 (b) Show how tu wite a THLS243 AS a MOD-0 counter (©) Depict how reduce frequency of a by using HF 6 (G@) Design a logic circuit whieh has th Fee input ADC and gives a high output whet 5 Miajorily of inputs is heb, 7 . " 7 (0) Draw Hogis iret ofa 4:1 muliptcver and explain its Working 5 , 7% (a) Desusn full adder using decoder with active low outputs, 4 (bh) Feplain following characters ies of logic families. 1) Puypagation detay i) Noise 6 marein. fh) Current parameters; 1) Fig re of ment: 4) Fan out - ‘ Scanned with CamScanner&e 21 J Begum Rokeya University, Rangpur B.Sc, Engg.) 2™ Year 1" Semester Final Examination - 2013 (Session: 201 1-2012) Course Code: CSE 2201 Course Title: Digital Logic Design Marks: 50 ‘Time: 03:00 (Answer any Five, Figures in (he right margin indicate full marks.) 1. G@) Write the maximum values of 12 bits number when it represents signed and unsigned value (h) Low many bytes are needed ta repseseet 546349 in BCID (8) Represent the decimal value 37 in each of the following ways G) BCD. (u) Hes, Gil Staight binary, (iy) Octal ‘Why can't the parity method detect a double error in urinsmitted data? (W) ts Il process control computer uses hexadecémal cudes tn represent its 16-bit meinan address (1) How many hor digits are requered? (ii) what fs the range of addresses in hen?, (ii) how many memory locations ore rete? 2 (a) Design the following eyuation by using NAND gates unly: X=(A’B+CBYY! (bh) Determine the ouipus swuvefurn for the AND gate shown in bellow giz LOY * UL ‘Also dela mine the output waveform if (e) State and prove Demotgan's thcoremis AND isteplaced by NUK and OR gate () Explain NAND and NOR as an universal delay 3+ (a) Depict the functional diagram at a digits vomputer (bp) Determine the minimons expression for map Lur the map in (a) co to co co tl alo 1lalo r}afo o}olo © Mastate the simplified form ofthe folowing figure by K-map 7 i aac + ABR Scanned with CamScanner Department of Computer Seienve & Engineering - wv 39322 (d) Describe don't care conditivns with an example, t 4. (a) Apply D Mip-tlop as a synchronizer. i (h) Destine stup time and hold time requirements of a clocked Mip-Mop. Also deting carry propagatien with an example. (e) Explain working of master JK flip-flop with necessury logie diagram, 74L5293 asa MOD-14 counter. (4) Show how to wi How many logic dev ices are required fir MOD-64 parallel counter? te) (ay Desenihe the operating of fnur-bit usyneluvnous counter (b) Construct a MOD-10) counter that will count from 000 theough 100) (6) Consider the circuit of given figure, initialls, all of Uke FF outputs ate in the 0 tock pulses ue applied These pulves have a sepetition rate of f state before KHz. Determine the waveforms at N.Y. and W tor eight cycles of the clack input Gta) usta the parle and sera das ransor shit reg {b) Whats clock skew? Has can it eause w problem? (0) Define carry propazation . Descibe the operation of sbils parle aldcr with registers 7 (2) Write short notes on {i) Propagation delas, (ii) Noswe margin, (ii) Current S=10 re AS= Parameters; (ix) Figure of meni, (¥) Fan ou, Page 2 of 2 Scanned with CamScanner+ Department of Computer Science & Engineering 29, Begum Rokeya University, Rangpur Session: 2013-2014 Course Title: Digital Logic Design ' Course Code: CSE 2102 Time: 3 Olours Full Marks: 50 Semester Final Examination-2015 2" year | INB. Answer any Five (5) Questions, Number of each question és indicated to the right] {44} What are the different way sto represent the numerical values? (b) What do you mean by digital and analoz systems? Write the advantages of techniques (c)_ Explain different methiods used to represent negative numbers in binary system 2 (4) Consent (i) decimal to binary 277.35, and (ii) binary to decimal 100110 EOL 2 2.(a) What are the diffexent fundamental fosic gates? Explai function with symbol 113-4 and uth table. (b) Write the Boolean theo (6) Show how a two-input NAND gate can he cunstructed from tWosinput NOR pate, 2 (4) Conver ns, 3 te iven gray ends number ta equivatent binary : 100100101 1110010, ' 3. (3) What da you mean by SOM and POS? 4b) What ave Minterais and Masterms? — - (6) Simply x- ALC +HAD-T Band dra te fl logic dhapram 2 (3) Simplify the following Boolean function using Kemap 4 Foway2)= 13.7118) (9) Define thes foto terms related 18 filp-Alops. set-up th Hlelay and show their position ina wave me, hold time, propagation 3 (61 Explain working of euster-stive JK fip-Rep with necessary togie diagram and 4 state diagram (©) Desene potential ining problem in FF citeits 3 Sa) Dusting ish between combinational Logic snd sequential logic {h) Explain the working procedie of fll act with prope logis eiteuit and signals 3 5 © ‘Shar do you mean by MOL auinber of counts” Explain the working of a MOD- Ins 16 synchronous counter with Proper cirewil diagram 60) Define desoder an encover Write their applications (0) Wate the working of LoFS tine docudee, 7 (co) Design a BUD to decimal decoder : 7a) Whatar mul - T= Muliplexer and denwiener? Wtite their maj sppicaions, nine (0) Explain the warking function of | inc-t-8:line demwhiplener. . (ec) What are the, Ahference bersuen decode an demultiplexer? Scanned with CamScannerversity, Rangpur gum Rokeya U ce mee Of Computer Seiense and Engineering 3" Year |" Semester Final Examinatian-- . Course Code: CSE 2101 > Course Title. Digital Logic Design ti Full Marks: $0 Time: 3 Hours Answer any five questions a) Suppose you purchase a BMW 2 series ear which uses different sie 3 Sent drivers through generating alert signal, BMAV2 generates alert when its speed is more than 140 kmh 1, road is not level plain, temperature is fess than 2200F, Moreover, BMW? generates alarm if its pressure is more than 250 psi Now present this context using Boolean expression, logical expression, truth tables, and timing diagram . b) Stale DeMorgan’s Theorems. Describe the implications of DeMurgan’s 3 Theorems c) Allogic circuit is needed to generate a sivnal x that will go HIGH whenever 4 conditions A and B exist simullancously or whenever conditions C dD exist simultncously. Clearly, the logic expression for x will be x=AB-CD. Firstly implement this circuit using primary gate, and then implement the ‘same circuil usi her universal pate, 2. a) State-seven major steps which are used in K-mmap method for simplifying 3 any Boolean expression b) Show how a three-input NAND gate can be constructed from three-inpul 3. NOR gates. ©) Design the toe piety that will conttol the horn when manufacturing 3 company needs to have a hom sound to signal quitting time. The horn should be activated when either the following condition is mat: ai after § Ulock an all machines ar shut down i's Friday, the production run for the da i EPIC Fata the production run forthe day is complet, and all machines 4) Explain Don'-Care condition 1 3, a) Mlusteate parity generator and ch Y wenerator and checker §) Explain hove J-K flip lop solves the ambiguity challenge i 2 2 Brey explain he operation ofthe elke $i ce SS 3 low do you implement D Mip-lo cc ‘hs plement D Mhip-Alop from J-K ips tloq’? 2 4. a) Design a logic circuit which ean d ich can do paralte i from one cel fo snore eee Pale transfer of four bit information 2 y Ulustrate Setup and Hold times, © What is clock skew? How can it eause a problem? a it cause a problem? 4) (Whi counter stars at 60000000, what wilt ein after $20 pulses? 2 é Scanned with CamScanner