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    Pat 7523373

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    2) United States Patent Russell et al. (64) MINIMUM MEMORY OPERATING VOL HINIQUE (75) Inventors , South Burlington, ws) (73) Assignee: (4) Notice: Subject to any disclaimer, the term of this pateat is extended or adjusted under 35 USC. 154(b) by 294 days, a Appl. Now 11/468 488 (22) Filed: Aug. 30, 2006 6s) Prior Publication Data US 200810082873 AI Apr. 3, 2008 Int. Cl GIR 3130 (2006.01) us.cl. T14I745; 713/300; Field of Classification Search 324765 “14745, mara ‘See application file for complete search history. 66) References Cited USS. PATENT DOCUMENTS S0M6501 A» 21992. Delsea eal 71300 v4 ' | firwevoarne 1 [tease t's a } | 2 | Rr 8 ' “ygutace | sOtmem PERIPHERAL 20 ' ECULATOR L Fn ~~ PROCESSOR ! Sor | eer = ‘om tet z Bo oR "aT ee Ta US007523373B2 (10) Patent No. 4s) Date of Patent: US 7,523,373 B2 Apr. 21, 2009 576452 A 611998 Capps. te ta 6.488672 BL 92002 Voogsli etal aa. 6748545 BL* 62004 Helms “r1s300 6772379 BL* $2004 Camera eal nam 6836848 B2 122004 Yuet al G97SSS1 B2* 122005 Iwata al 365226, 2006008917 AL 32006 Kawakami ta aovooz79318 AL* 122006 Iwaya snares 20070178542 AL* 7/2007 Comal tal. 713300 * cited by examiner Cynthia Brit Steve Nguyen Agent, or Firm Joanna G. Chix; James 1 Primary Examiner “Assistant Examiner (04) attorme Clingan, J 6 ABSTRACT A method ineludes an integrated circuit with a memory. The ‘memory opertes with an operating voltage. A value of a ‘nininnim operating voltage of the memory is determines Te value of the minimum operating voltage is stored in a ‘non-volatile memory location that maybe a non-volatile re ister. This minimum operatin fnformation can then be used in determining whea an alternative power supply voltage may be switehed tothe memory or ensuring that the ‘minimum voltage is otherwise met. The mininmim vollage can be used only intemal to the integrated circuit or also provided extemally to a user 16 Claims, 3 Drawing Sheets US 7,523,373 B2 Sheet 1 of 3 Apr. 21, 2009 U.S, Patent STWNOIS TOYINOD YOSSII0Ud ~ be YolvIno3y [GIA FOLIA VITO a150100A ONTLVY3dO_AYONSN ‘STWNOIS. 1 I 1 i I I I I TOLNOD AYONM [saistom Le le Ifa a YaTIOUINOD I ¥oss300¥d ! we YoLv N93 I Oz Wwaakalue wena] 30¥LT0A I é 1 “Sar avon a : 1sia oT ! suaisTo3y I SILYTOA-NON| 0 YXOQIA U.S. Patent ‘Apr. 21, 2009 Sheet 2 of 3 US 7,523,373 B2 wt L- 34 MIN VDDlogic RETENTION VOLTAGE FIRST MIN VODlogic READ VOLTAGE - 35 (WITHOUT INCREASE OF MEMORY OPERATING VOLTAGE) SECOND MIN VODlogic READ VOLTAGE -37 (WITH INCREASE OF MEMORY OPERATING VOLTAGE) 38 WIN VDDlogic WRITE VOLTAGE FIG. 2 > REGISTERS 30 ry _- PORTION OF STATE 0) FREQUENCY VOLTAGE CONTROLLER 28 STATE N FREQUENCY VOLTAGE 40 ‘SELECTED STATE FREQUENCY 1D) SELECTOR VOLTAGE SELECTOR VOLTAGE ID PARATOR AND OVERRIDE FROM NON-VOLATILE REGISTERS 2 SELECTED FREQUENCY (FD) SELECTED MEMORY VOLTAGE CONTROL SIGNALS FIG. 3 (VID) (TO/FROM MEMORY 18) U.S. Patent ‘Apr. 21, 2009 Sheet 3 of 3 US 7,523,373 B2 46 MANUFACTURE Ic MANUFACTURING TEST (E. PER Ic) | TEST IC MEMORY I 7 1 | STORE MIN VODiogie. VOLTAGES 60-1 | TO NON-VOLATILE REGISTERS : —— 3 BINNING 2 ponnn nnn pn nana _ CONTROLLER READS ; WIN. VDDlogic. VOLTAGES : UseR 4 CONTROLLER OPERATES REGULATOR BASED ON OPERATING STATE AND MIN VDDlogic VOLTAGES OPERATION ' ' ' ' ' ce FTG. Z US 7,523,373 B2 1 MINIMUM MEMORY OPERATING VOLTAGE, ‘TECHNIQUE FIELD OF THE INVENTION [Embodiments herein relate generally to memories, and more specifically to a minimum memory operating voltage technique. RELATED ART Today, processors ae typically able to operate at different voltages and frequencies, depending on the desired perfor mance. For example, processors may operate at maximum voltage and frequency when pesk performance is required, and may operate at low voltage and frequency to reduce power consumption. Therefore, tradoofls can be made between perfomance and power. Similarly, such tradsoffs between performance and power can be made for other cit ‘uitty within data processing systems such a memories. That Js, memories may be able to operate at higher voltages to achieve greater speed, and may also operate at lower voliages to save power, However, note tha dillereat types of circuitry ‘within data processing system may have different ranges of allowable operating voltages BRIEF DESCRIPTION OF THE DRAWINGS. “The present invention i illustrated by way oF example and jis not limited by the accompanying figures, ia which like references indicate similar elements IG. 1 illustrates a data processing system in aecondance with one embodiment of the present invention FIG. 2 ilkstrates the non-volatile episters of FIG. 1 in ‘seconiance with one embodiment of the present invention. FIG. 3illustates a portion of controller 28 in aecordance ‘with one embodiment ofthe present invention, FIG. 4 illustrates a low for testing and operating an inte= arated circuit, sueh a, for example, the data processing sys- tem of FIG. 1, in accordance with one embodiment of the present invention, ‘Skilled antisans appreciate tht elements in the figures are ithstated for simplicity and clarity and have not necessarily been drawn to scale Por example, dn dimensions ofsomeof the elements inthe figures may be exaggerated relative to other elements to help improve the understanding ofthe embodiments of the present invention, DETAILED DESCRIPTION OF THE DRAWINGS Asused herein, the tenn “bus” is used to refer to a plurality ‘ofsignals or conductors which may be used to transfer one oF ‘more various types of information, such as data, addresses, ‘control, or stats, The conductors as diseussed herein may be ithastated or described in reference to being a single conduc- ‘or, a plurality of conductors, unidirectional conductors, oF bidirectional conductors. However, different embodiments ‘may vary the implementation ofthe conductors, For example, Separate unidirectional conductors may be used rather than bidirectional conductors and vice vers. Also, plurality of ‘conductors may be replaced with a single conductor that transfers multiple signals serially or in time multiplexed ‘manner. Likewise, single conductors carrying multiple sig- nals may be separated out into various different conductors ‘crying subsets of these signals, Therefore, many options ‘exist for transferring signals. 0 o 2 As discussed above, radeofls between power and perfor: ‘mance canbe made for processors axl formemory by varying the operating. voltage and frequency. However, in one embodiment, the memory ina data processing system may hil ata higher vollage than the procestor Thats, the proces- sor may beable to operate at a lower voltage than is posible for the memory. ‘Therefore, in many embodiments, the memory has 2 higher minimum operating voltage than the racessor, Note that, a use herein, the minimum voltage oF ‘minimum operating voltage refers to a minimum whieh takes into consideration factors such a, for example, temperature “That is, there may be situations where the memory may actually be able to work aa voltage lower than the minimum vollage depending on, for example, factors such as temper Purbermore, this minimum operating voltage for a memory varies across pars, sich that one integrated circuit QC) may tolerate one minimum operating voluge while nother IC may be able to tolerate even a ker operating voltage, depending on the worst ease biteell present in each IC. Therefore, setting aparteularminimum operating woltage oratypeof memory, suchas forarangeof pars, which takes into consideration a Worst case scenario forall the parts may Deunnecessarily giving up the possibility for some pats to be ualitied to operate at even lover voltages i'those particular prt have, for example, more robust btcells, none of whieh Tall ino the worst case scenario. Therefore, in one embodi- ‘meat, cach particular par, or IC, is tested to determine values {or one or more minimum operating voltages, and these val tvs ofthe one or more aporating voltages are thon stored in ‘non-volatile memory locations on the par, such as trough the use of non-volatile registers or fuses. These programmed fon-volatile memory locations may thea be used, for ‘example, to bin the pats differently, eontrl voltage doing ‘operation af the IC, et FIG. 1 illusraes a block diggram of @ data processing system I in accordance with one embodiment of the present invention. System 10 includes a processor 16, built-in test (BIST) circuitry 14,amemory 18, non-volatile registers 1,9 ‘controller 28, and voltage regulators 24nd 26, Processor 16 js biirectonally coupled 19 non-volatile registers 12, BIST 14, memory 18, and coateoller 28. Memory 18 may be any type of memory suchas, for example a static random access memory (SRAM), a dynamic random aecess. memory (DRAM), ete, Memory 18 may be located extemal to proces- sor 16, as ilustrated, or may be located within processor 16 ‘Memory 18 may be, for example, a cache, an embedded ‘memory, or a stand alone memory. Memory 18 includes « memory amy 22 which inclides an array of bitells whic stores information. Memory 18 also includes a power supply Selector 21 which receives VDDmem and VDDlogic and provides one of these to memory array 22 as the memory ‘operating voltage. Power supply selector 21 selects one of VDDmem and VDDlogie baced on information provided by controller 28 via, for example, the memory control signals [Note that inanaltemate embodiment, posse supply selector 21 may be located outside memory 18, In yet another embodi- ‘meat, power supply selector 21 is nt present and memory 18 is permanently coupled to VDiogie or VDDmem, Meaiory 18 also includes periphery circuitry 20 whieh includes the cireuitey used to read and write memory array 22. For fexample, periphery’ 20 may include row and column decod- ers, sense amplifier, ete. In the illustrated embodiment periphery 20 is coupled to roceive VDDIngic is poser Supply. Memory 18 can be any type of memory W US 7,523,373 B2 3 ‘tes a8 know in the sr, and therefor, will only be discussed, to theextent necessary to understand various embodiments of the present invention, ‘Controller 28 provides memory control signals to memory 18 and processor control signals to processor 16. Controller 2B also provides a voltage identifier (VID) ta voltage regula- tor24 which coresponds toa desired voltage forthe output of voltage regulator 24 (eg. VDDlogic). Controller 28 may also provide one or more external voltage identifiers (VIDext via Integrated circuit terminals 32. In an alternate embodiment, negra circuit terminals 32 coupled to controller 28 may not be present, where coatmller 28 would not provide voliaze ‘identifiers externally. Controller 28 inchndes registers 30 which may be used to store voltage and fraqueney states of processor 16. For example, in one embodiment, controller 28 may include a dynamic’ voltage and frequency scaling (DVFS) controler, where repisters 30 includes various DVS states, each state indicating a particular voltage and eorre- sponding frequency, as will be described in more detail in reference to FIG, 3 below. ‘Voltage regulator 26 provides a substantially fined power supply voliage, VDDmem, to power supply selector 21 of memory 18. Voltage regulator 24, in response to VID, pro- vides power supply voltage, VDDIogie, to processor 16 and memory 18 (including both periphery 20 and power supp selector 21), where the value of VDDlogi is sealable, as ‘controlled by the VID output of controller 28. In one embod ‘ment, VDDmem is greater than VDDIogic, Altematively, \VDDmem may be greater than oF qual to VDDIog. In ono embodinient, while VDDIogie remains above 9 minimum operating voltage required for sucessful reads of riemory array 22, power supply selector 21 selects VDDIogic fs the memory operating voltage provided to memory array 22, such that the memory operating voltage is substantially ‘equal to VDDIogie, When VDDlogic is scaled to a voliage that is below the minimum memory operating voltage rexjired forreads, power supply selector 21 selects the higher voltage, VDDmem, during read eyeles to ensure that reads ‘can still be successfully performed. In this manner, the memory operating voltage provided to memory array 22 is increased when needed to ensure successful reads (while power supply selector 21 may continve to provide the sealed dowa VDDIogie to memory amy 22 when reade are aot occurring). However, note that in one embodiment, VDDlogic may be scaled down even lower toa voltage tha, ‘even with power supply selector 21 selecting the higher \Vbbavem, memory 18 would no longer perform reads prop- erly For example, the differential between tis further scaled ‘down VDDiogic and the higher VDDmem may be so great that switching from VDDlogic © VDDmem by power supply Selector 21 would result in deleterious eflets, such as bil Aipping where thedata stored in memory aray 22 sno longer ‘Also in the illustrated embodiment, when VDDlogic is sealed fo a voltage that is below the minimum operating voltage required for writes, write eyeles cannot successfully be performed. In an alternate embodiment, another voltage regulator, similar to voltage regulator 26, may be wsed to provide a substantially fixed power supply output (eg. ‘VbDmem-write) that is ess than VDDiogie and whichean be used during waite eyes to help perform the write. In this ‘embodiment, power supply selector 21 wouldseloct the lower voltage, VDDmem-rite, during write eycles, as needed, For ‘example, in this alternate embodiment, when VDDlogi is scaled 10 a voltage that is below the minimum operating voltage required for writes, power supply selector selects the lower voltage, VDDmematrite, daring the write eles 10 0 o 4 censure that writes can sil be successfully performed, since a lower memory operating voltage is helpful for write cycles. la ‘his manner, the memory operating vollage provided 10 ‘memory ary 22 can be decreased when needed to ensure suecessful writes (while power supply selector 21 may eon- tinue to provide the scale down VDDlogie to memory array 22 when writes are not accurring). Also, VDDlogic may be scaled doven even lower to a vole that, even with poser supply selector 21 selecting the lower VDDmemowrte to help the write eyele, memory 18 would no longer be able to perloem writes proper. "Therefore, nol tha diferent types of thresholds can be defined for memory array 22. For example frst minimam VDDlogic read voltage may indieate the minimum VDDiogic voliage where memory anray 22 can perform reads using VDDiogic rather than VDDmem. Also, a second minim \VDIogic ead voltage, which isa lower minimum than the fist VDDlogic read voltage, may indicate the minisaam VDDlogie voliage where memory array 22 can perform eas, even there ia switch tothe higher VDDmerm, That js, when“ VDDiogie falls belose the second minimum VDiogic vole, not even a switeh to VDDmem may censure proper read operations. In an altemate embodiment pote that onl a single minimum VDDlogic ead voltage may be indicated, such as in the case where an increase 10 ‘VbDmemis not available, Also, miniawum VDDlogie write vollage may indicate the minimum VDDIogic voltage at whieh memory array 22 can perform write operations. Inone embodiment (in which VDDmem-write, as described above, is availabe) frst and second minimum VDDIogie write volt. ‘ages canbe defined, where the first minimum V DDlogic write Vollage may indicate the minimum memory operating volt age allowed for writes without a decrease of the memory ‘operating voltage to VDDmem-vrite and the second mini- ‘sum VDDlogie write volte (les than the fist minim ‘VDDiogie write voltage) may indicate the minimum memory ‘operating voltage allowed for writes even with a deerease of the memory operating voltage to VDDmem-write, Also, note that there sa minimam data retention voltage such tat ifthe ‘memory operating voltage falls below this minimum data retention voltage, the data in memory army 22 may be los. Funermore, note that there may be a minimum standby vollage for memory array 22 which represents a minimum ‘operating vollge allowable for memory array 22 during standby, TInaltemate embodiments, other types of minimum read or write operating voltages can be defined for memory aray 22. For example, in addition to the fist and second minimam ‘VDIogic read voltages deseribed above, other minimnm read voltages may be defined svch as 8 third minimom VDDlogic read voltage indicating the minimum voltage ‘where memory aay 22 ean perform reads using VDDIogi rather than VDDmem when error correction cade (ECC) is ‘sed. In this case, ths third minimum VDDIogie read voltage (vithout increasing. the memory operating voltage to ‘VDDmem but with the use of ECC) may’be less than the first ‘minimum VDDiogie read voltage (without increasing the ‘memory operating voltage to VDmem and without the use ‘of :CC) but greater than the second minimum VDDiogic read voltage (with inereasing the memory operating voltage t0 ‘VDDmem and without BCC). That is, by enabling ECC, a Jower minimum read voltage may be acceptable for proper reads die to the use of ECC. Also, in addition tothe fist, socond, and third minimum VDDlogic read voltages described above, a forth minimum VDDIogie read voltage ‘may he defined which indicates the minimum VDDIogie read vollage where memory aay 22.an perform reads, even With US 7,523,373 B2 5 ‘a switeh fo VDDmem and the use of ECC, In one embodi ‘ment, tis fourth minimum read vollge is less than the fi second, and third minimum VDDlogic read voltages described above. Sinilarly, note tht the same type of minimum voltages hich take into consideration the use of ECC ean be defined Jor the minimum write voltages described above, That is, rather than defining a single minimum VDDIogie weit volt ‘age bolow which writes. cannot he performed (as was described in reference to FIG. 1), an alternate embodiment may instead use the first and second minimum VDDIogic ste voltages described above, and may additionally use third and fourth minimum VDDIogie write voltages where ECC is aio used, as was described in reference to the read voltages above, ‘Therefore, note that, s used herein, a minimum read volt- age of memory array 22 can refer to a single minimum VbDlegic read voltage bolow which reads cannot be stecess- {lly performed, ormay refer w one ormore different typesoF minimum VDDiogic read voltages, such as, for example, those described above (eg. the fist, second, third, fourth minimum VDDlogic read voltages, other minimum ‘VDDlegic read voltages, or combinations thereo!), Silay, minimum write voltage of momory array 22 ean refer to 8 ‘ingle minimum VDDlogie write voltage below which writes ‘cannot be succesfully performed, ormay referto ane or more ‘different types of minimum VDDIogie write voltages, sh 1, for example those described above (e-.the first, second, third, fourth minimum VDDlogie write voltages, other mum VDDlogic waite voltages, or combinations there). Similarly, inaltemate embodiments, other minimum readand ‘write voltages may be defined which indicate different mini- ‘mums depending on various other types of conditions. Also, in alienate embodiments, minimum read voltages ean be ‘combined! with minimum write voltages, such that a same ‘minimam voltage ean be ws for both reads and writes, Also, note that as used herein, 2 minimum operating voltage of memory array 22 can rele to any one or moreof the minimum read, write, retention, or standby voltages (or combinations there! described above. In one embodiment, controller 28 indicaes to power sup- ply selector 21 hich poster supply to seleet, VDDmem of VDDlowic (os, if available, VDDmem-write), by monitoring the VDDiogie VID selected within controller 28 (which will be described in more det in ference to FIG. 3) and core- sponds to the desired value for VDDlogie, and detemnining ‘shen the VDDlogie VID indicates a voltage tha s below any ‘of the minimum VDD logic voltages described above. Also, inoncembodiment, «signal may be provided by controler 28 in exponse tothe selested VDDiogie VID being below oneor more of the minimum read or write operating. voliages deseribod above, In the illustrated embodiment, when VIDDloge isto fall below the frst minimum operating voltage, power supply soletor 21 solcts the higher voltage, VDDmem, to inrease the memory operating voltage provided to memory array 22 during reads. However, in an altemate embodiment, \VDDlogic may be boosted during wads though the use of 3 ‘charge pump, wire this boosted VDDlogc is provided t0 memory array 22 for reads. In yet another embodiment, \VDmem ean be provided to memory aay 22 abways asthe memory operating. voliage, where VDDaiem may’ also be scalable such that it may be sealed down, under the contro, Tor example, of controller 28, to conserve power when pos: sible (such as when itis known that eads will not he per armed fora period of time) 0 o 6 altemateembodinents, ote that system 10 may'include any aumber of voltage regulators used to output various dif ‘erent supply voltages for use by different circuitry, such as, for example, by different voltage domains within system 10 ‘or processor 16. Altematively, voltage regulators 24 and 26 ‘an be implemented asa single voltage regulator with mul- tiple outputs. Also, inthe illstated embodiment, data pro- cessing system 10 is implemented as single IC. However, ia altemate embodiments, any number of ICs may be used. For ‘example, in one embodiment, voltaze regulators 24 and 26 ‘may be implemented with one or more separate ICs, One oF ‘more memories such as memory 18 ean also be implemented ‘with one or more separate ICs. Processor 16 may be any type fof processor such as, for example, a microcontroller, miero- processor, digital signal processor, ete, and operates as ‘known in the art Therefore, operation of processor 16 will ‘only be discussed to the extent necessary’ 10 describe various ‘embodiments ofthe preset invention. ARematively, proces: sor 16 may be aay type of functional circuit in system 10. ln fone embodiment, the functional circuit is exclusive of ‘memory I. Asdesribed abowe, memory 18 hasone or more minimum ‘operting voltages. os wasdescribed above in referenceto, for ‘example, the fist and second minima VDDIlogic read vole ages, the minimom VDDlogie write voltage, and the mini- ‘mum data retention voltage. Due to variations in manufactur ‘ng, though, these minimum operating voltages of a memory may differ across a range of parts, Therefore, one memory ‘may havediferent minimum operating voltages as compas {o another memory on a different IC. Therefore, in one cmbodinient, these minimum operating voltages are deter ‘mined for each part and stored in non-volatile registers on cach part. For example, in one embodiment, memory 18 is tested to determine the minimum operating voltages and there voles or values representative ofthese voltages are thea stored in non-volatile registers 12, For example, referring FIG. 1, BIST 14 may include any type of eieuity to perform any type of built-in self test. In fone embodiment, BIST 14 includes circuitry used to test for ‘minimum operating voltages for memory 18, For example, IST 1 may inchide circuitry to determine one or more of the minimum operating voltages discussed above. BIST 14 may also include other circuitry for determining olber types ‘of minimum operating voltages o other parameters, BIST M4 ‘may return these Values to processor 16 which may thea raid these values tobe writen to non-volatile registors 12 FIG. 2lusrates one embodiment of non-volatile registers 12, Theembodiment of FIG. 2 includes one or more registers whieh storea minimum VDDIogie retention voltage 34 and a fist minimum VDDIogie read voltage 3 (without the increase of the memory operating voltage). Note that the ‘minimum VDDiogie read voltage 3 (witout the inerease oF the memory operating vole) refers to the minimum volage \VDDlogie should have (within normal margins) in order for aus to be performed successfally. Note also that as long as \VDDlogie is at or above this minimum voltage, the memory operating voltage need not be increased 10 the higher VDDmem, as was described above. That is, so long. as VDDlogie is ator above this minimum voltage, VDDIogie can be provided asthe memory operating voltae "Note that fst minimum VDDlogie read voluage 38 may also be refered to as a minimum read memory operating voltage. That is, while VDDIogie remains above the first minimum VDDiogie read voltage, the memory operating vollage is substantially equal to VDDlogic. The frst mini- ‘mum VDDlogie read voltage 35 may also he refered toa 2 ‘minimum switching voltage sinee these values ean be used 10 US 7,523,373 B2 1 ‘determine when a switch is to be performed from one repu- lated power supply (eg. VDDlogic) to another reputed power supply (eg. VDDmem). Inthe illustrated embodiment of FIG. 2, non-volatile reg {ater 12 also storea second minimum VDDiogie ead voltage 37 (with the increase of the memory operating voltage). As ‘was described above in refereace © FIG. 1, there is @ point ‘where VDDlogic may be sealed down a such a level that even ‘with power suppl selector 21 selecting thehigher VDDmem, ‘operation of memory 18 may stil lal For example, ths may be due wo the large differential in voltage values between the scaled dowa VDDlogic andthe higher VDDaiem, Therefore, in one embodiment, BIST 14 may also include eireuity t0 ‘determine these minimums, and processor 16 may therefore also store these minimums in non-volatile registers 12. Tn the illustated embodiment of FIG. 2, non-volatile reg- {sters 12 also store a minimam VDDlogic write voltage 38 hich, as described above, can refer tothe minimum voltage VbDlogic most have (within normal margins) in order for writes to be performed succesfully. Note that minimum VDDiogie write voltage 38 may also be refered to as the ‘minimam write memory operating voltage. In an altemate ‘embodiment, non-volatile registers 12 can instead include 3 first and a second minimum VDDIogie write vollage (core- sponding to minimum VDDiogie write voltages without of With a decrease to VDDmemevrite, respectively), this altenate embodiment, note thatthe ist minimum VDDiogie weit voltage can also be relered (o as a minimum write ‘memory operating voltage or a minimum switehing voltage, Jorteasonsanalogous to those provided above with espect 10 first minimum VDDlogie read voltage 3S. ‘Note that in the example of FIG. 2, separate read and write voltages are provided: however, they may be combined such that same or single minimum is set for both readsand writes. Also, note that any number of non-volatile registers may be wed. Furthermore, ay number of minimum operating voll ages or other operating parameters of memory 18 may be included, Forexample, none embodiment, second minimum voltage 37 may not be present, of other minimum opersting voltages, such 9s a minimum standby voltage or those that ‘were described above in reference tothe use of ECC, may be present. Also, minimums for various different memories prevent within «system may be stored into non-volatile rey- ‘sters 12, In one embodiment, encoded versions ofthe mini- ‘um voliages (ie. VIDs foreach minimum voltage) may be sored instead where encoded versions ofthe operating vo- ‘ages (eg. VDDIogic VIDs) are monitored. In one embodi ‘ment, non-volatile rgisters 12 may be implemented as pro- zrammable fuses. Alternatively, they may be implemented as ‘ola registers For example, inone embodiment, the volar tleregistrs may store minimum operating voltages tha rep- resent the worst case across a group of pats. ‘Also, note that there may be other ways to determine these ‘minimum valves stored into non-volatile registers 12. Tati, BIST 14 may not be present, or, even present, BIST 14 may not perform the determination of the minimum operating voltages. In an altemate embodiment, an extemal tester may be used to apply a testing protocol extemal from system 10 ‘during or after manuficture of system 10 to determine the ‘minimom operating voltages. Tht is, other testing cireuitry, ‘iter internal to system 10 of external to system 10, may Be tused to determine these values. In yet another altemate ‘embodiment, different types of algorithms may be used t0 ‘determine these values foreach memory (he. foreach IC oF par) none embodiment, regardless of whether BIST 14s used ‘or another tester is used, the determination ofthe asim 0 o 8 ‘operating voltages is made specifically for memory 18 (and ‘may be made specifically for any aumber of memories that ‘may be present in system 10). Tht is, each memory ean be separately characterized with these minimum operating volt- ages which may allow, forexample,forimproved binning, for improved customer control, ete. By making thedetermination specifically per memory (re. per part or IC), a user or eus- tomer does not need to assume and plan for a worst case scenario eross al pats because they may have one or more parts that actually works better. Thats, by binning according ‘o the worst case scenario, a particular part may be restricted ‘rom use even though that purticular partis eapuble of oper- ating ata voltage below what binning alls. Other examples ‘of how to make use ofthe information in non-volatile regis: ters 12 will be discussed in reference to FIGS. 3 and 4 FIG, 3illustrates one embodimentof portion of controller 28, Registers 30 includes N¢1 registers, each eovtesponding toa voliazeltrequency sate, Thatis, acomesponding encoded ‘requency and voltage is provided for each of state 0 trough state (where each of state O through N may be referred to as a DVFS state). Controller 28 may provide a selocted state signal to seleet a DVFS state (where controller 28 may pro- vide this signal based ona state selected by processor 16). The selected sate signal is provided to feequeney selector 40 to select one of the N4I states, such that the selected frequency is provided ty frequency selector 40, The selected state signal ialso provided to voltage selector 42 such that voltage velec- tor 2 provides the corresponding selected encoded voltage 4 comparator and override 44. Therefore, the frequency and voltage sates selected by te selected state signal correspond to the desired frequency and voltage. For example, the selected voltage state corresponds tothe desired vole value Tor VDDlogic. Comparator and override 44 uses the informa- ‘ion stored in non-volatile registers 12 to determine if the selected voltage value output by voltage selector 42 (ie. the esired voltage value for VBDlogie) is appropriate for memory 18. For example, if the selected voltage value is below second minimum read voltage 37 oF minimum write voltage 38, operation of memory 18 may fail. In this case, ccomparaior and override 44 may force a different voltage selotion that remains abowe the appropriate minim vot age. Therefore, controller 28 may adjust VID accordingly to Prevent rogulsor 24 from outputting the desired voltage selected by the selected state signal. Therefore, while the selected frequency muy remain low, the corresponding selected low voltage is overridden to help ensure continued proper operation of memory 18. Similarly, comparator and override 44 ean vse first mini ‘num VDDiogie read voltage 38 t0 determine whether an increase to VDDmem is needed. That is, ifthe voltage selected by voltage selecor 42 in response tothe selected state signal indicates a voltage that fess than first minima ‘VbDlogic read voltage 38 (bu stil greater than second mini ‘mum VDDiogie read voltage 37) comparator andoverride 44 «an senda signal topower supply selector 21 (vinthememory ‘control signals) to indicate to power supply selector 21 t0 select VDDmem rather than VDDlogie to provide a¢ the ‘memory operating voltage to memory array 22, In an alter fale embodiment in which VDDmem-write is slso used (long with first and second minimum VDDlogie write volt ‘ages), comparator and overide-44 can send signal to poser supply selector 21 to indicate when a switch from VDDlogie fo VDDmem-rite is needed. Therefore, comparator and ‘override 44 can adjust or override the selected voltage VID t0 control VDDiogie as needed, as well a signal to power sup- ply selector 21 whea a switch in power supply voltages Is ‘edad, Comparator ad override 44 can make these adjust US 7,523,373 B2 9 iments or send these signals in response to comparing the selected or desired voltage with one or more ofthe various ‘minimum operating voltages that are stored in non-volatile registers 12 FIG, 4illutates a ow 46 which may be used determine ‘and use the minimum operating voliages of PIG. 2. For ‘example, flows 46 includes a manufacturing test portion 60 Which is performed per par (i.e. per IC), and includes a user ‘operation portion 62, Manufacturing test portion 60 incles, ‘manufacturing the IC (block 4) and testing the IC memory (block 50). For example, as discussed above, this may be performed by BIST 14 or some other tester or method of ‘esting. Manufacturing test portion 60 also includes storing the values of the minimum VDDlogic voltages or values representative of the actual values, determined by the IC testing performed in block 80, othe non-volatile registers of the IC being tested, such as non-volatile registers 12(block 52). In one emhodiment, the minimum VDDlogic voltages ‘can be determined per a group of pats or ICs. For example, testing cam be performed on a representative IC of particular Jot, where those values ate stored in the non-volatile registers ‘ofeach IC in the lot, After manufacturing tet portion 60, the stored values may be usod for improved power binning. For example the tested ICs may be binned according 1 liner power or speed bins since each par is tested individwally for the minimum VDDlogic voltages. Furthermore, a customer can he given ore precise information about each specific IC as apposed to relying on a global set of worst ease minimum Affe binning $4, flow 46 enters user operation portion 62 Useropemtion portion 62 includes using controller (suchas ‘controller 28) to read the minimum VDDIogie voltages (i block $6) and operating a regulator (such as regulator 26) based on an operating sate (suchas one of state O10 N)andon the minimum VDDDiogie voltages (in block $8). That is, as ‘was described in reference to FIG. 3, controller 28 may con- trol regulator 24 based on bath the sclected state of state 00 Nand the information stored in non-volatile registers 12. For ‘example, controller 28 may use the information stored in non-volatile registers 12 to selectively overide all oe 2 pot tion ofthe selected state [By now it should be appreciated dat there as bees pro= vided a technique for determining and storing specifi mini- ‘mum operating vollages foreach IC. la his manner, by deter ‘mining and storing this information unique to each IC Ge. by separately characterizing cach IC), an IC may be operated &t its lowest voltage, For example, by binning according to the worst case scenario, an IC may be restricted from use even though a particular IC or part is espable of operating at & voltage below what binning allows, This can be addressed by determining and storing information unigue to each IC, as discussed above. Also, with the stored information, the ‘increase of the memory operating voltage (uch as from VbDIegic to VDDmens, 28 was described shove), may’ be performed only when needed by using the stored first mi ‘mum values a8 triggering points for increasing the memory ‘operating voltage rather than relying ona global value (ie. 8 value that is common tal ICs). For example, ifglobal values ate relied on rather than the particular values detemined for ‘each IC, power selecior may switch 10 a higher povver supply voltage (such as VPDmemn) when it really 85 not necessary because the particular IC may have been able to ‘operate propery atthe lower voltage thus unnecessarily con- suming power. Furthermore, the decision 10 inerease the ‘memory operating voltage can also be made without a user's knowledge or intervention, 0 o 10 ‘one embodiment, method includes providing an inte- rated circuit with a memory, operating the memory with an ‘operating volage, determining a value of a minimum operat- ‘ng voltage ofthe memory, providing a non-volatile memory (NVM) location, and storing the value of the minimum oper- ting voltage of the memory inthe NVM location, ‘ina futher embodiment, te step of testing the memory is further characterized by the minimatin operating voltage com prising one ofa group consisting of minimum retention vot age, minimum waite voltage, minimum read voltage, and a ‘minimum standby vollage Tn another furher embodiment, the step of providing the integrated circuit with the memory is further characterized by ‘hememory comprising oneof a group coasisting of dyna random access memory and static random access memory. ‘another further embeadiment, the step of providing the [NVM location is further characterized by the NVM location comprising a non-volatile register In another further embodiment, the method furher includes providing a fanetioal eicuit om the integrated cir cit exchisiveof the memory, providing a first replated vot age to the functional eieuit, providing a second regulated voltage, and providing the fist regulated voltage as the oper ting voltage of the memory when te first regulated voltage js atleast the value of the minimum operating voltage and the second regulated voltage a the operating voltage of the ‘memory when the fist regulated voltages les than the value of the minimum operating voliage. In yet a further emibodi- ‘ment, the method Further inelides determining a value of a ‘minimum switehing voltage of the first regulated voltage for ‘switching from the fst regulated voltage tothe scoond rgs- Jated voltage in response to the first epulated vollge going ‘below the minimum operating voltage, and storing the value of the minimum switching voltage ia the NVM location, yet further embodiment, the method further includes pro- Viding a signal in response to a desired value forthe first regulated voltage being below the minimum operating vo ge, ‘In another further embodiment, the method furher includes providing @ controller on the integrated creuit that selects an opemting value for the operating voltage of the ‘memory, and providing the operating voltage to the memory ata value af leat as great asthe minimum operating voltage in sponse tothe operating value selected by the processor being below the minimum operating volage In another further embodiment, the method further includes providing the value ofthe minimum operating vol- fag extemal tothe integrated circuit Tn another further emhoxliment, the step of determining is further characterized as performing test applied externally ‘rom the integrate circu In another embodiment, an integrated circuit inches 3 memory tha operates using n operating olage, whereinthe ‘memory is chamcerized as having @ minimum operating voltage, and a memory Ioeation that stores a value represen- tative ofthe minimum operating voltage In a futher embodiment ofthe another embodiment, the {ntograte circuit further inches first voltage regulator for supplying a first regulated voltage, circuit that provides a unetion and uses the fist regulated voltage, second voltage egulstor for supplying a second regulated voltage, aad a power supply selector that supplies the first regulated voltage asthe operating volage ofthe memory when the first reg Jated voltage isa least the minimum operating voltage and supplies the second regulated voliage as the operating voltage ‘when the ist regulated voltage is below the minimum oper ating voltage. In yet a further embodiment of the another US 7,523,373 B2 vn ‘embodiment, the circuit that provides a function includes 2 processor, and the integrated circuit further includes «built-in self wst (BIST) eireuit, coupled the processor, useful in determining the minimum operating voltage. In anther yet further embodiment, the memory is funkier characterized as having a value of «minimum switehing voltage of the fist regulated voltage for switching from the fist eogulated volt age to the second regulated voltage in response to the first regulated voltage going below the minimum operating vol- age, and the memory location is further characterized as ‘oring the value ofthe minimum switching volag. Tnanolherluriier embodiment ofthe another embodiment, the minimum operating voltage comprises one of a group ‘consisting of minimum retention voltage, minimum read voltage, minimum write voltage, and minimum standby vol age. In yet a further embodiment, the minimum operating voltage comprises another one of the group consisting of ‘minimum reteation voltage, minimum read voltage, mini- ‘mum write voltage, and minimum standby voltage. Tnanotherfuriherembodiment of the another embodiment, > the memory comprises one of group consisting ofa static random access memory and a dynamic random access semony. Inanother further embodiment ofthe another embodiment, the integrated circuit includes a processor that selects an ‘operating value for the operating voltage ofthe memory, and means foe providing the operating voltage tothe memory at 2 value at least as great a the minimum operating voltage in response to the operating value selected by the processor being below the minimnm operating voltage. Tnanother further embodiment ofthe another embodiment, the memory location is characterized as eng non-volatile register. In yet another embodiment, method includes providing an integrated circuit with a memory that uses an operating voltage, testing the memory to determine the operating voll tage ofthe memory tha sa minimam operating voltage, and ‘oring, ia 8 non-volatile manner, the valve of the minimnm ‘operating voltage Ina further embodiment of the yet another embodiment, the method further includes providing «functional ereit on the integrated cieuit exelusive of the memory, providing @ first epulated voltage to the fictional circuit, proving & second repulated voltage, and providing the first regulated vollageas the operating vollage ofthe memory when the frst regulated voltage is at least the valu ofthe minimum oper- ating voltage andthe seeond regulated voltage asthe operat= ing voltage of the memory when the fist regulated voltage is Jess than the value ofthe minimum operating voltage. ‘Because the apparatus implementing the present invention Js, forthe most part, composed of electronic components and

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