P R ELIM IN A R Y

DATA

SH EET

M O t T K C H N O L O O V i INC.
V A L L E Y FORGE CORPORATE CEN TER (215) 666 7950 AUGUST, 1975
950 RITTEN HO USE ROAO, NORRISTOWN. PA. 19401

MCS6501 - MCS6505 MICROPROCESSORS

The MCS650X Microprocessor Family Concept —

The MCS6501 - MCS6505 represent the first five members of the MCS650X
m i croprocessor family. This family of products includes a range of
software compatible microprocessors which provide a selection of address­
able memory range, interrupt input options and on-chip clock oscillators
and drivers. The family includes the 40 pin MCS6501 for clock compati­
bility with the MC6800 microprocessor, the 40 pin MCS6502 with the same
features as the MCS6501 but including an on-chip clock, and the 28 pin
MCS6503, 4 and 5 providing in addition to the on-chip clock a set of
options allowing the user to tailor his microprocessor to suit the parti­
cular need. All of the microprocessors in the MCS6501 - MCS6505 group are
software compatible within the group and are bus compatible with the
M6800 product offering.

Features of the MCS6501 - MQS6505

. Single five volt supply . Instruction decoding and control

. N channel, silicon gate, de­ . Addressable memory range of up to
pletion load technology 65K bytes
. Eight bit parallel processing . "Ready" input
. 55 Instructions . Direct memory access capability
. Decimal and binary arithmetic . Bus compatible with MC6800
. Thirteen addressing modes . On-the-chip clock options
. True indexing capability * External single clock input
. Programmable stack pointer * RC time base input
. Variable length stack * Crystal time base input
. Interrupt capability . 40 and 28 pin package versions
. Non-maskable interrupt . Pipeline architecture
. Use with any type or speed memory
. Bi-directional Data Bus

Members of the Family

MCS6503 - 28 pin package
MCS6501 - 40 pin package
* On-the-chip clock
* Compatible with MC6800
* 4K addressable bytes
* 65K addressable bytes of memory
* Two interrupts

MCS6504 - 28 pin package

* On-the-chip clock
MCS6502 - 40 pin package * 8K addressable bytes
* One interrupt________
* 65K addressable bytes of memory
* On-the-chip clock MCS6505 - 28 pin package
/ External single phase input * On-the-chip clock
/ RC time base input * 4K addressable bytes
J Crystal time base input
* One interrupt, RDY signal
Comments on the Data Sheet

T his d a t a s h e e t d e s c r i b e s t h e first five m e m b e r s o f t h e M C S 6 5 0 X m i c r o p r o c e s s o r

f amily. T h e d a t a s h e e t is c o n s t r u c t e d to r e v i e w f i r s t t h e b a s i c " C o m m o n
Characteristics" - those features which, unless specifically stated otherwise,
are c o m m o n to all o f the M C S 6 5 0 1 - M C S 6 5 0 5 m i c r o p r o c e s s o r s . S u b s e q u e n t to a
r e v i e w of the f a m i l y c h a r a c t e r i s t i c s w i l l b e s e c t i o n s d e v o t e d to e a c h m e m b e r
o f the g r o u p w i t h s p e c i f i c f e a t u r e s o f each.

COMMON C H A R A C T E R IS T IC S

R EG IST ER SECTION CONTROL SECTION

RE5 IK U NMI

ADDRESS
BUS

NOTE: I. CLOCK G EN ERA TO R IS NOT INCLUDED ON MCS6S0I

2. ADDRESSING C A PA B ILITY AND CONTROL OPTIONS V A R Y WITH
EACH OF TH E MCS650X PRODUCTS

MCS6501 - MCS6505 Internal Architecture

 COMMON C H A R A C T E R IS T IC S
M A X IM U M R A T IN G S

RATING SYMBOL VALUE UNIT This device c o n tains in­

put protection against
SUPPLY VOLT A G E Vcc -0.3 to +7.0 Vdc damage due to high static
INPUT VOLTAGE Vin -0.3 to +7.0 Vdc vo l tages o r e l e ctric fields;
however, p r e cautions should
OPE R A T I N G T E MPERATURE 0 to +70 °C
Ta be taken to avoid appl i c a ­
tion of v o ltages higher
STO R A G E TEMPERATURE -55 to + 1 5 0 °C than the max i m u m rating.
t stg

E L E C T R I C A L C H A R A C T E R IS T IC S (V c c = 5 .0 V ± 5% . V ss = 0 , T A = 25” C )

01, 02 applies to MCS6501, 0o(tn) applies to MCS6502, 3, 4 and 5.

C H ARACTERISTIC SYMBOL MIN. TYP. MAX. UNIT

Input High Voltage Vdc

V IH
Vss + 2.4 Vcc
Vcc - 0.2 - Vcc + 0.25

Input L o w Vol t a g e Vdc

V IL
Vss - 0.3 Vss + 0.4
«O 8 i c,0°<i n >
01,02 V ss - 0.3 _ Vss + 0 . 2
Input High Thr e s h o l d Voltage
V IHT
R E S ,N M I ,R D Y ,I R Q ,D a t a ,
S . O . (6502,3,4,5) V s s + 2.0 - _ Vdc
Input Low Thr e s h o l d Voltage
V ILT
RES,NMI,RDY,IRQ,Data,
S . O . (6502,3,4,5) _ _ Vss + 0 . 8 Vdc
Input Leakage Current
*in
(V - 0 to 5.25V, Vcc - 0)
L o gic (Excl .RDY, S . O . ) - - 2.5 uA
01.02 100 uA

- - 10.0 uA
0o(In)
T hr e e - S t a t e (Off State) Input Current UA
't s i
(Vin - 0.4 to 2.4V, Vcc - 5.25V)
Data Lines 10
O u t p u t High Voltage
VOH
( L n . . - -lOOuAdc, Vcc - 4.75V)
B A ,D a t a ,A 0 - A 1 5 ,R/W Vss + 2.4 Vdc
Outpu t Low Voltage
VOL
(I - - 1.6mAdc, Vcc ■ 4.75V)
BA,Data,A0-A15, R/W Vss + 0.4 Vdc
Power D i ssipation - .25 .70 u
PD

C a pacitance C PF
(V, - 0. T - 25 C, f - 1MHz)
Logic - - 10
C in
Data - 15
A 0 - A 1 5,R / W , S Y N C , B .A . C _ _ 12

0 o(in) C0 15
o(ln)
01
: 30 50
C0,

02 - 50 80
C 02

Note: IR Q and N M I requite 3 K pull up resistors.

M CS6501 C lo ck Tim ing

CHARA C T E R I S T I C SYMBOL MIN. TYP. MAX. UNIT

Cycle Time 1.0 us ... — usee

tcyc

C lo c k Pul s e W i d t h 01 PWH 01 430

— ... n sec
(Measured at Vcc -f0.2v) 02 PWH 02 470

Fall Time
(Measured from 0 . 2 v t o Vcc - 0.2v) — ... 25 nsec
tf

D el a y T i m e between Clocks
(Measured at 0.2v) 0 ... ... nsec
td

Read /W rite Tim ing

C H A RACTERISTIC SYMBOL MIN. TYP. MAX. UNIT

Read/Write S e tup Time from MCS6 5 0 X ... 100 300 ns

TRWS

Address Setup Time from MCS650X ... 200 300 ns

tads

Memory Read Access Time T R — ---- 575 n9

tacc

tcyc " <t a d s " t dsu ' tr)

100 ---- ---- ns

Data Stability Time Period t dsu

Data Hold Time 10 30 ... na

th

Enable H i g h T i m e for DBE Input 470 ... ... ns

teh

Data S e tup Time from MCS6 5 0 X 150 200 ns

tmds

RDY S e tup Time 100 ... ... ns

t rdy

Bus Available Setup Time from MCS650X tba

... ... 470 ns

SYNC Setup Time from MCS 6 5 0 X ... ... 350 ns

t sync
 COMMON C H A R A C T E R IS T IC ^

Two Phase Clock Timing - MCS6501

u ------------------------------ T< Y C ----------------------------B

• l (6S01)
01 (O U T ) (6502. 3 ,4 .5 )
L VCC - 0.2V \
/ r ~

— — TR

• 2 (6501) \

r
• 2 (O U T ) (6502. 3. 4, 5 )\ __

«* T r w s -m
2.4V

R/W
2.4V
AD D R ESS 2.0V
FRO M MPU 0.8V 0.4V
2.4V
m- t a d s » 2.0V

DATA FROM _— 0.4V

0.8V
M EM O RY
Til —
w
RD Y X
^ T rd Y *«

BA (6501)
X
♦ Tb a *■

SYNC (6502)
X
^-Tsy n c *

Timing for Readi ng Data from Memory or Peripherals

w
 COMMON C H A R A C T E R IS T IC S

C l o c k s (0i, 0?)

T he M C S 6 5 0 1 r e q u i r e s a two p h a s e n o n - o v e r l a p p i n g c l o c k that r u n s at the V c c v o l t a g e level.

T he M C S 6 5 0 2 , 3, 4 and 5 c l o c k s are s u p p l i e d w i t h a n i n t e r n a l c l o c k g e n e r a t o r . T h e f r e q u e n c y of these c l o c k s

is e x t e r n a l l y controlled. D e t a i l s of this f e a t u r e a r e d i s c u s s e d in the M C S 6 5 0 2 p o r t i o n of this d a t a sheet.

A d d r e s s Bus ( A n ~ A i Q (See s e c t i o n s on MC S 6 5 0 3 , 4 a n d 5 for r e s p e c t i v e a d d r e s s lines o n t h o s e d e v i c e s . )

T h e s e o u t p u t s are T T L compa t i b l e , c a p a b l e o f d r i v i n g o n e s t a n d a r d T T L load a n d 130pf.

D a t a Bus ( D n - D 7)

Eight pins a r e used for the d a t a bus. T h i s is a b i - d i r e c t i o n a l bus, t r a n s f e r r i n g d a t a t o and f r o m the d e v i c e

and periph e r a l s . The o u t p u t s are tr i - s t a t e b u f f e r s c a p a b l e of d r i v i n g o n e s t a n d a r d T T L load a n d 130pf.

D ata Bus E n a b l e (DBE) (MCS6501 only)

T h i s T T L c o m p a t i b l e input a l l o w s e x t e r n a l c o n t r o l of the t r i - s t a t e d a t a o u t p u t b u f f e r s a n d w i l l e n a b l e the

m i c r o p r o c e s s o r bus d r i v e r w h e n in the h i g h state. In n o r m a l o p e r a t i o n D B E w o u l d be d r i v e n b y the p h a s e
two (02) clock, thus a l l o w i n g d a t a o u t p u t f r o m m i c r o p r o c e s s o r o n l y d u r i n g 02- D u r i n g the r e a d cycle, the
data bus d r i v e r s are i n t e r n a l l y dis a b l e d , b e c o m i n g e s s e n t i a l l y a n o p e n c ircuit. To disable data bus drivers
e x t e r n a l l y , DBE should be held low.

R e a d y (RDY) (MCS6501, MC S 6 5 0 2 , M C S 6 5 0 5 only)

T h i s input s i g n a l a l l o w s the u s e r to s i n g l e c y c l e the m i c r o p r o c e s s o r on a l l c y c l e s e x c e p t w r i t e cycles. A

n e g a t i v e t r a n s i t i o n to the low s t a t e d u r i n g o r c o i n c i d e n t w i t h p h a s e o n e (0j) w i l l h a l t the m i c r o p r o c e s s o r
w i t h the o u t p u t a d d r e s s lines r e f l e c t i n g the c u r r e n t a d d r e s s b e i n g f e t c h e d . T h i s c o n d i t i o n w i l l r e m a i n
t h r o u g h a s u b s e q u e n t p h a s e two (02) in w h i c h t h e R e a d y s i g n a l is high. This feature allows microprocessor
i n t e r f a c i n g w i t h low s p e e d P R O M S as w e l l a s fast (max. 2 cycle) D i r e c t M e m o r y A c c e s s (DMA). If R e a d y is
low d u r i n g a w r i t e cycle, it is i g n o r e d u n t i l the f o l l o w i n g r e a d o p e ration.

Bus A v a i l a b l e (BA) (MCS6501 only)

D u r i n g n o r m a l o p e r a t i o n the Bus A v a i l a b l e s i g n a l w i l l b e in t h e l o w s t a t e , w h e n in the h i g h s t a t e it

i ndicates that the m i c r o p r o c e s s o r has s t o p p e d a n d t h a t a l l b u s e s are a v a i l a b l e . This situation will
o c c u r if the RDY s i g n a l is l o w and the m i c r o p r o c e s s o r is n o t i n a W r i t e state.

Interrupt Request (IRQ)

This T T L level input r e q u e s t s that an i n t e r r u p t s e q u e n c e b e g i n w i t h i n the m i c r o p r o c e s s o r . The m i c r o ­

p r o c e s s o r w i l l c o m p l e t e the current i n s t r u c t i o n b e i n g e x e c u t e d b e f o r e r e c o g n i z i n g the request. At that
time, the interrupt m a s k bit in the S t a t u s C o d e R e g i s t e r w i l l b e e x a m i n e d . If the i n t e r r u p t m a s k f l a g
is n o t set, the m i c r o p r o c e s s o r w i l l b e g i n a n i n t e r r u p t s e q u e n c e . The P r o g r a m Counter and Processor
Status R e g i s t e r are s t o r e d in the stack. T h e m i c r o p r o c e s s o r w i l l t h e n s e t the i n t e r r u p t m a s k f l a g h i g h
so that n o f u r t h e r i n t e r r u p t s may occur. At the e n d o f this cycla, the p r o g r a m c o u n t e r l o w w i l l be
loaded from a d d r e s s FFFE, a n d p r o g r a m c o u n t e r h i g h f r o m l o c a t i o n FFFF, t h e r e f o r e t r a n s f e r r i n g p r o g r a m
c o n t r o l to the m e m o r y v e c t o r l o c a t e d at t h e s e a d d r e s s e s . T h e R D Y s i g n a l m u s t b e in the h i g h s t a t e for
any int e r r u p t to be recognized. A 3Kft e x t e r n a l r e s i s t o r s h o u l d b e u s e d for p r o p e r w i r e - O R o p e ration.

N o n - M a s k a b l e Interrupt (NMI) (MCS6501, MCS6 5 0 2 , M C S 6 5 0 3 only)

A n e g a t i v e g o i n g edge on this input req u e s t s that a n o n - m a s k a b l e i n t e r r u p t s e q u e n c e b e g e n e r a t e d w i t h i n

the m i c r o p r ocessor.

NMI is an u n c o n d i t i o n al interrupt. F o l l o w i n g c o m p l e t i o n o f the c u r r e n t i n s t r u c t i o n , the s e q u e n c e o f o p e r a ­

tions d e f i n e d for IRQ w i l l be performed , r e g a r d l e s s o f the s t a t e i n t e r r u p t m a s k flag. The vector address
l o a d e d into the p r o g r a m counter, low an d high, a r e l o c a t i o n s F F F A a n d FFFB r e s p e c t i v e l y . The instructions
l o a d e d at these loc a t i o n s c a u s e s the m i c r o p r o c e s s o r to b r a n c h t o a n o n - m a s k a b l e i n t e r r u p t r o u t i n e in memory.

NMI also re q u i r e s a n e x t e r n a l 3KJJ r e g i s t e r to V c c for p r o p e r w i r e - O R o p e rations.

Inputs IRQ a n d NMI are h a r d w a r e inte r r u p t s l i n e s t h a t a r e s a m p l e d d u r i n g 02 (phase 2) a n d w i l l b e g i n the

a p p r o p r i a t e in t e r r u p t r o u t i n e on the 0j (phase 1) f o l l o w i n g the c o m p l e t i o n of the c u r r e n t instruction.

Set O v e r f l o w F l a g (S.O.) (MCS6502 only)

This T T L level input s i g n a l a l l o w s ex t e r n a l c o n t r o l o f the o v e r f l o w b i t in the S t a t u s C o d e Register.

SYNC (MCS6502 only)

This output line is p r o v i d e d to id e n t i f y those c y c l e s in w h i c h the m i c r o p r o c e s s o r is d o i n g a n O P CODE

fetch. The S Y N C line goes h i g h d u r i n g 0i o f an O P C O D E f e t c h a n d s t a y s h i g h f o r t h e r e m a i n d e r of that
cycle. If the RDY line is p u l l e d low d u r i n g t h e 0j c l o c k p u l s e in w h i c h S Y N C w e n t h i g h , the p r o c e s s o r
w i l l s t o p in its c u r r e n t s t a t e and w i l l r e m a i n in t h e s t a t e u n t i l t h e R D Y l i n e goes high. In this
m ann er, the S Y N C s i g n a l can be u s e d to c o n t r o l R D Y to c a u s e s i n g l e i n s t r u c t i o n e x e cution.

R eset

T h i s input is used to r e s e t or start the m i c r o p r o c e s s o r f r o m a p o w e r d o w n c o n d i t i o n . D u r i n g the time

that this line is held low, w r i t i n g to o r f r o m the m i c r o p r o c e s s o r is i n h i b i t e d . W h e n a p o s i t i v e edge
is d e t e c t e d on the input, the m i c r o p r o c e s s o r w i l l i m m e d i a t e l y b e g i n the r e s e t sequence.

A f t e r a s y s t e m i n i t i a l i z a t i o n time of s i x c l o c k cycles, the m a s k i n t e r r u p t , ^ lag w i l l b e set a n d the

m i c r o p r o c e s s o r will load the p r o g r a m c o u n t e r f r o m the m e m o r y v e c t o r l o c a t i o n s F F F C and FFFD. T h i s is
the start lo c a t i o n for p r o g r a m control.

A f t e r Vcc reaches 4.75 volts In a p o w e r u p r o u t i n e , r e s e t m u s t b e h e l d l o w f o r a t least two c l o c k cycles.

At this time the R / W and (BA or SYNC) s i g n a l w i l l b e c o m e valid.

Wh e n the reset s i g n a l goes h i g h f o l l o w i n g t h e s e t w o c l o c k cycles, t h e m i c r o p r o c e s s o r w i l l p r o c e e d w i t h

the n o r m a l reset p r o c e d u r e d e t a i l e d above.

MCS6501 - MCS6505 Signal Description

 COMMON C H A R A C T E R IS T IC S

IN STR U C TIO N S E T - A L P H A B E T IC SEQ U EN C E

ADC A d d M e m o r y to A c c u m u l a t o r w i t h C a r r y D EC Decrement M e m o r y by One PHA Push A c c u m u l a t o r on Stack

AND "AND" Memory with Accumulator DEX Decrement Index X by One PHP Push Processor Status o n Stack
ASL S h i f t l e f t O n e Bit ( M e m o r y o r A c c u m u l a t o r ) DEY Decrement Index Y by One PLA Pull Accumulator from Stack
PLP Pull Processor Status from Stack
BCC Branch o n Carry Clear EOR "Exclusive-or" Memory with Accumulator
BCS B r a n c h o n C a r r y Set ROL R o t a t e O n e Bit L e f t ( M e m o r y o r A c c u m u l a t o r )
BEQ Branch on Result Zero INC Increment M e m o r y by One RTI Return from Interrupt
BIT T e s t B i t s in M e m o r y w i t h A c c u m u l a t o r INX I n c r e m e n t I n d e x X b y One RTS Return from Subroutine
BMI Branch on Result Minus INY Increment Index Y by One
BNE Branch on Result not Zero SBC Subtract Memory from Accumulator with Borrow
BPL Bra n c h o n Result Plus JMP Jump to New Location SEC Set C a r r y Flag
BRK Force Break JSR Ju m p to Ne w L o c a t i o n S a v i n g Re t u r n Add r e s s SED Set Decimal Mode
BVC Branch on Overflow Clear SEI Set Interrupt Disable Status
BVS B r a n c h o n O v e r f l o w Set LDA Load Acc u m u l a t o r wi t h Memory STA S t o r e A c c u m u l a t o r in M e m o r y
LDX Load Index X w i t h Memory STX S t o r e I n d e x X in M e m o r y
CLC Clear Carry Flag LDY Load Index Y wit h Memory STY Store In d e x Y in Me m o r y
OLD Clear Decimal Mode LSR Shift One Bit Right (Memory o r Accumulator)
CLI C l e a r I n t e r r u p t D i s a b l e Bit TAX Transfer A c c u m u l a t o r to I n d e x X
CLV Clear Overflow Flag NOP No Operation TAY Transfer A c c u m u l a t o r to I n d e x Y
CMP Compare Memory and Accumulator TSX Transfer Stack P o i n t e r to Index X
CPX Compare M e m o r y and Index X ORA "OR Memory with Accumulator TXA Transfer Index X to A c c u m u l a t o r
CPY Compare Memory and Index Y TXS Transfer Index X to S t a c k Pointer
TYA Transfer In d e x Y to A c c u m u l a t o r

A D D R ESSIN G M ODES

A C C U M U L A T O R A D D R E S S I N G - Thi s form of a d dressing is r e p r e s e n t e d wi t h a one byte instruction, imply i n g an

op e r a t i o n on the accumulator.
I M M E D I A T E A D D R E S S I N G - In immediate addressing, the o p erand is contained in the second by t e of the instruction,
w i t h no further m e m o r y a d d r e s s i n g required.
A B S O L U T E A D D R E S S I N G - In absolute addressing, the second byte of the i n s t r u c t i o n specifies the eight low ord e r
bits of the effective address w h i l e the third byt e specifies the eight hig h o r d e r bits. Thus, the
abs olute a d dressing mode allows access to the entire 65K bytes of a d d r e ssable memory.
Z E R O P A G E A D D R E S S I N G - T h e zero page instructions a l l o w for s h o rter code and e x e c u t i o n times by onl y fetc h i n g
the second byte of the i n s t r uction and assu m i n g a zero high a d dress byte. C a reful use of the zero
page can result in significant increase in code efficiency.
I N DEXED ZERO PAG E A D D R E S S I N G - (X, Y indexing) - This form of a d d ressing is used in c o n j unction wit h the index
register and is referred to as "Zero Page, X" or "Zero Page, Y". The eff e c t i v e address is calcul a t e d
by adding the second byte to the contents of the index register. Since this is a form of "Zer o Page"
a d dressing, the content of the second byte r e ferences a location in pag e zero. Additi o n a l l y due to
the "Zero Page" a d dressing nature of this mode, no carry is added to the high order 8 bits of memory
and crossing of pa g e b o u ndaries does not occur.
I N D E X E D A B S O L U T E A D D R E S S I N G - (X, Y indexing) - This form of ad d r e s s i n g is used in c o n j u nction wi t h X and Y
in dex register and is referred to as "Absolute, X", and "Absolute, Y " . The eff e c t i v e address is
formed by adding the contents of X or Y to the a d d ress contained in the second and third bytes of the
instruction. Thi s mod e allows the index register to contain the index or count va l u e and the in­
st r uction to contain the base address. This type of indexing allows any loca t i o n r e f e rencing and
the index to m o d i f y mult i p l e fields resulting in reduced coding and execution time.
I M P L I E D A D D R E S S I N G - In the implied ad d r e s s i n g mode, the a d d ress c o ntaining the o p erand is implicitly stated
in the op e r a t i o n code of the instruction.
RE L A T I V E A D D R E S S I N G - Relative a d dressing is used only wit h branch instructions and e s t a blishes a destin a t i o n
for the c o n d i tional branch.
Th e second byte of the i n s t r uction b e comes the operand w h i c h is an "Offset" added to the con t e n t s of
the lower eight bit s of the p r ogram counter w h e n the counter is set at the next instruction. The
range of the offset is -12 8 to +1 2 7 by£es from the next instruction.
I N DEXED INDI RECT AD D R E S S I N G - In indexed indirect a d d r e s s i n g (referred to as (Indir e c t , X ) ), the second b yte of
the i n s t r uction is added to the contents of the X index register, di s c a r d i n g the carry. The result
of this addi t i o n points to a m e m o r y location on pag e zero wh o s e contents is the low order eight bits
of the effective address. The next memory loca t i o n in page zero contains the hi g h order eight bits
of the effective address. Both m e m o r y locations s p ecifying the high and low order bytes of the
e f fective address mus t be in page zero.

INDI R E C T I N DEXED AD D R E S S I N G - In indirect indexed a d d ressing (referred to as ( I n d i r e c t ) , Y ) , the second byte

of the i n s t r uction points to a m e m o r y location in page zero. The contents of this m e m o r y location
is added to the contents of the Y index register, the result being the low order eight bits of the
e f fective address. The carry from this addi t i o n is added to the contents of the next page zero
m e mory location, the result b e i n g the high order eight bits of the effective address.
AB S O L U T E IND IRECT - The second byte of the i n s t r uction contains the low order eight bits of a memory location.
The high order eight bits of that memory location is contained in the third byte of the instruction.
The contents of the fully specified memory location is the low order byte of the effective address.
The next memory location contains the hig h order byte of the effective address wh i c h is loaded
into the sixteen bits of the program counter.
 COMMON C H A R A C T E R IS T IC S

PROGRAM M IN G M O DEL

PR O C ESSO R S T A T U S R E G ” P"

A
A CCU M ULAT O R

Y IN D EX R E G IS T E R CARRY 1 =TRUE

e ZERO 1 = R ESU LT ZERO

X
IN D EX R E G IS T E R IR O D IS A B L E 1 = D IS A B L E
'S 6 D EC IM A L MODE 1 = TRUE
PCH PCL
PR O G R A M C O U N T ER "P C " BRKCO M M AND
8 0
1 S ST A C K PO IN T ER O VERFLO W 1 « TRUE

N E G A T IV E 1 = NEG

IN STR U C TIO N S E T - OP CO D ES, Execution Tim e, Memory Requirements

INSTRUCTIONS CONDITION CODES

mmomc
ADC A*M*C A (i

AND A A M ♦A n

A S L c«g : _
B C C BRANCH ON C=0 13
B C S 8RANCH ON C-1 ca

BED BRANCH ON 2-1 it

B I T 4 AM

B M I BRANCH ON N-l (j
B N E BRANCH ON Z-9 <>

B P L BRANCH ON N-« <}

BRK (St F.9 1)

BV C BRANCH ON V-g it

BV S BRANCH ON V-1 t?

C L C a-c

CLP a —d

C L I 8♦ I
C L V 0♦ V

CMP A-M <1

C P X X M

C PY Y-M

D E C K-l ♦ M

D E X <-1 ♦ X

D E Y
E O R Ay M - A Vj 4 2

\ N C M ♦1 ♦ M F6 6 ?

I N X X •1 ♦ X

I N Y Y* 1 Y

J M P JUMP TO NEW LOC

J S R (S** F.9 2UUMP SUB

IDA M ♦ A „ 3 89 4 3

IMMEOIATE ABSOLUTE ZERO PAGE ACCUM IMPLIE0 (IN D .X) (IN D ).Y *.PAG E.X RELATIVE INDIRECT Z.PAGE.Y CONDITION CODES
N I C I D V

L D X
L D Y J - -- -

L S R J J - - -
NOP NO OPERATION

O R A
P H A
P H P
P L A
P L P (RESTORED)

R O L J J - -

R T I ISw F.g 1» RTRN INT

RTS (Sw F,9 2> RTRN SUB
SBC A-M-C I1» |

SEC ♦ C

S E P - 0
S E I 1— I
S T A A ♦ M

S T X
S T Y
TAX A ♦X
T A Y A ♦ Y

T S X S ♦ X
T X A X ♦ A

T X S X ♦ S
T Y A Y ♦ A 98
(1) ADD 1 TO "N " IF PAGE BOUNDRY IS CROSSED X INDEX X EXCLUSIVE OR
121 ADD 1 TO " N " IF BRANCH OCCURS TO SAME PAGE Y INDEX Y ADD MODIFIED
ADD 2 TO "N " IF BRANCH OCCURS TO DIFFERENT PAGE A ACCUMULATOR SUBTRACT NOT MODIFIED
<3) CARRY NOT - BORROW M MEMORY PER EFFECTIVE ADDRESS AND MEMORY BIT 7
M i MEMORY PER STACK POINTER MEMORY BIT 6
MCS6501 - 40 Pin Package

T h e M C S 6 5 0 1 is a b u s c o m p a t i b l e r e p l a c e m e n t f o r the M C 6 8 0 0 m i c r o p r o c e s s o r . As
such, t his p r o d u c t u s e s a two p h a s e h i g h l e v e l (5 volt) c l o c k i n p u t c o n s i s t e n t
w i t h the M C 6 8 0 0 d e v i c e r e q u i r e m e n t s . The MCS6501 w h i l e pinout compatible wit h
the M 6 8 0 0 a d d r e s s b u s d o e s n o t h a v e t h e t h r e e - s t a t e b u f f e r s o n t h e a d d r e s s p i n s
A s s u c h the M C S 6 5 0 1 a l w a y s h a s v a l i d a d d r e s s e s o n t h e a d d r e s s bus, w i t h t h i s
feature allowing the single cycle mod e of operation.

vss 1 40 RES
d
RDY ____ d 2 39 N.C.

9 1 (IN )------ d 3 38 N.C.

IRQ ------ ^ d 4 37 0 2 (IN)

VMA ^ ------ d 5 36 DBE

NMI ------ d 6 35 N.C.

BA ^ ------ d 7 34 R/W

VCC i= 8 33 DB0

ABO 9 32
!) DBI
MCS6S01
ABI | L _ 10 31 DB2

AB2 d II 30 DB3

AB3 d 12 29 DB4

AB4 d 13 28 DBS

ABS d 14 27 DB6

AB6 d IS 26 DB7

AB7 d 16 25 AB1S

AB8 d 17 24 AB14

AB9 d 18 23 ABO

AB10 d 19 22 AB12

21 Vss
ABI 1 0= 20

N.C. = NO CONNECTION

* VMA IS CONNECTED INTERNALLY TO VCC. THE VMA SIGNAL IS NOT REQUIRED

ON THE MCS650I AS ON THE MC6800, SINCE THE MCS6S01 ALWAYS PUTS OUT
KNOWN ADDRESSES ON THE ADDRESS BUS.

MCS6501 Pinout Designations

* 6 5 K A d d r e s s a b l e B y t e s of M e m o r y * 8 B i t B i - D i r e c t i o n a l D a t a Bus

* IRQ I n t e r r u p t * Pin Compatible With MC6800

* NMI Interrupt * Bus A v a i l a b l e S i g n a l

* RDY Signal * Data Bus Enable

(can b e u s e d for s i n g l e cycling)

Features of MCS6501
MCS6502 - 40 Pin Package

T h e M C S 6 5 0 2 c o m b i n e s the M C 6 8 0 0 b u s c o m p a t i b i l i t y f e a t u r e s of the M C S 6 5 0 1 w i t h
a n o n - t h e - c h i p c l o c k o s c i l l a t o r and d r i v e r w h i c h e l i m i n a t e s the r e q u i r e m e n t for
a two p h a s e 5 v o l t c l o c k input. T h i s f e a t u r e a l l o w s the chip to b e d r i v e n f r o m
a s i n g l e T T L l e v e l i n p u t clock, or a n R C time b a s e or C r y s t a l time base.
A d d i t i o n a l l y , the M C S 6 5 0 2 h a s a S Y N C line o u t p u t w h i c h s i g n a l s e a c h t i m e a n
OP C O D E f e t c h is b e i n g p e r f o r m e d , thus a l l o w i n g s i n g l e i n s t r u c t i o n execut i o n .

vss CZ i 40 = □ * * - rEs

RDY ► 1= 2 39 02 (OUT)

9 1 (OUT) - cz 3 38 S.O.

IRQ ► cz 4 37 00 (IN)

N.C. c= 5 36 N.C.

NMI ► cz 6 35 N.C.

SYNC - cz 7 34 R/W

VCC d 8 33 DB0

AB0 9 32 DB1
MCS6S02
A BI 31 DB2
^L - 10

AB2 1_____ 11 30 DB3

AB3 1 12 29 DB4

AB4 r~ 13 28 DB5

AB5 14 27 DB6
/
AB6 IS 26 DB7

AB7 i 16 25 AB1S

AB8 i— 17 24 AB14

AB9 i 18 23 A BB

ABIO 19 22 AB12
/=
ABI I 20 21 VSS
0=
N.C. = NO CONNECTION

MCS6502 Pinout Designations

* 6 5 K A d d r e s s a b l e B y t e s of M e m o r y * SYNC Signal
(can b e u s e d f o r s i n g l e i n s t r u c t i o n
* IRQ Interrupt execution)

* NMI I n t e r r u p t * RDY Signal

(can b e u s e d for s i n g l e cy c l e
* On-the-chip Clock execution)
/ T T L L e v e l S i n g l e P h a s e Input
* T w o P h a s e O u t p u t C l o c k for
/ RC Time Base Input
T i m i n g of S u p p o r t C h i p s
/ Crystal Time Base Input

Features of MCS6502
MCS6502

T IM E B A S E G E N E R A T IO N OF IN PU T C LO C K

CRYSTAL ( S u g g e s t e d r a n g e s for Rp, C f,: 0 < R ? < 500KJ2, 2pf < C < 12pf.)

Parallel Mode Crystal Controlled Oscillator

PIN
3 0 1 (OUT)
37 0o (IN)
39 02 (OUT)

Serial Mode Crystal Controlled Oscillator

PIN
3 0 | (OUT)
37 0o (IN)
39 02 (OUT)

RC

RC Network Tim e Base Generation

Rp PIN_

39 SYSTEM 3 0 1 (OUT)

T Cf B U FFER
02 37 0o (IN)
39 02 (OUT)

37 X
 MCS6503 - 28 Pin Package

R ES C 1 28 D02 (O UT)
v vss C 2 27 3«oON) * 4 K A d d r e s s a b l e B y t e s of
jr <5C 3 26 U R/W M e m o r y (AB00-AB11)
NM I C 4 25 D DB0

Vccc 5 24 D DBl * On-the-chip Clock

AB0C 6 23 3 DB2

ABI C 7 22 1 DB3 * IRQ I n t e r r u p t

AB2 C 8 21 D DB4
Ab3 C 9 20 D DBS * NMI Interrupt
AB4 C 10 19 3 DB6

ABS C 11 18 3 DB7 * 8 Bit B i - D i r e c t i o n a l D a t a Bus

AB6 C 12 17 □ A B I 1

A B 7 C 13 16 □ ABIO

AB8 C 14 15 □ AB9

MCS6503
Features of MCS6503

MCS6504 - 28 Pin Package

■r e s C 1 28 : 02 (OUT)

Vss C 2 27 D 00 (IN )

IRQ C 3 26 D R/w * 8K A d d r e s s a b l e B y t e s of
vcc C 4 25 : d b 0 M e m o r y (AB00-AB12)
AB0 C 5 24 U D B l

A BI C 6 23 D DB2 * On-the-chip Clock

AB2 C 7 22 D DB3

AB3 C 8 21 ] DB4 * IRQ Interrupt

AB4 C 9 20 D DBS

ABS C 10 19 3 DB6 ■k 8 Bit B i - D i r e c t i o n a l D a t a Bus

AB6 C 11 18 □ DB7

AB7 C 12 17 □ AB12

AB8 C 13 16 □ A B I 1
AB9 C 14 IS □ ABIO

MCS6504 Features of MCS6504

MCS6505 - 28 Pin Package

R ES C 1 28 J 0 2 (OUT)
vss C 2 27 3 00 (IN ) * 4 K A d d r e s s a b l e B y t e s of
RDY C 3 26 D R/W
M e m o r y (AB00-AB11)
W C 4 25 D DB0

vcc C 5 24 D DBl * On-the-chip Clock

AB0 L 6 23 D DB2

ABI C 22 3 DB3
7
* IRQ I n t e r r u p t
AB2 C 8 21 J DB4

AB3 C 9 20 3 DBS
* RDY Signal
AB4 C 10 19 U DB6

A BS C I I 18 2 DB7
* 8 Bit B i - D i r e c t i o n a l D a t a Bus
AB6 C 12 17 D A BM

AB7 C 13 16 3 ABIO

A BS C 14 15 □ AB9

MCS6S0S
Features of MCS6505
MCS6503, MCS6504, MCS6505

T IM E B A SE G E N E R A T IO N OF IN PU T C LO C K

CRYSTAL ( S u g g e s t e d r a n g e s for R p , C F : 0 < R p < 500Kft, 2pf < C p < 12pf.)

Parallel Mode Crystal Controlled Oscillator

SYSTEM
28
02

Rf
27
V A r PIN
27 0o (IN )
C=) C R Y ST A L 28 02 (OUT)

Serial Mode Crystal Controlled Oscillator

SYSTEM
02

PIN
27 0o (IN )
28 0 2 (OUT)
C R Y ST A L

RC
RC Network Tim e Base Generation

SYSTEM
28

lc 02

T^ \

PIN
27 0o (IN )
28 02 (OUT)