A Report on

Traffic Light Management System

for

Mini Project 2-B (REV- 2019 ‘C’ Scheme) of Third Year,

(TE Sem-VI)
in

Electronics and Telecommunication Engineering

by

Atharva Deherkar
Purva Hambire
Sumeet Sharma
Kritika Singh

under the guidancce of

Prof. Madhura Shirodkar
Prof. Shailaja Udtewar

UNIVERSITY OF MUMBAI

Department of Electronics and Telecommunication Engineering

Xavier Institute of Engineering
Mahim(West), Mumbai-400016
(2021-2022)
 Certificate

This is to certify that the project entitled Wireless Communication With

STM32, Interfaced With LoRa is a bonafide work of

Atharva Deherkar
Purva Hambire
Sumeet Sharma
Kritika Singh
submitted to the University of Mumbai in partial fulfillment of the requirement
for the award of Mini Project 2-B (REV- 2019 ‘C’ Scheme) of Third Year,
(TE Sem-VI) in Electronics & Telecommunication Engineering as laid
down by University of Mumbai during academic year 2021-22.

Internal Examiner Reviewer-1

External Examiner/Reviewer-2
 Acknowledgement

We would like to thank our project guide Prof. Madhura Shirodkar & Prof.
Sailaja Udtewar who initiated us into learning the subject of Mini Project 2B-
FPGA based Project. They have been a source of inspiration and his insight and
vision has made it possible for us to pursue and understand the developments in
these areas. Their patience, encouragement, critique and availability made this
dissertation possible.

We are also grateful to Xavier Institute of Engineering Management, Princi-

pal Dr. Y. D. Venkatesh and especially the Head of the Department Ms. Vidya
Sarode and all the faculty and staff who have helped us to be better acquainted
with the recent trends in technology and from whom we have learned so much.

Moreover, we are thankful to all our colleagues and friends for the wonderful
years and moments spent at XIE. They indeed have transformed our years at XIE
into happy memories, memories which will linger on for decades.

Above all we are grateful to our family because of whose motivation and sac-
rifice we were able to pursue our Engineering studies. We are immensely grateful
to our parents for their sacrifices and encouragement. We can never forget the
dreams they have for us and the support they gave us from the very first day they
held our hand and led us to school. We hope in the years to come our achievements
will indeed make them proud.
 Abstract

content...
Contents

List of Figures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . i
List of Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ii

1 Introduction 1
1.1 Motivation and Background . . . . . . . . . . . . . . . . . . . . . . 1
1.2 Ojective . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1.3 Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

2 Literature Survey 3
2.1 FPGA Boards . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
2.1.1 Spartan 6 FPGA Board . . . . . . . . . . . . . . . . . . . . 3
2.1.2 Tiny FPGA . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
2.1.3 Artix 7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2.1.4 Zynq-7000 SoC . . . . . . . . . . . . . . . . . . . . . . . . . 5
2.2 EDA Tools . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2.2.1 EDA Playground . . . . . . . . . . . . . . . . . . . . . . . . 6
2.2.2 Xilinx ISE WebPack . . . . . . . . . . . . . . . . . . . . . . 6
2.2.3 Xilinx Vivado . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2.3 Technical Papers/Websites Referred . . . . . . . . . . . . . . . . . . 7
2.3.1 Traffic Light Controller based on FPGA . . . . . . . . . . . 7
2.3.2 Real-Time Traffic Light Controller System based on FPGA
and Arduino . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2.4 Problem Statement . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

3 Methodology Used 8
3.1 Working of project . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
3.1.1 State Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 8
3.1.2 State Table . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
3.2 Hardware Software Components . . . . . . . . . . . . . . . . . . . . 9
3.2.1 Spartan-6 XC6SLX9 TQG144BIV2001 . . . . . . . . . . . . 10
3.2.2 Xilinx ISE WebPack . . . . . . . . . . . . . . . . . . . . . . 12

4 Implementation & Results 13

4.1 Module creation and Interfacing . . . . . . . . . . . . . . . . . . . . 13
4.2 Test Bench . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
4.3 RTL and Technology Schematic . . . . . . . . . . . . . . . . . . . . 14
4.4 UCF file . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
4.5 Configuration of Target Device . . . . . . . . . . . . . . . . . . . . 15
4.6 Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
4.6.1 State: S1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
4.6.2 State: S2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

1
 4.6.3 State: S3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
4.6.4 State: S4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
4.6.5 State: S5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
4.6.6 State: S6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
4.6.7 Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

5 Conclusion 21

References 22
List of Figures

2.1 Spartan-6 XC6SLX9 . . . . . . . . . . . . . . . . . . . . . . . . . . 4

2.2 Tiny FPGA BX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
2.3 Artix-7 Board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2.4 Zynq-7000 Board . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2.5 EDA Playground Software . . . . . . . . . . . . . . . . . . . . . . . 6
2.6 Xilinx Software . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2.7 Vivado Software . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

3.1 Representing different states of the traffic light system . . . . . . . 8

3.2 Block Diagram of Spartan-6 XC6SLX9 TQG144BIV2001 . . . . . . 10
3.3 Spartan-6 XC6SLX9 TQG144BIV2001 Board . . . . . . . . . . . . 11
3.4 Xilinx ISE WebPack Interface . . . . . . . . . . . . . . . . . . . . . 12

4.1 Creating Verilog Module . . . . . . . . . . . . . . . . . . . . . . . 13

4.2 Output waveform of the states . . . . . . . . . . . . . . . . . . . . . 14
4.3 RTL Schematic Diagram . . . . . . . . . . . . . . . . . . . . . . . . 14
4.4 Technology Schematic Diagram . . . . . . . . . . . . . . . . . . . . 15
4.5 UCF file generation . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
4.6 Generate Programming File successful . . . . . . . . . . . . . . 16
4.7 SPARTAN-6 board identified successfully . . . . . . . . . . . . . . . 16
4.8 Successfully burnt the program to SPARTAN-6 board . . . . . . . . 16
4.9 S1 State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
4.10 S2 State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
4.11 S3 State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
4.12 S4 State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
4.13 S5 State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
4.14 S6 State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
4.15 Reset State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

i
List of Tables

3.1 State Table of the project . . . . . . . . . . . . . . . . . . . . . . . 9

3.2 List of Components . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

ii
 Chapter 1

Introduction

1.1 Motivation and Background

Traffic congestion is a severe problem in many cities and towns. It has posed
numerous problems and setbacks in almost every major metropolis. Furthermore,
traffic congestion reduces the productivity of traders, suppliers, and workers, which
raises the cost of goods. Another difficulty emerges when there is no traffic yet
people are still waiting. The idea is to control the traffic light delay time and detect
the level of congestion. This issue necessitates an assessment of the situation and
a changeover to human traffic control.
This work aims that a traffic light system will provide a solution at a low
cost. A traffic light controller (TLC) can be made using an FPGA. There are
advantages and disadvantages to each. Some of the parameters that are used to
compare them are; the number of input/output ports, performance, speed, and
cost, all of which are very significant in TLC design.

1.2 Ojective
To implement a Traffic light controller using Verilog coding and Spartan 6
FPGA board.

1
1.3 Outline
This dissertation report consists of the following chapters. The contents of the
chapters are as follows,
Chapter 2: Literature review of the project
Chapter 3: Component-wise specification, Implemented circuit and Working
Chapter 4: Analysis based on the output
Chapter 5: Conclusion

2
 Chapter 2

Literature Survey

FPGAs (Field Programmable Gate Arrays) are semiconductor devices that

consist of a matrix of customizable logic blocks (CLBs) linked by programmable
interconnects. After production, FPGAs can be reprogrammed to meet specific
application or feature needs.

2.1 FPGA Boards

2.1.1 Spartan 6 FPGA Board

One of the most recent technologies is the Spartan-6 series of Field-Programmable
Gate Arrays, which was designed especially for high-volume, low-cost consumer
electronic applications. Logic cells and system gates with densities ranging from
3,840 to 147,443 are part of the thirteen-member family. The Spartan-6 family
expands logic resources, internal RAM capacity, total number of I/Os, and overall
performance, as well as enhancing clock management features, to build on the
success of the previous Spartan-IIE family.

3
 Figure 2.1: Spartan-6 XC6SLX9

2.1.2 Tiny FPGA

The Tiny FPGA BX is a small field-programmable gate array (FPGA) board
that has all of the necessary components and circuits for the FPGA to function.
The BX module allows you to design and implement digital logic circuits in
a tiny container, making it excellent for breadboards, small spaces, and custom
PCBs.
You can do things that ordinary microcontrollers can’t because of the Tiny
FPGA BX’s power.
Unlike microcontroller boards, which have a predetermined collection of periph-
eral devices on board, the Tiny FPGA BX may incorporate the precise peripheral
devices required to complete the task.

Figure 2.2: Tiny FPGA BX

4
2.1.3 Artix 7
In a cost-optimized FPGA, Artix-7 devices deliver the greatest performance-
per-watt fabric, transceiver line rates, DSP processing, and AMS integration. The
series provides the greatest value for a number of cost and power-sensitive ap-
plications, including software-defined radio, machine vision cameras, and low-end
wireless backhaul, thanks to the MicroBlaze soft processor and 1,066Mb/s DDR3
compatibility.

Figure 2.3: Artix-7 Board

2.1.4 Zynq-7000 SoC

The Zynq-7000 SoC series combines the software programmability of an ARM®-
based processor with the hardware programmability of an FPGA, allowing for cru-
cial analytics and hardware acceleration while combining CPU, DSP, ASSP, and
mixed signal functions on a single device. The Zynq-7000 series, which includes
single-core Zynq-7000S and dual-core Zynq-7000 devices, is the most cost-effective,
performance-per-watt, fully scalable SoC platform for your specific application
needs.

Figure 2.4: Zynq-7000 Board

5
2.2 EDA Tools

2.2.1 EDA Playground

Users may edit, simulate (and observe waveforms), synthesise, and share their
HDL code using EDA Playground, a free web programme. Its purpose is to make
design and testbench development easier to learn by sharing code and making
simulators and frameworks more accessible. EDA Playground was created with
modest prototypes and demonstrations in mind (it is not intended to be used for
a full-blown FPGA or ASIC design).

Figure 2.5: EDA Playground Software

2.2.2 Xilinx ISE WebPack

The industry’s only FREE, fully featured front-to-back FPGA design solution
for Linux, Windows XP, and Windows 7 is ISE WebPACK. With HDL synthe-
sis and simulation, implementation, device fitting, and JTAG programming, ISE
WebPACK is the ultimate downloadable solution for FPGA and CPLD design.
ISE WebPACK is a free, front-to-back design flow that gives you rapid access to
all of ISE’s features and capability. Xilinx has developed a system that enables for
easy productivity by delivering an always-up-to-date design solution with error-
free downloading and single-file installation.

Figure 2.6: Xilinx Software

6
2.2.3 Xilinx Vivado
Xilinx’s Vivado Design Suite is a software suite for synthesis and analysis of
hardware description language (HDL) designs, which replaces Xilinx ISE and adds
functionality for system on a chip development and high-level synthesis. Vivado
is a complete rewriting and rethinking of the whole design process (compared to
ISE).

Figure 2.7: Vivado Software

2.3 Technical Papers/Websites Referred

2.3.1 Traffic Light Controller based on FPGA

Using a Moore finite state machine, an efficient and intelligent traffic light
controller is constructed in this study (FSM). The programming language used
in the implementation is Verilog. The design is implemented using the Spartan-6
FPGA development kit (XC6SLX9). This model controls traffic at any four-road
junction. The technology helps to cut down on the amount of time motorists
spend waiting at crosswalks. It also cuts down on the amount of cars on the road.

2.3.2 Real-Time Traffic Light Controller System based on

FPGA and Arduino
Arduino and Spartan 3E were used to create a traffic light system. The Ar-
duino Mega is a basic prototype model that is inexpensive, user-friendly, readily
programmable, and can run on its own, but the FPGA Spartan 3E platform has
high security, high reliability, high efficiency, and runs at a fast rate. As a result,
the decision between FPGA and Arduino is based on the nature of the require-
ment.

2.4 Problem Statement

To design an efficient electronic traffic management system using verliog coding
on a FPGA [Link]

7
 Chapter 3

Methodology Used

3.1 Working of project

3.1.1 State Diagram

Figure 3.1: Representing different states of the traffic light system

8
3.1.2 State Table

Table 3.1: State Table of the project

Name Input NS M1 M2 MT S
+ + +
A B C (RYG) (RYG) (RYG) (RYG)
000 - 001 000 000 000 000
001 T MG 001 to 001 001 100 100
& TMG 010
010 TY & 010 to 001 010 100 100
TY 011
011 T T G & 011 to 001 100 001 100
TTG 100
100 TY & 100 to 010 100 010 100
TY 101
101 T SG & 101 to 100 100 100 001
TSG 110
110 TY & 110 to 100 100 100 010
TY 001
111 - 001 000 000 000 000

3.2 Hardware Software Components

Table 3.2: List of Components

Name Quantity
Spartan-6 XC6SLX9 TQG144BIV2001 1
Cable (USB Type-A to Micro USB Type-B) 1
LED
- 3
- Red
- 3
- Yellow
- 3
- Green

Resistor (330Ω) 3
Bread Board 2
Connecting Wires As required

9
3.2.1 Spartan-6 XC6SLX9 TQG144BIV2001
Key Features:

ˆ Up to 102 user-I/O pins

ˆ TQ-144 package

Figure 3.2: Block Diagram of Spartan-6 XC6SLX9 TQG144BIV2001

Key Components:

ˆ XC6SLX9 TQ144

ˆ OSCILLATOR – 12MHz

ˆ FLASH – M25P80

ˆ USB Power

ˆ On board USB Jtag

ˆ USB to serial

ˆ 10bit SPI ADC

ˆ 8bit SPI DAC

ˆ 8 LED

ˆ 8 DIP SWITCHS

ˆ 8 PUSH BUTTONS

10
ˆ 32 user I/O

ˆ LCD 16By2

ˆ 7-Seg

ˆ RELAY

ˆ Steeper & DC motor driver

ˆ BUZZER

ˆ RGB – LED

ˆ WiFi

Figure 3.3: Spartan-6 XC6SLX9 TQG144BIV2001 Board

11
3.2.2 Xilinx ISE WebPack
Xilinx ISE WebPack is a tool for the synthesis and analysis of HDL designs,
with a focus on embedded firmware development for the Xilinx FPGA and CPLD
IC product lines. ISE WebPack is succeeded by Vivado.
ISE allows programmers to synthesise (or ”compile”) their designs, do timing
analysis, study RTL diagrams, simulate a design’s response to various stimuli, and
configure the target device with the programmer.

Figure 3.4: Xilinx ISE WebPack Interface

We have used Verilog programming language. Verilog is a hardware description

language (HDL) for modelling electronic systems that is standardised as IEEE
1364.

12
 Chapter 4

Implementation & Results

4.1 Module creation and Interfacing

Figure 4.1: Creating Verilog Module

13
4.2 Test Bench

Figure 4.2: Output waveform of the states

4.3 RTL and Technology Schematic

Figure 4.3: RTL Schematic Diagram

14
 Figure 4.4: Technology Schematic Diagram

4.4 UCF file

Here, we have assigned the output variables, from our main verilog module
(Traffic.v), to the Pmod (Peripheral Module) pins of the SPARTAN-6 FPGA
board.

Figure 4.5: UCF file generation

4.5 Configuration of Target Device

After creating the UCF file, click on ”Generate Programming File” to generate
the programming bit file. Lastly, configure the target device, i.e., burn the program
to the SPARTAN-6 FPGA board.

15
 Figure 4.6: Generate Programming File successful

Figure 4.7: SPARTAN-6 board identified successfully

Figure 4.8: Successfully burnt the program to SPARTAN-6 board

16
4.6 Output

4.6.1 State: S1

Figure 4.9: S1 State

4.6.2 State: S2

Figure 4.10: S2 State

17
4.6.3 State: S3

Figure 4.11: S3 State

4.6.4 State: S4

Figure 4.12: S4 State

18
4.6.5 State: S5

Figure 4.13: S5 State

4.6.6 State: S6

Figure 4.14: S6 State

19
4.6.7 Reset

Figure 4.15: Reset State

20
Chapter 5

Conclusion

21
 Reference

[1] S. N. Apoorva, S. R. Karthik, and M. B. Rakesh, “Traffic Light Controller

based on FPGA,” Int. Res. J. Eng. Technol., vol. 4, no. 5, pp. 848–851, 2017,
[Online]. Available: [Link]

[2] S. Nath et al., “Design of an FPGA based intelligence traffic light controller
with VHDL,” 2012 Int. Conf. Radar, Commun. Comput. ICRCC 2012, pp.
92–97, 2012, doi: 10.1109/ICRCC.2012.6450554.

[3] S. E. E. Profile, “Design and Implementation of Spartan 6 Series FPGA Board

and Application of PID Controller for Robots Design and Implementation of
Spartan 6 Series FPGA Board and Application of PID Controller for Robots,”
no. February 2014, pp. 0–6, 2015.

[4] S. Qaddori and N. Gadawe, “Real-Time Traffic Light Controller System

based on FPGA and Arduino,” no. January 2020, 2020, doi: 10.4108/eai.28-
6-2020.2297938.

[5] A. Raza, A. Kumar, and E. Chaudhary, “TRAFFIC LIGHT CONTROLLER

USING VHDL”, doi: 10.21884/IJMTER.2017.4118.C529F.

22