TRAFFIC LIGHT CONTROLLER USING VHDL

Aamir Raza1, Arun Kumar2 and Ekta Chaudhary3

1,2,3
B.Tech, 4th yr, GIET GUNUPUR, RAYAGADA, PIN-765022
Abstract- Traffic light controller is a set of rules and instructions that drivers, pilots, train engineers,
and ship captains rely on to avoid collisions and other hazards. Traffic control systems include signs,
lights and other devices that communicate specific directions, warnings, or requirements. Traffic
light controller (TLC) has been implemented using verilog HDL. It has many advantages over other
with reference to the speed, number of input/output ports and performance which are all very
important in design. This paper concerns with an design implementation of an advanced traffic light
controller system that was built as a term project of a VLSI design subject using VHDL. The system
has been successfully tested and implemented in hardware using Xilinx Spartan 3 FPGA. The
system has many advantages over the other exciting Traffic Light Controller. The VHDL code is
being used in order to implement the design and the simulation is being tested using the ISim
Simulator. It is easy to use and the cost for the same is also less as compared to the others.
I. INTRODUCTION
Why Traffic Light Controller ?
The normal function of Traffic Light Controller requires more than slight control and
coordination to ensure that traffic moves as smoothly and safely as possible and that pedestrians are
protected when they cross the roads. A variety of different control systems are used to accomplish
this, ranging from simple clockwork mechanisms to sophisticated computerized control and
coordination systems that self-adjust to minimize delay to people using the road.
This traffic jam directly impacts the productivity of the workers, traders, suppliers and in all
effecting the market and raising the prices of the commodities in a way. To solve these traffic related
problems, we have to build new conveniences & infrastructure but at the same time make it smart.
The only drawback of making new roads on facilities is that it makes the surroundings more
congested, but then this will make a way to have new ways to ease the traffic. Perhaps all the
countries are working to accommodate the traffic flow and advance transportation and reduce the
demand of vehicle use.
Traffic congestion has been causing many setbacks and challenges in the major and most
occupied cities all over the globe. To travel within the cities to the place of work or recreation has
become a big problem to the commutates all along. Due to these problems people lose time, money
and most importantly the energy resources will be exhausted due to the continual use in the
automobiles. This traffic jam directly impacts the productivity of the workers, traders, suppliers and
in all effecting the market and raising theprices of the commodities in a way. To solve these traffic
related problems, we have to build new conveniences & infrastructure but at the same time make it
smart. The only drawback of making new roads on facilities is that it makes the surroundings more
congested, but then this will make a way to have new ways to ease the traffic. We have to build new
facilities and infrastructure making its use smarter for its efficient use. For this many ideas about the
traffic light systems have come up in the recent past to simplify the complex problem of the traffic
congestion.
Thus we have to implement the Street light controller using the VHDL code and the later is
simulated using Xilinx software and simulation is done with the ISE Simulator.

DOI:10.21884/IJMTER.2017.4118.C529F 57
 International Journal of Modern Trends in Engineering and Research (IJMTER)
Volume 04, Issue 4, [April– 2017] ISSN (Online):2349–9745; ISSN (Print):2393-8161

FIG.1. BLOCK DIAGRAM

II. FPGA
A field-programmable gate array (FPGA) is an integrated circuit designed to be configured by a
customer or a designer after manufacturing – hence "field-programmable". The FPGA configuration
is generally specified using a hardware description language (HDL), similar to that used for
an application-specific integrated circuit (ASIC).

FIG.2. A Spartan FPGA from Xilinx

FPGAs contain an array of programmable logic blocks, and a hierarchy of reconfigurable
interconnects that allow the blocks to be "wired together", like many logic gates that can be inter-
wired in different configurations.
III. FPGA DESIGN FLOW
FPGA design flow comprises the following steps: design entry, functional verification, time
verification and Xilinx device programming. Design verification, which includes both functional
verification and timing verification, takes places at different points during the design flow.
DESIGN ENTRY
>Create an ISE project as follows:
>Create a project.
>Create files and add them to your project, including a user constraints (UCF) file.
>Add any existing files to your project.
>Assign constraints such as timing constraints, pin assignments, and area constraints.
FUNCTIONAL VERIFICATION
You can verify the functionality of your design at different points in the design flow as follows:
1. Before synthesis, run behavioral simulation (also known as RTL simulation).

@IJMTER-2017, All rights Reserved 58

 International Journal of Modern Trends in Engineering and Research (IJMTER)
Volume 04, Issue 4, [April– 2017] ISSN (Online):2349–9745; ISSN (Print):2393-8161

2. After Translate, run functional simulation (also known as gate-level simulation), using the
SIMPRIM library.
3. After device programming, run in-circuit verification.

TIMING VERIFICATION
You can verify the timing of your design at different points in the design flow as follows:
 Run static timing analysis at the following points in the design flow:
o After Map
o After Place & Route
 Run timing simulation at the following points in the design flow:
o After Map (for a partial timing analysis of CLB and IOB delays)
o After Place and Route (for full timing analysis of block and net delays)
Xilinx Device Programming
Program your Xilinx device as follows:
1. Create a programming file (BIT) to program your FPGA.
2. Generate a PROM or ACE file for debugging or to download to your device.
3. Optionally, create a JTAG file.
4. Use iMPACT to program the device with a programming cable.

FIG.3. RTL Schematic for Traffic Light Controller

IV.SIMULATION RESULT
RTL Schematic
The figure 3 & 4 shows the RTL Schematic diagram and the simulation of the Traffic Light
Controller. Viewing a schematic allows you to see a technology level representation of your HDL
optimized for specific device architecture, which may help to you discover the design issues early in
design process.
In digital circuit design, Register Transfer Level (RTL) is a design abstraction which
models a synchronous digital circuit in terms of the flow of digital signals (data) between hardware
registers, and the logical operations performed on those signals.
Register-transfer-level abstraction is used in hardware description languages (HDLs)
like Verilog and VHDL to create high-level representations of a circuit, from which lower-level
representations and ultimately actual wiring can be derived. Design at the RTL level is typical
practice in modern digital design.

Fig. 3. Real time Simulatio

@IJMTER-2017, All rights Reserved 59

 International Journal of Modern Trends in Engineering and Research (IJMTER)
Volume 04, Issue 4, [April– 2017] ISSN (Online):2349–9745; ISSN (Print):2393-8161

Fig. 4. RTL Schematic design flow

V. VHDL CODE
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.std_logic_unsigned.all;
entity TLC is
Port (
Traffic lights:out STD_LOGIC_Vector (5 downto 0);
Clck : in STD_LOGIC;
Reset : in STD_LOGIC;
P_B : in STD_LOGIC);
end TLC;
architecture Behavioral of TLC is
type state_type is (st0_R1_G2, st1_R1_A1_A2, st2_G1_R2, st3_A1_R2_A2);
signal state: state_type;
signal count : std_logic_vector (3 downto 0);
constant sec10 : std_logic_vector ( 3 downto 0) := "1010";
constant sec2 : std_logic_vector (3 downto 0 ) := "0010";
constant sec16: std_logic_vector (3 downto 0 ) := "1111";
begin
process (Clck,Reset)
begin
if Reset='1' then
state <= st0_R1_G2; --reset to initial state
count <= X"0"; -- reset counter
elsif Clck' event and Clck = '1' then --
case (state) is
when st0_R1_G2 =>
if count < sec10 then
state <= st0_R1_G2;
count <= count + 1;
else
state <= st1_R1_A1_A2;
count <= X"0";
end if;

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 International Journal of Modern Trends in Engineering and Research (IJMTER)
Volume 04, Issue 4, [April– 2017] ISSN (Online):2349–9745; ISSN (Print):2393-8161

when st1_R1_A1_A2 =>

if count < sec2 then
state <= st1_R1_A1_A2;
count <= count + 1;
else
state <= st2_G1_R2;
count <= X"0";
end if;

when st2_G1_R2 =>

if count < sec10 then
state <= st2_G1_R2;
count <= count + 1;
else
state <= st3_A1_R2_A2;
count <= X"0";
end if;

when st3_A1_R2_A2 =>

if count < sec2 then
state <= st3_A1_R2_A2;
count <= count + 1;
else
state <=st0_R1_G2;
count <= X"0";
end if;

when others =>

state <= st0_R1_G2;
end case;
end if;
end process;

OUTPUT_DECODE: process (state)

begin
case state is
when st0_R1_G2 => Trafficlights <= "100001"; -- Traffic Red 1, Pedestrian Green 1
when st1_R1_A1_A2 => Trafficlights <= "110010";
when st2_G1_R2 => Trafficlights <= "001100";
when st3_A1_R2_A2 => Trafficlights <= "010110";
when others => Trafficlights <= "100001";
end case;
end process;
end Behavioral;
V. FPGA SPARTAN IMPLEMENTATION
As we know that once the design part is over, it is required to implement that software part
into the real time simulation. Thus FPGA board is used in order to provide the real time simulation.
The Traffic Light Controller designed using Verilog HDL code and is implemented on the hardware
using FPGA. The output of the Traffic light is displayed on the Spartan-3E FPGA board as shown in
the figure.

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 International Journal of Modern Trends in Engineering and Research (IJMTER)
Volume 04, Issue 4, [April– 2017] ISSN (Online):2349–9745; ISSN (Print):2393-8161

Fig. 5. FPGA SPARTAN 3E

VI. FUTURE SCOPE
The Traffic Light Controller has many future aspects in terms of reducing the life of the
humans and reducing the accidents. The big advantage is that it can be implanted anywhere. It’s not
compulsory that we only metros and cities should have this controller, but it can be implemented in
rural areas too.
Also using this technique of verilog HDL FPGA implementation it has reduced the design
complexity as compared to the other technique used in the market.

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