Analog Circuit Design

Chapter 2. MOS Device Physics

2019 Fall
Jaeduk Han

Analog Circuit Design, 2019 Fall 1

Resistor, Capacitor, MOSFET
• Three main components of analog circuits and their major purposes
• Resistors – V to I (or I to V) conversions
• Capacitors – storing charges (memory)
• MOS transistors (MOSFETs) – V to I conversions between 3 nodes
• “Transconductance”

Analog Circuit Design, 2019 Fall 2

Why MOSFET is useful for building analog circuits (amplifiers)?
• 3-terminal device that effectively isolates the input and output port
• Its transconductance ratio can be controlled by setting the bias
conditions and/or changing the size (W/L)

Output

Input

Reference

Analog Circuit Design, 2019 Fall 3

Why MOSFET amplifiers are better than the resistor dividers?
• Both have 3-terminals in their small-signal models
• Input/output/reference
• How about their voltage gains?
• How about input resistance?

Analog Circuit Design, 2019 Fall 4

Okay it looks like a useful thing. How does it look like?
• n-type MOS (NMOS) has n-doped source (S) and drain (D) on p-type
substrate (“bulk” or “body”).
• The S terminal provides charge carriers and the D terminal collects
them.
• As voltages at the three terminals change, the source and drain may
exchange roles.

Analog Circuit Design, 2019 Fall 5

A hidden terminal
• MOSFETs actually have four terminals.
• Substrate potential greatly influences device characteristics.
• Typically S/D junction diodes are reversed-biased and the NMOS
substrate is connected to the most negative supply in the system.

Analog Circuit Design, 2019 Fall 6

PMOS Structure
• PMOS is obtained by inverting all of the doping types (including the
substrate).

Analog Circuit Design, 2019 Fall 7

CMOS Technology
• In complementary MOS (CMOS) technologies both NMOS (NFET) and
PMOS (PFET) are needed and fabricated on the same wafer.
• In today’s CMOS, the PMOS is fabricated in an n-well, where the n-
well is tied to the most positive supply voltage.

Analog Circuit Design, 2019 Fall 8

MOSFET Symbols
• Substrate is denoted by “B” (bulk).
• PMOS source is positioned on top since it has a higher potential than
the gate (a).
• Most circuits have NMOS and PMOS bulk tied to ground and VDD,
respectively, so we tend to omit the connections (b,c).

Analog Circuit Design, 2019 Fall 9

 NMOS Threshold Voltage
• As VG increases from zero, holes in p-substrate are repelled leaving
negative ions behind to form a depletion region.
• If the VG further increases beyond a certain value, a channel is
formed beneath the gate oxide
• The certain voltage value is called the threshold voltage (VTH) of the transistor

VG>0V VG>VTH
Analog Circuit Design, 2019 Fall 10
This slide is updated from the previous version, on Sep 14
 PMOS Threshold Voltage
• Turn-on phenomena in PMOS is similar to that of NMOS but with all
polarities reversed.
• If the gate-source voltage becomes sufficiently negative, an inversion
layer consisting of holes is formed at the oxide-silicon interface,
providing a conduction path between source and drain.
• PMOS threshold voltage is negative.

Analog Circuit Design, 2019 Fall 11

This slide is updated from the previous version, on Sep 14
MOS I/V Characteristics after the Threshold
• The starting point

• Qd is the mobile charge density along the direction of current I.

• v is the charge velocity.
• Finding out the Qd and v will give the channel current

Analog Circuit Design, 2019 Fall 12

MOS I/V Characteristics - Qd
• Local voltage difference between the gate and the channel varies
from VG to VG − VD across the channel
• Charge density is given by the following equation:

• Where WCox is the total capacitance per unit length and V(x) is the channel
potential at x.

Analog Circuit Design, 2019 Fall 13

MOS I/V Characteristics - v
• The carrier velocity of MOSFET is given by the following equation
%&
! = #$ = #
%'
• Where µ is the mobility of the carrier (µn≠µp)

Analog Circuit Design, 2019 Fall 14

MOS I/V Characteristics – Putting Everything Together
• Plug in the expression to the Qd and v terms in the current equation

%&
! = #$ = #
%'
• Then the channel current equation becomes as follows

• Rearranging the term and integrate both sides

Analog Circuit Design, 2019 Fall 15

MOS I/V Characteristics – Triode Region
• VGS−VTH is known as the “overdrive voltage.”
• If VDS ≤ VGS−VTH, we say the device is operating in the “triode region.”

Analog Circuit Design, 2019 Fall 16

MOS I/V Characteristics – Deep Triode Region
• If VDS << 2(VGS−VTH), then

• In this case, the drain current is a linear function of VDS so the path
from source to drain can be represented by a linear resistor:

A voltage controlled resistor

Analog Circuit Design, 2019 Fall 17

MOS I/V Characteristics – Saturation
• In reality, if VDS > VGS−VTH, ID becomes relatively constant and we say
that the device operates in “saturation region.”
• VD,sat = VGS−VTH denotes the minimum VDS necessary for operation in
saturation.

Analog Circuit Design, 2019 Fall 18

MOS I/V Characteristics – PMOS I/V characteristics
• For PMOS devices, the equations become

• The negative sign shows up due to the assumption that drain current
flows from drain to source, whereas holes in a PMOS flow in the
reverse direction.
• VGS, VDS, VTH, and VGS−VTH are negative for a PMOS transistor that is
turned on.
• Since the mobility of holes is about ½ the mobility of electrons, PMOS
devices suffer from lower “current drive” capability.
• Well, this does not hold for very recent technology nodes
Analog Circuit Design, 2019 Fall 19
MOS as a Current Source
• A saturated MOSFET can be used as a current source connected
between the drain and the source.
• With a proper Vb provided – “biasing”.
• NMOS current sources inject current into ground while PMOS current
sources draws current from VDD.

Analog Circuit Design, 2019 Fall 20

MOS Transconductance (1)
• Transconductance (usually defined in the saturation region) is defined
as the change in drain current divided by the change in the gate-
source voltage.
• gm represents the sensitivity of the device since a high value implies a
small change in VGS will result in a large change in ID.
• Higher V-I conversion gain

Small-signal model

Analog Circuit Design, 2019 Fall 21

MOS Transconductance (2)
• Each expression for transconductance is useful in studying its
behavior.

Analog Circuit Design, 2019 Fall 22

MOS Transconductance - Exercise
• Plot the VDS vs. gm curve for the circuit on the
left
• So long as VDS ≥ Vb − VTH, M1 is in saturation, so ID is
relatively constant, and therefore so is gm.
• When M1 enters triode region (VDS < Vb − VTH),

Analog Circuit Design, 2019 Fall 23

MOS Transconductance - PMOS
• Almost the same except the sign and the mobility parameter

Analog Circuit Design, 2019 Fall 24

MOS I/V Second-Order Effects – Body Effect
• Actually the MOS devices have 4-terminals (Gate/Source/Drain/Body)
• The body (bulk) voltage (VB) is normally assumed to be the same with
the source voltage. Otherwise, the voltage difference (VSB) modulates
the threshold voltage (VTH) by affecting the depletion region.
• Body effect (back-gate effect)

• Note: ignore the body effect for the rest of this course, unless
specified

Analog Circuit Design, 2019 Fall 25

MOS I/V Second-Order Effects – Channel Length Modulation
• Originally, when the device was in saturation region, drain current
was characterized by

• The actual length of the channel (L’ = L − ΔL) is a function of VDS,

which is an effect called “channel length modulation.”
• The effect is captured by introducing an additional parameter λ
*Note: usually I’m not assuming the
channel length modulation in ‘bias’
calculations because it does not make a
lot of difference.
The channel length modulation effect is
more critical in small-signal analysis
(modeled by ro)

Analog Circuit Design, 2019 Fall 26

MOS I/V Second-Order Effects – Subthreshold Conduction
• MOSFETs do not turn off abruptly when VGS < VTH, but finite current
flows from drain to source with an exponential dependence on VGS.
• When VGS < VTH,

• where I0 and ξ are fitting parameters, and VT = kT/q.

Analog Circuit Design, 2019 Fall 27

MOS Device Capacitances
• At high frequencies, the capacitive loadings between MOS terminals
affect the device performance
• Capacitance exists between every two of the four terminals, and their
values depend on the bias conditions of the transistor

Analog Circuit Design, 2019 Fall 28

MOS Device Capacitances – Capacitance Components (1)
• Capacitances include
• The oxide capacitance between the gate and the channel C1.
• The depletion capacitance between the channel and the substrate C2.
• The capacitance due to the overlap of the gate poly with the source and drain
areas C3 and C4.
• The junction capacitance between the source/drain areas and the substrate
C5 and C6.

Analog Circuit Design, 2019 Fall 29

MOS Device Capacitances – Capacitance Components (2)
• Channel capacitance (C1)

• Depletion capacitance (C2)

!" = $%!&'(
• Overlap capacitances (C3, C4)
!) = !* = $!+,

Analog Circuit Design, 2019 Fall 30

MOS Device Capacitances – Capacitance Components (3)
• Junction capacitances (C5, C6)
!" = !$ = %&!' + 2 % + & !'*+
• Where E is the horizontal width of the source/drain diffusion regions

Analog Circuit Design, 2019 Fall 31

MOS Device Capacitances – Capacitance Components (4)
• The linear combinations of C1~C6 are mapped to capacitances
between MOSFET terminals
• The combination coefficients are different across the operation regions of
MOSFET devices

Analog Circuit Design, 2019 Fall 32

MOS Device Capacitances – CGD and CGS (1)
• When the device is off, there’s no channel

• When the device is in linear, the channel is almost uniformly defined,

so C1 is divided equally between the CGD and CGS

Analog Circuit Design, 2019 Fall 33

MOS Device Capacitances – CGD and CGS (2)
• In saturation, the nonuniform channel distribution results in
asymmetric distribution of capacitances

!"# = %!&'

Analog Circuit Design, 2019 Fall 34

MOS Device Capacitances – CGB
• CGB is almost neglected in triode and saturation due to the large
inversion layer
• In cut-off, CGB is the series combination of C1 and C2
!%& !'()
!"# =
!%& + !'()

Analog Circuit Design, 2019 Fall 35

MOS Device Capacitances – CDB and CSB
• They are mostly from the junction and sidewall caps. Assuming one-
finger device, they are given by the following equation

!"# = !%# = &'!( + 2 & + ' !(+,

• CDB and CSB are highly impacted by the device layout.

Analog Circuit Design, 2019 Fall 36

MOS Small-Signal Model
• If perturbation in bias conditions are small, a “small-signal” model can
be used to simplify calculations (derived for saturation region).

The small-signal model of a MOSFET without channel length modulation, body effect, and
parasitic capacitances

Analog Circuit Design, 2019 Fall 37

MOS Small-Signal Model – Channel Length Modulation
• Due to channel-length modulation, drain current also varies with VDS ,
but a current source whose value linearly depends on the voltage
across it is equivalent to a linear resistor:

The small-signal model of a MOSFET with channel length modulation

Analog Circuit Design, 2019 Fall 38
MOS Small-Signal Model – Body Effect
• Due to body effect, bulk potential influences VTH and hence gate-
source overdrive.
• With all other terminals held at a constant voltage, the bulk behaves
as a second gate since the drain current is a function of the bulk
voltage given by gmbVBS

The small-signal model of a MOSFET with channel length modulation and body effect
Analog Circuit Design, 2019 Fall 39
MOS Small-Signal Model – Complete Model Including Caps
• The complete MOS small-signal model not only includes channel-
length modulation and body effect, but also the capacitances
between each terminal.

• Very complex; need to simply the model in real circuit analysis

• Will be covered in following lectures

Analog Circuit Design, 2019 Fall 40

Recap
• MOSFET I-V characteristic
(linear)

(saturation)

• MOSFET capacitances
(linear)

!"# = %!&' (saturation)

• MOS small signal model

Analog Circuit Design, 2019 Fall 41

Next Topic
• Single-stage amplifier

Analog Circuit Design, 2019 Fall 42