ROEVER ENGINEERING COLLEGE

Approved by AICTE, New Delhi and Affiliated to Anna University, Chennai

Inclusion under Section 2(f) and 12(B) of the UGC act, 1956
ELAMBALUR, PERAMBALUR – 621 220

COMPUTER SCIENCE AND ENGINEERING

COURSE DESCRIPTION

Course Code : CS8592

Course Title : OBJECT ORIENTED ANALYSIS AND DESIGN
 Course Code / Title C 203 / OBJECT ORIENTED ANALYSIS AND DESIGN
Program / Department B.E / COMPUTER SCIENCE AND ENGINEERING
Semester / Year III / II
Regulation / Course Type R 2017 / Professional Core [ THEORY ]
Course Coordinator Ms. M. Suganthi / Assistant Professor / CSE
Course Pre-Requisites
Course Overview
The main objective of the course is to provide
 To understand the fundamentals of object modeling
 To understand and differentiate Unified Process from other approaches.
 To design with static UML diagrams.
 To design with the UML dynamic and implementation diagrams.
 To improve the software design with design patterns.
 To test the software against its requirements specification
Marks Distribution CIA 20 END SEMESTER EXAM 80

Mode Of Content Delivery BB ICT

PPT VIDEO NPTEL ANIMATION
   

Instructional Methodologies Lecture Tutorial Assignment Seminar Others

  
Other Instruction Methodologies

Evaluation Methodology
Total Marks 100
Internal Marks 20
Internal Test conducted for 50 marks
Question Pattern Part A 10 *2 = 20 Marks [no choice] & Part B 3*10 = 30 Marks [ Either or Type]
Three CIA Test marks reduced to 5 and Attendance 5 Marks, Total 20 marks
End Semester Exam marks 80
Exam conducted for 100 marks and reduced to 80 marks
Question Pattern Part A 10 *2 = 20 Marks, Part B 5*13 = 65 Marks [ Either or Type]
Part C 1*15 = 15 Marks [ Either or Type]

Blooms Taxonomy Percentage of cognitive level

Remember 80 4/5[4 out of 5 Cos maps remember]
Understand 80
Apply 80
Analyse 80
Evaluate 20 CO 5 is about simulation of circuits otherwise no level 5,6 in theory subjects
Create 20
Course Objectives:
Objectives of this course is to

1 To understand the fundamentals of object modeling

2 To understand and differentiate Unified Process from other approaches.
3 To design with static UML diagrams.
4 To design with the UML dynamic and implementation diagrams.
5 To improve the software design with design patterns.
Course Outcomes:
At the end of this course students should be able to
Highest
CO. No Course Outcome BL
C311.1 Express software design with UML diagrams 4
C311.2 Design software applications using OO concepts. 4
C311.3 Identify various scenarios based on software requirements 4
C311.4 Transform UML based software design into pattern-based design using design patterns 4
C311.5 Understand the various testing methodologies for OO software 6

Cognitive Level in Course Outcomes

Cognitive Level
6
5
4
3
2
1
0
Remember Understand Apply Analyse Evaluate Create

CO – PO – PSO MAP

COs PO1 PO2 PO3 PO4 PO5 PO6 PO7 PO8 PO9 PO10 PO11 PO12 PSO1 PSO2 PSO3
C203.1   - - - - - - -   - 
C203.2     - - - - - - -   - 
C203.3     - - - - - - -   - 
C203.4     - - - - - - -   - 
C203.5      - - - - - -    
 Justification of CO PO PSO Mapping

No of
COs POs Justification of Mapping
Competency
Apply laws of natural science to an engineering problem
1 Apply fundamental engineering concepts to solve engineering problems 2
C203.1 2 Articulate problem statements and identify objectives 1
12 Describe the rationale for the requirement for continuing professional development 1
Apply mathematical techniques
Apply laws of natural science to an engineering problem
1 Apply fundamental engineering concepts to solve engineering
4
problems Apply engineering concepts to solve engineering problems
Articulate problem statements and identify objectives
2 Identify engineering systems, variables, and parameters to solve problems 3
Identify mathematical, engineering and knowledge that applies to a given problem
C203.2 Recognize that need analysis is key to good problem definition
3 Elicit and document, engineering requirements from stakeholders 3
Synthesize engineering requirements from a review of the state-of-the-art
Define a problem, its scope and importance for purposes of investigation
4 Examine the relevant methods, tools and techniques of experiment design. 3
Apply appropriate instrumentation tools to make measurements of physical quantities
12 Describe the rationale for the requirement for continuing professional development 1
Apply laws of natural science to an engineering problem
1 Apply fundamental engineering concepts to solve engineering problems 3
Apply engineering concepts to solve engineering problems
Articulate problem statements and identify objectives
2 Identify engineering systems, variables, and parameters to solve problems 3
Identify mathematical, engineering and knowledge that applies to a given problem
C203.3 Recognize that need analysis is key to good problem definition
3 Elicit and document, engineering requirements from stakeholders 3
Synthesize engineering requirements from a review of the state-of-the-art
Define a problem, its scope and importance for purposes of investigation
4 Examine the relevant methods, of experiment design. 3
Design and develop experimental approach, specify appropriate equipment and procedures
12 Describe the rationale for the requirement for continuing professional development 1
Apply fundamental engineering concepts to solve engineering problems
1 Apply engineering concepts to solve engineering problems 2
Articulate problem statements and identify objectives
2 Identify engineering systems, variables, and parameters to solve problems 3
Identify mathematical, engineering and knowledge that applies to a given problem
Recognize that need analysis is key to good problem definition
C204.4 3 Elicit and document, engineering requirements from stakeholders 3
Synthesize engineering requirements from a review of the state-of-the-art
Define a problem, its scope and importance for purposes of investigation
4 Examine the relevant methods, of experiment design. 3
Design and develop experimental approach, specify appropriate equipment and procedures
12 Describe the rationale for the requirement for continuing professional development 1
Apply laws of natural science to an engineering problem
1 Apply fundamental engineering concepts to solve engineering problems
Articulate problem statements and identify objectives
2 Identify engineering systems, variables, and parameters to solve problems 3
Identify mathematical, engineering and knowledge that applies to a given problem
Recognize that need analysis is key to good problem definition
C205.5 3 Elicit and document, engineering requirements from stakeholders 3
Synthesize engineering requirements from a review of the state-of-the-art
Define a problem, its scope and importance for purposes of investigation
4 Examine the relevant methods, of experiment design. 3
Design and develop experimental approach, specify appropriate equipment and procedures
Use of modern tools, simulation of digital logic circuits
4 3
12 Describe the rationale for the requirement for continuing professional development 1
 COs PSOs Justification of Mapping No of mapped Key
Competencies
1 Scientific, Mathematical principles and laws of science.
1
C203.1 3
Update new developments in relevant field. 1
1 Scientific, Mathematical principles and laws of science.
Problem statement, definition, formulation, identification, Validation and 2
C203.2 Solution development.
3
Update new developments in relevant field. 1
1 Scientific, Mathematical principles and laws of science.
Problem statement, definition, formulation, identification, Validation and 2
C203.3 Solution development.
3
Update new developments in relevant field. 1
1 Scientific, Mathematical principles and laws of science.
Problem statement, definition, formulation, identification, Validation and 2
C203.4 Solution development.
3
Update new developments in relevant field. 1
1 Scientific, Mathematical principles and laws of science.
Problem statement, definition, formulation, identification, Validation and 2
Solution development.
C203.5
2 Use of modern tools
1
3
Update new developments in relevant field. 1

CO – PO – PSO MAP – No of Key Elements

COs PO1 PO2 PO3 PO4 PO5 PO6 PO7 PO8 PO9 PO10 PO11 PO12 PSO1 PSO2 PSO3
C311.1 2 1 - - - - - - - 1 1 - 1
C311.2 4 3 3 3 - - - - - - - 1 2 - 1
C311.3 3 3 3 3 - - - - - - - 1 2 - 1
C311.4 3 3 3 3 - - - - - - - 1 2 - 1
C311.5 3 3 3 3 3 - - - - - - 1 2 1 1

No of key elements NK = 1 Weight W =1 NK=2 w =2 NK =3 W=3 NK > 3 W = 3 NK < 1 W = 0 or -

Course Articulation Matrix:

COs PO1 PO2 PO3 PO4 PO5 PO6 PO7 PO8 PO9 PO10 PO11 PO12 PSO1 PSO2 PSO3
C311.1 2 1 - - - - - - - - - 1 1 - 1
C311.2 3 3 3 3 - - - - - - - 1 2 - 1
C311.3 3 3 3 3 - - - - - - - 1 2 - 1
C311.4 3 3 3 3 - - - - - - - 1 2 - 1
C311.5 3 3 3 3 3 - - - - - - 1 2 1 1
3 3 3 3 1 - - - - - - 1 2 1 1

PO & PSO Assessment

Assessment Method
PO Strength
Direct method In Direct Method
CIA Test Assignment Semeste Tutorial Quiz Seminar Contest Survey
r Exam

1 3    
2 3   
3 3    
4 3    
5 1 
  
6
7
8
9
10
11

12 1   
PSO

1 2    
2 1
   
3 1    
 Syllabus

EE3302 DIGITAL LOGIC CIRCUITS LTPC 3003

COURSE OBJECTIVES:

 To introduce the fundamentals of combinational and sequential digital circuits.

 To study various number systems and to simplify the mathematical expressions using Boolean functions
word problems
 To study implementation of combinational circuits using Gates` and MSI Devices.
 To study the design of various synchronous and asynchronous circuits
 To introduce digital simulation techniques for development of application oriented logic circuit

UNIT I NUMBER SYSTEMS AND DIGITAL LOGIC FAMILIES 9

Number system, error detection, corrections & codes conversions, Boolean algebra: DeMorgan’s theorem,
switching functions and minimization using K-maps & Quine McCluskey method - Digital Logic Families -
comparison of RTL, DTL, TTL, ECL and MOS families - operation, characteristics of digital logic family.
UNIT II COMBINATIONAL CIRCUITS 9
Combinational logic - representation of logic functions-SOP and POS forms, K-map representations - minimization
using K maps - simplification and implementation of combinational logic – multiplexers and de multiplexers - code
converters, adders, subtractors, Encoders and Decoders.
UNIT III SYNCHRONOUS SEQUENTIAL CIRCUITS 9
Sequential logic- SR, JK, D and T flip flops - level triggering and edge triggering - counters - asynchronous and
synchronous type - Modulo counters - Shift registers - design of synchronous sequential circuits – Moore and
Mealy models- Counters, state diagram; state reduction; state assignment.
UNIT IV ASYNCHRONOUS SEQUENTIAL CIRCUITS AND PROGRAMMABILITY LOGIC DEVICES 9
Asynchronous sequential logic Circuits-Transition stability, flow stability-race conditions, hazards &errors in digital
circuits; analysis of asynchronous sequential logic circuitsintroduction to Programmability Logic Devices: PROM –
PLA –PAL, CPLD-FPGA.
UNIT V VHDL 9
RTL Design – combinational logic – Sequential circuit – Operators – Introduction to Packages – Subprograms – Test
bench. (Simulation /Tutorial Examples: adders, counters, flip flops, Multiplexers & De multiplexers).
TOTAL : 45 PERIODS
TEXTBOOKS:
1. Morris Mano.M, ’Digital Logic and Computer Design’, Prentice Hall of India, 3rdEdition, 2005.
2. Donald D.Givone, ‘Digital Principles and Design’, Tata McGraw Hill,1st Edition, 2003
3. Thomas L Floyd, ‘Digital fundamentals’, Pearson Education Limited, 11th Edition, 2018
REFERENCES:
1. Tocci R.J., Neal S. Widmer, ‘Digital Systems: Principles and Applications’, Pearson Education Asia, 12th Edition,
2017.
2. Donald P Leach, Albert Paul Malvino, Goutam Sha, ‘Digital Principles and Applications’, Tata McGraw Hill, 7th
Edition, 2010.
 Teaching Plan
Content Delivery [CD] : BB - 1 ICT – 2
Instruction Methodology [IM] : Lecture: 1 Tutorial: 2 Assignment: 3 Seminar: 4 Others: 5

S.N.O Topic to Covered Cos CD IM Reference

Book Chapter
UNIT I NUMBER SYSTEMS AND DIGITAL LOGIC FAMILIES
1 Number system 1 1 1 T1 1.1
2 error detection, corrections & codes conversions, 1 1 1 T1 1.1
3 Boolean algebra: DeMorgan’s theorem, 1 1 1 T1 1.2
4 switching functions and minimization using K-maps 1 1 1 T1 1.3
5 minimization using K-maps 1 1 1 T1 1.4
6 Quine McCluskey method 1 1 1 T1 1.4
7 Digital Logic Families RTL, DTL. 1 1 1 T1 1.5
8 Digital Logic Families TTL, ECL and MOS families 1 1 1 T1 1.6
9 Digital Logic Families MOS families 1 1 1 T1 1.7
UNIT II COMBINATIONAL CIRCUITS
10 Combinational logic 2 1 1 T1 3.1
11 representation of logic functions 2 1 1 T1 3.2
12 SOP and POS forms, 2 1 1 T1 3.2
13 K-map representations - minimization using K maps 2 2 1 T1 3.4
14 simplification and implementation of combinational logic 2 2 1 T1 3.5
15 simplification and implementation of combinational logic 2 2 1 T1 3.5
16 multiplexers and de multiplexers - 2 2 3 T1 3.7
17 code converters, adders, subtractors, 2 2 1 T1 3.8
18 Encoders and Decoders 2 2 1 T1 3.11,12
UNIT III SYNCHRONOUS SEQUENTIAL CIRCUITS
19 Sequential logic- SR, JK, D and T flip flops 3 3 1 T1 5.1
20 Sequential logic- SR, JK, D and T flip flops 3 3 1 T1 5.4
21 level triggering and edge triggering 3 3 1 T1 5.4
22 counters - asynchronous and synchronous type 3 3 1 T1 5.4
23 Modulo counters 3 3 3 T1 5.5
24 Shift registers 3 3 3 T1 5.5
25 design of synchronous sequential circuits 3 3 1 T1 5.6
26 Moore and Mealy models 3 3 1 T1 5.7
27 Counters, state diagram; state reduction; state assignment 3 3 1 T1 5.8
 Teaching Plan

Content Delivery [CD] : BB - 1 ICT – 2

Instruction Methodology [IM] : Lecture: 1 Tutorial: 2 Assignment: 3 Seminar: 4 Others: 5

S.N.O Topic to Covered Cos CD IM Reference

Book Chapter
UNIT IV Asynchronous Sequential Circuits & Programmability Logic
Devices .
28 Asynchronous sequential logic Circuits 4 2 1 T1 6.1
29 Asynchronous sequential logic Circuits 4 2 1 T1 6.3
30 Transition stability, 4 2 1 T1 6.4
31 Flow stability-race conditions, 4 2 1 T1 6.5
32 Hazards &errors in digital circuits; 4 2 1 T1 6.7
33 Analysis of asynchronous sequential logic circuits 4 2 1 T1 6.8
34 Analysis of asynchronous sequential logic circuits 4 2 1 T1 6.9
35 PROM, PLA . 4 2 1 T1 6.11
36 PAL, CPLD,FPGA 4 2 1 T1 6.12
UNIT V VHDL
37 RTL Design 5 2 4 T1 7.1
38 combinational logic 5 2 4 T1 7.2
39 combinational logic 5 2 1 T1 7.3
40 Sequential circuit 5 2 1 T1 7.3
41 Operators – Introduction to Packages 5 2 1 T1 7.4
42 Subprograms – Test bench 5 2 1 T1 7.5
43 Simulation /Tutorial Examples: adders, counters 5 2 1 T1 7.6
44 Simulation /Tutorial Examples: flip flops 5 2 1 T1 7.7
45 Simulation /Tutorial Examples: Multiplexers & De multiplexers 5 2 1 T1 7.8