EET 3350 Digital Systems Design Textbook: John Wakerly Chapter 8: 8.5 Shift RegistersDefinition * A register is a digital circuit with two basic functions: Data Storage and Data Movement —A shift register provides the data movement function —A shift register “shifts” its output once every clock cycle * A shift register is a group of flip-flops set up in a linear fashion with their inputs and outputs connected together in such a way that the data is shifted from one device to another when the circuit is activeShift Register Applications * converting between serial data and parallel data * temporary storage in a processor — scratch-pad memories * some arithmetic operations — multiply, divide * communications —UART * some counter applications —ring counter — Johnson counter — Linear Feedback Shift Register (LFSR) counters * time delay devices *more ...Shift Register Characteristics ° Types — Serial-in, Serial-out — Serial-in, Parallel-out Parallel in (Y — Parallel-in, Serial-out Parallel out (X —Parallel-in, Parallel-out — Universal en | scieshin PBS At OW * Direction — Left shift _— — Right shift ae ‘ in a — Rotate (right or left) — BidirectionalData Movement * The bits in a shift register can move in any of the following manners Data in —_ Datain—* —e—e—* be Datwout — Dataout = +2 2— fe Datain eee be ata ow Serial i/shit rightserial out Serial inshiftleftserial out Parallel i/serial out Data in oe Data in = —>—e— L eee i LI ted iu ee SoS Data out Data out Serial in/parallel out Parallel in/parallel out Rotate right Rotate leftData Movement * Block diagrams for shift registers with various input/output options: SL mbitshit [PS register bit shift Sent) bit shift rogister registerSerial-In Serial-Out * Data bits come in one at a time and leave one at a time | wbieanit [ST * One Flip-Flop for each bit to ae be handled GS * Movement can be left or ee right, but is usually only ina single direction in a given register —~ L456. * Asynchronous preset and 2p, 2 a} fo ero | clear inputs are used to set cer | initial valuesSerial-In Serial-Out * The logic circuit diagram below shows a generalized serial-in serial-out shift register — SR Flip-Flops are shown — Connected to behave as D Flip-Flops — Input values moved to outputs of each Flip-Flop with the clock (shift) pulse N-Bit Shift RegisterShift Registers The simplest shift register is one that uses only Flip-Flops The output of a given Flip-Flop is connected to the D input of the Flip-Flop at its right. Each clock pulse shifts the contents of the register one bit position to the right. The Serial input (S/) determines what goes into the leftmost Flip- Flop during the shift. The Serial output (SO) is taken from the output of the rightmost Flip-Flop. serial__St_[D O DO D oO DD O|_SO_ Serial input output iG c a iC CLK es ee ee 4-Bit Shift RegisterSerial-In Serial-Out * A simple way of looking at the serial shifting operation, with a focus on the data bits, is illustrated at right * The 4-bit data word “1011” is to be shifted into a 4-bit shift register * One shift per clock pulse * Data is shown entering at left and shifting right batain i Cock ] pulse 1 Datain ‘eit 1/1 pulse 2 stalin wo —>7 0/1] 1 pulse 3 Datain 1011 pulse 4Serial-In Serial-Out * The diagram at right of of ep shows the 4-bit | Pe | res [c sequence “1010” ox being loaded into the 4-bit serial-in serial- | ; | - | | = out shift register * Each bit moves one | ay | : position to the right each time the clock’s . Oe el naecus leading edge occurs aw | | * Four clock pulses ' loads the registerSerial-In Serial-Out * This diagram shows the 4-bit sequence | “1010” as itis ox 4 unloaded from the 4- TPP ye bit serial-in serial-out shift register * Each bit moves one AL | position to the right “Tu reeE each time the clock’s re | rhe | pe leading edge occurs awn. | * Four clock pulses unloads the register us LL J 1Serial-In Serial-Out * Serial-in, serial-out SERIN shift registers are clock often used for data communications —such as RS-232 — modem transmission and reception tt — Ethernet links \ —SONET etc. D a SEROUTSerial-to-Parallel Conversion * We often need to convert from serial to parallel — e.g., after receiving a series transmission nit shill register * The diagrams at the right illustrate a 4-bit serial-in — parallel-out shift register t t t t * Note that we could also use Me the Q of the right-most Flip- Flop as a serial-out outputSerial-to-Parallel Conversion * We would use a SERIN serial-in parallel-out — guocx shift register of arbitrary length N to convert an N-bit word from serial to parallel * It would require N tt clock pulses to LOAD iS and one clock pulse to UNLOADSerial-to-Parallel Conversion * These two shift 4 = registers are used to convert serial data to parallel data * The upper shift register would “grab” the data once it was shifted into the lower registerParallel-to-Serial Conversion * We use a Parallel-in Serial-out | Shift Register bit shift * The DATA is applied in parallel as form to the parallel input pins PA aren to PD of the register * Itis then read out sequentially from the register one bit at a time | | + | from PA to PD on each clock cycle in a serial format * One clock pulse to load * Four pulses to unload BeParallel-to-Serial Conversion * Logic circuit for a parallel-in, serial-out shift register cLock LOAD/SHIFT —rd>> SERIN 5) ; U 1D Oe) = ° J JE ee Mux-likeParallel-In Parallel-Out * Parallel-in Parallel-out Shift Registers can serve as a temporary storage device or t { { { as atime delay device * The DATA is presented in a parallel format to the parallel input pins PA to PD and then shifted to the corresponding output pins QA to QD when the registers are clocked * One clock pulse to load * One pulse to unloadUniversal Shift Register * Universal shift register * Can do any combination of parallel and serial input/output operations * Requires additional inputs to specify desired function * Uses a Mux-like input gating us—-d> is B fe MA nbitshitt [Po register 20Universal Shift Register * Parallel-in, parallel-out shift register clock LOAD/SHIFT ‘SERIN 1D ee Mux-like JU I o cKUniversal Shift Register * Parallel shift register (can serve as converting parallel-in to serial-out shifter): o Paralle| Output Implereniaton using Mp-lops and MUXes GQ; a, Q SO (Serial Out Si(Serial In) ‘shiShit Enable) oe] “Bt Parlin, (Load Enable) et Inputs Next State Action it Register SH Sh(Shitt} LdjLoad) | Q* a," a" QF ged 0 0 no change Parallel Intput ° 1 load = 1 x right shift 22MSI Shift Registers * 74LS164 is an 8-Bit Serial- In Parallel-Out Shift Register * Typical Shift Frequency of 35 MHz * Asynchronous Master Reset * Gated Serial Data Input * Fully Synchronous Data Transfers SNTaLS164 Serial. h® 23MSI Shift Registers 74LS164 logic diagram cae ope a Yec=PN GND = PIN7 ® ® (O= Pounumaers eo => 45 j -—L —/ [> -——4 45 ° =, = 45 os. 8 @e. @e ex. @ A LOW level on the Master Reset (MR) input overrides all other inputs and clears the register asynchronously, forcing all Q outputs Low. 24MSI Shift Registers * 74LS164 8-Bit Serial-In Parallel-Out Shift Register Voc Q) Os 0 MR cP “Gl fl Gl) fe) Gl LoGic SYMBOL i A Lsi64 2—18 — SBITSHIFTREGISTER c s4 Pp. TMR_Qo Q1 Op Qs Qy 5 Q§ Oy 9345 6unw Voc = PIN 14 GND = PINT a VY PIN NAMES 1 AB Data Inputs cP Clock (Active HIGH Going Edge) Input 7 Master Reset (Active LOW) Input Qo -Q7 Outputs 25MSI Shift Registers * The 74LS164 is an edge- triggered 8-bit shift register with serial data entry and an output from each of the eight stages. Locic SYMBOL * Data is entered serially through 1— iste 2—{B —BBITSHIFTREGISTER one of two inputs (A or B); sa “is s m : 03 04 05 Oy 0 — either of these inputs can be used PT TTT T I as an active HIGH Enable for data Yoo KPI entry through the other input GND= PINT — an unused input must be tied HIGH, or both inputs connected together 26MSI Shift Registers * Each LOW-to-HIGH transition on the Clock (CP) input shifts data one place to the right * This also outputs at Q, the logical AND of the two data inputs (A*B) that existed before the rising clock edge. LOGIC SYMBOL 1—A 2—|B — 8-BITSHIFT REGISTER om Fiz Gp. 01 Q2 03 Oy Qs O5 Or PPT TTT T 9 3°94 5 6 10 1112 13 Voc = PIN 14 GND = PIN7MSI Shift Registers MODE SELECT — TRUTH TABLE OPERATING INPUTS OUTPUTS MODE Reset (Clear) Shift L (|) = LOW Voltage Levels H (h) = HIGH Voltage Levels X = Don't Care Gn = Lower case letters indicate the state of the referenced input or output one set-up time prior to the LOW to HIGH clock transition. 28MSI Shift Registers * 74LS166 is an 8-Bit Shift Register * Parallel-in or serial-in — shift/load input establishes the parallel-in or serial-in mode * Serial-out * Synchronous Load — Serial data flow is inhibited during parallel loading * Direct Overriding Clear | osMSI Shift Registers * 74LS166 is an 8-Bit Shift Register PARALLEL PARALLEL INPUTS SHIFT) INPUT OUTPUT Voc LOAD H Qy G F_ E CLEAR SERIAL AB CD CLOCK CLOCK GND INPUT INHIBIT PARALLEL INPUTS: 30MSI Shift Registers * 74LS166 8-Bit Shift Register is a parallel-in or serial-in, serial-out shift register FUNCTION TABLE INPUTS: INTERNAL OUTPUT CLEAR SHE! | CLOCK CLOCK | SERIAL [Paraccet | ome Quy L 31MSI Shift Registers * 74LS166 is an 8-Bit Shift Register CLEAR SERIAL INPUT SHIFT/LOADMSI Shift Registers * 74LS166 is an 8-Bit Shift Register Typical Clear, Shift, Load, Inhibit, and Shift Sequences cvock STULL | | es CLEAR | | sera. nput | ff | | — SHIFTILOAD a 1 | i A Hy 8 rf ul c4 a parattel J 0 ul | INPUTS. E + + 7 | t | TT r—Lt | Ly it LI Lom 6 H TT Teh Hj + Hy i output ay: 11 7S gar FP LEAL LLL 1 ke-———— SERIAL SHIFT————+ ke} e- ——. SERIAL SHIFT ———> CLEAR LOAD 33