Biestable d en maestro / esclavo ----------------------------------------------------------------------------------- Company: -- Engineer: --- Create Date: 22:40:22 06/13/2011 -- Design Name: -- Module Name:

flip - Behavioral -- Project Name: -- Target Devices: -- Tool versions: -- Description: --- Dependencies: --- Revision: -- Revision 0.01 - File Created -- Additional Comments: ----------------------------------------------------------------------------------library IEEE; use IEEE.STD_LOGIC_1164.ALL; -- Uncomment the following library declaration if using -- arithmetic functions with Signed or Unsigned values --use IEEE.NUMERIC_STD.ALL; -- Uncomment the following library declaration if instantiating -- any Xilinx primitives in this code. --library UNISIM; --use UNISIM.VComponents.all; entity flip is Port ( Ck, Clr, d : in std_logic; Q : out std_logic); end flip; architecture Behavioral of flip is --Seales internas signal Q1 : std_logic; begin master: PROCESS(Ck,Clr,d) BEGIN If Clr = '0' then Q1 <= '0';

ELSIF (Ck'event and Ck ='1') then Q1 <= d; END IF; END PROCESS master; ----------------------------------------slave: PROCESS(Ck) BEGIN IF (Ck'event and Ck ='0') then Q <= Q1; END IF; END PROCESS slave; end Behavioral;

--- Simulacin --------------------------------------------------------------------------------- Company: -- Engineer: --- Create Date: 12:25:45 06/14/2011 -- Design Name: -- Module Name: D:/dvd programas icasio/UPQ_INTROFPGA/Lab_user/Examenp19/flip_tb.vhd -- Project Name: Examenp19 -- Target Device: -- Tool versions: -- Description: --- VHDL Test Bench Created by ISE for module: flip --- Dependencies: --- Revision: -- Revision 0.01 - File Created -- Additional Comments: --- Notes: -- This testbench has been automatically generated using types std_logic and -- std_logic_vector for the ports of the unit under test. Xilinx recommends -- that these types always be used for the top-level I/O of a design in order -- to guarantee that the testbench will bind correctly to the post-implementation -- simulation model. --------------------------------------------------------------------------------

LIBRARY ieee; USE ieee.std_logic_1164.ALL; -- Uncomment the following library declaration if using -- arithmetic functions with Signed or Unsigned values --USE ieee.numeric_std.ALL; ENTITY flip_tb IS END flip_tb; ARCHITECTURE behavior OF flip_tb IS -- Component Declaration for the Unit Under Test (UUT) COMPONENT flip PORT( Ck : IN std_logic; Clr : IN std_logic; d : IN std_logic; Q : OUT std_logic ); END COMPONENT;

--Inputs signal Ck : std_logic := '0'; signal Clr : std_logic := '0'; signal d : std_logic := '0'; --Outputs signal Q : std_logic; signal Q1 : std_logic; -- No clocks detected in port list. Replace <clock> below with -- appropriate port name

BEGIN -- Instantiate the Unit Under Test (UUT) uut: flip PORT MAP ( Ck => Ck, Clr => Clr, d => d, Q => Q ); Clr <= '1' after 10 ns; d <= '0', '0' after 10 ns;

Ck <= '0', '1' after 10 ns,'0' after 20 ns; END;

Segundaa etapa ----------------------------------------------------------------------------------- Company: -- Engineer: --- Create Date: 22:40:22 06/13/2011 -- Design Name: -- Module Name: flip - Behavioral -- Project Name: -- Target Devices: -- Tool versions: -- Description: --- Dependencies: --- Revision: -- Revision 0.01 - File Created -- Additional Comments: ----------------------------------------------------------------------------------library IEEE; use IEEE.STD_LOGIC_1164.ALL; -- Uncomment the following library declaration if using -- arithmetic functions with Signed or Unsigned values --use IEEE.NUMERIC_STD.ALL; -- Uncomment the following library declaration if instantiating -- any Xilinx primitives in this code. --library UNISIM; --use UNISIM.VComponents.all; entity flip is Port ( Ck, Clr, x : in bit; Qa, Qb,px : out bit); end flip; architecture Behavioral of flip is --Seales internas signal D1 : bit; signal Q1 : bit;

signal Q2 : bit; --signal D1, Q1, Q2 : std_logic; --signal D1, Q1, Q2 : std_logic; begin master: PROCESS(Ck,Clr,x) BEGIN If Clr = '0' then Q1 <= '0';

ELSIF (Ck'event and Ck ='1') then

D1 <= x xor Q2; px <= D1; Q1 <= D1; Qa <= Q1; END IF; END PROCESS master; ----------------------------------------slave: PROCESS(Ck) BEGIN IF (Ck'event and Ck ='0') then Q2 <= Q1; Qb <= Q2; END IF; END PROCESS slave; end Behavioral; sim --------------------------------------------------------------------------------- Company: -- Engineer: --- Create Date: 13:25:16 06/14/2011 -- Design Name: -- Module Name: D:/dvd programas icasio/UPQ_INTROFPGA/Lab_user/Examenp19/flip_tb.vhd -- Project Name: Examenp19 -- Target Device: -- Tool versions: -- Description: --

-- VHDL Test Bench Created by ISE for module: flip --- Dependencies: --- Revision: -- Revision 0.01 - File Created -- Additional Comments: --- Notes: -- This testbench has been automatically generated using types std_logic and -- std_logic_vector for the ports of the unit under test. Xilinx recommends -- that these types always be used for the top-level I/O of a design in order -- to guarantee that the testbench will bind correctly to the post-implementation -- simulation model. -------------------------------------------------------------------------------LIBRARY ieee; USE ieee.std_logic_1164.ALL; -- Uncomment the following library declaration if using -- arithmetic functions with Signed or Unsigned values --USE ieee.numeric_std.ALL; ENTITY flip_tb IS END flip_tb; ARCHITECTURE behavior OF flip_tb IS -- Component Declaration for the Unit Under Test (UUT) COMPONENT flip PORT( Ck : IN bit; Clr : IN bit; x : IN bit; Qa : OUT bit; Qb : OUT bit; px : OUT bit ); END COMPONENT;

--Inputs signal Ck : bit := '0'; signal Clr : bit := '0'; signal x : bit := '0'; --Outputs signal Qa : bit;

signal Qb : bit; signal px : bit; -- No clocks detected in port list. Replace <clock> below with -- appropriate port name

BEGIN -- Instantiate the Unit Under Test (UUT) uut: flip PORT MAP ( Ck => Ck, Clr => Clr, x => x, Qa => Qa, Qb => Qb, px => px ); ck <= '0', '0' after 10 ns, '1' after 20 ns, '1' after 30 ns, '0' after 40 ns, '0' after 50 ns, '1' after 60 ns, '1' after 70 ns, '0' after 80 ns, '0' after 90 ns, '1' after 100 ns, '1' after 110 ns; clr <= '0', '0' after 10 ns, '0' after 20 ns,'0' after 30 ns, '0' after 40 ns, '1' after 50 ns, '1' after 100 ns; x <= '0', '1' after 10 ns, '1' after 20 ns,'0' after 30 ns, '0' after 40 ns, '0' after 50 ns, '0' after 60 ns, '1' after 70 ns, '1' after 80 ns,'1' after 90 ns, '1' after 100 ns, '1' after 110 ns;

END;

Compuerta -- Company: -- Engineer: --- Create Date: 22:40:22 06/13/2011 -- Design Name: -- Module Name: flip - Behavioral -- Project Name: -- Target Devices: -- Tool versions: -- Description: --- Dependencies: --- Revision: -- Revision 0.01 - File Created -- Additional Comments: ----------------------------------------------------------------------------------library IEEE; use IEEE.STD_LOGIC_1164.ALL; -- Uncomment the following library declaration if using -- arithmetic functions with Signed or Unsigned values --use IEEE.NUMERIC_STD.ALL; -- Uncomment the following library declaration if instantiating -- any Xilinx primitives in this code. --library UNISIM; --use UNISIM.VComponents.all; entity flip is Port ( a, b: in std_logic; s : out std_logic); end flip; architecture Behavioral of flip is

BEGIN D <= a xor b; end Behavioral;