2010-LDPC Final Patent

A Novel Architecture for Low Density Parity Check
Decoder for the WiMAX
Authors:
Harihara Subramanyam.G, Dr.M.Girish Chandra, Venkataratnam .N, Ravindra.P,

Pramod.D.N, Balamuralidhar.P, Dr B.S.Adiga.
Wireless Research Group, Centre of Excellence, Embedded systems Practice,
TATA Consultancy Services, Plot No: 96, EPIP Industrial Area, White field
Bangalore-560066, India.
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TABLE OF CONTENTS
1. Introduction ........................................................................................................................................3
2. Summary of Invention .......................................................................................................................4
3. Claims ..................................................................................................................................................4
4. Detailed Description of Invention......................................................................................................5
4.1 Standardized LDPC code................................................................................................................5
4.2 Decoder Hardware Mapping...........................................................................................................7
4.2.1Motivation ................................................................................................................................7
4.2.2Processing Elements .................................................................................................................9
4.3 Decoder Architecture......................................................................................................................9
4.4 The Sum-Product and Min Sum Algorithm..................................................................................11
4.5 Simulation Results and Discussion...............................................................................................13
4.6 Implementation of Min-Sum Algorithm on the Proposed Architecture .......................................20
5. Appendix ...........................................................................................................................................23
List of Figures
Figure 1: Decoder architecture depicting the required blocks………………………………………….5

Figure 2: BER Vs EbNo for n= [2304 1440 576] and r=1/2…………………………………………...13
Figure 3: BER Vs EbNo for n= [2304 1440 576] and r=2/3A…………………………………………14
Figure 4: BER Vs EbNo for n= [2304 1440 576] and r=2/3B…………………………………………14
Figure 5: BER Vs EbNo for n= [2304 1440 576] and r=3/4A…………………………………………15
Figure 6: BER Vs EbNo for n= [2304 1440 576] and r=3/4B…………………………………………15
Figure 7: FER Vs EbNo for n= [2304 1440 576] and r=1/2…………………………………………...16
Figure 8: FER Vs EbNo for n= [2304 1440 576] and r=2/3A…………………………………………16
Figure 9: FER Vs EbNo for n= [2304 1440 576] and r=2/3B…………………………………………17
Figure 10: FER Vs EbNo for n= [2304 1440 576] and r=3/4A………………………………………..17
Figure 11: FER Vs EbNo for n= [2304 1440 576] and r=3/4B………………………………………..18
Figure 12: BER Vs EbNo for n= [2304 1440 576] and r=1/2……………………………………….....18
Figure 13: BER Vs EbNo for n= [2304] and r=1/2& r=2/3A………………………………………….19
Figure 14: FER Vs EbNo for n= [2304 1440 576] and r=1/2………………………………………….19
Figure 15: FER Vs EbNo for n= [2304] and r=1/2 & 2/3A……………………………………………20
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1. Introduction
This literature intends to make the claims which are novel in the aspect of the architectural design of a
reconfigurable LDPC (Low Density Parity Check) decoder (code being either regular or carefully
constructed irregular codes). The implementation of this decoder is however focused on the Worldwide
Interoperability for Microwave Access (WiMAX) standard [4], which uses LDPC codes as optional.
The proposal also reveals the details of implementation of the Min-Sum decoding algorithm ([2], [6],
[7]) on the decoder architecture.
WiMAX has become synonymous with the IEEE 802.16 standard family, an emerging
standard for fixed and mobile MAN (Metropolitan Area Network) Broadband Wireless Access (BWA).
The original 802.16 and the subsequently amended 802.16a standards are both used for fixed BWA.
The latter caters for non-line of sight (NLOS) applications, as BWA is increasingly becoming a
residential application. The latest 802.16e amendment is supporting for mobility (mobility at vehicular
speeds, around 120 km/h) in WiMAX system. The 802.16e standard will allow users’ hardware
(notebooks, personal digital assistants (PDAs)) to access high speed Internet, and while roaming outside
of the WiFi (Wireless Fidelity) hotspots. The 802.16 standard supports high data rates (up to about 70
Mbps) with a variety of channel coding options. The mandatory scheme is a convolutional code (later
also concatenated with a Reed-Solomon code). Convolutional turbo codes, turbo product codes, and, in
802.16e, LDPC codes are optional. These optional codes can be used to ensure robustness in extreme
fading channels.
LDPC codes are linear block codes originally proposed by Gallager in the early 1960s [1].
Their parity check matrix is sparse having low density of one (1) entries. The original codes were
regular codes (having uniform column and row weight in the parity check matrix). Recently, these
codes have emerged as competitors for turbo codes, with capacity approaching performance. Carefully
constructed long irregular (number of 1’s in each row or column is not constant) LDPC codes approach
the Shannon capacity by a fraction of a decibel (dB). Similar to turbo codes, the good performance of
LDPC codes is achieved with a proper choice of code and decoding signal processing. The popular
LDPC decoding algorithm is the Belief Propagation algorithm (also referred to as Sum-Product
algorithm). This can be viewed as a message passing algorithm operating on the Tanner graph, which is
a bipartite graph representing the parity check matrix, and consisting of variable nodes and check (or
constraint) nodes. The algorithm starts with initialization, in each iteration message passing occurs
from each check node to all adjacent variable nodes (first half of iteration) and then in the second half,
from each variable node to its adjacent check nodes. The decoding performance is achieved through
repeated iterations of the message passing along the edges of the graph, with some stopping criterion
([6], [7], [2]).
The popularity of LDPC codes from the past couple of years led into the proposals for utilizing
the code for various applications and standards (both for wireless and wired). Also, vigorous research
and efforts are put into VLSI/ASIC/FPGA realizations of the decoders and encoders ([6], [7], [3], [5]).
Concentrating on the decoders, one can see the proposals of different structures on various platforms.
There are different issues to be considered in the realization like, serial, parallel or semi-parallel
architectures, edge memory requirement, processing unit complexity (for check node processing), and
so on ([6], [7], [3], [5]).
Apart from the implementation of regular Sum-Product algorithm, various approximate versions
are proposed in the direction of reducing the check node computations and/or edge memory
requirement ([6], [7], [2], [3]). One popular algorithm in this direction is the Min-Sum algorithm,
including its compensated version ([6], [7], [2], [3]).
2. Summary of Invention
The architecture proposed in the Fig.1 can be utilized for both the regular LDPC codes and carefully
constructed irregular codes with a cyclic repetition. The structure consists of check node computation
units (CCU), variable node computation units (VCU), and associated memory banks, all of them being
worked out methodically.
3. Claims
A vigorous and vast research in the field of coding theory with a prime focus on the vastly acclaimed
LDPC codes which are predicted to be used in emerging communication systems in the coming years
lead us to these claims which are to our best knowledge not yet explored and acclaimed.
The focus here would be to merely stipulate the claims. An explanation of them with the relevant
justification would be provided in the subsequent sections.
• Claim 1: Both the regular LDPC codes and carefully constructed irregular codes with a cyclic
repetition can be easily implemented in hardware structure of Fig.1, which is semi-parallel.
The structure consists of CCUs, VCUs, and associated memory banks, all of them being
worked out methodically (as remarked earlier). The structure proposed would, to our best
knowledge would be an efficient architecture in addressing the reconfigurability required for
different rates and /or different frame lengths. The latter is commonly seen in many emerging
standards including WiMAX.
• Claim 2: Apropos to claim 1, the bank selector and the location pointer (which specify the
location inside the selected bank) are worked out based on the novel mathematical expression
which utilizes the cyclic factor or the repetition factor of the code. The said mechanisms are
necessary to achieve the Tanner graph connectivity over which the message passing takes
place during the decoding.
• Claim 3: Apropos to claim1 and claim2, a complete decoder architecture is worked out
considering the compensated version of Min Sum algorithm. The way of executing this
algorithm in the proposed decoder architecture is novel to the best of our knowledge.
4. Detailed Description of Invention
The section is divided into three parts. The first part would present a mention about the standardized
LDPC code (for WiMAX). The second part would highlight the details of the architecture proposed by
us and the final part talks about the message passing algorithm and its mode of implementation on the
proposed architecture.
Figure.1 Decoder architecture depicting the required blocks
4.1 Standardized LDPC code

The LDPC code proposed in the Standard [4] has excellent performance, and contains features that
provide flexibility and low encoding/decoding complexity. The structure of parity check matrix, which
determines the connections between different processing nodes in the decoder according to the Tanner
graph, has a major role in the performance of the decoder. As in many cases, the code and hence parity
check matrix is designed to facilitate the decoder design. Based on the study carried out and also our
experience with DVB-S2 code [2],[3],[5], it can be inferred that WiMAX uses a class of LDPC codes
called extended irregular repeat accumulate (eIRA) codes. These codes facilitate systematic encoding
and are especially suitable for high code rates. With irregular codes improved performance is possible,
since variable nodes with higher degrees (degree is number of adjacent nodes) collect more information
from their adjacent check nodes and they get corrected first after a small number of iterations. They
then help other variable nodes to get corrected through iterative decoding, similar to “wave effect”.
When all variable nodes have the same degrees, as in regular codes, this wave effect is not present and
all variable nodes can get stuck during the decoding process. Further, encoding can be carried out using
the parity check matrix with linear complexity (not the generator matrix, which being dense results in
quadratic encoding complexity); the encoding can be done recursively or parallely.
For eIRA codes, it is well known that the parity check matrix H can be written down in the form
[10], [11], [3].
H = [H 1 H2 ] (1)
where, H1 is a sparse ( N − K ) × K matrix with N is the block length and K is the number of
message bits (length of information block); ( N − K ) = M is the number of parity bits added. The H2
portion has a simple deterministic structure (stair-case lower triangular) and accounts for the accumulation
operation or differential encoding or accumulation:
1 O
1 1 
  (2)
H2 =  1 1 
 
 O 
O 1 1 
For proposed WiMAX codes, there is a slight deviation from Eqn.1 in the final H matrix, due to the way
the latter is constructed from what are called as base matrices. The base matrices facilitate compact
representation as well as introduction of additional structure for decoder implementation. The first step in
the compact representation is to utilize a binary base matrix H b of size M b × N b , where M b and N b
are related to M and N by what is referred to as z factor by M = zM b and N = zN b . The z factor,
which is an integer ≥ 1 is an important parameter for reconfigurability of the decoder for different rates
and block lengths (as we will see). There are four rates 1/2, 2/3, 3/4, 5/6 proposed as well as 19 different
frame lengths (from 576 to 2304). For each of the rates, N b is chosen as 24. Thus, z can be obtained as
N
z= (3)
24
For example, for N = 2304 , z = 96 . The expansion of H b to H is by simply replacing the entry 1 in
H b by a z × z permutation matrix and the entry 0 by a z × z zero matrix. The permutation value, which
corresponds to right circular shift of the identity matrix is noted separately. Obviously, the binary base
matrix information and permutation replacement information can be combined, resulting in a single
compact model matrix H bm . For the model matrix, each 0 of H b is replaced by -1 and each 1 of H b is
replaced by a circular shift value, p (i, j ) . Each sub matrix in H obtained through the replacement by a
z × z matrix can be represented as Pp ( i , j ) . The value p (i, j ) = 0 corresponds to the replacement by an
identity matrix.
Before listing the base matrices, it is worthwhile to consider H b in some more detail. This
binary base matrix can be partitioned as
H b = H b1[ H b2 ] (4)
where, H b1 of dimension M b × K b (with K = zK b ) corresponds to systematic bits and H b2 of
dimension M b × M b corresponds to the parity-check bits. H b2 can be further partitioned as
H b2 = hb [ H b′2 ] (5)
where H b2 has dual diagonal structure and hb has odd weight. That is,
 hb 0 1 O
 h 
 b1 1 1 
H b2 =  . 1 1  (6)
 
 . 1 O 1
hb( M −1) O 1 
 b
The base matrix has hb 0 = 1 , hb ( M b −1) = 1 and a third value hbj = 1 ( 0 < j < ( M b − 1) ). This
structure avoids multiple weight-1 columns in the expanded matrix, which may deteriorate the
performance, particularly with the short block length codes of WiMAX.
The down selected code provides for 19 different frame lengths (from 576 to 2304) and 4
different code rates (1/2, 2/3, 3/4, 5/6), as already mentioned. The parity check matrices are compactly
represented using a base matrix for each of the rates. Different frame lengths are obtained by replacing
entries of the base matrix by a power of the permutation matrix (the size of it and power can be
calculated by the equations provided in the Standard proposal). The details of the code are available in
[4] and further are neatly summarized in [13].
4.2 Decoder Hardware Mapping

As in our paper [5] (see [3] also), the decoder hardware mapping issues are logically presented in the
following under the headings, Motivation, Processing Elements and Hardware Mapping.
4.2.1Motivation
Based on our previous experience with DVB-S2 decoder and since WiMAX codes also possess “most”
of the eIRA structure, as detailed in Section 4.1, the structure obtained for WiMAX codes is a
modification of our DVB-S2 architecture [5], [3]. As mentioned in these references the architecture
follows the philosophy of [8]; see also [12]. But, our structure is worked out in such a way that there is
no address clash in the semi-parallel architecture of Fig.1. The entries for bank selector and location
pointer are obtained through general mathematical expressions (see Section 4.3). Additionally, the
structure we are suggesting for the emerging WiMAX standard is a refined version of those for DVB-
S2 and as far as we are aware, it is novel. Further, the structure is rather general as remarked earlier.
The main challenge in the LDPC code decoder hardware implementation is how to effectively
manage the message passing during the iterative belief propagation (BP) decoding (see [5] and the
references there in). Decoder implementation fall into three categories: (1) Parallel (2) Serial and (3)
Semi Parallel.
Fully parallel decoders directly instantiate the bipartite graph of the LDPC code to the
hardware. Each individual variable node or check node is physically implemented as node functional
unit, and all the units are connected through an interconnection network reflecting the bipartite graph
connectivity. There is no need for central memory blocks to store the messages. They can be latched
close to the processing units. Such fully parallel decoders can achieve very high decoding throughput
in terms of bits per second. But, area of implementation (due to the implementation of all the processing
units) and interconnect routing make this approach infeasible for large block lengths (more than couple
of thousands of bits). Further, the parallel hardware design is fixed to a particular parity check matrix.
This prohibits the reconfigurability required when the block length or rate of the code changes (both
changes the parity check matrix).
Fully-serial architecture has the smallest area since it is sufficient to have just one VCU and
one CCU. The fully-serial approach is suitable for DSPs in which there are only a few functional units
available to use. However, the speed of decoding is very low in a serial decoder.
Partially parallel or semi-parallel decoder targets on appropriate trade-offs between hardware
complexity and decoding speed. They consist of an array of node computation units to perform all the
node computation (in time-division multiplexing mode) and an array of memory blocks to store all
decoding message. The message passing that reflects the bipartite graph connectivity is jointly realized
by the memory address generation and the interconnection among memory blocks and node
computation units. They can support flexible code rate configurations and degree distributions.
Based on the arguments provided above, we are going to consider a semi-parallel architecture
for the decoder.
For the decoder mapping issue, a good starting point is to view the Tanner graph as a
collection of variable nodes on one side and check nodes on the other side. Edge interleaver or
permutation network realizes the connection between the nodes. A further enhancement is possible
when the eIRA nature of the codes is considered; the resulting structure is as in Fig1 of [8]. As
suggested in [8], for the eIRA codes variable nodes can be grouped into three categories, depending on
the three degree values; degree2, degree 3 and degree j, where j depends upon the rate. For rate 1/2 and
block length 2304, j is 6. Being an irregular LDPC code, the optimal check node degree of an eIRA
code can be proved to be proved to be concentrated on one or two degrees [10, pp.53]. For example,
again for rate 1/2 and block length 2304, out of 1152 check nodes, we have 768 nodes with degree 6
and 384 nodes with degree 7. Similar degree distribution is found for different rates and thus the codes
are optimal in terms of degree distribution for the check nodes.
Now, we come to the slight deviation of WiMAX codes from the conventional eIRA structure.
In the latter codes, the variable nodes with degree 2 would be M = N − K and they would form a
zigzag pattern. The zig-zag pattern was considered separately in our DVB-S2 architecture, referred to
as PN (parity nodes) portion. That is, for rate 1/2 and block length 2304, for a strict eIRA code, the
number of node with degree 2 would be exactly half of the total variable nodes that would be 1152. But,
from the study carried out it is observed it is only 1056 there is a decrease of 96 ( z value for 2304; see
Section 4.1). This arises due to the structure H 2 of the expanded matrix. Since the first column of the
parity-check portion of base matrix is forced to be different, as suggested in Eqn.6 and Section 3, when
replaced with 96 × 96 matrices, the zig-zag portion and hence degree-2 variable nodes reduces by 96.
In general, this reduction in number of nodes in the PN portion varies with the block length and equals
the z factor.
In our DVB-S2 architecture, the decoder architecture was partitioned into IN (information
nodes) and PN portions [5] (see [3] also). For WiMAX codes on the other hand, we have not
partitioned the architecture, which also seems logical based on the deviation of the WiMAX codes from
the strict eIRA structure (as mentioned above). In other words, the PN portion is also included in the
single structure (and hence single permutation network) as shown in the Fig.1.
Further, as in our earlier work on DVB-S2, the WiMAX codes are studied in detail to exploit
the structural properties to arrive at the proper decoder architecture.
4.2.2Processing Elements
The node computational units can be serially (one input and at most one output in a clock cycle) or
parallely implemented. In serial processing all incoming edges is used in our design as it relaxes the
constraints on the memory organization [6]. Further serial computational units can be pipelined and
hence they are not in critical path [8]. Additionally, the sequential processing is advantageous when it is
required to handle different degrees .The structure of the processing elements is described in more
detail in [3]. A good number of issues in the implementation of VCU and CCU in general can be found
in [6] (pp.46-50).
4.3 Decoder Architecture

As mentioned earlier, Fig.1 depicts the architecture; the decoder shown is for rate 1/2 and frame length
2304. As in [5] (see [3] also), it is required to work out the choice of number of processing elements
and hence the number of memory banks, as well as the connection mechanism between these to achieve
Tanner graph, for the WiMAX code.
The design is based on the cyclic behaviour of the codes. A slight modification with respect to the
number of memory banks and number of addresses stored in each bank would be required during the
reconfigurability issue being addressed; reconfigurability for different lengths and different rates.
Similar to the DVB-S2 architecture, we use the bank selector and location pointer registers to instantiate
the Tanner graph connectivity. Even though the discussion revolves around, block length 2304 and rate
half code in the following, in Appendix 1, the requisite location pointer and bank selector entries for the
frame lengths 576, 1440 and 2304 (lowest, intermediate and maximum in the Standard) for rates 1/2,
2/3 and 3/4, are listed.
By the extensive and detailed study carried out, it is found that the addresses of the neighbors
of a check node as well as those of a variable node are related to the rate-dependent z factor (see
Appendix 1). For both the variable nodes and the check nodes similar pattern is observed. For
N = 2304 and rate 1/2, from the standard, this factor is 96. A set of z nodes starting from 0th node till
z − 1 node there would be general increment of one in the corresponding node connected, i.e. if we
look from check node to the variable nodes connectivity, for every set of z check nodes, the address
values of the variable nodes generally gets incremented by one. As far as the variable nodes portion,
similarly for every z variable nodes the address of check nodes gets incremented by one. For example,
for rate 1/2, the for the first set of 96 check nodes from 0th node till 95th node, the variable node
addresses for 1st node are one incremented values of that of the 0th node. The word “generally”
mentioned twice accounts for the wrap around which takes place when the address is a multiple of z.
For example, while incrementing, if the address obtained is 96, it becomes zero, if the address is 192, it
becomes 96 and so on. That is, there is a decrement of 96. Based on this observation, it is decided to
use 96 elements each for VN (variable node) and CN (check node) processing in the serial-parallel
architecture, with a connection mechanism to take care of the wrap around problem. This connection
mechanism is depicted in Fig.1.
In Fig.1, the entries shown in the memory banks are the addresses of variable nodes and check
nodes. The 96 processing units work in parallel and fetch the inputs one-by-one based on the entries
given in the bank selector, which selects the bank and the location pointer, which suggests the location
within the selected bank. The number of addresses in the banks is rate dependent (hence on z). Fig.1
shows the addresses for rate 1/2 and block length 2304; hence there are 2304 variable nodes and 1152
check nodes. The number of entries in the location-pointer register and the bank selector apart from
rate dependent vary during the iterative procedure. The entries shown are for the first 96 check-node
processing operations; the check nodes in this set are 0, 1, 2, …, 95 (see Fig.1). For the next 96 (96, 97,
…, 191), different entries need to be loaded into these registers. To elaborate the iterative procedure
further, assume that the entire frame of 2304 received values is scaled ([4],[3],[2]) to get appropriate
LLRs and are stored in banks as suggested by addresses in Fig.1. The check-node units can then start
processing. They get either six or seven values sequentially. For example, the six values for check
node 0 are taken from first location of ninety fourth bank, second location of seventy third bank etc. 96
check node units can get the values this way. Once the processing is completed, they generate the same
number of outputs as inputs and these are put into the memory banks in the CN portion in the respective
addresses. The processing for the next 96 check nodes can then be taken up by loading different
relevant entries into the bank selector and location pointer. The inputs of the bank selector and the
locations pointer can be obtained from the novel mathematical expressions we have identified (for the
architecture of Fig.1). For each group of 96 check nodes the location pointer can be obtained from
LPC =
[I − mod(I , z )] (7)
z
Where I is the address of the variable node connected to a particular parity check node. The entries can
be worked out by picking any parity-check node in the group. With this the zeroth bank for any
processing unit is the exactly opposite bank in Fig.1 and the remaining are counted downwards in
circular fashion. Further, in (7) mod (I , z ) gives the bank selector value. All the different register
entries required for different rates are provided in Appendix 1.
Once all the check-node processing is completed, the variable node processing can be started again 96
at a time, fetching the values from the CN memory banks. The novel expression for location pointer
values is:
LPV =
[C − mod (C , z )] (8)
z
where C is the check-node address and again mod(C, z ) is the bank selector value. This completes
the decoder architecture design and in implementation a controller is required to make sure that all the
units are synchronized.
4.4 The Sum-Product and Min Sum Algorithm
The Sum-Product algorithm is now well understood and very neat interpretations of the mechanism of
algorithm operation are now available. The algorithm uses log-likelihood ratios (LLRs), that is, the
values handled are LLRs. The steps involved are given in the following for sign-magnitude processing
form:
Initialization: Tn(,0m) = I n ; E n(0,m) = 0

Iteration:
For iteration counter l = 1, 2, Ll max , do the following updates

Check node update rule
 
E n(l,m) = ∏ sgn (T ( ) ) × Φ ∑ Φ( T ( ) )
l −1
n′ , m
l −1
n′ , m (9)
n′∈Ν ( m ) \ n  n′∈Ν ( m ) \ n 
Variable node update rule: Tn(,lm) = I n + ∑E

m′∈Μ ( n ) \ m
(l )
n , m′ (10)
Last variable node update rule: Tn(l ) = I n + ∑ E( )

m∈Μ ( n )
l
n , m′ (11)
In the above, Tn ,m is the information sent by a variable node n to its connected check node m; E n , m is
the message passed from check node m to the connected variable node n (information given by the
parity check m on bit n); Μ (n ) is the set of check nodes connected to variable node n; Ν ( m ) is the
  x 
set of variable nodes connected to check node m; Φ( x) = − log tanh   with x > 0 . I n is the
  2 
channel LLR value and can be obtained depending on the channel (Additive White Gaussian Noise
(l )
(AWGN), binary symmetric, etc). “\” is the usual exclusion symbol. indicates the iteration number
with l max being the number of iterations. It can be observed that check node computation is more
complex. The nonlinear function Φ(x) is implemented using the look-up table (LUT).
One popular modification of the regular Sum-Product algorithm is the Min-Sum algorithm,
which is based on the fact that the summation in Eqn.(9) (that is, ∑ Φ( x) ) is dominated by the
x
smallest extrinsic information (due to the shape of Φ (x) , see [3]). In Min-Sum, only the magnitude
part of the check node update rule differs, which is captured below:
Check node update rule: E n(l,m) = ∏ sgn(T ( ) ) ×

n′∈Ν ( m ) \ n
l −1
n′ , m min Tn(′l,m−1)
n′∈Ν ( m ) \ n
(12)
Following remarks about Min-Sum algorithm are useful: (a) Check node update is replaced by a
selection of the minimum input value. (b) No more LLR are to be computed. (c) Only two magnitudes
need to be saved for each parity check equation. (d) No need to estimate the noise variance to compute
the intrinsic information (see next section). The simplicity of Min-Sum is associated with a
performance penalty in terms of bit error rate. It is known that the performance penalty is due to over
estimation of extrinsic information (compared to the regular Sum-Product and hence compensation in
terms of subtraction (offset) or multiplication (normalized) is suggested in the literature. Based on the
extensive simulation studies carried out by us, we found that a factor of 0.75 multiplication of the
variable node outputs result in performance of the (compensated) min-sum algorithm close to that of the
regular sum-product algorithm. This factor can be simply implemented in the VCUs by multiplying the
output by 0.5 and 0.25 (both are shift operations) and adding the results to get the compensated values.
An algorithm in between Regular Sum-Product and Min-Sum algorithms for check node
processing is the λ − Min algorithm [6], which takes into account the λ input values which have the
minimum magnitude. Here, instead of two values as in the case of Min-Sum, λ + 1 magnitudes need to be
saved. A detailed discussion of the algorithm is available in Chapter 4 of [6]. But, the computation
involves nonlinear function Φ(x) and hence LUT. Another algorithm worth considering is the A − Min * ,
where the check node update rule is approximated for all the incoming messages except for the one with
the smallest magnitude for which there is no approximation. See [3], for details regarding different
variations of the regular BP algorithm. Similar to Min-Sum algorithm, A − Min * computes only two
outgoing magnitudes at each check node, but instead of minimum value as default, LLR of all the variables
is the default value [14]. The computation here also requires Φ(x) if it is implemented in the form given in
[6]. In [14], the algorithm is formulated for recursive computation using the alternate non-linear function
−x *
log (1 + e ) (and corresponding LUT). It is demonstrated in [14] that the A − Min algorithm suffers little
or no performance loss and compared to Min-Sum, it is essentially “self tuning”.
In the next section, we present few simulation results.
4.5 Simulation Results and Discussion
The simulation study has been carried out for frame lengths 576, 1440, and 2304 (lowest, intermediate and
maximum in the standard) as well as for rates ½, ⅔ and ¾.Some typical simulation results showing both the
bit error rate (BER) and frame error rate (FER) are plotted against E b / N 0 for AWGN case, the results are
for all-zero code word. The results confirm the known facts-performance improves as the frame length
increases for a given rate and for a given length performance improves with the decrease in rate. For
λ − Min algorithm the value of λ is chosen as 3. It is observed that both the λ − Min and
A − Min * algorithms perform close to the regular sum-product algorithm, but with more complexity than
Min-Sum. The Min-Sum algorithm has some performance penalty of about 0.5 dB. If we use the
compensation factor of 0.75, as mentioned earlier, the performance of Min-Sum algorithm can be brought
closer to the regular BP algorithm (see Fig.12,13,14,15). Similar results are observed with randomly
generated codewords.
Figure 2: BER Vs EbNo for n= [2304 1440 576] and r=1/2
Figure 3: BER Vs EbNo for n= [2304 1440 576] and r=2/3A
Figure 4: BER Vs EbNo for n= [2304 1440 576] and r=2/3B
Figure 5: BER Vs EbNo for n= [2304 1440 576] and r=3/4A
Figure 6: BER Vs EbNo for n= [2304 1440 576] and r=3/4B
Figure 7: FER Vs EbNo for n= [2304 1440 576] and r=1/2
Figure 8: FER Vs EbNo for n= [2304 1440 576] and r=2/3A
Figure 9: FER Vs EbNo for n= [2304 1440 576] and r=2/3B
Figure 10: FER Vs EbNo for n= [2304 1440 576] and r=3/4A
Figure 11: FER Vs EbNo for n= [2304 1440 576] and r=3/4B.
Figure 12: BER Vs EbNo for n= [2304 1440 576] and r=1/2.
Figure 13: BER Vs EbNo for n= [2304] and r=1/2& r=2/3A
Figure 14: FER Vs EbNo for n= [2304 1440 576] and r=1/2.
Figure 15: FER Vs EbNo for n= [2304] and r=1/2 & 2/3A
4.6 Implementation of Min-Sum Algorithm on the Proposed Architecture
The architecture of Fig.1 is a conceptual block and there is a necessity to work out finer details depending
on the algorithm chosen. The two algorithms Sum-Product and Min-Sum are outlined in the previous
section. See [2], [3] and [12] for some other popular decoding algorithms. Based on the simplicity of the
Min-Sum algorithm (which avoids LUT as well as reduce the edge memory requirement) and since with
compensation the performance in terms of bit error rate (BER) and frame error rate (FER) can be made on
par with that of the regular Sum-Product algorithm, we have chosen to implement Min-Sum algorithm
within the framework of Fig.1.
The received channel LLR values are stored in the memory banks of VN portion of Fig.1. In
fact, each of the memory location on the VN side holds two values: one the already mentioned channel
LLR and another value Tn (see Eqn.11), which to start with is the channel LLR value itself. The
check-node processing is then started. It is to be noted that we have chosen sequential processing
elements in the semi-parallel architecture of Fig.1. The sequential processing elements fetch one value
(channel LLR) at a time (clock cycle) performs computation and store the results on the CN side
memory banks. With no address clash, all the CCUs fetch their input values and perform computation
on them parallely. As mentioned earlier, the values picked from the VN side memory banks are
governed by the bank selector and location pointer values. The Eqn.12 represents the computation to be
performed by check node processor, which in our implementation translates into determining the first
minimum (min1) and second minimum (min2) of the absolute (without considering signs) input values,
storing the address of the first minimum (min1addr), storing the product of the signs of all its input
values, storing the individual signs of its input values. Each memory location in the CN side holds all
these mentioned values. The values (min1, min2) in the actual implementation are fixed point values,
say with 16-bit precision. When all the check-node computations are completed, that is, for the case of
Fig.1, when the 96 CCUs work 12 times, first half iteration is completed.
Then the variable node processing starts. VCU fetches values from CN banks one at a time (clock
cycle) and adds those values with the intrinsic information and stores the result which is required for the
updation of check nodes in next iteration. The value fetched from the check node will be +min1 or –min1
or +min2 or –min2. Firstly, VCU fetches min1addr that is stored in one of the six memory locations of
check node. Min1addr is compared with the address of variable node that is under updation and if it
matches, it fetches min2. Otherwise, it fetches min1. The sign of min1 or min2 is obtained by multiplying
the overall sign with its own sign. The same operation is done by all the processors parallelly on their own
data, received at their inputs. The fetching locations are again governed by the location pointer and bank
selector as in the case of check-node processing, but the entries are different. After repetition of the
operation for 24 times on 96 processors the updation of all variable nodes will be completed (for the case of
Fig.1). This completes the first iteration and the VN side memory locations hold the computed Tn values
as well as I n .
In the next iteration, CCUs fetch the requisite Tn values and compute the necessary Tn ,m values
using the relationship
Tn(,lm) = Tn(l ) − E n(l,m) (13)
The E n ,m values computed utilizing the values available in the CN memory locations. Elaborating further,
the CCU fetches Tn from the connected variable node address. Then it compares min1addr with the
variable node address from which it has fetched Tn . If the addresses are matched, min2 is used for
computation, otherwise min1. The sign of min1 or min2 is evaluated from the individual signs as well as
the overall product of all the signs. The relevant individual sign is picked using a counter logic, elaborated
in [13]. With these extrinsic messages, the CCUs complete processing as in the first iteration. Then VCUs
complete the processing, ending the second iteration. The iterations are continued for a certain maximum
number and finally the sign bit of Tn values can be examined to make thresholded decisions of +1 or -1.
The switching or permutation network of Fig.1 can be implemented using the logarithmic
barrel shifter. The barrel shifter would act as a switching network which would establish the connectivity
between the memory banks and the processing elements. Once the connection between the first bank is
established, the other banks are connected is by a simple shifting operation. The number of stages in the
shifter is given by the logarithm to the basis 2 of number of parallel banks beings used.
References:
[1].R. G. Gallager, “Low Density Parity Check Codes” , PhD dissertation,MIT, 1963 .
[2]. M. Girish Chandra, Harihara S.G, B.S. Adiga, Balamuralidhar. P, P.S. Subramanian, “Effect of Check
Node Processing on the Performance of Message Passing Algorithm in the Context of LDPC Decoding for
DVB-S2”, ICICS 2005, Dec.2005 (Accepted).
[3]. M. Girish Chandra, Harihara S.G, B.S. Adiga, Balamuralidhar. P, P.S. Subramanian, “LDPC Decoder
Design for DVB-S2”, TCS Technical Report, July 2005.
[4]. IEEE 802.16 related material from http://ieee802.16.org/16
• http://www.ieee802.org/16/tge/contrib/C80216e-05_066r3.pdf
• http://www.ieee802.org/16/tge/contrib/C80216e-05_126.pdf
[5].Harihara S.G, M. Girish Chandra, B.S. Adiga, Pramod D.N, Balamuralidhar. P, “A Proposal for the
LDPC Decoder Architecture for DVB-S2”, NCC 2006, Jan 2006.(Accepted)
[6]. F. Guilloud, “Generic Architecture for LDPC Codes Decoding”, PhD Thesis under SPRING project,
July 2004.
[7]. M. Karkooti, J.R. Cavallaro, “Semi-Parallel Reconfigurable Architectures for Real-Time LDPC
Decoding”, ITCC 2004.
[8]. F. Kienle, N. When, “Design Methodology for IRA Codes, Proceedings of ASP-DAC’04, 2004.
[9]. H. Zhong, T. Zhang, “Design of VLSI Implementation-Oriented LDPC Codes”, IEEE Semiannual
Vehicular Technology Conference (VTC), Oct. 2003.
[10]. M. Ardakani, “Efficient Analysis, Design and Decoding of Low-Density Parity-Check Codes”, PhD
Thesis, 2004.
[11]. Frank Kienle, Torben Brack, Norbert Wehn. "A Synthesizable IP Core for DVB-S2 LDPC Code
Decoding," date, pp. 100-105, Design, Automation and Test in Europe (DATE'05) Volume 3, 2005.
[12]. M. Girish Chandra, Harihara S.G, Ravindra..P, Balamuralidhar. P. “Performance Of Some Popular
Decoding Algorithms In The Context of LDPC Codes For WiMAX” , TCS Global Technical Architects
Conference, Dec 2005.
[13]. M. Girish Chandra, Harihara S.G, Ravindra..P, Venkataratnam.N, Balamuaralidhar.P, “LDPC
Decoder Design for WiMAX”, TCS Technical Report, Nov 2005.
[14]. C. E. Jones, M. Valles, M. Smith, and J. Villasenor, “Approximate Min* Constraint Node Updating
for LDPC Code Decoding”, IEEE MILCOM Conference, Oct. 2003.
5. Appendix
Check node addresses for rate=1/2 and n=576
47 66 205 236 289 312

30 125 163 170 267 312 336
78 101 140 176 264 336 360
15 59 208 222 360 384
57 165 226 258 384 408
107 130 188 283 288 408 432
71 85 219 244 432 456
26 66 144 227 456 480
3 116 126 178 276 480 504
143 182 257 282 504 528
49 88 201 228 528 552
10 136 178 270 289 552
Corresponding memory bank addresses
23 18 13 20 1 0
6 5 19 2 3 0 0
6 5 20 8 0 0 0
15 11 16 6 0 0
9 21 10 18 0 0
11 10 20 19 0 0 0
23 13 3 4 0 0
2 18 0 11 0 0
3 20 6 10 12 0 0
23 14 17 18 0 0
1 16 9 12 0 0
10 16 10 6 1 0
Corresponding addresses for location pointer
1 2 8 9 12 13
1 5 6 7 11 13 14
3 4 5 7 11 14 15
0 2 8 9 15 16
2 6 9 10 16 17
4 5 7 11 12 17 18
2 3 9 10 18 19
1 2 6 9 19 20
0 4 5 7 11 20 21
5 7 10 11 21 22
2 3 8 9 22 23
0 5 7 11 12 23
Variable Node Addresses For N=576 and R=1/2
81 213 278
1 42 190
6 85 111 145 174 263
66 155 248
67 133 196
43 52 134 210 217 272
29 99 168
46 64 124 206 226 278
11 80 255
4 90 110 165 181 252
102 164 223
45 48 125 204 222 282
23 120 287
0 24
24 48
48 72
72 96
96 120
120 144
144 168
168 192
192 216
216 240
240 264
Corresponding Memory Bank Entries

0 0
9 21 14
1 18 22
6 13 15 1 6 23
18 11 8
19 13 4
19 4 14 18 1 8
5 3 0
22 16 4 14 10 14
11 8 15
4 18 14 21 13 12
6 20 7
21 0 5 12 6 18
23 0 23
0 0
0 0
0 0
0 0
0 0
0 0
0 0
0 0
0 0
0 0
The corresponding location pointer addresses.
3 8 11
0 1 7
0 3 4 6 7 10
2 6 10
2 5 8
1 2 5 8 9 11
1 4 7
1 2 5 8 9 11
0 3 10
0 3 4 6 7 10
4 6 9
1 2 5 8 9 11
0 5 11
0 1
1 2
2 3
3 4
4 5
5 6
6 7
7 8
8 9
9 10
10 11
Check node addresses for r=2/3A and n=576
3 24 98 120 171 199 241 265 385 408

49 108 178 202 282 290 339 360 408 432
60 74 135 184 219 279 314 349 432 456
67 72 123 144 198 257 344 375 456 480
20 54 130 149 220 278 326 384 480 504
58 100 140 200 252 297 357 381 504 528
11 25 85 141 197 264 316 356 528 552
30 54 148 206 222 267 300 350 385 552
Corresponding memory back addresses
3 0 2 0 3 7 1 1 1 0
1 12 10 10 18 2 3 0 0 0
12 2 15 16 3 15 2 13 0 0
19 0 3 0 6 17 8 15 0 0
20 6 10 5 4 14 14 0 0 0
10 4 20 8 12 9 21 21 0 0
11 1 13 21 5 0 4 20 0 0
6 6 4 14 6 3 12 14 1 0
Corresponding location pointer addresses.
0 1 4 5 7 8 10 11 16 17
2 4 7 8 11 12 14 15 17 18
2 3 5 7 9 11 13 14 18 19
2 3 5 6 8 10 14 15 19 20
0 2 5 6 9 11 13 16 20 21
2 4 5 8 10 12 14 15 21 22
0 1 3 5 8 11 13 14 22 23
1 2 6 8 9 11 12 14 16 23
Variable node addresses for n=576 and rate=2/3A
21 100 157
0 167 186
47 60 77 114 134 186
70 72 155
22 36 140
0 57 93 110 124 147
72 115 188
21 38 56
17 38 90 136 163 178
69 116 186
23 79 132
23 30 57 106 144 189
46 135 180
70 106 164
45 59 88 123 148 178
24 81 123
23 96 191
0 24
24 48
48 72
72 96
96 120
120 144
144 168
21 4 13
0 23 18
23 12 5 18 14 18
22 0 11
22 12 20
0 9 21 14 4 3
0 19 20
21 14 8
17 14 18 16 19 10
21 20 18
23 7 12
23 6 9 10 0 21
22 15 12
22 10 20
21 11 16 3 4 10
0 9 3
23 0 23
0 0
0 0
0 0
0 0
0 0
0 0
0 0
Corresponding location pointer addresses
0 4 6
0 6 7
1 2 3 4 5 7
2 3 6
0 1 5
0 2 3 4 5 6
3 4 7
0 1 2
0 1 3 5 6 7
2 4 7
0 3 5
0 1 2 4 6 7
1 5 7
2 4 6
1 2 3 5 6 7
1 3 5
0 4 7
0 1
1 2
2 3
3 4
4 5
5 6
6 7
Check node addresses for n=576 and rate=2/3B
0 52 107 156 201 260 299 339 407 408

41 94 128 168 220 273 322 372 408 432
2 69 111 151 213 244 296 354 432 456
31 80 140 174 238 265 326 369 456 480
5 55 99 151 208 246 300 351 480 504
31 88 133 171 216 271 330 360 504 528
8 48 99 158 213 241 289 349 384 528 552
24 83 123 183 237 277 331 370 407 552
0 4 11 12 9 20 11 3 23 0
17 22 8 0 4 9 10 12 0 0
2 21 15 7 21 4 8 18 0 0
7 8 20 6 22 1 14 9 0 0
5 7 3 7 16 6 12 15 0 0
7 16 13 3 0 7 18 0 0 0
8 0 3 14 21 1 1 13 0 0 0
0 11 3 15 21 13 19 10 23 0
0 2 4 6 8 10 12 14 16 17
1 3 5 7 9 11 13 15 17 18
0 2 4 6 8 10 12 14 18 19
1 3 5 7 9 11 13 15 19 20
0 2 4 6 8 10 12 14 20 21
1 3 5 7 9 11 13 15 21 22
0 2 4 6 8 10 12 14 16 22 23
1 3 5 7 9 11 13 15 16 23
Variable node addresses for n=576 and rate=2/3B
0 70 115 160
31 89 137 168
20 51 113 144
26 88 128 181
13 57 117 165
40 76 131 189
12 65 113 154
24 90 141 177
15 51 104 147
44 74 120 171
4 68 114 167
39 95 137 179
13 64 108 167
38 82 126 173
21 54 105 155
36 87 120 182
1 144 169
0 24
24 48
48 72
72 96
96 120
120 144
144 168
0 22 19 16
7 17 17 0
20 3 17 0
2 16 8 13
13 9 21 21
16 4 11 21
12 17 17 10
0 18 21 9
15 3 8 3
20 2 0 3
4 20 18 23
15 23 17 11
13 16 12 23
14 10 6 5
21 6 9 11
12 15 0 14
1 0 1
0 0
0 0
0 0
0 0
0 0
0 0
0 0
0 2 4 6
1 3 5 7
0 2 4 6
1 3 5 7
0 2 4 6
1 3 5 7
0 2 4 6
1 3 5 7
0 2 4 6
1 3 5 7
0 2 4 6
1 3 5 7
0 2 4 6
1 3 5 7
0 2 4 6
1 3 5 7
0 6 7
0 1
1 2
2 3
3 4
4 5
5 6
6 7
Check node addresses for n=576 and rate=3/4A
1 33 48 95 175 209 261 297 321 337 362 419 444 456
15 47 52 93 143 163 195 287 323 342 368 391 456 480
17 61 99 136 155 187 235 290 341 373 401 428 480 504
9 39 88 98 138 155 184 225 255 274 407 416 432 504 528
104 133 157 188 215 221 241 276 294 334 347 365 528 552
39 55 94 101 193 226 254 268 305 325 390 414 444 552
Corresponding addresses for bank selector
1 9 0 23 7 17 21 9 9 1 2 11 12 0
15 23 4 21 23 19 3 23 11 6 8 7 0 0
17 13 3 16 11 19 19 2 5 13 17 20 0 0
9 15 16 2 18 11 16 9 15 10 23 8 0 0 0
8 13 13 20 23 5 1 12 6 22 11 5 0 0
15 7 22 5 1 10 14 4 17 13 6 6 12 0
0 1 2 3 7 8 10 12 13 14 15 17 18 19
0 1 2 3 5 6 8 11 13 14 15 16 19 20
0 2 4 5 6 7 9 12 14 15 16 17 20 21
0 1 3 4 5 6 7 9 10 11 16 17 18 21 22
4 5 6 7 8 9 10 11 12 13 14 15 22 23
1 2 3 4 8 9 10 11 12 13 16 17 18 23
23 33 55 87
15 25 81 129
0 44 59 137
1 27 80 122
69 94 112 139
25 56 78 107
29 61 85 107
17 53 80 100
7 45 97 143
53 87 115 134
3 81 119 130
25 86 108 140
15 70 114 127
15 37 98 131
23 42 67 109
22 40 59 115
41 55 73 138
13 52 88 138
12 72 132
0 24
24 48
48 72
72 96
96 120
23 9 7 15
15 1 9 9
0 20 11 17
1 3 8 2
21 22 16 19
1 8 6 11
5 13 13 11
17 5 8 4
7 21 1 23
5 15 19 14
3 9 23 10
1 14 12 20
15 22 18 7
15 13 2 11
23 18 19 13
22 16 11 19
17 7 1 18
13 4 16 18
12 0 12
0 0
0 0
0 0
0 0
0 0
0 1 2 3
0 1 3 5
0 1 2 5
0 1 3 5
2 3 4 5
1 2 3 4
1 2 3 4
0 2 3 4
0 1 4 5
2 3 4 5
0 3 4 5
1 3 4 5
0 2 4 5
0 1 4 5
0 1 2 4
0 1 2 4
1 2 3 5
0 2 3 5
0 3 5
0 1
1 2
2 3
3 4
4 5
44 79 147 174 196 285 295 325 355 383 389 431 432 456
10 51 89 104 233 250 266 297 322 344 374 393 414 456 480
53 135 153 209 232 273 289 330 347 367 399 409 452 480 504
16 24 111 168 204 260 267 311 314 357 369 387 412 504 528
37 63 92 126 162 285 307 312 336 378 399 414 528 552
19 99 127 176 234 247 281 309 333 342 376 386 430 432 552
Corresponding bank selector addresses
20 7 3 6 4 21 7 13 19 23 5 23 0 0
10 3 17 8 17 10 2 9 10 8 14 9 6 0 0
5 15 9 17 16 9 1 18 11 7 15 1 20 0 0
16 0 15 0 12 20 3 23 2 21 9 3 4 0 0
13 15 20 6 18 21 19 0 0 18 15 6 0 0
19 3 7 8 18 7 17 21 21 6 16 2 22 0 0
1 3 6 7 8 11 12 13 14 15 16 17 18 19
0 2 3 4 9 10 11 12 13 14 15 16 17 19 20
2 5 6 8 9 11 12 13 14 15 16 17 18 20 21
0 1 4 7 8 10 11 12 13 14 15 16 17 21 22
1 2 3 5 6 11 12 13 14 15 16 17 22 23
0 4 5 7 9 10 11 12 13 14 15 16 17 18 23
38 80 125
4 72 107
45 67 105
17 31 100
40 81 141
57 114 137
21 63 102
18 72 136
20 55 84
31 56 126
38 76 137
3 46 63 93 99 127
17 39 71 73 101 123
11 38 54 94 96 123
5 40 61 75 96 138
1 34 65 87 102 128
19 39 57 93 105 142
1 42 71 92 114 122
0 52 120
0 24
24 48
48 72
72 96
96 120
14 8 5
4 0 11
21 19 9
17 7 4
16 9 21
9 18 17
21 15 6
18 0 16
20 7 12
7 8 6
14 4 17
3 22 15 21 3 7
17 15 23 1 5 3
11 14 6 22 0 3
5 16 13 3 0 18
1 10 17 15 6 8
19 15 9 21 9 22
1 18 23 20 18 2
0 4 0
0 0
0 0
0 0
0 0
0 0
Corresponding address for location pointer
1 3 5
0 3 4
1 2 4
0 1 4
1 3 5
2 4 5
0 2 4
0 3 5
0 2 3
1 2 5
1 3 5
0 1 2 3 4 5
0 1 2 3 4 5
0 1 2 3 4 5
0 1 2 3 4 5
0 1 2 3 4 5
0 1 2 3 4 5
0 1 2 3 4 5
0 2 5
0 1
1 2
2 3
3 4
4 5
Addresses for n=1440 and rate=1/2
118 165 514 591 724 780

76 313 409 425 667 780 840
195 253 350 440 660 840 900
38 149 520 555 900 960
144 412 565 645 960 1020
268 325 471 709 720 1020 1080
179 213 548 611 1080 1140
66 165 361 569 1140 1200
7 291 315 446 691 1200 1260
358 456 643 705 1260 1320
124 220 504 570 1320 1380
26 341 445 676 724 1380
Addresses of the memory bank
58 45 34 51 4 0
16 13 49 5 7 0 0
15 13 50 20 0 0 0
38 29 40 15 0 0
24 52 25 45 0 0
28 25 51 49 0 0 0
59 33 8 11 0 0
6 45 1 29 0 0
7 51 15 26 31 0 0
58 36 43 45 0 0
4 40 24 30 0 0
26 41 25 16 4 0
Addresses for the location pointer
1 2 8 9 12 13
1 5 6 7 11 13 14
3 4 5 7 11 14 15
0 2 8 9 15 16
2 6 9 10 16 17
4 5 7 11 12 17 18
2 3 9 10 18 19
1 2 6 9 19 20
0 4 5 7 11 20 21
5 7 10 11 21 22
2 3 8 9 22 23
0 5 7 11 12 23
202 533 694

2 104 474
15 211 276 361 435 656
165 387 620
167 332 489
107 130 335 525 542 679
71 248 479
115 160 309 514 564 695
26 200 636
9 225 275 412 451 630
255 409 557
113 120 311 509 555 704
56 300 716
0 60
60 120
120 180
180 240
240 300
300 360
360 420
420 480
480 540
540 600
600 660
Addresses for memory bank
22 53 34
2 44 54
15 31 36 1 15 56
45 27 20
47 32 9
47 10 35 45 2 19
11 8 59
55 40 9 34 24 35
26 20 36
9 45 35 52 31 30
15 49 17
53 0 11 29 15 44
56 0 56
0 0
0 0
0 0
0 0
0 0
0 0
0 0
0 0
0 0
0 0
0 0
Addresses for the location pointer
3 8 11
0 1 7
0 3 4 6 7 10
2 6 10
2 5 8
1 2 5 8 9 11
1 4 7
1 2 5 8 9 11
0 3 10
0 3 4 6 7 10
4 6 9
1 2 5 8 9 11
0 5 11
0 1
1 2
2 3
3 4
4 5
5 6
6 7
7 8
8 9
9 10
10 11
3 60 242 300 423 487 601 661 961 1020

121 276 454 490 678 722 843 900 1020 1080
132 182 315 460 543 675 782 853 1080 1140
139 204 303 360 486 617 848 939 1140 1200
20 126 310 389 568 674 818 960 1200 1260
130 268 320 488 636 729 861 945 1260 1320
35 85 217 321 485 660 784 860 1320 1380
66 126 364 494 570 663 756 854 961 1380
3 0 2 0 3 7 1 1 1 0
1 36 34 10 18 2 3 0 0 0
19 24 3 0 6 17 8 39 0 0
20 6 10 29 28 14 38 0 0 0
10 28 20 8 36 9 21 45 0 0
35 25 37 21 5 0 4 20 0 0
6 6 4 14 30 3 36 14 1 0
0 1 4 5 7 8 10 11 16 17
2 4 7 8 11 12 14 15 17 18
2 3 5 6 8 10 14 15 19 20
0 2 5 6 9 11 13 16 20 21
2 4 5 8 10 12 14 15 21 22
0 1 3 5 8 11 13 14 22 23
1 2 6 8 9 11 12 14 16 23
Variable node addresses for n=1440 and rate =2/3 A
57 280 385
0 395 474
119 168 221 294 350 474
178 216 383
58 84 332
0 165 237 290 340 399
180 271 476
57 86 140
53 110 234 352 415 466
177 272 450
59 223 324
59 102 165 286 360 477
118 351 444
178 262 416
117 167 232 339 400 466
60 201 315
59 240 479
0 60
60 120
120 180
180 240
240 300
300 360
360 420
Corresponding addresses for memory bank
57 40 25
0 35 54
59 48 41 54 50 54
58 36 23
58 24 32
0 45 57 50 40 39
0 31 56
57 26 20
53 50 54 52 55 46
57 32 30
59 43 24
59 42 45 46 0 57
58 51 24
58 22 56
57 47 52 39 40 46
0 21 15
59 0 59
0 0
0 0
0 0
0 0
0 0
0 0
0 0
0 4 6
0 6 7
1 2 3 4 5 7
2 3 6
0 1 5
0 2 3 4 5 6
3 4 7
0 1 2
0 1 3 5 6 7
2 4 7
0 3 5
0 1 2 4 6 7
1 5 7
2 4 6
1 2 3 5 6 7
1 3 5
0 4 7
0 1
1 2
2 3
3 4
4 5
5 6
6 7
1 131 269 390 502 651 749 849 1019 1020

103 235 320 421 550 683 805 930 1020 1080
6 173 278 377 533 610 741 885 1080 1140
77 200 350 436 595 663 815 923 1140 1200
14 138 249 378 521 615 751 878 1200 1260
78 220 333 428 540 678 826 900 1260 1320
20 120 249 395 533 603 723 872 960 1320 1380
60 209 308 458 592 694 828 925 1019 1380
Corresponding addresses for memory bank selector
1 11 29 30 22 51 29 9 59 0
43 55 20 1 10 23 25 30 0 0
6 53 38 17 53 10 21 45 0 0
17 20 50 16 55 3 35 23 0 0
14 18 9 18 41 15 31 38 0 0
18 40 33 8 0 18 46 0 0 0
20 0 9 35 53 3 3 32 0 0 0
0 29 8 38 52 34 48 25 59 0
0 2 4 6 8 10 12 14 16 17
1 3 5 7 9 11 13 15 17 18
0 2 4 6 8 10 12 14 18 19
1 3 5 7 9 11 13 15 19 20
0 2 4 6 8 10 12 14 20 21
1 3 5 7 9 11 13 15 21 22
0 2 4 6 8 10 12 14 16 22 23
1 3 5 7 9 11 13 15 16 23
59 174 286 400

77 223 342 420
49 127 282 360
65 220 320 451
31 142 291 411
100 190 327 472
30 163 282 385
119 224 352 442
38 127 259 367
110 185 300 428
9 170 285 417
97 237 342 446
31 159 269 417
95 205 314 432
51 135 262 388
90 217 300 455
1 360 421
0 60
60 120
120 180
180 240
240 300
300 360
360 420
59 54 46 40
17 43 42 0
49 7 42 0
5 40 20 31
31 22 51 51
40 10 27 52
30 43 42 25
59 44 52 22
38 7 19 7
50 5 0 8
9 50 45 57
37 57 42 26
31 39 29 57
35 25 14 12
51 15 22 28
30 37 0 35
1 0 1
0 0
0 0
0 0
0 0
0 0
0 0
0 0
0 2 4 6
1 3 5 7
0 2 4 6
1 3 5 7
0 2 4 6
1 3 5 7
0 2 4 6
1 3 5 7
0 2 4 6
1 3 5 7
0 2 4 6
1 3 5 7
0 2 4 6
1 3 5 7
0 2 4 6
1 3 5 7
0 6 7
0 1
1 2
2 3
3 4
4 5
5 6
6 7
Check node addresses for n=1440 and rate =3/4A
3 83 121 238 438 523 653 743 803 842 906 1048 1110 1140
38 118 131 232 357 408 489 717 808 855 920 978 1140 1200
44 154 247 341 388 469 588 726 853 934 1003 1071 1200 1260
23 98 221 245 345 389 460 564 638 686 1019 1040 1080 1260 1320
260 332 394 470 539 553 603 691 735 836 867 912 1320 1380
99 139 235 252 483 565 635 670 764 813 976 1036 1110 1380
3 23 1 58 18 43 53 23 23 2 6 28 30 0
38 58 11 52 57 48 9 57 28 15 20 18 0 0
44 34 7 41 28 49 48 6 13 34 43 51 0 0
23 38 41 5 45 29 40 24 38 26 59 20 0 0 0
20 32 34 50 59 13 3 31 15 56 27 12 0 0
39 19 55 12 3 25 35 10 44 33 16 16 30 0
0 1 2 3 7 8 10 12 13 14 15 17 18 19
0 1 2 3 5 6 8 11 13 14 15 16 19 20
0 2 4 5 6 7 9 12 14 15 16 17 20 21
0 1 3 4 5 6 7 9 10 11 16 17 18 21 22
4 5 6 7 8 9 10 11 12 13 14 15 22 23
1 2 3 4 8 9 10 11 12 13 16 17 18 23
57 82 136 217
37 62 202 321
59 109 146 341
2 68 199 305
173 235 280 348
63 139 195 268
72 152 211 266
42 131 200 250
17 111 241 357
132 216 287 335
7 202 297 325
63 214 269 350
37 174 285 316
37 92 244 327
58 105 167 273
54 100 146 288
102 137 181 344
32 129 220 344
30 180 330
0 60
60 120
120 180
180 240
240 300
57 22 16 37
37 2 22 21
59 49 26 41
2 8 19 5
53 55 40 48
3 19 15 28
12 32 31 26
42 11 20 10
17 51 1 57
12 36 47 35
7 22 57 25
3 34 29 50
37 54 45 16
37 32 4 27
58 45 47 33
54 40 26 48
42 17 1 44
32 9 40 44
30 0 30
0 0
0 0
0 0
0 0
0 0
0 1 2 3
0 1 3 5
0 1 2 5
0 1 3 5
2 3 4 5
1 2 3 4
1 2 3 4
0 2 3 4
0 1 4 5
2 3 4 5
0 3 4 5
1 3 4 5
0 2 4 5
0 1 4 5
0 1 2 4
0 1 2 4
1 2 3 5
0 2 3 5
0 3 5
0 1
1 2
2 3
3 4
4 5
110 197 368 435 490 713 738 812 888 959 973 1077 1080 1140
26 128 222 260 583 626 666 742 805 860 935 983 1035 1140 1200
132 339 384 523 581 683 722 825 869 918 997 1023 1130 1200 1260
40 61 279 421 511 650 669 778 785 893 922 968 1031 1260 1320
93 157 230 316 406 713 768 780 841 945 997 1035 1320 1380
48 249 317 441 585 618 702 773 832 856 940 966 1075 1080 1380
50 17 8 15 10 53 18 32 48 59 13 57 0 0
26 8 42 20 43 26 6 22 25 20 35 23 15 0 0
12 39 24 43 41 23 2 45 29 18 37 3 50 0 0
40 1 39 1 31 50 9 58 5 53 22 8 11 0 0
33 37 50 16 46 53 48 0 1 45 37 15 0 0
48 9 17 21 45 18 42 53 52 16 40 6 55 0 0
1 3 6 7 8 11 12 13 14 15 16 17 18 19
0 2 3 4 9 10 11 12 13 14 15 16 17 19 20
2 5 6 8 9 11 12 13 14 15 16 17 18 20 21
0 1 4 7 8 10 11 12 13 14 15 16 17 21 22
1 2 3 5 6 11 12 13 14 15 16 17 22 23
0 4 5 7 9 10 11 12 13 14 15 16 17 18 23
94 200 312
10 239 267
112 168 263
43 78 250
100 201 351
141 284 343
52 156 254
45 239 339
50 137 209
77 139 315
94 190 342
7 114 157 231 247 318
42 98 178 182 252 307
28 95 135 235 240 308
12 100 151 187 299 344
1 85 162 218 255 320
47 97 143 232 263 354
3 105 177 229 285 305
0 130 300
0 60
60 120
120 180
180 240
240 300
Corresponding address for bank selector

34 20 12
10 59 27
52 48 23
43 18 10
40 21 51
21 44 43
52 36 14
45 59 39
50 17 29
17 19 15
34 10 42
7 54 37 51 7 18
42 38 58 2 12 7
28 35 15 55 0 8
12 40 31 7 59 44
1 25 42 38 15 20
47 37 23 52 23 54
3 45 57 49 45 5
0 10 0
0 0
0 0
0 0
0 0
0 0
1 3 5
0 3 4
1 2 4
0 1 4
1 3 5
2 4 5
0 2 4
0 3 5
0 2 3
1 2 5
1 3 5
0 1 2 3 4 5
0 1 2 3 4 5
0 1 2 3 4 5
0 1 2 3 4 5
0 1 2 3 4 5
0 1 2 3 4 5
0 1 2 3 4 5
0 2 5
0 1
1 2
2 3
3 4
4 5
190 265 823 947 1159 1248

123 502 655 681 1068 1248 1344
312 406 561 705 1056 1344 1440
61 239 833 889 1440 1536
231 660 905 1032 1536 1632
430 520 754 1135 1152 1632 1728
287 341 878 978 1728 1824
107 265 578 911 1824 1920
12 467 504 715 1107 1920 2016
574 731 1030 1128 2016 2112
199 353 807 913 2112 2208
43 546 713 1082 1159 2208
94 73 55 83 7 0
27 22 79 9 12 0 0
24 22 81 33 0 0 0
61 47 65 25 0 0
39 84 41 72 0 0
46 40 82 79 0 0 0
95 53 14 18 0 0
11 73 2 47 0 0
12 83 24 43 51 0 0
94 59 70 72 0 0
7 65 39 49 0 0
43 66 41 26 7 0
1 2 8 9 12 13
1 5 6 7 11 13 14
3 4 5 7 11 14 15
0 2 8 9 15 16
2 6 9 10 16 17
4 5 7 11 12 17 18
2 3 9 10 18 19
1 2 6 9 19 20
0 4 5 7 11 20 21
5 7 10 11 21 22
2 3 8 9 22 23
0 5 7 11 12 23
323 852 1109

2 165 757
23 337 441 577 695 1049
264 619 991
266 530 781
170 207 536 840 866 1086
113 396 766
183 255 494 821 901 1111
41 319 1017
13 359 439 658 721 1007
408 654 890
180 192 497 813 888 1126
89 480 1145
0 96
96 192
192 288
288 384
384 480
480 576
576 672
672 768
768 864
864 960
960 1056
Corresponding Addresses for memory bank
35 84 53
2 69 85
23 49 57 1 23 89
72 43 31
74 50 13
74 15 56 72 2 30
17 12 94
87 63 14 53 37 55
41 31 57
13 71 55 82 49 47
24 78 26
84 0 17 45 24 70
89 0 89
0 0
0 0
0 0
0 0
0 0
0 0
0 0
0 0
0 0
0 0
0 0
3 8 11
0 1 7
0 3 4 6 7 10
2 6 10
2 5 8
1 2 5 8 9 11
1 4 7
1 2 5 8 9 11
0 3 10
0 3 4 6 7 10
4 6 9
1 2 5 8 9 11
0 5 11
0 1
1 2
2 3
3 4
4 5
5 6
6 7
7 8
8 9
9 10
10 11
3 96 386 480 675 775 961 1057 1537 1632

193 420 706 778 1074 1154 1347 1440 1632 1728
204 290 495 712 867 1071 1250 1357 1728 1824
211 312 483 576 774 977 1352 1479 1824 1920
20 198 490 605 892 1070 1286 1536 1920 2016
202 412 500 776 996 1161 1365 1485 2016 2112
35 121 325 501 773 1056 1252 1364 2112 2208
102 198 580 782 894 1059 1188 1358 1537 2208
3 0 2 0 3 7 1 1 1 0
1 36 34 10 18 2 3 0 0 0
12 2 15 40 3 15 2 13 0 0
19 24 3 0 6 17 8 39 0 0
20 6 10 29 28 14 38 0 0 0
10 28 20 8 36 9 21 45 0 0
35 25 37 21 5 0 4 20 0 0
6 6 4 14 30 3 36 14 1 0
0 1 4 5 7 8 10 11 16 17
2 4 7 8 11 12 14 15 17 18
2 3 5 7 9 11 13 14 18 19
2 3 5 6 8 10 14 15 19 20
0 2 5 6 9 11 13 16 20 21
2 4 5 8 10 12 14 15 21 22
0 1 3 5 8 11 13 14 22 23
1 2 6 8 9 11 12 14 16 23
Variable node addresses for n=2304 and rate =2/3A
93 460 637
0 647 762
191 276 365 474 566 762
286 360 635
94 156 548
0 273 381 470 556 651
288 451 764
93 158 248
89 182 378 568 667 754
285 452 738
95 367 540
95 174 273 466 576 765
190 567 732
286 442 668
189 275 376 555 652 754
96 345 531
95 384 767
0 96
96 192
192 288
288 384
384 480
480 576
576 672
93 76 61
0 71 90
95 84 77 90 86 90
94 72 59
94 60 68
0 81 93 86 76 75
0 67 92
93 62 56
89 86 90 88 91 82
93 68 66
95 79 60
95 78 81 82 0 93
94 87 60
94 58 92
93 83 88 75 76 82
0 57 51
95 0 95
0 0
0 0
0 0
0 0
0 0
0 0
0 0
0 4 6
0 6 7
1 2 3 4 5 7
2 3 6
0 1 5
0 2 3 4 5 6
3 4 7
0 1 2
0 1 3 5 6 7
2 4 7
0 3 5
0 1 2 4 6 7
1 5 7
2 4 6
1 2 3 5 6 7
1 3 5
0 4 7
0 1
1 2
2 3
3 4
4 5
5 6
6 7
2 211 431 624 804 1042 1199 1359 1631 1632

165 376 513 675 880 1093 1288 1488 1632 1728
10 278 446 604 853 976 1186 1417 1728 1824
124 320 561 699 952 1061 1304 1477 1824 1920
23 221 399 606 834 984 1202 1406 1920 2016
126 353 534 686 864 1086 1322 1440 2016 2112
32 192 399 632 853 965 1158 1396 1536 2112 2208
96 335 493 733 948 1111 1326 1481 1631 2208
2 19 47 48 36 82 47 15 95 0
69 88 33 3 16 37 40 48 0 0
10 86 62 28 85 16 34 73 0 0
28 32 81 27 88 5 56 37 0 0
23 29 15 30 66 24 50 62 0 0
30 65 54 14 0 30 74 0 0 0
32 0 15 56 85 5 6 52 0 0 0
0 47 13 61 84 55 78 41 95 0
0 2 4 6 8 10 12 14 16 17
1 3 5 7 9 11 13 15 17 18
0 2 4 6 8 10 12 14 18 19
1 3 5 7 9 11 13 15 19 20
0 2 4 6 8 10 12 14 20 21
1 3 5 7 9 11 13 15 21 22
0 2 4 6 8 10 12 14 16 22 23
1 3 5 7 9 11 13 15 16 23
94 278 457 640

123 356 546 672
77 202 451 576
104 352 511 721
49 226 465 657
159 303 522 755
48 260 450 616
189 357 562 707
60 203 414 587
176 296 480 684
14 272 456 667
155 379 546 713
49 254 430 666
152 328 502 690
81 215 418 620
144 347 480 727
1 576 673
0 96
96 192
192 288
288 384
384 480
480 576
576 672
94 86 73 64
27 68 66 0
77 10 67 0
8 64 31 49
49 34 81 81
63 15 42 83
48 68 66 40
93 69 82 35
60 11 30 11
80 8 0 12
14 80 72 91
59 91 66 41
49 62 46 90
56 40 22 18
81 23 34 44
48 59 0 55
1 0 1
0 0
0 0
0 0
0 0
0 0
0 0
0 0
0 2 4 6
1 3 5 7
0 2 4 6
1 3 5 7
0 2 4 6
1 3 5 7
0 2 4 6
1 3 5 7
0 2 4 6
1 3 5 7
0 2 4 6
1 3 5 7
0 2 4 6
1 3 5 7
0 2 4 6
1 3 5 7
0 6 7
0 1
1 2
2 3
3 4
4 5
5 6
6 7
6 134 195 381 702 838 1046 1189 1286 1348 1451 1678 1776 1824
62 190 211 372 572 654 783 1148 1293 1368 1472 1566 1824 1920
71 247 396 546 621 751 942 1162 1366 1495 1606 1714 1920 2016
38 157 354 393 553 623 736 903 1021 1099 1631 1664 1728 2016 2112
416 532 631 752 863 886 966 1107 1176 1338 1388 1460 2112 2208
159 223 376 404 774 904 1016 1072 1223 1301 1563 1658 1776 2208
6 38 3 93 30 70 86 37 38 4 11 46 48 0
62 94 19 84 92 78 15 92 45 24 32 30 0 0
71 55 12 66 45 79 78 10 22 55 70 82 0 0
38 61 66 9 73 47 64 39 61 43 95 32 0 0 0
32 52 55 80 95 22 6 51 24 90 44 20 0 0
63 31 88 20 6 40 56 16 71 53 27 26 48 0
0 1 2 3 7 8 10 12 13 14 15 17 18 19
0 1 2 3 5 6 8 11 13 14 15 16 19 20
0 2 4 5 6 7 9 12 14 15 16 17 20 21
0 1 3 4 5 6 7 9 10 11 16 17 18 21 22
4 5 6 7 8 9 10 11 12 13 14 15 22 23
1 2 3 4 8 9 10 11 12 13 16 17 18 23
90 130 217 346

58 98 323 513
93 173 233 545
3 108 318 488
276 375 448 556
100 222 311 428
114 243 337 425
66 209 320 400
26 177 385 570
210 345 458 536
10 323 474 520
100 341 429 560
59 278 456 505
58 147 390 523
92 168 266 436
85 160 233 460
162 218 289 549
50 206 352 550
48 288 528
0 96
96 192
192 288
288 384
384 480
90 34 25 58
58 2 35 33
93 77 41 65
3 12 30 8
84 87 64 76
4 30 23 44
18 51 49 41
66 17 32 16
26 81 1 90
18 57 74 56
10 35 90 40
4 53 45 80
59 86 72 25
58 51 6 43
92 72 74 52
85 64 41 76
66 26 1 69
50 14 64 70
48 0 48
0 0
0 0
0 0
0 0
0 0
0 1 2 3
0 1 3 5
0 1 2 5
0 1 3 5
2 3 4 5
1 2 3 4
1 2 3 4
0 2 3 4
0 1 4 5
2 3 4 5
0 3 4 5
1 3 4 5
0 2 4 5
0 1 4 5
0 1 2 4
0 1 2 4
1 2 3 5
0 2 3 5
0 3 5
0 1
1 2
2 3
3 4
4 5
177 316 590 697 785 1141 1181 1300 1422 1535 1558 1724 1728 1824
42 206 356 416 934 1003 1067 1188 1288 1377 1497 1574 1656 1824 1920
212 543 615 838 931 1094 1156 1320 1391 1469 1596 1637 1808 1920 2016
64 98 447 675 819 1041 1071 1246 1257 1429 1476 1550 1651 2016 2112
149 252 368 506 651 1142 1229 1249 1347 1512 1596 1657 2112 2208
77 399 508 707 936 990 1124 1237 1332 1370 1504 1547 1721 1728 2208

81 28 14 25 17 85 29 52 78 95 22 92 0 0
42 14 68 32 70 43 11 36 40 33 57 38 24 0 0
20 63 39 70 67 38 4 72 47 29 60 5 80 0 0
64 2 63 3 51 81 15 94 9 85 36 14 19 0 0
53 60 80 26 75 86 77 1 3 72 60 25 0 0
77 15 28 35 72 30 68 85 84 26 64 11 89 0 0
1 3 6 7 8 11 12 13 14 15 16 17 18 19
0 2 3 4 9 10 11 12 13 14 15 16 17 19 20
2 5 6 8 9 11 12 13 14 15 16 17 18 20 21
0 1 4 7 8 10 11 12 13 14 15 16 17 21 22
1 2 3 5 6 11 12 13 14 15 16 17 22 23
0 4 5 7 9 10 11 12 13 14 15 16 17 18 23
150 320 499
15 382 427
178 268 420
68 124 400
160 321 561
225 454 548
82 249 405
71 381 541
79 218 333
122 221 504
149 303 546
11 181 250 369 394 508
67 156 284 290 403 491
44 152 216 375 479 492
18 159 241 299 477 550
1 135 259 348 408 512
74 154 228 370 420 565
4 168 283 365 455 487
0 208 480
0 96
96 192
192 288
288 384
384 480
54 32 19
15 94 43
82 76 36
68 28 16
64 33 81
33 70 68
82 57 21
71 93 61
79 26 45
26 29 24
53 15 66
11 85 58 81 10 28
67 60 92 2 19 11
44 56 24 87 95 12
18 63 49 11 93 70
1 39 67 60 24 32
74 58 36 82 36 85
4 72 91 77 71 7
0 16 0
0 0
0 0
0 0
0 0
0 0
1 3 5
0 3 4
1 2 4
0 1 4
1 3 5
2 4 5
0 2 4
0 3 5
0 2 3
1 2 5
1 3 5
0 1 2 3 4 5
0 1 2 3 4 5
0 1 2 3 4 5
0 1 2 3 4 5
0 1 2 3 4 5
0 1 2 3 4 5
0 1 2 3 4 5
0 2 5
0 1
1 2
2 3
3 4
4 5
Table 1: LDPC Block sizes and Code rates:
K NUMBER OF SUB
N(bits) N(bytes) z factor BYTES CHANNELS
R=1/2 R=2/3 R=3/4 QPSK 16QAM 64QAM
576 72 24 36 48 54 6 3 2
672 84 28 42 56 63 7
768 96 32 48 64 72 8 4
864 108 36 54 72 81 9 3
960 120 40 60 78 90 10 5
1056 132 44 66 84 99 11
1152 144 48 72 96 108 12 6 4
1248 156 52 78 104 117 13
1344 168 56 84 112 126 14 7
1440 180 60 90 120 135 15 5
1536 192 64 96 128 144 16 8
1632 204 68 102 136 153 17
1728 216 72 108 144 162 18 9 6
1824 228 76 114 152 171 19
The base matrices for the three rates mentioned in the Table 1 are as follows (as can be seen there are two
different codes for rate 2/3 and 3/4):
Rate 1/2:
-1 94 73 -1 -1 -1 -1 -1 55 83 -1 -1 7 0 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
-1 27 -1 -1 -1 22 79 9 -1 -1 -1 12 -1 0 0 -1 -1 -1 -1 -1 -1 -1 -1 -1
-1 -1 -1 24 22 81 -1 33 -1 -1 -1 0 -1 -1 0 0 -1 -1 -1 -1 -1 -1 -1 -1
61 -1 47 -1 -1 -1 -1 -1 65 25 -1 -1 -1 -1 -1 0 0 -1 -1 -1 -1 -1 -1 -1
-1 -1 39 -1 -1 -1 84 -1 -1 41 72 -1 -1 -1 -1 -1 0 0 -1 -1 -1 -1 -1 -1
-1 -1 -1 -1 46 40 -1 82 -1 -1 -1 79 0 -1 -1 -1 -1 0 0 -1 -1 -1 -1 -1
-1 -1 95 53 -1 -1 -1 -1 -1 14 18 -1 -1 -1 -1 -1 -1 -1 0 0 -1 -1 -1 -1
-1 11 73 -1 -1 -1 2 -1 -1 47 -1 -1 -1 -1 -1 -1 -1 -1 -1 0 0 -1 -1 -1
12 -1 -1 -1 83 24 -1 43 -1 -1 -1 51 -1 -1 -1 -1 -1 -1 -1 -1 0 0 -1 -1
-1 -1 -1 -1 -1 94 -1 59 -1 -1 70 72 -1 -1 -1 -1 -1 -1 -1 -1 -1 0 0 -1
-1 -1 7 65 -1 -1 -1 -1 39 49 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0 0
43 -1 -1 -1 -1 66 -1 41 -1 -1 -1 26 7 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0
Rate 2/3 A code:

3 0 -1 -1 2 0 -1 3 7 -1 1 1 -1 -1 -1 -1 1 0 -1 -1 -1 -1 -1 -1
-1 -1 1 -1 36 -1 -1 34 10 -1 -1 18 2 -1 3 0 -1 0 0 -1 -1 -1 -1 -1
-1 -1 12 2 -1 15 -1 40 -1 3 -1 15 -1 2 13 -1 -1 -1 0 0 -1 -1 -1 -1
-1 -1 19 24 -1 3 0 -1 6 -1 17 -1 -1 -1 8 39 -1 -1 -1 0 0 -1 -1 -1
20 -1 6 -1 -1 10 29 -1 -1 28 -1 14 -1 38 -1 -1 0 -1 -1 -1 0 0 -1 -1
-1 -1 10 -1 28 20 -1 -1 8 -1 36 -1 9 -1 21 45 -1 -1 -1 -1 -1 0 0 -1
35 25 -1 37 -1 21 -1 -1 5 -1 -1 0 -1 4 20 -1 -1 -1 -1 -1 -1 -1 0 0
-1 6 6 -1 -1 -1 4 -1 14 30 -1 3 36 -1 14 -1 1 -1 -1 -1 -1 -1 -1 0
Rate 2/3 B code:

2 -1 19 -1 47 -1 48 -1 36 -1 82 -1 47 -1 15 -1 95 0 -1 -1 -1 -1 -1 -1
-1 69 -1 88 -1 33 -1 3 -1 16 -1 37 -1 40 -1 48 -1 0 0 -1 -1 -1 -1 -1
10 -1 86 -1 62 -1 28 -1 85 -1 16 -1 34 -1 73 -1 -1 -1 0 0 -1 -1 -1 -1
-1 28 -1 32 -1 81 -1 27 -1 88 -1 5 -1 56 -1 37 -1 -1 -1 0 0 -1 -1 -1
23 -1 29 -1 15 -1 30 -1 66 -1 24 -1 50 -1 62 -1 -1 -1 -1 -1 0 0 -1 -1
-1 30 -1 65 -1 54 -1 14 -1 0 -1 30 -1 74 -1 0 -1 -1 -1 -1 -1 0 0 -1
32 -1 0 -1 15 -1 56 -1 85 -1 5 -1 6 -1 52 -1 0 -1 -1 -1 -1 -1 0 0
-1 0 -1 47 -1 13 -1 61 -1 84 -1 55 -1 78 -1 41 95 -1 -1 -1 -1 -1 -1 0
Rate 3/4 A code:
6 38 3 93 -1 -1 -1 30 70 -1 86 -1 37 38 4 11 -1 46 48 0 -1 -1 -1 -1
62 94 19 84 -1 92 78 -1 15 -1 -1 92 -1 45 24 32 30 -1 -1 0 0 -1 -1 -1
71 -1 55 -1 12 66 45 79 -1 78 -1 -1 10 -1 22 55 70 82 -1 -1 0 0 -1 -1
38 61 -1 66 9 73 47 64 -1 39 61 43 -1 -1 -1 -1 95 32 0 -1 -1 0 0 -1
-1 -1 -1 -1 32 52 55 80 95 22 6 51 24 90 44 20 -1 -1 -1 -1 -1 -1 0 0
-1 63 31 88 20 -1 -1 -1 6 40 56 16 71 53 -1 -1 27 26 48 -1 -1 -1 -1 0
Rate 3/4 B code:

-1 81 -1 28 -1 -1 14 25 17 -1 -1 85 29 52 78 95 22 92 0 0 -1 -1 -1 -1
42 -1 14 68 32 -1 -1 -1 -1 70 43 11 36 40 33 57 38 24 -1 0 0 -1 -1 -1
-1 -1 20 -1 -1 63 39 -1 70 67 -1 38 4 72 47 29 60 5 80 -1 0 0 -1 -1
64 2 -1 -1 63 -1 -1 3 51 -1 81 15 94 9 85 36 14 19 -1 -1 -1 0 0 -1
-1 53 60 80 -1 26 75 -1 -1 -1 -1 86 77 1 3 72 60 25 -1 -1 -1 -1 0 0
77 -1 -1 -1 15 28 -1 35 -1 72 30 68 85 84 26 64 11 89 0 -1 -1 -1 -1 0

2010-LDPC Final Patent

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2010-LDPC Final Patent

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A Novel Architecture for Low Density Parity Check

Decoder for the WiMAX

Harihara Subramanyam.G, Dr.M.Girish Chandra, Venkataratnam .N, Ravindra.P,

Wireless Research Group, Centre of Excellence, Embedded systems Practice,

Figure 1: Decoder architecture depicting the required blocks………………………………………….5

Figure.1 Decoder architecture depicting the required blocks

4.1 Standardized LDPC code

where, H b1 of dimension M b × K b (with K = zK b ) corresponds to systematic bits and H b2 of

dimension M b × M b corresponds to the parity-check bits. H b2 can be further partitioned as

4.2 Decoder Hardware Mapping

4.3 Decoder Architecture

4.4 The Sum-Product and Min Sum Algorithm

Initialization: Tn(,0m) = I n ; E n(0,m) = 0

For iteration counter l = 1, 2, Ll max , do the following updates

Variable node update rule: Tn(,lm) = I n + ∑E

Last variable node update rule: Tn(l ) = I n + ∑ E( )

Check node update rule: E n(l,m) = ∏ sgn(T ( ) ) ×

Figure 2: BER Vs EbNo for n= [2304 1440 576] and r=1/2

Figure 4: BER Vs EbNo for n= [2304 1440 576] and r=2/3B

Figure 6: BER Vs EbNo for n= [2304 1440 576] and r=3/4B

Figure 8: FER Vs EbNo for n= [2304 1440 576] and r=2/3A

4.6 Implementation of Min-Sum Algorithm on the Proposed Architecture

using the relationship

Tn(,lm) = Tn(l ) − E n(l,m) (13)

Check node addresses for rate=1/2 and n=576

47 66 205 236 289 312

Corresponding memory bank addresses

Corresponding addresses for location pointer

Corresponding Memory Bank Entries

3 24 98 120 171 199 241 265 385 408

Corresponding memory back addresses

Corresponding location pointer addresses.

Corresponding memory bank addresses

0 52 107 156 201 260 299 339 407 408

Corresponding memory bank addresses

Corresponding location pointer addresses

Corresponding memory bank addresses

Corresponding addresses for bank selector

Corresponding addresses for location pointer

Corresponding addresses for bank selector

Corresponding bank selector addresses

Corresponding location pointer addresses

Corresponding addresses for bank selector

118 165 514 591 724 780

Addresses of the memory bank

Addresses for the location pointer

202 533 694

Addresses for memory bank

3 60 242 300 423 487 601 661 961 1020

Corresponding addresses for bank selector

Corresponding addresses for location pointer

Corresponding addresses for memory bank

1 131 269 390 502 651 749 849 1019 1020

Corresponding addresses for memory bank selector

Corresponding addresses for location pointer

59 174 286 400

Corresponding addresses for bank selector

Corresponding addresses for bank selector

Corresponding addresses for location pointer

Corresponding addresses for bank selector

Corresponding bank selector addresses

Corresponding location pointer addresses

Corresponding address for bank selector

190 265 823 947 1159 1248