DESIGN THE FOLLOWING USING 3:8 DECODER AND OTHER EXTERNAL GATES.

WRITE THE
MAIN MODULE IN STRUCTURAL LEVEL HDL AND THE SUB MODULE USING DATAFLOW HDL

F=M(1,2,3,4,7,8,10,12,14,15)
Code:

module Decoder1(A,B,C,D,d0,d1,d2,d3,d4,d5,d6,d7);

input A,B,C,D;

//A is taken as the enable pin

output d0,d1,d2,d3,d4,d5,d6,d7;

wire d0,d1,d2,d3,d4,d5,d6,d7;

assign d0=~(A&~B&~C&~D);

assign d1=~(A&~B&~C&D);

assign d2=~(A&~B&C&~D);

assign d3=~(A&~B&C&D);

assign d4=~(A&B&~C&~D);

assign d5=~(A&B&~C&D);

assign d6=~(A&B&C&~D);

assign d7=~(A&B&C&D);

endmodule

module Decoder2(A,B,C,D,d0,d1,d2,d3,d4,d5,d6,d7,d8,d9,d10,d11,d12,d13,d14,d15);

input A,B,C,D;

output d0,d1,d2,d3,d4,d5,d6,d7,d8,d9,d10,d11,d12,d13,d14,d15;

wire A,d0,d1,d2,d3,d4,d5,d6,d7,d8,d9,d10,d11,d12,d13,d14,d15;

Decoder1 X(~A,B,C,D,d0,d1,d2,d3,d4,d5,d6,d7);

Decoder1 Y(A,B,C,D,d8,d9,d10,d11,d12,d13,d14,d15);

and gate(F,d1,d2,d3,d4,d7,d8,d10,d12,d14,d15);

endmodule
Output wave form: