MICROCHIP PIC16F84A 18-pin Enhanced FLASH/EEPROM 8-Bit Microcontroller High Performance RISC CPU Features: + Only 35 single word instructions to learn + All instructions single-cycle except for program branches which are two-cycle + Operating speed: DC - 20 MHz clock input DC 200 ns instruction cycle + 1024 words of program memory + 68 bytes of Data RAM + 64 bytes of Data EEPROM, + 1A-bitwide instruction words + B-bit wide data bytes + 16 Special Function Hardware registers. + Eight-level deep hardware stack + Direet, indirect and relative addressing modes + Four interrupt sources: = External RBOIINT pin = TMRO timer overflow = PORTB<7:4> interupt-on-change ~ Data EEPROM write complete Peripheral Features: + 13.10 pins with individual direction control + High current sink’source for direct LED drive = 25 mA sink max. per pin = 25 mA source max. per pin + TMRO: 8-bit timer/counter with 8-bit programmable prescaler Special Microcontroller Features: + 10,000 eraselwrite cycles Enhanced FLASH Program memory typical + 10,000,000 typical erase/urite cycles EEPROM Data memory typical + EEPROM Data Retention > 40 years, + In-Circuit Serial Programming™ (|CSP™) - via two pins + Power-on Reset (POR), Power-up Timer (PWRT), Oscillator Start-up Timer (OST) + Watchdog Timer (WDT) with its own On-Chip RC Oseillator for reliable operation + Code protection + Power saving SLEEP mode + Selectable oscilator options Diagrams PDIP, SOIC. a pa (et 1eb=— na rag (]2 w+ Rao raarocn (3p oscncuxn wer—-4 15f)—~ oscacixour vss 3 4D -—veo reont=—(}@ @ afl-~ ner rov-+7 5B i2hl+=nee rez} D+ es nea] iof=> rat ssoP a ra ()e1 Rat naa =f = R90 rauocn =] ta] —oscucuen wor—-4 9 7—oscacixour vss 8 wos g roont——j7 5 rei==Le nea —(fo pes + 10 CMOS Enhanced FLASH/EEPROM. Technology: + Low power, high speed technology + Fully static design + Wide operating voltage range = Commercial: 2.0V to 5 5V Industria: 2.0 to 5.5V + Low power consumption: = <2mA typical @ 5, 4 MHz ~ 18 uA typical @ 2V, 32 kHz ~ <0 wA typical standby current @ 2V 1© 2001-2013 Microchip Technology Inc. 3s007C-page 1PIC16F84A Table of Contents 1.0 Device Overview 3 20 Memory Organization 5 3.0. Data EEPROM Memory 3 40° WO Pons 16 50° TimerO Module 9 6.0 Special Features of the CPU. 2 7.0 _Insttucton Set Summary 35 8.0 Development Suppor. 8 9.0 Electrical Characteristics a7 300 DCIAC Characterste Graphe 5 41.0. Packaging Information 6 ‘Appendix A: Revision History 7 ‘Appenix B: Conversion Considerations. % ‘Appendix C: Migration trom Baseline to Mic-range Devices80 INDEX. at ‘The Microchip Web Ste 85 Customer Change Notifeaton Service as Customer Support. 85 Reader Response 86 PICIEFB4A Product identification System a TO OUR VALUED CUSTOMERS Its cur intention to provide our valued customers vith the best dacumentaion possible fo ensure successful use of your Microchip products. To this ene, we wll contnue to mprove our publications to better sult your needs. Our publications wil be refined ang enhanced as new volumes and updates ae introduced, Ityau have any questions or comments regarding this publication, please contact the Marketing Communications Deparment via E-mall at docerrors@microchip.com or fx the Reader Response Form inthe back ofthis data sheet to (480) 792-4150. We ‘welcome your feedback. Most Current Data Sheet To obian the most upto-date version of his datasheet, please register at our Workdwide Web ste at |ttp:swwwmicrochip.com You can determine the version ofa data sheet by examining is Iterature number found on the bottom outside comer of any page. ‘The last character of the Iterture numbers the version number, (e.g. DS30000A i version A of document 0530000). Errata An erata sheet, describing miner operational diferences rom the data sheet and recommended workarounds, may exis for current devices, As deviceldocumentation issues become knovn tous, we wil publish an errata sheet, The errata will spect the revision Of slicon and revsion of document fo which kt applies. To determine i an errata sheet exists for a particular deviee, please check wih one ofthe following + Microchip's Worldwide Web site; http:/iwww.microchip.com + Your local Microchip sales office (see lst page) When contacting a sales ofc, please specify which device, revision of slicon and data sheet (include erature number) you are using. Customer Notification System Register on our web site at wrwicrochip.com to receive the most cuent information on all of our products S360076-page 2 © 2001-2013 Microchip Technology ine.PIC16F84A 1.0 DEVICE OVERVIEW This document contains device speci information for the operation of the PICTOFE#A device. Adltonal information may be found in the PIC® Mid-Range Ret- erence Manual, (0833023), which may be downloaded trom the Microchip website. The Reference Manual should be considered a complementary document this data sheet, and is highly recommended reading for a better understanding ofthe device architecture and operation ofthe peripheral modules ‘The PIC16F84A belongs to the mid-range family of the PIC® merocontoler devices. A block dlagram of the deviee fs shown n Figure 11 ‘The program memory contains 1K words, which trans~ lates to 1024 instructions, since each 14-bit program. memory wordis the same width as each device instruc- tion. The data memory (RAM) contains 68 bytes. Data, EEPROM is 64 bytes. ‘There are also 19 /0 pins that are user-configured on apin-to-pin basis, Some pins are multiplexed with other device functions. These functions include: + Extemal interrupt + Change on PORTS interupt + Time10 clock input Table 1-1 details the pinout ofthe device with descrip- tions and details for each pin. FIGURE 1-1: PIC16F84A BLOCK DIAGRAM an atau g <1 Praran Cour} Ses Fash Frcgam ‘emory EEPROM ant : Level Sack Moe zeoaTa of oat tere hae as Ae [_zeou +) one exe Program Bus “["* Tf RAM Addr EEADR Instruction Register eid Mt or Uf nae Ro S__Drect Ad Hf ae FeRieg fo | raarocis STATUS eg | 8 | & Mx Poe? 1 a) WoPats Instruction ‘Seciar Becse't etapa Power-on LR] rasrao Ting |_| | Watendoe L, Generation |= Timer baad F by [Reoner osezicuKour —WELR von, vos SSeELRN 1© 2001-2013 Mlerochip Technology Inc. 1D38007C-page 3PIC16F84A TABLE 1-1: PIC16F84A PINOUT DESCRIPTION PDIP] Soic | SSOP | VOIP | Buffer PinName "No. | No. | No. | Type | Type Description oscrclKIN | 16 | 16 | 18 | __|STICMOS®)|Oscillator crystal inputiexternal clock source input ‘OscuclKOUT| 15 | 15 | 19 | 0 = [Oscillator crystal output. Connects fo crystal or resonator in Crystal Oscillator mode. In RC mode, |OSc2 pin outputs CLKOUT, which has 1/4 the Irequency of OSCt and denotes the instruction cycle rate NLR a[4 [4 lw ST [Master Clear (Reset) input/programming voltage input. This pin is an active low RESET to the device. PORTA is a bi-cirectional VO port RAO wi) aw] | vo} om RAt 18) 1% | 2 | vo | om RAZ a}o1 fa | wo) om RAS 2] 2/2] uw] m RAATOCK! 3| 3 | 3 | wo st Can also be selected to be the clock input to the ‘TRO timericounter. Output is open drain type, PORTB is a bi-directional 1] port. PORTS can be sofware programmed for internal weak pull-up on al inputs. RBOINT 6 | 6 | 7 | vo | Trust | RBOANT can also be selected as an external interrupt pin. Ret 7/7] 8 | wo] om Re2 e/|s |e |v} m RBs e| 9 | | vo} m Rea to} 0 | 1 | wo} om Interrupt-on-change pin RS en Interrupt-on-change pin Res 12) 12 | 13 | wo | TrusT® | Intemupt-on-change pin Serial programming clock Re7 13. | 13 | 14 | vo | TrusT® | Intorupt-on-change pin Serial programming data, Ves Ee eno. aare [Ground reference for fogie and VO pins: Vo 4 | 4 [1616] —___[Postive supply for logic and VO pins. Legend: F input O= Output VWO=InpuOutput P= Power —=Not used TTL=TTLinput ST = Schmitt Trigger input Note 1: This buffer is a Schmitt Trigger input when configured as the external interrupt. 2: This buffer is @ Schmitt Trigger input when used in Serial Programming mode. 3: This buffer is a Schmitt Trigger input when configured in RC oscillator mode and a CMOS input otherwise. S36007C-page 4 © 2001-2013 Microchip Technology ine.PIC16F84A 2.0 MEMORY ORGANIZATION FIGURE 2-1: PROGRAM MEMORY MAP AND STACK -PIC16F84A Thete are two memory biocks in the PICISFB4A, These are the program memory and the data memory. Each block has its own bus, so that access to each fee Reroa 3 block can occur during the same oscillator cycle Reteie, RETLW ‘Slack Level The data memory can further be broken down into the general purpose RAM and the Special Function Registers (SFRs). The operation of the SFRs that Sack Level control the “core” are described here. The SFRs used {0 control the peripheral modules are described in the section discussing each individual peripheral module. ParipheralInierupt Vector The data memory area also contains the data EEPROM memory. This memory isnot directly mapped into the data memory, but isinctectly mapped. Thatis, {an indirect address pointer specifies the address of the dala EEPROM memory to readiwite. The 64 bytes of data EEPROM memory have the address range h-3Fh. More details on the EEPROM memory can be found in Section 3.0, RESET Vector ‘Additional information on device memory may be found in the PIC® Mid-Range Reference Manual, (DS33023) 2.1 Program Memory Organization ‘The PICT6FXX has a 13-bit program counter capable of addressing an 8K x 14 program memory space. For the PICT6FB4A, the frst 1K x 14 (0000h-03FFh) are physically implemented (Figure 2-1), Accessing a loca- tion above the physically implemented address will cause a wraparound. For example, for locations 20h, 420h, 820h, C20h, 1020, 1420h, 1820h, and 1C20h, the instruction willbe the same, The RESET vector is at 0000h and the interrupt vector is at 0004h, 1© 2001-2013 Mlerochip Technology Inc. s38007C-page 5PIC16F84A 2.2 Data Memory Organization FIGURE 2-2; REGISTER FILE MAP - “The data memory is patoned into two areas. The fist = isthe Special Function Registers (SFR) area, while the Fe Address aes ‘seconds the General Purpose Registers (GPR) area, con | indirect carl] indrest aac] eon ‘The SFRS control the operation of the device. om [two | OPTION REG | ath Portions of data memory are banked. This is for both = the SFR area and the GPR area. The GPR area is ca emmnc pcesaeea F220 banked to allow greater than 116 bytes of general osm [_starus | starus | aan purpose RAM. The banked areas ofthe SFR are forthe nae |e rae) oa registers that contol the peripheral functions. Banking requires the use of control bits for bank selection osm | _PORTA TRIsA_| 65h “These control bits are located in the STATUS Register. osm [__FoRTa: Tass | as Figure 2-2 shows the data memory map organization na = — a Instructions Movui? and wove ean move values from oan | EEDATA | EECONT | ah the W register to any location inthe register file (F"), oon | eeAOR | EECONZT | con and vice-versa. can | potaTa | PCLATH | Ban The entire data memory can be accessed either oan [iron | wwrcon | san directly using the absolute address of each register file or indirectly through the File Select Register (FSR) cn Co (Section 2.5). Indirect addressing uses the present vvalue ofthe RPO bit for access into the banked areas of data memory ° Data memory ‘is pattioned into two banks which Surpece | (ataelaes Sancta teeel acre ae ve ae ‘a | Few function registers. Bank Ois selected by clearing the RPO bt (STATUS ). Seting the RPO bi selects Bank 4. Each Bank extends up to 7Fh (128 bytes). The fst twelve locations of each Bank are reserved forthe Special Function Registers. The remainder are Gon- eal Purpose Registers, implemented as static RAM. an oh Soh on 221 GENERAL PURPOSE REGISTER FILE _ Each General Purpose Register (GPR) is &-bits wide HS and is accessed ether directly or indirect through the Loo; FSR (Section 25) 7h Fen The GPR addresses in Bank 1 are mapped to BankO Bank addresses in Bank 0. As an example, addressing loca- tion OCh or &Ch will access the same GPR. Z Unimptemented data memary location, read as Note 1: Nota physical register S36007C-page 6 © 2001-2013 Microchip Technology ine.PIC16F84A 2.3 Special Function Registers The Special Function Registers (Figure 2-2 and Table 2-1) are used by the CPU and Peripheral functions to control the device operation, These registers are static RAM. ‘The special function registers can be classified into two sets, core and peripheral. Those associated with the ‘core functions are described in this section. Those related to the operation of the peripheral features are described in the section for that specifi feature, TABLE 2-1: SPECIAL FUNCTION REGISTER FILE SUMMARY value on | potas addr) Name | sit? | site | sits | pita | wits | Bitz | Bit | Bito | Poweron ‘ower-0M ton page Banko [ooh [NDF Uses contents of FSR to address Data Memory (nota physical register) Hi loin [THRO B-bi Real-Time CloekiCounter eae se0ce| 20 [oan [PeL Law Order @ bs of the Program Gourter (PO) eee ceee p11 loon [starus® [RP [RPA] RPO | To | PO | Zz [oc] © |cceaixm| 8 [oan FSR Indirect Data Memory Address Pointer 0 er aoe) TT fosh-_[PORTA® = == [RATT] RAS [RAZ [RAT | RAD |---x wece] 16 loch [PORTSUT | -RB7 | RBS | RBS | RB | RBS | RB2Q | ROT [RBOINT| om woe] 18 [ov — [inimptementedTocation read a = = [och |EEDATA | EEPROM Data Register veo soo) 13,14 [ooh /EEADR EEPROM Aderess Register eee 9606 | 13,14 joan |PCLATH = [= _|_ = Pits Butter tor upper 5 bis of the POW ce cece] 1 [oak [INTCON ce | eee | Toe | NTE | Ree | TOF [WTF] RAF [ccc ccc] 0 Bank t [Soh INDE Uses Contents of FSR to address Data Memory (nota physical register) 7 [sth [OPTION_REG | REPU | INTEDG | Toos | Tose | PSA | PS2 | PS1| PSO [ria nini] ® [aah [PEL Law order 6 bits of Program Counter (PC) ecee ceeep fash stavus@® | RP | Rei | Reo | TO pT Zz [oc] © feceaixm| 8 [aah [FSR Indirect dala memory aderess pois 0 moor sao) TT lash _|TRISA = [= _[_ = _ [PORTA Data Direction Register ran] 16 seh (TRIS PORTS Data Direction Register mn np lame = [BnimplementedTocation, read as % = = [seh |EECONT = [|= | — | fF [WRERR] WREN| WR] RD |--c mee] 19 [29h [EECON2 [EEPROM Control Register 2 (nat a physical register) 4 joan [PLATA [=| ts bater for uppers bits ofthe Pom ec eece] [oan _INTCON Ge | eg [TOE | NTE | RBI | TOF [WHF] RAF [ccc ccc] 10 Legend: x = unknown, «= unchanged. ~= unimplemerieg reads U, «= value depends on condition Note 1 “The upper bye ofthe program counter isnot crectly accessible, PCLATH isa slave register for PC<12:8>, The contents ‘of PCLATH can be transfered tothe upper byte ofthe program counter, but the contents of PC<12:8> are never rans- ferred to PCLATH, This is the value that will be inthe port output atch ‘The TO and PD status bits inthe STATUS register are no affected by a NLR Reset ‘other (non power-up) RESETS inchide: external RESET through HCLR and the Watchdog Timer Reset (On any device RESET, these pins are configured as inputs. 1© 2001-2013 Mlerochip Technology Inc. s38007C-page 7PIC16F84A 23.1 STATUS REGISTER ‘The STATUS register contains the arithmetic status of the ALU, the RESET status and the bank select bit for data memory. ‘As with any register, the STATUS register can be the )| fare not used by the PICTOFS4A and should be programmed as cleared. Use of these bits as general purpose RIW bit is| NOT recommended, since this may affect upward compatiblity with future products, 2: The C and DC bits operate as a Borrow land digit borrow out bit, respectively, in subtraction. See the SUBLat and SUBWE| instructions for examples. 3: When the STATUS register is the destination for an instruction that affects| the Z, DC or C bits, then the write to these three bits is disabled. The specified bi(s)| will be updated according to device logic REGISTER 2-1: STATUS REGISTER (ADDRESS 03h, 83h) Rwo RW RWO RI Rt RWx RWx RW iRP | RPi_ | RPO | TO PD. Zz De c bi ito bit7-6 _Unimplemented: Maintain as ‘0’ bit 5 RPO: Register Bank Select bts (used for direct addressing) 1 = Bank 1 (80h - Fh) 00 = Bank 0 (00h - 7h) bit 4 TO: Time-out bit ‘After power-up, CLAN? instruction, or SLEEP instruction AWOT time-out occurred bits PD: Power-down bit ‘After power-up or by the CLRHD instruction By execution of the S222? instruction bit 2 Z Zero bit 1 = The result of an arithmetic or logie operation is zero ‘The result of an arithmetic or logic operation is nat zero bitt DC: Digit cary/Borrow bit (.0DKe, ADDLWY, SUBLH, SUBIF instructions) (for BarTOW, the polarity is reversed) 1 = Acarry-out from the 4th low order bit ofthe result occurred = No carry-out from the 4th low order bit ofthe result bito : Carryiborrow bit (ADDWE, ADDLN, SUBLM, SUBIE instructions) (for BOTFOW, the polarity is reversed) 1 = Acarry-out from the Most Significant bit ofthe result occurred No earry-out from the Most Significant bit ofthe result ocurred Note: A subtraction is executed by adding the two's complement of the second operand For rotate (RR=, RLE) instructions, this bits loaded with either the high or low order bitof the source register Legend Readable bit n= Value at POR W=Writable bit U = Unimplemented bit, ead as ‘0 "0'= itis cleared x= Bits unknown S360070-page 8 © 2001-2013 Microchip Technology ine.PIC16F84A 2.3.2 OPTION REGISTER Note: When the prescaler is assigned to The OPTION register is a readable and writable the WDT (PSA TMRO has 21:1 register which contains various control bits to configure prescaler assignment the TMROMIDT prescaler, the extemal INT interrupt, TMRO, and the weak pull-ups on PORTB, REGISTER 2.2: _ OPTION REGISTER (ADDRESS 81h) RWWA RW ORM ORM RW RMT ORR RePU_| INTEDG | Tocs | Tose | PSA | PS2 | PSt PSO) bit7 ito bit7 RBPU: PORTE Pull.up Enable bit 1 = PORTS pul-ups are disabled = PORTB pull-ups are enabled by incividual por latch values bit 6 INTEDG Interrupt Edge Select bit 1 = Interrupt on rising edge of RBO/INT pin © = Interrupt on faling edge of RBO/INT pin bits TOCS: TMRO Clock Source Select bit ‘Transition on RASITOCKI pin Intemal instruction cycle clock (CLKOUT) bit TOSE: TMRO Source Edge Select bit Increment on high-to-ow transition on RAA/TOCK\ pin = Increment on low-to-high transition on RAA/TOCK\ pin | bits PSA: Prescaler Assignment bit 1 = Prescaler is assigned to the WOT Prescaler is assigned to the Timer module bit20 _PS2:PS0: Prescaler Rate Select bits Bit Value TMRORate WOT Rate ee ] a2 tt 1 14 1:2 eo} ae 14 a tite | 1:8 zee | tiaz | 1:18 1c 464 | 1:32 nic | titga | 1:64 m1 42256 | 1: 128 Legend: R= Readable bit W=Writable bit U= Unimplemented bit, read as. == Value at POR = Bits set '0'=Bitis cleared x= Bitis unknown 1© 2001-2013 Mlerochip Technology Inc. 1Ds3s007C-page 9PIC16F84A Ce ee es Note: Interrupt flag bits are set when an interupt ‘The INTCON register is @ readable and writable Concition occurs, regardless of the state of register that contains the various enable bits for all its corresponding enable bit or the global interrupt sources, enable bit, GIE (INTCON<7>). REGISTER 2-3: bit7 bit 6 bits bit 4 bit 3 bit2 bit 1 bit o INTCON REGISTER (ADDRESS OBh, 88h) Rwo RWO RWO RWO RWO RWO RWO RWx Ge | cee | Toe | INTE RBIE | TOF | INTF bit7 ito GIE: Giobal Interrupt Enable bit 1 = Enables all unmasked interrupts = Disables all interrupts EEIE: EE Write Complete Interrupt Enable bit nables the EE Write Complete interrupts, sables the EE Write Complete interrupt TOIE: TMRO Overflow Interrupt Enable bit 1 = Enables the TMRO interrupt (C= Disables the TMRO interrupt INTE: RBO/INT External Interrupt Enable bit nables the RBOVINT extemal interrupt \isables the RBOIINT external interupt RBIE: RB Port Change Interrupt Enable bit 1 = Enables the RB port change interrupt = Disables the RB port change interrupt TOIF: TMRO Overflow Interrupt Flag bit MRO register has overfiowed (must be cleared in software) TMRO register did not overtiow INTF: RBOVINT External Interrupt Flag bit 1 = The RBOJINT extemal interrupt occutred (must be cleared in software) = The RBO/INT external interrupt did not occur RBIF. RB Port Change Interrupt Flag bit ‘Atleast one of the RB7:RB4 pins changed state (must be cleared in software) jone of the R87-RB4 pins have changed state c Legend: R= Readable bit W=Writable bit U= Unimplemented bit, ead as ‘0! Value at POR 1'=Bitis set (O'= Bitis cleared _x= Bit is unknown S36007C-page 10, © 2001-2013 Microchip Technology ine.PIC16F84A 24 PCLand PCLATH The program counter (PC) specifies the address of the instruction to fetch for execution, The PC is 13 bits ‘wide. The low byte is called the PCL register. Tis reg- ister is readable and viitable. The high byte is called the PCH register. This register contains the PC<12:8> bits and is not directly readable or writable, Ifthe pro- gram counter (PC) is modified or a conditional test is, true, the instruction requires two cycles. The second cycle is executed as a NOF. All updates to the PCH reg- ister go through the PCLATH register 24.1 STACK The stack allows a combination of upto 8 program calls {and interrupts to occur. The stack contains the return ‘address from this branch in program execution. Mid-range devices have an 8 level deep x 13-bit wide hardware stack. The stack space is not part of either program or data space and the stack pointer is not readable or writable. The PC is PUSHed onto the stack ‘when @ CALL instruction is executed or an interrupt ‘causes a branch, The stack is POPed in the event of a RETURN, RETLI of a RETEZE instruction execution. PCLATH is not modified when the stack is PUSHed or POPed, ‘After the stack has been PUSHed eight times, the ninth push overwrites the value that was stored from the first push, The tenth push ovenwrites the second push (and 00n) 2.5 Indirect Addressing; INDF and FSR Registers ‘The INDF register isnot a physical register. Addressing INDF actually addresses the register whose address is contained in the FSR register (FSR is a pointer) This is Indirect addressing EXAMPLE 2-1: INDIRECT ADDRESSING + Register file 05 contains the value 10h + Register file 06 contains the value OAM + Load the value 05 into the FSR register + read of the INDF register will return the value cf 10h Increment the value of the FSR register by one (FSR = 08) + read of the INDF register now will return the vvalue of An, Reading INDF itself indirecty (FSR = 0) will produce (00h. Writing to the INDF register indirectly results in & ‘no-operation (although STATUS bits may be affected). ‘A simple program to clear RAM locations 20h-2Fh using indirect addressing is shown in Example 2-2. HOW TO CLEAR RAM USING INDIRECT ADDRESSING twat initialize pointer Fen 4 all Genet goto NEXT HO. clear next An effective 9-bit address is obtained by concatenating the &-bit FSR register and the IRP bit (STATUS<7>), as, shown in Figure 2-3. However, IRP is not used in the PICIEFB4A, 1© 2001-2013 Mlerochip Technology Inc. S360076-page 11PIC16F84A Indirect Addressing FIGURE 2-3: __DIRECTINDIRECT ADDRESSING Direct Aderessing apineo 6 FomOpiade 0 ea CITT) funk Select Location Stet oon eon oh oe = Acresso oft imap back to Memory" Bank 0 an son mo] © | © ler sarko Bank Note 1: For memory map deta, see Figure 2.2 2: Maintain a clear for upward compatbilty with future products Not implemented S36007C-page 12 © 2001-2013 Microchip Technology ine.PIC16F84A 3.0 DATA EEPROM MEMORY The EEPROM data memory is readable and writable during normal operation (full Voo range), This memory is not ditectly mapped inthe register file space. Instead itis indirectly addressed through the Special Function Registers, There are four SFRs used to read and write this memory, These registers are: + EECON1 + EECON2 (not a physically implemented register) + EEDATA + EEADR EEDATA holds the bit data for readiwrite, and EEADR holds the address of the EEPROM location being accessed, PICTBF&4A devices have 64 bytes of data EEPROM with an address range from Oh to 3F>. REGISTER 3-1: uo uo uo ‘The EEPROM data memory allows byte read and write, A byte write automatically erases the location and \wrtes the new data (erase before write). The EEPROM data memory is rated for high erase/wnite cycles. The \wnte time is controlled by an on-chip timer. The write time will vary with voltage and temperature as well as, from chip to chip. Please refer to AC specifications for exact limits When the device is code protected, the CPU may continue to read and write the data EEPROM memory. The device programmer can no longer access this memory. ‘Additional information on the Data EEPROM is avail. ‘able in the PIC® Mid-Range Reference Manual (833023) EECON1 REGISTER (ADDRESS 88h) RW0 RWx RWO RISO RISO EEIF | WRERR | WREN | WR RD bit7 bit7-5 __Unimplemented: Read as 0° ito ita bits bit2 bitt bito EEIF: EEPROM Write Operation Interrupt Flag bit he write operation completed (must be cleared in software) = The write operation is not complete or has not been started WRERR: EEPROM Error Flag bit 1 = A write operation is prematurely terminated (any MCLR Reset or any WDT Reset during normal operation) he write operation completed WREN: EEPROM Write Enable bit 1 = Allows write cycles (c= Inhibits write to the EEPROM WR: Write Control bit 1 = Initiates a ite cycle. The bits cleared by hardware once write is complete. The WR bit can only be set (not cleared) in software. = Write eycle to the EEPROM is complete RD: Read Control bit Initiates an EEPROM read RO is cleared in hardware, The RD bit can only be set (nat cleared) in software = Does not initiate an EEPROM read Legend: R= Readable bit n= Value at POR W=Writable bit U= Unimplemented bit, read as 0" 1 = Bitis set ‘o itis cleared _x = Bit is unknown 1© 2001-2013 Mlerochip Technology Inc. S36007C-page 13,PIC16F84A 3.1 Reading the EEPROM Data Memory ‘To read a data memory location, the user must write the address to the EEADR register and then set control bit RD (EECON1<0>), The data is available, in the very next cycle, in the EEDATA register; therefore, it can be read in the next instruction. EEDATA will hold this value until another read or until tis written to by the user (during a write operation). EXAMPLE 31: DATA EEPROM READ 3.2 Writing to the EEPROM Data Memory ‘To write an EEPROM data location, the user must first write the address to the EEADR register and the data to the EEDATA register. Then the user must folow a ‘specific sequence to initiate the write for each byte. ‘Additionally, the WREN bit in EECON1 must be set to tenable write. This mechanism prevents accidental writes. to data EEPROM due to errant (unexpected) code exe- cution (1e., lost programs). The user should keep the WREN bit clear at all times, except when updating EEPROM, The WREN bitis not cleared by hardware, Aer a write sequence has been initiated, clearing the WREN bit wil not affect this write cycle, The WR bit will be inhibited from being set unless the WREN bitis set. ‘At the completion of the write cycle, the WR bit is cleared in hardware and the EE Write Complete Interrupt Flag bit (EEIF) is set. The user can either enable this interrupt or poll this bit. EEIF must be cleared by software. Write Verify Depending on the application, good programming practice may dictate that the value witten to the Data EEPROM should be verified (Example 3-3) to the desired value to be written, This should be used in applications where an EEPROM bit will be stressed rear the specification limit Generally, the EEPROM write failure willbe a bit which ‘was written as a0, but reads back as a '1' (due to leakage off the bit 33 ‘The write will not initiate i the above sequence is not exactly followed (write SSh to EECON2, write Ah to EECON2, then set WR bit) for each byte. We strongly recommend that interrupls be disabled during this ‘code segment. EXAMPLE 3-2: _ DATA EEPROM WRITE. EXAMPLE 3-3: __ WRITE VERIFY ‘BSF ‘STATUS. RP Bank 1 lel wc. Bank ¢ ECF INTCON GIE Disable Inte bem tte Scr cou wean | anable write ee MOVE S58 IS. REC . Bank 1 SS scr —nzcom we Ser ae ei ec is REC, Bank C read in EEDATA REGISTERS/BITS ASSOCIATED WITH DATA EEPROM Value on | Value on address | Name | at7 | ate ets | ers | ats | atz | ats | Bito | Poweron | allother Reset | RESETS. co EEDATA | EEPROM Data Register Sasa soos [uaus woun! (08h EEADR [EEPROM Adaress Register pecs: son [usua uuuul 8h eeconi| — | — | — | cei [wrerr| wren | we | RO ce xcec|---¢ gece 0h EECON2 [EEPROM Control Register 2 Legend: <= unknown, = unchanged, - = unimplemented, read a8 ‘Shaded cals are not used by data EEPROM, S36007C-page 14 © 2001-2013 Microchip Technology ine.