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IMPLEMENTATION OF DIGITAL BEAMFORMING IN GNSS RECEIVERS

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 IMPLEMENTATION OF DIGITAL BEAMFORMING IN GNSS RECEIVERS

Carles Fernández–Prades, Pau Closas, and Javier Arribas

Centre Tecnològic de Telecomunicacions de Catalunya (CTTC)

Av. Carl Friedrich Gauss 7, 08860 Castelldefels, Spain.
E-mail: carles.fernandez@cttc.es, pau.closas@cttc.es, javier.arribas@cttc.es

ABSTRACT In the literature there can be found a number of digital beam-

Sources of accuracy degradation in Global Navigation Satellite
Systems (GNSS) are well known. While atmospheric-dependant
sources (delays that depend on the ionosphere and troposphere con-
ditions) can be greatly mitigated by differential systems external
to the receiver’s operation, the multipath effect and interferences
are location-dependant and remain as the most important causes of
accuracy degradation. An antenna-array based receiver can make
use of digital beamforming techniques, providing appealing spatial
filtering capabilities. The goal of this paper is to provide details
about the design and implementation of a real-time beamformer
based on FPGA technology.
1. INTRODUCTION
Global marketplace for GNSS receivers has been traditionally based
on application specific integrated circuit (ASIC) technology, an ap-
proach with high development costs but extremely low cost per unit
(thus ensuring revenues) and high performance. However, recent
and forthcoming changes in the space segment (the modernization
of GPS and GLONASS, also the advent of Galileo and Compass)
are pushing developers to new approaches and targeting designs to
unforeseen accuracy levels. This requires more flexibility in the de-
sign and implementation processes, driving to more agile develop-
ment tools. Although ASIC technology remains pervasive for mass
market applications, other technologies such as field programmable
gate arrays (FPGAs) or software–defined receivers running in dig-
ital signal processors, microprocessors, or even regular PCs are of
great interest for limited–market but highly demanding applications
such as reference stations, geodesy and surveying, timing, machine
control, and others.
This is the case of antenna–array based GNSS receivers. It is
well known that sources of accuracy degradation due to atmospheric
effects can be effectively mitigated by differential systems, but in-
terferences and multipath remain as potential causes of downgraded
performance. The spatial diversity provided by antenna arrays adds
another degree of freedom for the rejection of such nuisance signals.
Among the wide range of antenna array architectures, from the all–
analog to the all–digital approaches, the adaptive digital beamform-
ing strategy has revealed as a potentially effective tool when applied
to the problems involved in a GNSS receiver, specifically multipath
and interference rejection [1].
This work has been partially supported by the Spanish and Cata-
lan Science and Technology Commissions: CENIT2007-2002 (TIMI) and
TEC2008-02685/TEC (NARRA), and by the European Commission in the
framework of the FP7 Network of Excellence in Wireless COMmunications
NEWCOM++ (contract n. 216715) and COST Action IC0803 (RFCSET).
forming implementations aimed to GNSS. One of the firstly reported
platforms is the NAVSYS High Gain Advanced GPS Receiver
(HAGR) [2], which is composed of a 16 antenna–element array
receiver and uses dedicated hardware to create up to 12 indepen-
dent and parallel beamformings to simultaneously point the antenna
array beam to 12 GPS satellites. HAGR also includes a software
defined GPS receiver to control the beamforming algorithm. How-
ever, very few technical information about the implementation is
available. Other achievements in hardware-based digital beamform-
ing platforms are focused on specific beamforming algorithms. It is
worth mentioning the QR decomposition (QRD)-based beamform-
ing engine [3] made by Xilinx engineers, and the minimum variance
distortionless response (MVDR) beamformer implementation re-
ported in [4]. The trend in digital beamforming implementations
is to tightly combine hardware and software design in order to im-
prove the execution speed of the adaptive beamforming algorithms,
which usually require matrix inversion operations. In that sense, it
is important to mention the recent advances achieved by the efficient
implementation of the QRD-RLS algorithm [5], that validates the
hardware-software co-design strategy.
RF front-end
LNA
PC
FPGA
ADC Beamformer SDR GNSS
Receiver
RF front-end
LNA
Fig. 1. Block diagram of the complete system. The beamformer
module described in this paper is boxed in grey.
The contribution of this work is the proposal of an architec-
ture for adaptive digital beamforming in the context of GNSS re-
ceivers, providing details about the implementation. The overall de-
sign is shown in Figure 1. Since antennas and RF front–ends can
be built with commercial off–the–shelf (COTS) components based
on ASIC technology, and there are many software defined GNSS
receivers available (from MATLAB–based toolboxes [6] to real–
time, C–based implementations [7] published under the GNU Gen-
eral Public License), this work will focus in the implementation of
the beamformer, boxed in grey in Figure 1. The use of FPGA de-
vices for digital beamforming has been already reported [3, 8–11]
as a viable technology for real–time applications. In this work, we
address the specifities of a GNSS receiver.
The organization of this paper is as follows: Section 2 defines
the GNSS signal model for an antenna–array receiver. Section 3
proposes the overall architecture of the system and provides a quick
overview of the building blocks. Sections 4 and 6 discuss two main
issues in the design process, namely clock synchronization and the
computation of the beamweights. Section 5 provides details of an
implementation aimed to be a proof–of–concept for the proposed
beamformer module. Finally, Section 7 provides experimental re-
sults and concludes the paper.
2. SIGNAL MODEL
2.1. Radio Frequency signal model
Considering the signals coming from M satellites, the received sig-
nal can be written as
M
X −1 n • g(ψ, θ) ∈ CN ×1 is the spatial signature vector related to ar-
xRF (t) = αi (t)< ej(2πfc (t−τm (t))+φm )
m=0

× sT,m (t − τm (t)) + n(t) (1)
where <{·} denotes the real part of the complex–valued quantity in
the brackets, fc is the carrier frequency, {αm , τm (t), φm } are the
amplitude, delay and carrier phase of the signal coming from the
mth satellite, n(t) is additive white Gaussian noise plus other un-
desired terms (such as multipath or interferences), and sT,m (t) is
the Direct–Sequence Spread–Spectrum (DS-SS) complex baseband
signal transmitted by the mth satellite. Amplitudes αm and the ini-
tial carrier phases φm are modeled as piecewise constants, that is,
we consider them constants during the observation window but we
allow changes from window to window. We explicitly allow time–
varying delays τm (t). In order to compute the position, the receiver
should estimate the pseudoranges (directly related to time delay of
the line–of–sight paths, τm (t)) and pseudorange rate (related to the
evolution of the carrier phase).
When xRF (t) is received in an N –element antenna array, each
antenna receives a different replica of this signal, with a different
delay depending on the array geometry and the direction of arrival.
Considering a local coordinate system (for example east–north–up
or [e, n, u] system with origin in a reference point, usually the phase
center of the whole array), we can express the delay between ar-
ray elements ∆tmn , where subindex m refers to a given source and
subindex n refers to a given antenna, as the dot product of the wave
vector km (with modulus 2π λc
and direction pointing to the signal
source, defined by its azimuth θm and elevation ψm ) and the posi-
tion of the antenna center of phase, rc :
∆tmn = km rn = (2)
2π
= [cos(θm ) cos(ψm ), sin(θm ) cos(θm ), sin(ψm )] ·
λc
· [rec , rnc , ruc ]T
Since a natural choice for a GNSS receiver architecture is the
parallelization of the synchronization process of each in–view satel-
lite, we can particularize the signal model for a single satellite. As-
suming and array with N antenna elements in an arbitrary geometry,
the relative phase at each antenna can be expressed as
g = exp {jπkR}T , (3)
where k ∈ R 1×3
is the wavenumber vector, defined as
 
k = cos(θ) cos(ψ) sin(θ) cos(θ) sin(ψ) , (4)
with θ being the angle of the direction of arrival defined anticlock-
wise from the e axis on the en plane and ψ the angle with respect to
the en plane. On the other hand,
 
re1 . . . reN
R =  rn1 . . . rnN  ∈ R3×N (5)
ru1 . . . ruN
is the matrix of sensor element positions normalized to units of half
wavelengths with respect to the e, n and u axes. This can be ex-
pressed by a vector signal model, where each row corresponds to
one antenna:
xRF (t) = < {g(ψ, θ)αd(t)} + n(t), (6)
where
• xRF (t) ∈ RN ×1 is the received signal vector,
ray geometry and Directions Of Arrival (DOAs),
• ψ and θ are the elevation and azimuth angles of the satellite,
• α is the signal amplitude,
• d(t) = ej(2πfc (t−τ (t))+φ) sT (t − τ (t)), d(t) ∈ C, and
• n(t) ∈ RN ×1 represents additive noise and all other disturb-
ing terms.
In this model, the narrowband array assumption has been made.
This assumption considers that the time required for the signal to
propagate along the array is much smaller than inverse of its band-
width. So, a phase shift can be used to describe the propagation from
one antenna to another. Current navigation signals are reported to be
emitted with a bandwidth of ∼ 20 MHz (see Table 1), which inverse
is 50 ns or 15 m in spatial terms. The array is expected to be much
smaller, since the carrier wavelength is on the order of 10 cm, so the
assumption seems reasonable. However, it must be pointed out that
this signal model becomes invalid for large arrays.
2.2. Intermediate Frequency signal model
When these signals impinge the antenna array, they pass through
Radio Frequency (RF) front–ends (one per antenna, see Figure 2),
usually composed of a Low Noise Amplifier (LNA) and a down-
conversion stage to an Intermediate Frequency (IF). Modeling the
LNAs with their complex baseband impulse response hLN A (t), as-
suming that all the N front-ends share a local oscillator with fre-
quency fLO and carrier phase φLO , and defining fIF = fc − fLO
and ϕ = φ − φLO , the signal at the output of the front–ends can be
modeled as
xIF (t) = < {g(ψ, θ)ar(t)} + η(t) (7)
where
• r(t) = sR (t − τ (t)) ej(2πfIF t−2πfc τ (t)+ϕ) ,
• a is the amplitude of the received signal after the LNA and
the downconversion stage,
• sR,m (t) = sT,m (t) ∗ hLN A (t) is the filtered complex base-
band signal received from the satellite, where ∗ stands for the
convolution operator, and
• η(t) is the filtered and down–converted noise term n(t).
 Front-End Clock line Complex BUS Single Ch. BUS

8 Ch. BUS Control BUS Analog signal

Front-End

Front-End
50 Msps

Downconverter
Downconverter
Downconverter
and
8 Ch. and Spatial Ethernet
Front-End and
Decimating Filter FIFO 1 FIFO 2
A/D Decimating Filter Filter Output
Decimating Filter

x8
Front-End
BB 25 Msps

Beamforming
Real-Time
Front-End
Logic

Weights
Beamforming
Front-End Clock RS232
CPU
Manager Level Converter PC
MicroBlaze

Front-End

FPGA

DEVELOPED PROTOTYPE
L.O

Fig. 2. High level block diagram of the proposed architecture.

3. DIGITAL BEAMFORMING PLATFORM: DESIGN AND cessed in real–time by a software receiver.

BLOCK DIAGRAM This structure is highly parallelizable, in the sense that it can be
replicated for each system and/or band of interest. The implemen-
Figure 2 represents the high level block diagram of the proposed ar- tation described in Section 5 provides enough bandwidth for any of
chitecture. From left to right, the antenna array outputs are fed into the current and forthcoming GNSS signals, except for Galileo E6,
eight analog front-ends which perform a low noise amplification and which would require a higher sampling rate (see Table 1).
a downconversion from RF to IF. Next, the analog–to–digital con-
verter (ADC) synchronously performs the sampling operation for the
4. SYNCHRONIZATION ISSUES
eight antenna channels controlled by the FPGA logic circuitry. Then,
the FPGA reads the digital samples coming from the ADC and per-
In order to define the system low–level architecture, an important
forms a digital downconversion from IF to baseband. In this step, in
design principle is the synchronous methodology, in which all the
order to reduce the sample rate, the digital downconverter stage im-
storage components (registers composed by a set of flip–flops1 ) are
plements a decimation filter. The output of the digital downconverter
controlled by a common clock signal. Implicitly, digital signal pro-
stage is the baseband snapshot of the antenna array, which is fed both
cessing techniques and the associated mathematical tools assume a
into a First–In, First–Out (FIFO) memory and into the beamforming
synchronized system. Indeed, design and analysis so far are based
real-time processing block simultaneously.
on an ideal clocking scenario, assuming that the entire system can
At this point, the FPGA provides computational resources for be driven by a single clock signal and that the sampling edge of this
the implementation of a wide range of beamforming algorithms. clock signal can reach all the components at the same time. In real-
Most of them require the computation of the autocorrelation and ity, this is hardly possible, since each input port of a gate and each
the cross-correlation matrices of the received data, as well as inver- wire introduce small values of resistance and capacitance. Thus, the
sions of such matrices and other sophisticated matrix algebra opera- design must consider a non–ideal clock signal and data distribution.
tions that requires floating point precision. The computation can be
The clock distribution network is the circuit that delivers the
splitted in logic circuitry blocks implemented in Very High Speed
clock signal to all the flip–flops in the system. FPGA devices usu-
Integrated Circuit Hardware Description Language (VHDL), or in
ally have one or more pre–routed and prefabricated clock distribu-
an embedded processor that provides floating point capabilities and
tion networks, and if the VHDL code is developed properly, the
higher–level programming. In addition, the algorithm could require
synthesis software can recognize the existence of the clock signal
external data, such as DOAs of satellite signals and synchronization
and automatically map it to one (or more) of such networks. The
parameters coming from the software–defined GNSS receiver run-
effect of the clock distribution network can be modeled by propaga-
ning in an external device (that could range from a digital signal pro-
tion delays from the clock source to various registers. Because of
cessor to a general purpose PC). This feedback channel can be im-
the variation in buffering and routing, the propagation delays may
plemented through a serial control bus with RS–232 interface. The
be different. The key characteristic is the difference between the ar-
resulting beamweights calculated by the beamforming algorithm are
rival times of the sampling edges, which is known as the clock skew.
loaded into the spatial filter block which computes the weighted sum
For multiple registers, we consider the worst-case scenario and de-
of the eight antenna channels obtaining a single spatially–filtered
fine the clock skew as the difference between the arrival times of the
output sample stream. Finally, a Gigabit Ethernet block is in charge
of encapsulating the data in Ethernet frames and transmitting them 1 A flip–flop is an electronic circuit that has two stable states and thereby
to the PC, where samples can be stored for post–processing, or pro- is capable of serving as one bit of memory.
 by the same clock signal, even in the case of using a derived clock
Table 1. Current and forthcoming GNSS signals signal with different (but known) clock frequency or phase. Note
Signal Carrier freq. Bandwidth Servicea that these derived clock signals need their own individual clock dis-
[MHz] [MHz] tribution networks even though they are in the same clock domain.
Galileo E5A 1176.45 20.46 OS The proper operation of a clocked flip–flop depends on the input
Galileo E5B 1207.14 20.46 OS/CS/SoL being stable for a certain period of time before and after the clock
Galileo E6 1278.75 40.92 CS edge. If the setup and hold–time requirements are met, the cor-
Galileo E1 1575.42 24.552 SoL rect output will appear at a valid output level at the flip–flop output
(i.e., the output voltage will be either above the “high” or below the
GPS L1 C/A 1575.42 20.46 SPS
“low” thresholds) after a certain clock–to–output delay. However,
GPS L1 P(Y) 1575.42 20.46 PPS
if these setup and hold-time requirements are not met, the output
GPS L1Cb 1575.42 30.69 Civil
of the flip–flop may take much longer than the expected maximum
GPS L1 M–codec 1575.42 ≈ 24 M
clock–to–output delay to reach a valid logic level. This is called
GPS L2 P(Y) 1227.60 20.46 PPS
unstable behavior, or metastability [19]. When a flip–flop enters a
GPS L2 M–code 1227.60 ≈ 24 M
metastable state, its output voltage is somewhere between the low
GPS L2Cd 1227.60 20.46 Civil
and the high thresholds, and cannot be interpreted as either logic “0”
GPS L5e 1176.45 24 SoL
or logic “1”. If the output of the flip–flop is used to drive other logic
Glonass L1f 1602.00 7.875 SP cells, the in–between value may propagate to downstream logic cells
Glonass L1 1602.00 undisclosed HP and lead the entire digital system into an unknown state, and thus a
Glonass L2 1246.00 7.875 SP functional failure. Since the error patterns and failures are not eas-
Glonass L2 1246.00 undisclosed HP ily repeatable (a typical setup consist of an external clock source
Compass B1g 1561.10 4.092 OS/M with random phase), we should adopt good design practices in sys-
Compass B1-2 1589.74 4.092 OS/M tems with multiple clock domains, specially in asynchronous clock–
Compass B2 1207.14 24 OS/M domain crossing paths. In the design of Figure 2 we can identify such
Compass B3 1268.52 24 M clock–domain crossings before and after the decimation process, in
a the computation of matrices related to the beamforming computation
OS: Open Service. CS: Commercial Service. SoL: Safety–of–Life.
SPS: Standard Positioning Service. PPS: Precise Positioning Service.
(see Section 6), and in the interface with the Gigabit Ethernet port.
SP: Standard precision. HP: High Precision. M: Military/Authorized. The problem of metastability can be prevented by adding special
b L1C will be available with first Block III launch, currently scheduled devices between the source and the destination domains [20]. These
for 2013. Defined in IS-GPS-800 [12]. devices, known as synchronizers, isolate metastability, delivering a
c The whole Earth M-code signal is available on the Block IIR-M
clean signal to the downstream logic. Such devices commonly con-
satellites, the spot beam antennas will not be deployed until the Block sist of multiple flip–flop stages with a handshake protocol. In the
III satellites are deployed, tentatively in 2013.
d L2C is defined in IS-GPS-200D [13]. proposed design, we have used asynchronous FIFOs as a way to
e L5 is implemented with first GPS IIF launch, SVN49 (April 10, 2009). make the clocks independent at the write and the read port. This
Defined in IS-GPS-705 [14]. solution, when implemented using a RAM memory block in combi-
f Glonass signal–in–space defined in [15]. nation with Gray encoding/decoding of input/output pointers in or-
g Signals of Compass-M1 experimental satellite, launched in April 14, der to minimize bit transitions, is also known to mitigate glitches and
2007, have been unraveled by independent research [16–18]. latency-related problems. A FIFO memory used as a synchronizer
Compass-G2, a geostationary satellite, was launched in April 15, 2009, has an independent read and write clock ports, dividing the FIFO in
and 10 more satellites are planned to be launched before the end of
two clock regions and providing a suitable data path between both
2012, covering China and adjacent regions. Global coverage is planned
by 2020. To the authors’ knowledge, no official Interface Control clock domains. Each of the FIFO clock regions have their own set of
Document has been made public. control signals, synchronous to the respective clock signal. This fea-
ture allows the use of FIFOs as data buffers when both clocks have a
different frequency. FPGA vendors provide such Intellectual Prop-
erty (IP) cores, that could even include correction checking [21].
earliest and latest sampling edges.
Multiple clocks may exist or become necessary for several rea-
sons, such as inherent multiple-clock sources (interaction with ex- 5. DIGITAL BEAMFORMING: IMPLEMENTATION
ternal systems), circuit size (clock skew increases with the size of DETAILS
the circuit and the number of flip–flops), design complexity (since
a large digital system is frequently composed of several small sub- As a proof–of–concept, we implemented a prototype on the Xilinx
systems of different performance and power requirements, apply- ML505 Evaluation Platform [22], a general purpose development
ing pure synchronous design methodology may introduce unneces- board populated with a Virtex-5 XC5VLX50T FPGA [23], onboard
sary constraints), and power considerations (the dynamic power of a memory, and a number of convenient I/O ports, such as the high–
CMOS device is proportional to the switching frequency of transis- speed Xilinx Generic Interface (XGI) expansion headers, Gigabit
tors, which is correlated to the system clock frequency). These con- Ethernet, and RS-232 serial bus. For the development, we used Xil-
siderations have a direct impact in the synchronous design method- inx ISE Design Suite 11.2 [24].
ology, since they imply the need for dividing a system into multiple
synchronous subsystems, and to design special interfaces between
5.1. Multichannel signal sampling
those subsystems.
In such a multiple–clock system, the term clock domain is used The ADC block is in charge of sampling the output of the N = 8
to describe a block of circuitry in which the flip–flops are controlled front–ends simultaneously at a suitable rate. The implementation
 LVDS SIGNALS

CH #1
Front-End SERIAL TO PARALLEL

CH #2
Front-End SERIAL TO PARALLEL

CH #3
Front-End SERIAL TO PARALLEL

CH #4
Front-End SERIAL TO PARALLEL OUTPUT Downconverter
ADS5273 FIFO and
CH #5
Front-End SERIAL TO PARALLEL 12x8 bits Decimating Filter
CH #6
Front-End SERIAL TO PARALLEL

CH #7
Front-End L L SERIAL TO PARALLEL
S V V
M D D CH #8
Front-End A S S
SERIAL TO PARALLEL
WR RD

BIT CLOCK IN BIT CLOCK IN

CLOCK
SAMPLE CLOCK IN SAMPLE CLOCK IN MANAGER

Fig. 3. Picture of the developed prototype. SAMPLE CLOCK OUT

50 MHz
CLOCK
GENERATOR

FPGA
100 MHz

is based on the ADS527xEVM Evaluation Module of Texas Instru-

ments, a board based on the ADS5273 [25] eight–channel ADC inte-
grated circuit, supporting a sampling frequency up to 70 Msps with
12 bits of resolution per sample. In the prototype described in this
paper, the sampling frequency was set to fs = 50 Msps. This im-
plies that each digital output transmits at a bit rate of 50 × 12 = 600
Mbps. All the analog input channels are sampled by a common sam-
ple clock, generated by the FPGA Digital Clock Manager (DCM) in
charge of generating the sample rate from an onboard crystal oscil-
lator (100 MHz ± 10 kHz). This oscillator can be easily replaced by
an external clock with better accuracy, using a dedicated clock input.
The ADS5273 provides eight pairs of Low Voltage Differen-
tial Signaling (LVDS) [26] outputs plus two extra LVDS signals for
clock managing. The electrical connections from the ADC board
to the FPGA are based on the differential signal XGI expansion con-
nectors of the ML505 evaluation platform, that use standard 0.1-inch
headers [22].
The FPGA logic reads the signal samples from the ADC outputs
and converts from serial to parallel using a specifically programmed
Fig. 4. ADC block diagram.
5.2. Digital downconversion & decimation
After signal sampling, a Digital Downconverter (DDC) for each an-
tenna is in charge of shifting the satellite signals from IF to base-
band. In our setup we used the IF-sampling approach in order to
simplify the process and significantly reduce the amount of FPGA
resources [27]. From IF-sampling theory we know that, if the fol-
lowing holds:
fs
fIF = kfs ± , ∀k ∈ Z|k ≥ 1
4
fs ≥ 4B , (8)
where B is the receiver’s bandwidth and the integer k is a design
choice, then a non-overlapped signal replica appears centered at
fs /4. A simple way to obtain the baseband signal is to use the
logic, dumping the data samples into a 12 × 8 bits register that con- frequency-shift property
π
of the Fourier transform, thus multiplying
tains the snapshot xIF [n] = xIF (t)

, where Ts = f1s is the the alias by e−j 2 n . The latter is a straightforward operation with
t=nTs cyclic values {1, −j, −1, j}, with j 2 = −1, which can be imple-
sampling period. mented using multiplexers, avoiding complex multipliers and thus
In order to reduce the clock jitter, the clock skew for the in- saving valuable resources on the FPGA. Therefore, each antenna
ternal logic, and to assure a 50% duty cycle, it is recommended channel is downconverted using the scheme shown in Figure 5,
to regenerate the incoming clocks using a DCM in the FPGA. In extracting Inphase (I) and Quadrature (Q) baseband components
our setup, the ADC delivers 2 clock signals to the FPGA. Namely, from
bit clock in and sample clock in , which correspond to the seri- π
alized bit stream clock and the 12-bits-sample clock, respectively. xBB [n] = xIF [n]e−j 2 n
Since the serial to parallel converters operate with bit clock in in = [xIF [0], −jxIF [1], −xIF [2], jxIF [3], . . .] (9)
a double data rate fashion (i.e., using both rising and falling edges),
bit clock in is recognized to be six times faster than the sample as the real and imaginary parts of xBB [n], defined as xBB,I [n] and
clock. Thus, the serial to parallel conversion design would require xBB,Q [n], respectively. Particularly, in our setup the external IF was
2 DCMs, whose synchronization implies a large area on the FPGA set to fIF = fs − f4s = 37.50 MHz.
and a complex design. Taking into account this constraint, the con- Decimation is a very common procedure in digital signal pro-
version was implemented using the minimum logic to avoid extra cessing applications since it reduces the sample rate (and thus the
input delays in data and clock lines, i.e., no DCM was used. Ac- computational load) and the noise power. It consists on the regular
tually, bit clock in and sample clock in have only input drivers, elimination of samples in a sequence with a given ratio D. Without
discarding the use of any clock reconditioning technique to mini- considering noise,
mize the differential delay with respect to the ADCs input data lines. xD [n] = xBB,I [nD] + jxBB,Q [nD]. (10)
In order to avoid the metastability problems described in Section 4, a
FIFO memory is in charge of crossing the clock domain from the ex- In the frequency domain, if we denote XBB (ejω ) as the Fourier trans-
ternal sample clock in clock domain to the internal DCM stabilized form of the complex baseband digital, the signal after the decimation
sample clock domain. The stabilized sample clock signal is deliv- process can be written as:
ered to the downconverter module, which is connected in cascade to D−1
the FIFO read port. The detailed diagram for the ADC block can be
  1 X  ω 2π 
XD ejω = XBB ej ( D − D k) . (11)
found in Figure 4. D
k=0
 ADC OUTPUT
A OUT FIR FILTER DECIMATE
follows:
CH #1 12 b 19 b 19 b
12 b
"000000000000" B     
50 Msps MUX
 H 2 H
MULT -1 C
ŵM V DR = arg min E w X = w R̂XX w (12)
"000000000000" D w
AGC FIFO 1
8+8b

wH g = 1
SELECT

2b
25 Msps subject to (13)

"000000000000" A
OUT
12 b
FIR FILTER
19 b
DECIMATE
19 b where X = [xD [n] · · · xD [n + K − 1]] ∈ CN ×K is called the spa-
MULT -1 B
MUX tiotemporal data matrix, K is the number of samples in a spreading
C
1
XXH is the estimation of the data autocorrela-
"000000000000"

D
RESOURCES SUMMARY FOR 8 CHANNELS:
code, and R̂XX = K
SELECT - 32 MULTIPLEXERS (12 bits x 4 inputs).
tion matrix. Applying the Lagrange multipliers method, the MVDR
2b
- 16 FIR (6 coef x 6 bits) FILTERS.
- 1 BINARY COUNTER (2 bits)
beamweight results in
VALUE
BINARY
SAMPLE CLOCK
COUNTER
 −1
ŵM V DR = R̂−1 H −1
50 MHz

XX g g R̂XX g . (14)

Fig. 5. DDC block diagram for one antenna channel.

Instead of having a spatial reference, we can rely on a temporal ref-
erence waveform d = [d[n] · · · d[n + K − 1]] ∈ C1×K , where
d[n] = sT (t − nDTs ). In this case, we can write the problem as
As can be observed in (11), all the frequency components of the
π
original signal beyond ω = D will be mapped beyond ω = π in  2 
ŵT RB = arg min E wH X − ad . (15)
 
the spectrum of the decimated sequence, thus producing overlapping w
of the spectrums, and hence distortion. To avoid so, the original
π
signal is low–pass filtered with a cut–off pulsation of ωco = D ,
fs A straightforward gradient computation leads to
which corresponds to an analog frequency of fco = 2D . The design
of D depends on the LNA bandwidth, the sampling frequency, and
the intermediate frequency. In our implementation, we assumed a 8 ŵT RB = R̂−1
XX r̂Xd a , (16)
MHz-wide passband LNA, a sampling frequency of fs = 50 Msps,
and a decimation rate of D = 3 that implies a cut–off frequency for
1
where R̂XX is defined as above, and r̂Xd = K XdH .
the FIR filter of fco = 8.3 MHz. The FIR filter was implemented We can even combine both temporal and spatial reference, lead-
with the Xilinx LogiCORE IP FIR Compiler core [28], using six ing to the space–time hybrid beamforming [1]:
6–bit coefficients.  2 
At the output of the FIR filter each of the complex signal sample
ŵHB = arg min E wH X − ad (17)
 
had 19 + 19 bits of resolution. In order to save FPGA resources, w
an Automatic Gain Control (AGC) was implemented. The function
subject to wH g = 1 (18)
of the AGC stage is to keep dynamically the 8 Most Significant Bits
(MSB) of the sample, keeping one bit for the two’s complement sign
and 7 bits for the magnitude, truncating the remaining bits. This which is solved by
process assures that the next stages will work with a resolution of 8  −1  
bits per sample, both for the real and imaginary components. ŵHB = R̂−1 −1 H −1
XX r̂Xd a+R̂XX g g R̂XX g 1 − gH R̂−1XX r̂Xd a .
(19)
6. BEAMWEIGHT COMPUTATION These operations are computationally intensive and requires either
a high number of bits or floating point operations. In addition, the
computation of (14), (16), (19), or any other beamforming strategy
Beamforming with antenna arrays is a technique that consists of
should be performed in real–time, which constitutes a challenging
several antennas which outputs are controlled in phase and gain,
i.e., multiplied by complex weights, in order to achieve a gain pat- constraint. For instance, the direct computation of R̂XX involves a
tern that can be manipulated electronically. Then, all the weighted matrix multiplication of size (N × K) × (K × N ), with complexity
signals are combined to obtain a single output. Considering again O(KN 2 ). Since K samples should comprise a whole code length (1
an N –element array, these mentioned weights can be stacked in a ms in the GPS L1 C/A signal), it is reasonable to state that K  N .
complex–valued vector w ∈ CN ×1 , and the output signal of the
beamformer can be computed as y[n] = wH xD [n].
6.2. Recursive computation of the autocorrelation matrix

In addition to those described, there are other more sophisticated

6.1. Beamforming algorithms
beamforming algorithms. Most of them require the computation of
The weighting vector w, also known as beamvector, can be designed the inverse of the autocorrelation matrix. Therefore, we are indeed
following several criteria. For instance, we can minimize the total interested in the computation of such inverse. Moreover, this com-
output power while forcing the beamformer to always point to the putation should be recursive, in order to alleviate the computational
desired DOA, an information that is available when the receiver has load and to make the algorithm adaptive to changes in the scenario.
a coarse estimation of its position and has demodulated the naviga- This section addresses two possible alternatives to compute R̂−1 XX

tion message. This strategy is known as Minimum Variance Dis- namely, (i) recursive computation of R̂XX with a further direct in-
tortionless Response (MVDR) beamforming, and can be stated as version and (ii) recursive computation of R̂−1XX .
6.2.1. Recursive R̂XX computation and inversion 6.3. Beamformer module
The computation of R̂XX admits the following equivalent expres- The beamformer module collects the baseband snapshot vectors
sion: defined as xD [n] and enroutes them into two different processing
K
1 X blocks: a FIFO memory (implemented with [21]) to be processed
R̂XX = xD [i]xHD [i] , (20) by the spatial filter block, and into the beamforming real–time logic
K i=1
block. The spatial filter block reads the snapshots from the FIFO and
which constructs recursively the matrix as snapshots are recorded. multiplies them by the complex weights coming from the embedded
Afterwards, a matrix inversion algorithm can be used to obtain R̂−1
XX . soft processor. The resulting products are added together to form the
spatially–filtered output signal:
6.2.2. Recursive computation of the inverse
y[n] = wH xD [n], (23)
The inverse of R̂XX can be obtained recursively without requiring
any matrix inversion at all, thus reducing the computational load. performed in the block labeled as “Spatial Filter” in Figure 1, where
For each received snapshot, k = {1, . . . , K}, we realize that the the complex weights resolution is set to 8 + 8 bits and the output of
recursive formula in (20) can be written as the multipliers is set to 16 + 16 bits. Thus, the final complex sample
stream resolution is 16 + 16 bits.
k
(k) 1X The block in charge of streaming the data to the PC reads the
R̂XX = xD [i]xH
D [i] (21)
k i=1 samples coming from the spatial filter and groups them to form a
custom Gigabit Ethernet frame.
k−1
1X 1
= xD [i]xH
D [i] + xD [k]xH
D [k]
k i=1 k
6.4. Ethernet signal transmission
k − 1 (k−1) 1
= R̂XX + xD [k]xH
D [k] .
k k The spatially–filtered signal coming from the spatial filter block is
sent in real–time to the PC by means of a dedicated Gigabit Ethernet
If we invert both sides in (21) and apply the Sherman-Morrison for- bus [30]. A special type of frame has been designed to minimize
mula [29], we obtain the overhead imposed by network protocols, and the corresponding
−1 driver has been implemented with the Xilinx LogiCORE IP Virtex-5

(k) k  (k−1) −1
R̂XX = R̂XX + (22) FPGA Embedded Tri-Mode Ethernet MAC Wrapper core [31].
k−1
 −1  −1 At the PC, device drivers make network cards to generate an
(k−1) (k−1)
k R̂XX xD [k]xH D [k] R̂XX interrupt whenever the card needs attention (e.g. for informing the
− −1 . operating system that there is an incoming packet to handle). In
(k − 1)2

1 (k−1)
1 + k−1 xH
D [k] R̂ XX xD [k] case of high traffic rate, the operating system spends most of its time
handling interrupts, leaving little time for other tasks. This problem
Notice that the inverse calculation in (22) does not require any is referred to as interrupt livelock [32], and it could provoke packet

(0)
−1 losses than will be seen as signal glitches, or phase discontinuities,
inversion. At the first iteration (k = 1), we can set R̂XX =I that can affect the GNSS software receiver performance. In order
and let the algorithm to converge. to avoid so, we have adopted the strategy proposed in [33, 34], that
implies a Linux kernel patching and recompilation, as a solution for
6.2.3. Tradeoff analysis of the implementations signal capturing at the PC.
Further work will be related to the implementation of the VITA-
In general, the implementation of digital beamforming algorithms 49 radio transport standard [35] on the Ethernet packets. This stan-
can be shared by the FPGA circuitry logic and an embedded micro- dard defines the packetized transport of time domain digital samples
processor. On the one hand, certain parts of the algorithm demand of RF, IF, or baseband signals, along with any necessary metadata,
high processing rates. This is the case for instance of the compu- across a digital link, constituting a useful building block to support
tation of the autocorrelation matrix. Thus, the implementation of data streaming for Software Defined Radio.
such process should be implemented by the programmable logic of
the FPGA device, at the expenses of increasing the area of the de-
sign. On the other hand, calculation of array weights involves ma- 7. EXPERIMENTAL RESULTS AND CONCLUSIONS
trix inversion and other operations, which should be carried out by
floating–point enabled devices in order to provide accurate design Since the set of coherent RF front–ends is still not available to the
values. Therefore, the computation of required matrices is imple- authors of this work, the prototype has been tested by injecting tones
mented in the FPGA logic and fed to the digital beamforming algo- at their IF inputs and checking coherence among channels and fur-
rithm, which is programmed in an embedded processor. ther validated using a Agilent E4438C ESG vector signal genera-
Specifically, the method proposed in 6.2.1 should resort to the tor [36] equipped with GPS Personality [37], which is able to sim-
FPGA logic in order to implement (20) and leave the inversion of ulate multi-satellite, synchronized GPS signals containing accurate
R̂XX to the processor. On the other hand, the alternative in 6.2.2 navigation messages, allowing a GPS receiver to acquire a location
is conceived to provide R̂−1
XX before entering the processor domain. fix. These results are shown in Figure 6, using the software pro-
Indeed, the approach choice is left as a design issue, which basi- cessor provided by [6]. Experimental results show the feasibility of
cally depends on the critical resources to safe: operating frequency the Xilinx Virtex-5 FPGA and the MicroBlaze embedded software
or FPGA’s area, respectively. processor for GNSS array processing.
 Coordinates variations in UTM system
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