2.7 V to 5.

5 V, <100 μA, 8-/10-/12-Bit

nanoDAC, SPI Interface in LFCSP and SC70
Data Sheet AD5601/AD5611/AD5621
FEATURES FUNCTIONAL BLOCK DIAGRAM
6-lead SC70 and LFCSP packages VDD GND

Micropower operation: 100 µA maximum at 5 V

Power-down typically to 0.2 µA at 3 V POWER-ON AD5601/AD5611/AD5621
RESET
2.7 V to 5.5 V power supply
Guaranteed monotonic by design REF(+)
Power-on reset to 0 V with brownout detection DAC
REGISTER
12-/10-/8-BIT OUTPUT
BUFFER
VOUT
DAC
3 power-down functions
Low power serial interface with Schmitt-triggered inputs
On-chip output buffer amplifier, rail-to-rail operation INPUT POWER-DOWN
SYNC interrupt facility CONTROL
LOGIC
CONTROL LOGIC RESISTOR
NETWORK
Minimized zero-code error
AD5601 buffered 8-bit DAC

06853-001
B version: ±0.5 LSB INL
AD5611 buffered 10-bit DAC SYNC SCLK SDIN
B version: ±0.5 LSB INL Figure 1.
A version: ±4 LSB INL
Table 1. Related Devices
AD5621 buffered 12-bit DAC
B version: ±1 LSB INL Part Number Description
A version: ±6 LSB INL AD5641 2.7 V to 5.5 V, <100 µA, 14-bit nanoDAC in
SC70 and LFCSP packages
APPLICATIONS They also provide software-selectable output loads while in
Voltage level setting
power-down mode. The parts are put into power-down mode
Portable battery-powered instruments
over the serial interface.
Digital gain and offset adjustment
Programmable voltage and current sources The low power consumption of these parts in normal operation
Programmable attenuators makes them ideally suited to portable battery-operated equip-
ment. The combination of small package and low power makes
GENERAL DESCRIPTION these nanoDAC devices ideal for level-setting requirements,
The AD5601/AD5611/AD5621, members of the nanoDAC® such as generating bias or control voltages in space-constrained
family, are single, 8-/10-/12-bit, buffered voltage output DACs and power-sensitive applications.
that operate from a single 2.7 V to 5.5 V supply, consuming PRODUCT HIGHLIGHTS
typically 75 µA at 5 V. The parts come in tiny LFCSP and SC70
1. Available in 6-lead LFCSP and SC70 packages.
packages. Their on-chip precision output amplifier allows rail-
2. Low power, single-supply operation. The AD5601/
to-rail output swing to be achieved. The AD5601/AD5611/
AD5611/AD5621 operate from a single 2.7 V to 5.5 V
AD5621 utilize a versatile 3-wire serial interface that operates at
supply with a maximum current consumption of 100 µA,
clock rates up to 30 MHz and is compatible with SPI, QSPI™,
making them ideal for battery-powered applications.
MICROWIRE™, and DSP interface standards.
3. The on-chip output buffer amplifier allows the output of
The reference for the AD5601/AD5611/AD5621 is derived the DAC to swing rail-to-rail with a typical slew rate of
from the power supply inputs and, therefore, gives the widest 0.5 V/µs.
dynamic output range. The parts incorporate a power-on reset 4. Reference is derived from the power supply.
circuit, which ensures that the DAC output powers up to 0 V 5. High speed serial interface with clock speeds up to
and remains there until a valid write to the device takes place. 30 MHz. Designed for very low power consumption.
The AD5601/AD5611/AD5621 contain a power-down feature The interface powers up only during a write cycle.
that reduces current consumption to typically 0.2 µA at 3 V. 6. Power-down capability. When powered down, the DAC
typically consumes 0.2 µA at 3 V. Power-on reset with
brownout detection.

Rev. I Document Feedback

Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Tel: 781.329.4700 ©2005–2019 Analog Devices, Inc. All rights reserved.
Trademarks and registered trademarks are the property of their respective owners. Technical Support www.analog.com
AD5601/AD5611/AD5621
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications ....................................................................................... 1
General Description ......................................................................... 1
Functional Block Diagram .............................................................. 1
Product Highlights ........................................................................... 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
Timing Characteristics ................................................................ 4
Absolute Maximum Ratings............................................................ 5
ESD Caution .................................................................................. 5
Pin Configurations and Function Descriptions ........................... 6
Typical Performance Characteristics ............................................. 7
Terminology .................................................................................... 13
Theory of Operation ...................................................................... 14
DAC Section ................................................................................ 14
Resistor String ............................................................................. 14
REVISION HISTORY
4/2019—Rev. H to Rev. I
Changes to Table 2 ............................................................................ 5
Change to Figure 16 ......................................................................... 8
Updated Outline Dimensions ....................................................... 20
Changes to Ordering Guide .......................................................... 21
2/2016—Rev. G to Rev. H
Changes to Noise Parameter, Table 2 ............................................. 3
Changes to Serial Interface Section .............................................. 14
6/2013—Rev. F to Rev. G
Change to Ordering Guide ............................................................ 21
2/2012—Rev. E to Rev. F
Added 6-Lead LFCSP ......................................................... Universal
Changes to Features Section, General Description Section,
Table 1, and Product Highlights Section ....................................... 1
Changes to Table 4 ............................................................................ 5
Added Figure 4; Renumbered Sequentially .................................. 6
Changes to Table 5 ............................................................................ 6
Changes to Choosing a Reference as Power Supply for the
AD5601/AD5611/AD5621 Section .............................................. 18
Updated Outline Dimensions ....................................................... 20
Changes to Ordering Guide .......................................................... 21
7/2010—Rev. D to Rev. E
Changes to Figure 1 .......................................................................... 1
Rev. I | Page 2 of 21
Data Sheet
Output Amplifier........................................................................ 14
Serial Interface ............................................................................ 14
Input Shift Register .................................................................... 14
SYNC Interrupt .......................................................................... 14
Power-On Reset .......................................................................... 16
Power-Down Modes .................................................................. 16
Microprocessor Interfacing ....................................................... 16
Applications Information .............................................................. 18
Choosing a Reference as Power Supply for the
AD5601/AD5611/AD5621 ....................................................... 18
Bipolar Operation Using the AD5601/AD5611/AD5621 ..... 18
Using the AD5601/AD5611/AD5621 with a Galvanically
Isolated Interface ........................................................................ 19
Power Supply Bypassing and Grounding ................................ 19
Outline Dimensions ....................................................................... 20
Ordering Guide .......................................................................... 21
5/2008—Rev. C to Rev. D
Changes to General Description Section .......................................1
Changes to Table 2.............................................................................3
Changes to Choosing a Reference as Power Supply for the
AD5601/AD5611/AD5621 Section.............................................. 18
Changes to Ordering Guide .......................................................... 20
12/2007—Rev. B to Rev. C
Changes to Features ..........................................................................1
Changes to Table 2.............................................................................3
Changes to AD5601/AD5611/AD5621 to ADSP-2101
Interface Section ............................................................................. 16
Updated Outline Dimensions ....................................................... 20
Changes to Ordering Guide .......................................................... 20
7/2005—Rev. A to Rev. B
Changes to Figure 48...................................................................... 17
Changes to Galvanically Isolated Interface Section ................... 19
Changes to Figure 52...................................................................... 19
3/2005—Rev. 0 to Rev. A
Changes to Timing Characteristics .................................................4
Changes to Absolute Maximum Ratings ........................................5
Changes to Full Scale Error Section ................................................7
Changes to Figure 20...................................................................... 10
Changes to Theory of Operation.................................................. 14
Changes to Power Down Modes .................................................. 15
1/2005—Revision 0: Initial Version
Data Sheet AD5601/AD5611/AD5621

SPECIFICATIONS
VDD = 4.5 V to 5.5 V; RL = 2 kΩ to GND; CL = 200 pF to GND; all specifications TMIN to TMAX, unless otherwise noted. Temperature range
for A/B grades is −40°C to +125°C, typical at 25°C.

Table 2.
A Grade B Grade
Parameter Min Typ Max Min Typ Max Unit Test Conditions/Comments
STATIC PERFORMANCE
AD5601
Resolution 8 Bits
Relative Accuracy 1 (INL) ±0.5 LSB
Differential Nonlinearity (DNL) ±0.5 LSB Guaranteed monotonic by design
AD5611
Resolution 10 Bits
Relative Accuracy1 (INL) ±4 ±0.5 LSB
Differential Nonlinearity (DNL) ±0.5 ±0.5 LSB Guaranteed monotonic by design
AD5621
Resolution 12 Bits
Relative Accuracy1 (INL) ±6 ±1 LSB
Differential Nonlinearity (DNL) ±0.5 ±0.5 LSB Guaranteed monotonic by design
Zero-Code Error 0.5 10 0.5 10 mV All 0s loaded to DAC register
Full-Scale Error ±0.5 ±0.5 mV All 1s loaded to DAC register
Offset Error ±0.063 ±10 ±0.063 ±10 mV
Gain Error ±0.0004 ±0.037 ±0.0004 ±0.037 %FSR
Zero-Code Error Drift 5.0 5.0 µV/°C
Gain Temperature Coefficient 2.0 2.0 ppm
FSR/°C
OUTPUT CHARACTERISTICS 2
Output Voltage Range 0 VDD 0 VDD V
Output Voltage Settling Time 6 10 6 10 µs Code ¼ scale to ¾ scale
Slew Rate 0.5 0.5 V/µs
Capacitive Load Stability 470 470 pF RL = ∞
1000 1000 pF RL = 2 kΩ
Output Noise Spectral Density 120 120 nV/√Hz DAC code = midscale,1 kHz
Noise 2 2 µV rms DAC code = midscale,
0.1 Hz to 10 Hz bandwidth
Digital-to-Analog Glitch Impulse 5 5 nV-s 1 LSB change around major carry
Digital Feedthrough 0.2 0.2 nV-s
Short-Circuit Current 15 15 mA VDD = 3 V/5 V
DC Output Impedance 0.5 0.5 Ω
LOGIC INPUTS
Input Current 3 ±2 ±2 µA
Input High Voltage, VINH 1.8 1.8 V VDD = 4.7 V to 5.5 V
1.4 1.4 V VDD = 2.7 V to 3.6 V
Input Low Voltage, VINL 0.8 0.8 V VDD = 4.7 V to 5.5 V
0.6 0.6 V VDD = 2.7 V to 3.6 V
Pin Input Capacitance 3 3 pF

Rev. I | Page 3 of 21
AD5601/AD5611/AD5621 Data Sheet
A Grade B Grade
Parameter Min Typ Max Min Typ Max Unit Test Conditions/Comments
POWER REQUIREMENTS
VDD 2.7 5.5 2.7 5.5 V All digital inputs at 0 V or VDD
IDD for Normal Mode DAC active and excluding load
current
VDD = 4.5 V to 5.5 V 75 100 75 100 µA VIH = VDD and VIL = GND
VDD = 2.7 V to 3.6 V 60 90 60 90 µA VIH = VDD and VIL = GND
IDD for All Power-Down Modes VIH = VDD and VIL = GND
VDD = 4.5 V to 5.5 V 0.5 0.5 µA VIH = VDD and VIL = GND
VDD = 2.7 V to 3.6 V 0.2 0.2 µA VIH = VDD and VIL = GND
POWER EFFICIENCY
IOUT/IDD 96 96 % ILOAD = 2 mA and VDD = ±5 V
1
Linearity calculated using a reduced code range: AD5621 from Code 64 to Code 4032; AD5611 from Code 16 to Code 1008; AD5601 from Code 4 to Code 252.
2
Guaranteed by design and characterization, not production tested.
3
Total current flowing into all pins.

TIMING CHARACTERISTICS
VDD = 2.7 V to 5.5 V; all specifications TMIN to TMAX, unless otherwise noted. See Figure 2.

Table 3.
Parameter Limit 1 Unit Test Conditions/Comments
t1 2 33 ns min SCLK cycle time
t2 5 ns min SCLK high time
t3 5 ns min SCLK low time
t4 10 ns min SYNC to SCLK falling edge setup time
t5 5 ns min Data setup time
t6 4.5 ns min Data hold time
t7 0 ns min SCLK falling edge to SYNC rising edge
t8 20 ns min Minimum SYNC high time

t9 13 ns min SYNC rising edge to next SCLK falling edge ignored

1
All input signals are specified with tr = tf = 1 ns/V (10% to 90% of VDD) and timed from a voltage level of (VIL + VIH)/2.
2
Maximum SCLK frequency is 30 MHz.

t4 t2 t1 t9

SCLK
t8 t3 t7
SYNC
t6
t5
06853-002

SDIN D15 D14 D2 D1 D0 D15 D14

Figure 2. Timing Diagram

Rev. I | Page 4 of 21
Data Sheet AD5601/AD5611/AD5621

ABSOLUTE MAXIMUM RATINGS

TA = 25°C, unless otherwise noted. Stresses at or above those listed under Absolute Maximum
Table 4. Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
Parameter Rating
or any other conditions above those indicated in the operational
VDD to GND −0.3 V to +7.0 V
section of this specification is not implied. Operation beyond
Digital Input Voltage to GND −0.3 V to VDD + 0.3 V
the maximum operating conditions for extended periods may
VOUT to GND −0.3 V to VDD + 0.3 V
affect product reliability.
Operating Temperature Range
Industrial (A/B Grades) −40°C to +125°C
Storage Temperature Range −65°C to +160°C ESD CAUTION
Maximum Junction Temperature 150°C
SC70 Package
θJA Thermal Impedance 433.34°C/W
θJC Thermal Impedance 149.47°C/W
LFCSP Package
θJA Thermal Impedance 95°C/W
Lead Temperature, Soldering
Vapor Phase (60 sec) 215°C
Infrared (15 sec) 220°C
ESD (Human Body Model) 2.0 kV

Rev. I | Page 5 of 21
AD5601/AD5611/AD5621 Data Sheet

PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS

VOUT
VDD 1 AD5601/ 6 VOUT
SYNC 1 6
AD5601/ AD5611/
AD5611/ SCLK 2 AD5621 5 GND
SCLK 2 5 GND TOP VIEW
AD5621 SDIN 3 (Not to Scale) 4 SYNC
TOP VIEW

06853-003
SDIN 3 4 VDD
(Not to Scale)

06853-053
NOTES:
1. CONNECT THE EXPOSED PAD TO GND.
Figure 3. 6-Lead SC70 Pin Configuration Figure 4. 6-Lead LFCSP Pin Configuration

Table 5. Pin Function Descriptions

SC70 LFCSP
Pin No. Pin No. Mnemonic Description
1 4 SYNC Level-Triggered Control Input (Active Low). This is the frame synchronization signal for the input
data. When SYNC goes low, it enables the input shift register, and data is transferred in on the falling
edges of the clocks that follow. The DAC is updated following the 16th clock cycle, unless SYNC is
taken high before this edge, in which case the rising edge of SYNC acts as an interrupt and the write
sequence is ignored by the DAC.
2 2 SCLK Serial Clock Input. Data is clocked into the input shift register on the falling edge of the serial clock
input. Data can be transferred at rates up to 30 MHz.
3 3 SDIN Serial Data Input. This device has a 16-bit shift register. Data is clocked into the register on the falling
edge of the serial clock input.
4 1 VDD Power Supply Input. The AD5601/AD5611/AD5621 can be operated from 2.7 V to 5.5 V. Decouple VDD
to GND.
5 5 GND Ground. Ground reference point for all circuitry on the AD5601/AD5611/AD5621.
6 6 VOUT Analog Output Voltage from the DAC. The output amplifier has rail-to-rail operation.
EP Exposed Pad. Connect to GND.

Rev. I | Page 6 of 21
Data Sheet AD5601/AD5611/AD5621

TYPICAL PERFORMANCE CHARACTERISTICS

1.0 2.5
VDD = VREF = 5V VDD = VREF = 5V
TA = 25°C 2.0 TA = 25°C

TOTAL UNADJUSTED ERROR (LSB)

1.5
0.5
1.0
INL ERROR (LSB)

0.5

0 0

–0.5

–1.0
–0.5
–1.5

–2.0

–1.0 –2.5

06853-007
06853-004
64 564 1064 1564 2064 2564 3064 3564 4064 64 564 1064 1564 2064 2564 3064 3564 4064
DAC CODE DAC CODE

Figure 5. Typical AD5621 INL Figure 8. AD5621 Total Unadjusted Error (TUE)

0.5 0.6
VDD = VREF = 5V VDD = VREF = 5V
0.4 TA = 25°C TA = 25°C

TOTAL UNADJUSTED ERROR (LSB)

0.4
0.3

0.2
0.2
INL ERROR (LSB)

0.1

0 0

–0.1
–0.2
–0.2

–0.3
–0.4
–0.4

–0.5

06853-008
–0.6
06853-005

16 116 216 316 416 516 616 716 816 916 16 116 216 316 416 516 616 716 816 916
DAC CODE DAC CODE

Figure 6. Typical AD5611 INL Figure 9. AD5611 Total Unadjusted Error (TUE)

0.100 0.20
VDD = VREF = 5V VDD = VREF = 5V
TA = 25°C TA = 25°C
0.075 0.15
TOTAL UNADJUSTED ERROR (LSB)

0.050 0.10
INL ERROR (LSB)

0.025 0.05

0 0

–0.025 –0.05

–0.050 –0.10

–0.075 –0.15

–0.100 –0.20
06853-009
06853-006

4 54 104 154 204 4 54 104 154 204

DAC CODE DAC CODE
Figure 7. Typical AD5601 INL Figure 10. AD5601 Total Unadjusted Error (TUE)

Rev. I | Page 7 of 21
AD5601/AD5611/AD5621 Data Sheet
0.20 12
V DD = 5V VDD = 3V VDD = 5V
T A = 25°C VIH = DVDD VIH = DVDD
0.15 VIL = GND VIL = GND
10 TA = 25°C TA = 25°C
0.10

NUMBER OF DEVICES
DNL ERROR (LSB)

8
0.05

0 0 6

–0.05
4
–0.10

2
–0.15

–0.20 0

06853-010

0.05456
0.05527

0.05599

0.05671

0.05742

0.05814

0.05885
0.06648
0.06710
0.06773
0.06835
0.06897
0.06960
0.07022
0.07084
0.07147
0.07209
0.07271
0.07334
64 564 1064 1564 2064 2564 3064 3564
DAC CODE

06853-013
IDD (mA)

Figure 11. Typical AD5621 DNL Figure 14. IDD Histogram (3 V/5 V)

0.05
VDD = 5V TA = 25°C
0.04 TA = 25°C VDD = 5V
CH1 = SCLK
0.03

0.02
DNL ERROR (LSB)

0.01

–0.01

–0.02

–0.03
CH2 = VOUT
–0.04

06853-014
–0.05
06853-011

16 116 216 316 416 516 616 716 816 916 CH1 = 5V/DIV CH2 = 1V/DIV TIME BASE = 2µs/DIV
DAC CODE

Figure 12. Typical AD5611 DNL Figure 15. Full-Scale Settling Time

0.010
TA = 25°C
VDD = 5V
VDD = 5V
0.008 TA = 25°C
CH1 = SCLK
0.006

0.004
DNL ERROR (LSB)

0.002

0
CH2 = VOUT
–0.002

–0.004

–0.006
06853-015

–0.008

–0.010
06853-012

4 54 104 154 204 CH1 = 5V/DIV CH2 = 1V/DIV TIME BASE = 1µs/DIV
DAC CODE

Figure 13. Typical AD5601 DNL Figure 16. Half-Scale Settling Time

Rev. I | Page 8 of 21
Data Sheet AD5601/AD5611/AD5621
VDD = 5V
VDD = 5V VDD
TA = 25°C
TA = 25°C MIDSCALE LOADED

CH1 CH1

VOUT = 70mV

06853-019
06853-016
CH2
CH1 1V, CH2 20mV, TIME BASE = 20µs/DIV CH1 5µV/DIV

Figure 17. Power-On Reset to 0 V Figure 20. 1/f Noise, 0.1 Hz to 10 Hz Bandwidth

CH1
VDD VDD = 5V
VDD = 5V
CH1 TA = 25°C
TA = 25°C

VOUT

CH2

CH2

VOUT

06853-020
06853-017

CH1 1V, CH2 5V, TIME BASE = 50µs/DIV CH1 5V, CH2 1V, TIME BASE = 2µs/DIV

Figure 18. VDD vs. VOUT Figure 21. Exiting Power-Down Mode

2.458 140
3/4 SCALE
2.456 FULL SCALE
120
2.454
MIDSCALE
2.452 100
1/4 SCALE
AMPLITUDE (V)

2.450
80
2.448
IDD (µA)

2.446
60
ZERO SCALE
2.444

2.442 40
TA = 25°C
2.440 VDD = 5V
LOAD = 2kΩ AND 220pF 20
2.438 CODE 0x2000 TO 0x1FFF
10ns/SAMPLE NUMBER
2.436 0
06853-018

0 100 200 300 400 500

06853-021

0 5 10 15 20 25
SAMPLE NUMBER FREQUENCY (MHz)

Figure 19. Digital-to-Analog Glitch Energy Figure 22. IDD vs. SCLK vs. Code

Rev. I | Page 9 of 21
AD5601/AD5611/AD5621 Data Sheet
700 0.3
VDD = 5V VDD = 5V AD5621 MAX INL ERROR
OUTPUT NOISE SPECTRAL DENSITY (nV/ Hz)

TA = 25°C 0.2
600 UNLOADED OUTPUT
0.1 AD5611 MAX INL ERROR AD5601 MAX INL ERROR
500
0

INL ERROR (LSB)

400 –0.1 AD5611 MIN INL ERROR

300 –0.2 AD5601 MIN INL ERROR

MIDSCALE –0.3
200
FULL SCALE –0.4
100 AD5621 MIN INL ERROR
–0.5
ZERO SCALE
0

06853-022
–0.6

06853-025
100 1k 10k 100k –40 –20 0 20 40 60 80 100 120
FREQUENCY (Hz) TEMPERATURE (°C)

Figure 23. Noise Spectral Density Figure 26. INL vs. Temperature (5 V)

70 0.08
TA = 25°C 0.07 VDD = 5V
VDD = 5V
60 0.06
AD5621 MAX DNL ERROR
0.05
0.04
50
0.03
VDD = 3V
DNL ERROR (LSB)

0.02 AD5611 MAX DNL ERROR

40 0.01
IDD (µA)

0
30 –0.01
–0.02 AD5611 MIN DNL ERROR AD5601 MAX DNL ERROR
–0.03 AD5601 MIN DNL ERROR
20
–0.04
–0.05
10 –0.06
AD5621 MIN DNL ERROR
–0.07
0 –0.08

06853-026
06853-023

0 2000 4000 6000 8000 10000 12000 14000 16000 –40 10 60 110 160
DIGITAL INPUT CODE TEMPERATURE (°C)

Figure 24. Supply Current vs. Digital Input Code Figure 27. DNL vs. Temperature (5 V)

0.8 0.00149
VDD = 5V VDD = 5V
TA = 25°C AD5621 ZERO-CODE ERROR
0.6
DAC LOADED WITH ZERO-SCALE CODE
0.00099
0.4
ERROR (LSB)
∆VOUT (V)

0.2 AD5611 ZERO-CODE ERROR

AD5601 ZERO-CODE ERROR
0.00049
AD5601 FULL-SCALE ERROR
0.0

–0.2
–0.00001
DAC LOADED WITH FULL-SCALE CODE
–0.4
AD5611 FULL-SCALE ERROR
AD5621 FULL-SCALE ERROR
06853-024

06853-027

–0.6 –0.00051
–15 –10 –5 0 5 10 15 –40 –20 0 –20 40 60 80 100 120 140
TEMPERATURE (°C)
I (mA)

Figure 25. Sink and Source Capability Figure 28. Zero-Code Error and Full-Scale Error vs. Temperature

Rev. I | Page 10 of 21
Data Sheet AD5601/AD5611/AD5621
1.5 0.10

1.3 AD5621 MAX TUE 0.09

TOTAL UNADJUSTED ERROR (LSB)

1.1 0.08

0.9 0.07 VDD = 5V

0.7 0.06

IDD (mA)
0.5 AD5601 MAX TUE 0.05
AD5611 MAX TUE VDD = 3V
0.3 0.04

0.1 0.03

–0.1 0.02
AD5601 MIN TUE
–0.3 AD5611 MIN TUE 0.01
AD5621 MIN TUE
–0.5 0

06853-028
–40 –20 0 20 40 60 80 100 120 140

06853-031
–40 –20 0 20 40 60 80 100 120 140
TEMPERATURE (°C)
TEMPERATURE (°C)

Figure 29. Total Unadjusted Error (TUE) vs. Temperature (5 V) Figure 32. Supply Current vs. Temperature (3 V/5 V Supply)

1.5
TA = 25°C
1.4 0.4
1.3
1.2
AD5621 MAX INL ERROR
1.1 0.2
OFFSET ERROR (mV)

1.0 VDD = 5V AD5601 MAX INL ERROR

INL ERROR (LSB)
AD5611 MAX INL ERROR
0.9
0
0.8
AD5601 MIN INL ERROR
0.7 VDD = 3V
0.6 AD5611 MIN INL ERROR
–0.2
0.5
0.4
0.3 –0.4
0.2 AD5621 MIN INL ERROR
0.1
0 –0.6
06853-029

06853-032
–40 –20 0 20 40 60 80 100 120 140 2.7 3.2 3.7 4.2 4.7 5.2
TEMPERATURE (°C) SUPPLY VOLTAGE (V)

Figure 30. Offset Error vs. Temperature (3 V/5 V Supply) Figure 33. INL vs. Supply Voltage at 25°C

0 0.10
0.09 TA = 25°C
0.08
–0.002
0.07
VDD = 5V 0.06
–0.004 0.05
0.04
GAIN ERROR (%FSR)

AD5621 MAX DNL ERROR

DNL ERROR (LSB)

0.03
–0.006
0.02
AD5611 MAX DNL ERROR
0.01
–0.008 0
–0.01
–0.02 AD5611 MIN DNL ERROR
–0.010
–0.03 AD5601 MAX DNL ERROR
VDD = 3V
–0.04
AD5601 MIN DNL ERROR
–0.012 –0.05
–0.06
–0.07
–0.014 AD5621 MIN DNL ERROR
–0.08
–0.09
–0.016 –0.10
06853-033
06853-030

–40 –20 0 20 40 60 80 100 120 140 2.7 3.2 3.7 4.2 4.7 5.2 5.7 6.2 6.7
TEMPERATURE (°C) SUPPLY VOLTAGE (V)

Figure 31. Gain Error vs. Temperature (3 V/5 V Supply) Figure 34. DNL vs. Supply Voltage at 25°C

Rev. I | Page 11 of 21
AD5601/AD5611/AD5621 Data Sheet
1.5 0.10
TA = 25°C TA = 25°C
1.3 0.09
AD5621 MAX TUE
TOTAL UNADJUSTED ERROR (LSB)

0.08
1.1
0.07
0.9
0.06

IDD (mA)
0.7
0.05
0.5
AD5611 MAX TUE 0.04
0.3
AD5621 MIN TUE 0.03
0.1
0.02

–0.1 AD5601 MAX TUE

AD5611 MIN TUE 0.01

06853-036
AD5601 MIN TUE

06853-034
–0.3 0
2.7 3.2 3.7 4.2 4.7 5.2 2.7 3.2 3.7 4.2 4.7 5.2
SUPPLY VOLTAGE (V) SUPPLY VOLTAGE (V)

Figure 35. Total Unadjusted Error (TUE) vs. Supply Voltage at 25°C Figure 37. Supply Current vs. Supply Voltage at 25°C

0.0010 450
TA = 25°C TA = 25°C SCLK/SDIN
AD5621 ZERO-CODE ERROR INCREASING
400
SCLK/SDIN
0.0008 VDD = 5V
DECREASING
350 VDD = 5V
0.0006
300
SCLK/SDIN
ERROR (LSB)

0.0004 AD5601 FULL-SCALE ERROR 250 INCREASING

IDD (µA)

VDD = 3V
AD5611 ZERO-CODE ERROR 200
0.0002
AD5601 ZERO-CODE ERROR 150
0
AD5611 FULL-SCALE ERROR 100

–0.0002 AD5621 FULL-SCALE ERROR 50

SCLK/SDIN DECREASING V DD = 3V
06853-035

–0.0004 0

06853-037
2.7 3.2 3.7 4.2 4.7 5.2 5.7 6.2 6.7 0 1 2 3 4 5 6
SUPPLY VOLTAGE (V) VLOGIC (V)

Figure 36. Zero-Code Error and Full-Scale Error vs. Supply Voltage at 25°C Figure 38. SCLK/SDIN vs. Logic Voltage

Rev. I | Page 12 of 21
Data Sheet
TERMINOLOGY
Relative Accuracy
For the DAC, relative accuracy or integral nonlinearity (INL) is
a measure of the maximum deviation, in LSBs, from a straight
line passing through the endpoints of the DAC transfer func-
tion. See Figure 5 to Figure 7 for plots of typical INL vs. code.
Differential Nonlinearity
Differential nonlinearity (DNL) is the difference between the
measured change and the ideal 1 LSB change between any two
adjacent codes. A specified differential nonlinearity of ±1 LSB
maximum ensures monotonicity. This DAC is guaranteed
monotonic by design. See Figure 11 to Figure 13 for plots of
typical DNL vs. code.
Zero-Code Error
Zero-code error is a measure of the output error when zero
code (0x0000) is loaded to the DAC register. Ideally, the output
is 0 V. The zero-code error is always positive in the
AD5601/AD5611/AD5621 because the output of the DAC cannot
go below 0 V. Zero-code error is due to a combination of the
offset errors in the DAC and output amplifier. Zero-code error
is expressed in mV. See Figure 28 for a plot of zero-code error
vs. temperature.
Full-Scale Error
Full-scale error is a measure of the output error when full-scale
code (0xFFFF) is loaded to the DAC register. Ideally, the output
is VDD − 1 LSB. Full-scale error is expressed in mV. See Figure
28 for a plot of full-scale error vs. temperature.
Gain Error
Gain error is a measure of the span error of the DAC. It is the
deviation in slope of the DAC transfer characteristic from the
ideal, expressed as a percent of the full-scale range.
Rev. I | Page 13 of 21
AD5601/AD5611/AD5621
Total Unadjusted Error
Total unadjusted error (TUE) is a measure of the output error,
taking all the various errors into account. See Figure 8 to
Figure 10 for plots of typical TUE vs. code.
Zero-Code Error Drift
Zero-code error drift is a measure of the change in zero-code
error with a change in temperature. It is expressed in µV/°C.
Gain Temperature Coefficient
Gain temperature coefficient is a measure of the change in gain
error with changes in temperature. It is expressed in (ppm of
full-scale range)/°C.
Digital-to-Analog Glitch Impulse
Digital-to-analog glitch impulse is the impulse injected into the
analog output when the input code in the DAC register changes
state. It is normally specified as the area of the glitch in nV-s
and is measured when the digital input code is changed by
1 LSB at the major carry transition (0x2000 to 0x1FFF). See
Figure 19.
Digital Feedthrough
Digital feedthrough is a measure of the impulse injected into
the analog output of the DAC from the digital inputs of the
DAC, but is measured when the DAC output is not updated.
It is specified in nV-s and is measured with a full-scale code
change on the data bus—from all 0s to all 1s and vice versa.
AD5601/AD5611/AD5621 Data Sheet

THEORY OF OPERATION
DAC SECTION OUTPUT AMPLIFIER
The AD5601/AD5611/AD5621 DACs are fabricated on a The output buffer amplifier is capable of generating rail-to-rail
CMOS process. The architecture consists of a string DAC voltages on its output, giving an output range of 0 V to VDD. It is
followed by an output buffer amplifier. Figure 39 is a block capable of driving a load of 2 kΩ in parallel with 1000 pF to
diagram of the DAC architecture. GND. The source and sink capabilities of the output amplifier
VDD are shown in Figure 25. The slew rate is 0.5 V/µs, with a half-
scale settling time of 8 µs with the output loaded.
REF (+)
RESISTOR
SERIAL INTERFACE
DAC REGISTER VOUT
NETWORK
The AD5601/AD5611/AD5621 have a 3-wire serial interface
REF (–)
OUTPUT
AMPLIFIER
(SYNC, SCLK, and SDIN) that is compatible with SPI, QSPI,
and MICROWIRE interface standards as well as most DSPs. See

06853-038
GND
Figure 2 for a timing diagram of a typical write sequence.
Figure 39. DAC Architecture The write sequence begins by bringing the SYNC line low. Data
Because the input coding to the DAC is straight binary, the ideal from the SDIN line is clocked into the 16-bit shift register on
output voltage is given by the falling edge of SCLK. The serial clock frequency can be as
high as 30 MHz, making the AD5601/AD5611/AD5621 com-
D patible with high speed DSPs. On the 16th falling clock edge,
VOUT = VDD ×  n 
2  the last data bit is clocked in and the programmed function is
where: executed (a change in DAC register contents and/or a change
D is the decimal equivalent of the binary code that is loaded to in the mode of operation). At this stage, the SYNC line can be
the DAC register. kept low or brought high. In either case, it must be brought high
n is the bit resolution of the DAC. for a minimum of 20 ns before the next write sequence so that a
falling edge of SYNC can initiate the next write sequence.
RESISTOR STRING
Because the SYNC buffer draws more current when VIN = 1.8 V
The resistor string structure is shown in Figure 40. It is simply a
than it does when VIN = 0.8 V, idle the SYNC buffer low between
string of resistors, each of Value R. The code loaded to the DAC
register determines at which node on the string the voltage is write sequences for even lower power operation of the device, as
tapped off to be fed into the output amplifier. The voltage is mentioned previously. However, it must be brought high again
tapped off by closing one of the switches connecting the string just before the next write sequence.
to the amplifier. Because it is a string of resistors, it is guaran- INPUT SHIFT REGISTER
teed monotonic. The input shift register is 16 bits wide (see Figure 41). The first
two bits are control bits, which control the operating mode of
R the part (normal mode or any one of three power-down
modes). For a complete description of the various modes, see
the Power-Down Modes section. For the AD5621, the next
R
12 bits are the data bits, which are transferred to the DAC
register on the 16th falling edge of SCLK. The information in
R TO OUTPUT
AMPLIFIER
the last two bits is ignored by the AD5621. See Figure 42 and
Figure 43 for the AD5611 and AD5601 input shift register map.
SYNC INTERRUPT
In a normal write sequence, the SYNC line is kept low for at
least 16 falling edges of SCLK and the DAC is updated on the
16th falling edge. However, if SYNC is brought high before the
R
16th falling edge, this acts as an interrupt to the write sequence.
The shift register is reset and the write sequence is seen as
R invalid. Neither an update of the DAC register contents nor a
change in the operating mode occurs (see Figure 44).
06853-039

Figure 40. Resistor String Structure

Rev. I | Page 14 of 21
Data Sheet AD5601/AD5611/AD5621
DB15 (MSB) DB0 (LSB)

PD1 PD0 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 X X

DATA BITS

0 0 NORMAL OPERATION
0 1 1kΩ TO GND
POWER-DOWN MODES

06853-040
1 0 100kΩ TO GND
1 1 THREE-STATE

Figure 41. AD5621 Input Register Contents

DB15 (MSB) DB0 (LSB)

PD1 PD0 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 X X X X

DATA BITS

0 0 NORMAL OPERATION
0 1 1kΩ TO GND
POWER-DOWN MODES

06853-041
1 0 100kΩ TO GND
1 1 THREE-STATE

Figure 42. AD5611 Input Register Contents

DB15 (MSB) DB0 (LSB)

PD1 PD0 D8 D7 D6 D5 D4 D3 D2 D1 X X X X X X

DATA BITS

0 0 NORMAL OPERATION
0 1 1kΩ TO GND
POWER-DOWN MODES 06853-042
1 0 100kΩ TO GND
1 1 THREE-STATE

Figure 43. AD5601 Input Register Contents

SCLK

SYNC
06853-043

SDIN DB15 DB0 DB15 DB0

INVALID WRITE SEQUENCE: VALID WRITE SEQUENCE, OUTPUT UPDATES

SYNC HIGH BEFORE 16TH FALLING EDGE ON THE 16TH FALLING EDGE

Figure 44. SYNC Interrupt Facility

Rev. I | Page 15 of 21
AD5601/AD5611/AD5621 Data Sheet
POWER-ON RESET MICROPROCESSOR INTERFACING
The AD5601/AD5611/AD5621 contain a power-on reset circuit AD5601/AD5611/AD5621 to ADSP-BF531 Interface
that controls the output voltage during power-up. The DAC Figure 46 shows a serial interface between the AD5601/AD5611/
register is filled with 0s and the output voltage is 0 V. It remains AD5621 and the ADSP-BF531. The ADSP-BF531 processor has
there until a valid write sequence is made to the DAC. This is an integrated SPI port that can connect directly to the SPI pins of
useful in applications in which it is important to know the state the AD5601/AD5611/AD5621.
of the DAC output while it is in the process of powering up.
POWER-DOWN MODES
The AD5601/AD5611/AD5621 have four separate modes of
operation. These modes are software-programmable by setting
two bits (DB15 and DB14) in the control register. Table 6 shows
how the state of the bits corresponds to the operating mode of
the device.

Table 6. Operating Modes of the AD5601/AD5611/AD5621

Figure 46. AD5601/AD5611/AD5621 to ADSP-BF531 Interface
DB15 DB14 Operating Mode
0 0 Normal operation AD5601/AD5611/AD5621 to 68HC11/68L11 Interface
Power-down modes: Figure 47 shows a serial interface between the AD5601/
0 1 1 kΩ to GND AD5611/AD5621 and the 68HC11/68L11 microcontroller. SCK
1 0 100 kΩ to GND of the 68HC11/68L11 drives the SCLK of the AD5601/AD5611/
1 1 Three-state AD5621, while the MOSI output drives the serial data line of
the DAC. The SYNC signal is derived from a port line (PC7).
When both bits are set to 0, the part has normal power
The setup conditions for proper operation of this interface are
consumption of 100 μA maximum at 5 V. However, for the
as follows: the 68HC11/68L11 must be configured so that the
three power-down modes, the supply current falls to typically
CPOL bit is 0 and the CPHA bit is 1. When data is being trans-
0.2 μA at 3 V.
mitted to the DAC, the SYNC line is taken low (PC7). When the
Not only does the supply current fall, but the output stage is 68HC11/68L11 are configured as indicated, data appearing on
also internally switched from the output of the amplifier to a the MOSI output is valid on the falling edge of SCK. Serial data
resistor network of known values. This has the advantage that from the 68HC11/68L11 is transmitted in 8-bit bytes with only
the output impedance of the part is known while the part is in eight falling clock edges occurring in the transmit cycle. Data is
power-down mode. transmitted MSB first. To load data to the AD5601/AD5611/
There are three different options: the output is connected AD5621, PC7 is left low after the first eight bits are transferred
internally to GND through a 1 kΩ resistor or a 100 kΩ resistor, and a second serial write operation is performed to the DAC.
or the output is left open-circuited (three-stated). Figure 45 PC7 is taken high at the end of this procedure.
shows the output stage.
68HC11/ AD5601/AD5611/
68L11* AD5621*
RESISTOR AMPLIFIER
STRING DAC VOUT PC7 SYNC
SCK SCLK
06853-046

MOSI SDIN

POWER-DOWN
CIRCUITRY RESISTOR *ADDITIONAL PINS OMITTED FOR CLARITY
NETWORK
06853-044

Figure 47. AD5601/AD5611/AD5621 to 68HC11/68L11 Interface

Figure 45. Output Stage During Power-Down

The bias generator, output amplifier, resistor string, and other

associated linear circuitry are all shut down when power-down
mode is activated. However, the contents of the DAC register
are unaffected when in power-down. The time to exit power-
down is typically 13 μs for VDD = 5 V and 16 μs for VDD = 3 V.
See Figure 21 for a plot.

Rev. I | Page 16 of 21
Data Sheet AD5601/AD5611/AD5621
AD5601/AD5611/AD5621 to Blackfin® ADSP-BF53x and a second write cycle is initiated to transmit the second byte
Interface of data. P3.3 is taken high following the completion of this
Figure 48 shows a serial interface between the AD5601/AD5611/ cycle. The 80C51/80L51 output the serial data LSB first. The
AD5621 and the Blackfin ADSP-BF53x microprocessor. The AD5601/AD5611/AD5621 require data with the MSB as the
ADSP-BF53x processor family incorporates two dual-channel first bit received. The 80C51/80L51 transmit routine must take
synchronous serial ports, SPORT1 and SPORT0, for serial and this into account.
multiprocessor communications. Using SPORT0 to connect to
80C51/80L51* AD5601/AD5611/
the AD5601/AD5611/AD5621, the setup for the interface is as AD5621*
follows: DT0PRI drives the SDIN pin of the AD5601/AD5611/
AD5621, while TSCLK0 drives the SCLK of the part. The SYNC P3.3 SYNC
TxD SCLK
is driven from TFS0.

06853-048
RxD SDIN

ADSP-BF53x* AD5601/AD5611/
AD5621* *ADDITIONAL PINS OMITTED FOR CLARITY

DT0PRI SDIN
Figure 49. AD5601/AD5611/AD5621 to 80C51/80L51 Interface
TSCLK0 SCLK AD5601/AD5611/AD5621 to MICROWIRE Interface
06853-047
TFS0 SYNC
Figure 50 shows an interface between the AD5601/AD5611/
AD5621 and any MICROWIRE-compatible device. Serial data
*ADDITIONAL PINS OMITTED FOR CLARITY
is shifted out on the falling edge of the serial clock and is
Figure 48. AD5601/AD5611/AD5621 to Blackfin ADSP-BF53x Interface clocked into the AD5601/AD5611/AD5621 on the rising edge
AD5601/AD5611/AD5621 to 80C51/80L51 Interface of the SK.
Figure 49 shows a serial interface between the AD5601/ MICROWIRE* AD5601/AD5611/
AD5611/AD5621 and the 80C51/80L51 microcontroller. The AD5621*
setup for the interface is as follows: TxD of the 80C51/80L51
CS SYNC
drives SCLK of the AD5601/AD5611/AD5621, while RxD
SK SCLK
drives the serial data line of the part. The SYNC signal is again

06853-049
SO SDIN
derived from a bit programmable pin on the port. In this case,
Port Line P3.3 is used. When data is to be transmitted to the
*ADDITIONAL PINS OMITTED FOR CLARITY
AD5601/AD5611/AD5621, P3.3 is taken low. The 80C51/80L51
Figure 50. AD5601/AD5611/AD5621 to MICROWIRE Interface
transmit data only in 8-bit bytes; therefore, only eight falling
clock edges occur in the transmit cycle. To load data to the
DAC, P3.3 is left low after the first eight bits are transmitted,

Rev. I | Page 17 of 21
AD5601/AD5611/AD5621 Data Sheet

APPLICATIONS INFORMATION
CHOOSING A REFERENCE AS POWER SUPPLY FOR BIPOLAR OPERATION USING THE
THE AD5601/AD5611/AD5621 AD5601/AD5611/AD5621
The AD5601/AD5611/AD5621 come in tiny LFCSP and SC70 The AD5601/AD5611/AD5621 have been designed for single-
packages with less than a 100 µA supply current. Because of this, supply operation, but a bipolar output range is also possible
the choice of reference depends on the application requirements. using the circuit shown in Figure 52. The circuit in Figure 52
For applications with space-saving requirements, the ADR02 gives an output voltage range of ±5 V. Rail-to-rail operation at
is recommended. It is available in an SC70 package and has the amplifier output is achievable using an AD820 or OP295 as
excellent drift at 9 ppm/°C (3 ppm/°C in the R-8 package) and the output amplifier.
provides very good noise performance at 3.4 µV p-p in the R2 = 10kΩ
0.1 Hz to 10 Hz range.
+5V
Because the supply current required by the AD5601/AD5611/ +5V R1 = 10kΩ

AD5621 is extremely low, the parts are ideal for low supply AD820/
+5V
OP295
applications. The ADR395 voltage reference is recommended in V VOUT
DD
this case. It requires less than 100 µA of quiescent current and 10µF 0.1µF AD5601/AD5611/
can, therefore, drive multiple DACs in one system, if required. AD5621 –5V

It also provides very good noise performance at 8 µV p-p in the

0.1 Hz to 10 Hz range. 3-WIRE

06853-051
SERIAL
7V INTERFACE
5V Figure 52. Bipolar Operation with the AD5601/AD5611/AD5621
ADR395
The output voltage for any input code can be calculated as

VOUT = VDD ×  N
D   R1 + R2  − V ×  R2 
×  DD  
 R1 
3-WIRE SYNC VOUT = 0V TO 5V
SERIAL SCLK
AD5601/AD5611/
  2   R1 
INTERFACE AD5621
SDIN
06853-050

where D represents the input code in decimal (0 – 2N).

Figure 51. ADR395 as Power Supply to the AD5601/AD5611/AD5621 With VDD = 5 V, R1 = R2 = 10 kΩ

Some recommended precision references for use as supplies to  10 × D 

VOUT =  N  − 5 V
the AD5601/AD5611/AD5621 are listed in Table 7.  2 

Table 7. Precision References for the AD5601/AD5611/AD5621 This is an output voltage range of ±5 V, with 0x0000 corre-
Initial
sponding to a −5 V output and 0x3FFF corresponding to a
Accuracy Temp Drift 0.1 Hz to 10 Hz +5 V output.
Part No. (mV max) (ppm/°C max) Noise (µV p-p typ)
ADR435 ±2 3 (R-8) 8
ADR425 ±2 3 (R-8) 3.4
ADR02 ±3 3 (R-8) 10
ADR02 ±3 3 (SC70) 10
ADR395 ±5 9 (TSOT-23) 8

Rev. I | Page 18 of 21
Data Sheet AD5601/AD5611/AD5621
USING THE AD5601/AD5611/AD5621 WITH A POWER SUPPLY BYPASSING AND GROUNDING
GALVANICALLY ISOLATED INTERFACE When accuracy is important in a circuit, it is helpful to carefully
In process control applications in industrial environments, consider the power supply and ground return layout on the
it is often necessary to use a galvanically isolated interface to board. The PCB containing the AD5601/AD5611/AD5621 must
protect and isolate the controlling circuitry from any hazardous have separate analog and digital sections, each having its own
common-mode voltages that might occur in the area where the area of the board. If the AD5601/AD5611/AD5621 are in a
DAC is functioning. iCoupler® provides isolation in excess of system where other devices require an AGND-to-DGND
2.5 kV. Because the AD5601/AD5611/AD5621 use a 3-wire serial connection, the connection must be made at one point only.
logic interface, the ADuM1300 3-channel digital isolator This ground point must be as close as possible to the
provides the required isolation (see Figure 53). The power AD5601/AD5611/AD5621.
supply to the part also needs to be isolated, which is done by Bypass the power supply to the AD5601/AD5611/AD5621 with
using a transformer. On the DAC side of the transformer, a 5 V 10 μF and 0.1 μF capacitors. The capacitors must be physically
regulator provides the 5 V supply required for the AD5601/ as close as possible to the device, with the 0.1 μF capacitor ideally
AD5611/AD5621. right up against the device. The 10 μF capacitors are the tantalum
5V bead type. It is important that the 0.1 μF capacitor have low
REGULATOR
POWER 10µF 0.1µF effective series resistance (ESR) and effective series inductance
(ESI), such as in common ceramic types of capacitors. This 0.1 μF
capacitor provides a low impedance path to ground for high
VDD
frequencies caused by transient currents due to internal logic
switching.
SCLK VIA VOA SCLK
The power supply line itself must have as large a trace as possible to
ADuM1300 AD5601/ provide a low impedance path and reduce glitch effects on the
AD5611/ supply line. Shield clocks and other fast switching digital signals
VOUT
SDI VIB VOB SYNC AD5621
from other parts of the board by digital ground. Avoid crossover of
digital and analog signals, if possible. When traces cross on oppo-
DATA VIC VOC SDIN site sides of the board, ensure that they run at right angles to
each other to reduce feedthrough effects on the board. The best
06853-052

GND board layout technique is the microstrip technique, where the

component side of the board is dedicated to the ground plane
Figure 53. AD5601/AD5611/AD5621 with a Galvanically Isolated Interface only and the signal traces are placed on the solder side. However,
this is not always possible with a two-layer board.

Rev. I | Page 19 of 21
AD5601/AD5611/AD5621 Data Sheet

OUTLINE DIMENSIONS
2.20
2.00
1.80

1.35 6 5 4 2.40
1.25 2.10
1.15 1 2 3 1.80

0.65 BSC
1.30 BSC

1.00 0.40
1.10
0.90 0.10
0.80
0.70

0.46
SEATING 0.22
0.10 MAX 0.30 0.36
PLANE 0.08
COPLANARITY 0.15 0.26
0.10

072809-A
COMPLIANT TO JEDEC STANDARDS MO-203-AB

Figure 54. 6-Lead Thin Shrink Small Outline Transistor Package [SC70]
(KS-6)
Dimensions shown in millimeters

DETAIL A
(JEDEC 95)
1.50
2.10 1.40
2.00 1.30
1.90 0.65 REF
4 6 0.20 MIN

3.10 EXPOSED 1.70

3.00 PAD
1.60
2.90 1.50
PIN 1 INDEX 0.45
AREA 0.40
0.35
3 1
TOP VIEW BOTTOM VIEW P IN 1
IN D IC ATO R AR E A OP T IO N S
(SEE DETAIL A)

0.80 0.203 REF FOR PROPER CONNECTION OF

0.05 MAX THE EXPOSED PAD, REFER TO
0.75 SIDE VIEW
0.00 MIN THE PIN CONFIGURATION AND
0.70 FUNCTION DESCRIPTIONS
SECTION OF THIS DATA SHEET.
SEATING 0.35
COPLANARITY
PLANE 0.30 0.08
08-17-2018-B

0.25
PKG-003859

COMPLIANT TO JEDEC STANDARDS MO-229

Figure 55. 6-Lead Lead Frame Chip Scale Package [LFCSP]

2.00 × 3.00 mm Body and 0.75 mm Package Height
(CP-6-5)
Dimensions shown in millimeters

Rev. I | Page 20 of 21
Data Sheet AD5601/AD5611/AD5621
ORDERING GUIDE
Temperature Package
Model1 Range INL Package Description Option Branding
AD5601BKSZ-500RL7 –40°C to +125°C ±0.5 LSB 6-Lead Thin Shrink Small Outline Transistor Package [SC70] KS-6 D3V
AD5601BKSZ-REEL7 –40°C to +125°C ±0.5 LSB 6-Lead Thin Shrink Small Outline Transistor Package [SC70] KS-6 D3V
AD5601BCPZ-RL7 –40°C to +125°C ±0.5 LSB 6-Lead Lead Frame Chip Scale Package [LFCSP] CP-6-5 89
AD5611AKSZ-500RL7 –40°C to +125°C ±4.0 LSB 6-Lead Thin Shrink Small Outline Transistor Package [SC70] KS-6 D3U
AD5611AKSZ-REEL7 –40°C to +125°C ±4.0 LSB 6-Lead Thin Shrink Small Outline Transistor Package [SC70] KS-6 D3U
AD5611ACPZ-RL7 –40°C to +125°C ±4.0 LSB 6-Lead Lead Frame Chip Scale Package[LFCSP] CP-6-5 8B
AD5611BKSZ-500RL7 –40°C to +125°C ±0.5 LSB 6-Lead Thin Shrink Small Outline Transistor Package [SC70] KS-6 D3T
AD5611BKSZ-REEL7 –40°C to +125°C ±0.5 LSB 6-Lead Thin Shrink Small Outline Transistor Package [SC70] KS-6 D3T
AD5621AKSZ-500RL7 –40°C to +125°C ±6.0 LSB 6-Lead Thin Shrink Small Outline Transistor Package [SC70] KS-6 D3S
AD5621AKSZ-REEL7 –40°C to +125°C ±6.0 LSB 6-Lead Thin Shrink Small Outline Transistor Package [SC70] KS-6 D3S
AD5621ACPZ-RL7 –40°C to +125°C ±6.0 LSB 6-Lead Lead Frame Chip Scale Package[LFCSP] CP-6-5 D3S
AD5621BKSZ-500RL7 –40°C to +125°C ±1.0 LSB 6-Lead Thin Shrink Small Outline Transistor Package [SC70] KS-6 D3R
AD5621BKSZ-REEL7 –40°C to +125°C ±1.0 LSB 6-Lead Thin Shrink Small Outline Transistor Package [SC70] KS-6 D3R
EVAL-AD5621EBZ Evaluation Board
1
Z = RoHS Compliant Part.

©2005–2019 Analog Devices, Inc. All rights reserved. Trademarks and

registered trademarks are the property of their respective owners.
D06853-0-4/19(I)

Rev. I | Page 21 of 21
Mouser Electronics

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EVAL-AD5621EBZ AD5611BKSZ-REEL7 AD5611AKSZ-500RL7 AD5601BKSZ-500RL7 AD5611AKSZ-REEL7
AD5601BKSZ-REEL7 AD5621AKSZ-REEL7 AD5621BKSZ-REEL7 AD5611ACPZ-RL7 AD5601BCPZ-RL7
AD5621AKSZ-500RL7 AD5621BKSZ-500RL7 AD5611BKSZ-500RL7 AD5621ACPZ-RL7