APA2051

2.4W Stereo Audio Power Amplifier (with Gain Setting) & Capfree Headphone Driver

Features General Description

• Operating Voltage
– HVDD= 3.0~3.6V
– VDD= 4.5~5.5V
• No Output Capacitor at Headphone Amplifier
Required
• Meeting VISTA Requirement
• Low Distortion
AMP Mode
– THD+N=56dB, at VDD = 5V, RL = 4Ω, PO=1.5W
– THD+N=64dB, at VDD = 5V, RL = 8Ω, PO=0.9W
HP Mode
– THD+N=73dB, at HVDD=3.3V, RL=16Ω
PO=125mW
– THD+N=77dB, at HVDD=3.3V, RL=32Ω,
PO=88mW
– THD+N=85dB, at HVDD=3.3V, RL=10kΩ,
VO=1.7Vrms
• Output Power at 1% THD+N
– 1.9W, at VDD = 5V, AMP Mode, RL = 4Ω
– 1.2W, at VDD = 5V, AMP Mode, RL = 8Ω
• at 10% THD+N
–2.4W at VDD = 5V, AMP Mode, RL = 4Ω
–1.5W at VDD = 5V, AMP Mode, RL = 8Ω
• Depop Circuitry Integrated
• Internal 19-Steps Gain Setting for Flexible Appli
cation
• Thermal Shutdown Protection and Over-Current
Protection Circuitry
• High Supply Voltage Ripple Rejection
• Surface-Mount Packaging
– TQFN4x4-28 (with Enhanced Thermal Pad)
• Lead Free and Green Devices Available
(RoHS Compliant)
The APA2051 is a monolithic integrated circuit, which
combines a stereo power amplifier and a stereo output
capacitor-less headphone amplifier. The stereo power
amplifier provides 19-steps gain setting for flexible
application. The headphone amplifier is ground-refer-
ence output, and no need the output capacitors for DC
blocking. The advantages of eliminating the output ca-
pacitor are saving cost, PCB’s space, and component
height.
Both the de-pop circuitry and the thermal shutdown pro-
tection circuitry are integrated in the APA2051, which re-
duces pops and clicks noise during power on/off and in
shutdown mode. Thermal shutdown protects the chip
from being destroyed by over-temperature failure. To sim-
plify the audio system design in notebook computer
applications, the APA2051 provides the internal gain
setting, and these features can minimize components
and PCB area.
The APA2051 is available in TQFN4x4-28 package. This
package is characterized by space saving and thermal
efficiency.
Simplified Application Circuit
Stereo
Speakers
Audio Codec
Stereo
Headphone

Applications
• Note Book PCs
• LCD Monitor

ANPEC reserves the right to make changes to improve reliability or manufacturability without notice, and
advise customers to obtain the latest version of relevant information to verify before placing orders.

Copyright  ANPEC Electronics Corp. 1 www.anpec.com.tw

Rev. A.4 - Aug., 2009

Free Datasheet http://www.datasheet4u.com/

APA2051

Ordering and Marking Information

APA2051 Package Code
QB : TQFN4x4-28
Assembly Material Operating Ambient Temperature Range
Handling Code I : -40 to 85 oC
Handling Code
Temperature Range
TR : Tape & Reel
Package Code Assembly Material
G : Halogen and Lead Free Device

APA2051 QB : APA2051 XXXXX - Date Code

XXXXX

Note: ANPEC lead-free products contain molding compounds/die attach materials and 100% matte tin plate termination finish; which
are fully compliant with RoHS. ANPEC lead-free products meet or exceed the lead-free requirements of IPC/JEDEC J-STD-020D for
MSL classification at lead-free peak reflow temperature. ANPEC defines “Green” to mean lead-free (RoHS compliant) and halogen
free (Br or Cl does not exceed 900ppm by weight in homogeneous material and total of Br and Cl does not exceed 1500ppm by
weight).

Pin Configuration
19 ROUT+
21 HP_EN

18 ROUT-
20 PGND

15 HVDD
17 PVDD
16 HP_L

BIAS 22 14 NC
SET 23 13 HP_R
AMP_EN 24 12 VSS
VDD 25 APA2051 11 CP-
GND 26 10 CGND
INR_A 27 9 CP+
INR_H 28 8 CVDD
INL_A 1
INL_H 2
NC 3
PGND 4
LOUT+ 5
LOUT- 6
PVDD 7

(TQFN4X4-28)
(Top view)

Absolute Maximum Ratings (Note 1)

(Over operating free-air temperature range unless otherwise noted.)
Symbol Parameter Rating Unit
VDD Supply Voltage (PVDD, CVDD, VDD) V
-0.3 to 6
HVDD, Supply Voltage (HVDD)
VSS Supply Voltage (VSS) +0.3 to -6 V
VSET, VAMP_EN,
Input Voltage 0 to VDD+0.3V
VHP_EN
TA Operating Ambient Temperature Range -40 to 85 °C
TJ Maximum Junction Temperature 150 °C
TSTG Storage Temperature Range -65 to +150 °C
TSDR Maximum Lead Soldering Temperature, 10 Seconds 260 °C
PD Power Dissipation Internally Limited W
Note 1 : Absolute Maximum Ratings are those values beyond which the life of a device may be impaired. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.

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Rev. A.4 - Aug., 2009

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APA2051

Thermal Characteristics
Symbol Parameter Typical Value Unit
(Note 2)
Thermal Resistance - Junction to Ambient
θJA
o
45 C/W
TQFN4x4-28
Note 2 : 3.42 in2 printed circuit board with 2OZ trace and copper through 10 vias of 15mil diameter vias. The thermal pad on the TQFN4x4-
28 packages with solder on the printed circuit board.

Recommended Operating Conditions

Symbol Parameter Range Unit
VDD Supply Voltage 4.5 ~ 5.5 V
HVDD Supply Voltage 3.0 ~ 3.6 V
VIH High Level Threshold Voltage AMP_EN, HP_EN 2~ V
VIL Low Level Threshold Voltage AMP_EN, HP_EN ~ 0.8 V
for Amplifier ~ VDD-1
Vicm Common Mode Input Voltage V
for Headphone Amplifier ~ HVDD-1
Shutdown ~ 0.8
VSET Input Voltage Gain Setting 2 ~ 4.2 V
Fix Gain 4.5 ~ V

Electrical Characteristics
VDD = 5V, HVDD = 3.3V, GND = PGND = CPGND = 0V, TA= 25°C (unless otherwise noted).

APA2051
Symbol Parameter Test Conditions Unit
Min. Typ. Max.
VDD Supply Voltage 4.5 - 5.5 V
Headphone Amplifier Supply
HVDD 3.0 - 3.6 V
Voltage
IVDD VDD Supply Current Only Speaker mode, - 17.5 29
IHVDD HVDD Supply Current AMP_EN = HP_EN = 0V - 0.15 1
IVDD VDD Supply Current Only Headphone mode, - 12 20
mA
IHVDD HVDD Supply Current HP_EN = AMP_EN = 5V - 3 5
IVDD VDD Supply Current All Enable, HP_EN=5V and - 20 35
AMP_EN = 0V
IHVDD HVDD Supply Current - 3 5
ISD(HVDD) HVDD Shutdown Current - 50 90 µA
SET = 0V
ISD(VDD) VDD Shutdown Current - 1 10
IAMP_EN Input Current AMP_EN - 1 - µA
IHP_EN Input Current HP_EN - 10 15 µA
SPEAKER MODE
THD+N =1%, fin =1kHz
RL =4Ω 1.9 -
RL =8Ω 1.0 1.2
PO Output Power W
THD+N =10%, fin =1kHz
RL =4Ω 2.4 -
RL =8Ω 1.3 1.5
VOS Output Offset Voltage RL =8Ω, Gain =10.5dB - - 10 mV

Copyright  ANPEC Electronics Corp. 3 www.anpec.com.tw

Rev. A.4 - Aug., 2009

Free Datasheet http://www.datasheet4u.com/

APA2051

Electrical Characteristics (Cont.)

VDD = 5V, HVDD = 3.3V, GND = PGND = CPGND = 0V, TA= 25°C (unless otherwise noted).

APA2051
Symbol Parameter Test Conditions Unit
Min. Typ. Max.
SPEAKER MODE (CONT.)
fin =1kHz
Total Harmonic Distortion Plus
THD+N PO = 1.5W, RL =4Ω - 0.15 - %
Noise
PO = 0.9W, RL =8Ω 0.06
fin =1kHz, CB=2.2µF, RL=8Ω, PO=0.92W - 80 - dB
Crosstalk Channel Separation
fin =1kHz, CB=2.2µF, RL =4Ω, PO=1.5W - 83 -
PSRR Power Supply Rejection Ratio CB =2.2µF, RL =8Ω, fin =120Hz - 70 - dB
S/N PO =0.8W, RL =8Ω, A-weighting Filter - 90 - dB
µV
Vn Noise Output Voltage Gain =10.5dB, RL =8Ω, CB =2.2µF - 80 -
(rms)
HEADPHONE MODE
THD+N = 1%, fin =1kHz
RL = 16Ω 160 -
RL = 32Ω 100 120
Po Output Power mW
THD+N = 10%, fin =1kHz
RL =16Ω 200 -
RL =32Ω 150 165
THD+N=10% - 2.9 -
Vo Output Voltage Swing RL =10kΩ Vrms
THD+N=1% - 2.4 -
Vos Output Offset Voltage RL =32Ω -10 +10 mV
fin = 1kHz
Total Harmonic Distortion Plus PO = 125mW, RL =16Ω 0.02
THD+N - - %
Noise PO = 88mW, RL =32Ω 0.02
VO=1.7Vrms, RL=10kΩ 0.005
fin =1kHz, RL =16Ω, PO =125mW - 80 -
Crosstalk Channel Separation fin =1kHz, RL =32Ω, PO =88mW - 85 - dB
fin =1kHz, RL=10kΩ, VO =1.7Vrms - 105 -
PSRR Power Supply Rejection Ratio CB = 2.2µF, RL=32Ω, fin =120Hz - 80 - dB
With A-weighting Filter
S/N PO = 70mW, RL =32Ω 95 - dB
VO =1.2Vrms, RL=10kΩ 92
µV
Vn Noise Output Voltage CB =2.2µF - 30 -
(rms)
Rf Input Feedback Resistance 38 40 42 kΩ
CHARGE PUMP
Fosc Switching Frequency 460 540 620 kHz
-0.98
CVSS Charge Dump (CVSS) No load - - V
VDD
Charge Pump Requirement
Req - 9 12 Ω
Resistance

Copyright  ANPEC Electronics Corp. 4 www.anpec.com.tw

Rev. A.4 - Aug., 2009

Free Datasheet http://www.datasheet4u.com/

APA2051

Electrical Characteristics (Cont.)

VDD = 5V, HVDD = 3.3V, GND = PGND = CPGND = 0V, TA= 25°C (unless otherwise noted).

APA2051
Symbol Parameter Test Conditions Unit
Min. Typ. Max.
ATTENUATION
RL = 32Ω, VO = 1.1Vrms, fin = 1kHz - 115 - dB
Att (HP_EN) HP Disable Attenuation
RL = 10kΩ, VO = 1.1Vrms, fin = 1kHz - 85 - dB

AMP Disable RL = 8Ω, VO = 2Vrms, fin = 1kHz - 112 - dB

Att (AMP_EN) Attenuation RL = 4Ω, VO = 2Vrms, fin = 1kHz - 112 - dB
RL = 10kΩ on the Headphone Mode,
Att_SD (HP_EN) Shutdown Active - 90 - dB
VO = 1.1Vrms, fin = 1kHz
RL = 8Ω on the AMP Mode, VO = 1Vrms,
Att_SD(AMP_EN) Shutdown Active - 100 - dB
fin = 1kHz
HEADPHONE TO SPEAKER CROSSTALK
AMP_EN = 0V, RL = 8Ω
Crosstalk Channel Separation HP_EN = 5V, RL = 16Ω, fin = 1kHz, - 85 - dB
PO = 125mW
SPEAKER TO HEADPHONE CROSSTALK
HP_EN = 5V, RL = 10kΩ
Crosstalk Channel Separation AMP_EN = 0V, RL = 4Ω, fin = 1kHz, - 80 - dB
PO = 1.5W
AMPLIFIER START-UP TIME
Tstart-up Start-Up Time - 120 - msec

Gain Setting Table _AMP Mode (VDD=5V)

Input Voltage (VSET) Recommended Voltage
Gain (dB) Hysteresis (mV)
Low (V) High (V) (V)

-70 0 2.00 SD 0.00

-7 2.04 2.12 47 2.08
-5 2.15 2.24 36 2.20
-3 2.28 2.35 41 2.31
-1 2.39 2.47 41 2.43
1 2.51 2.58 35 2.54
3 2.62 2.70 41 2.66
4 2.74 2.81 48 2.78
5 2.86 2.92 43 2.89
6 2.97 3.04 47 3.01
7 3.09 3.15 45 3.12
8 3.21 3.27 54 3.24
9 3.33 3.39 59 3.36
10 3.45 3.51 64 3.48
11 3.56 3.62 53 3.59
12 3.68 3.73 59 3.70
13 3.80 3.85 66 3.82

Copyright  ANPEC Electronics Corp. 5 www.anpec.com.tw

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APA2051

Gain Setting Table _AMP Mode (Cont.) (VDD=5V)

Input Voltage (VSET) Recommended Voltage
Gain (dB) Hysteresis (mV)
Low (V) High (V) (V)

14 3.92 3.96 69 3.94

15 4.02 4.07 64 4.05
16 4.15 4.17 76 4.16
10.5 4.26 5.00 94 5.00

Recommend Resistance’s Value for Gain Setting

Gain (dB) R1 (1%) R# (1%)
-70 10k 0
-7 18k 13k
-5 20k 16k
-3 18k 16k
-1 16k 15k
1 15k 16k
3 13k 15k
4 24k 30k
5 13k 18k
6 13k 20k
7 13k 22k
8 16k 30k
9 13k 27k
10 13k 30k
11 15k 39k
12 13k 39k
13 13k 43k
14 13k 50k
15 15k 68k
16 13k 68k
10.5 10k >90k

Copyright  ANPEC Electronics Corp. 6 www.anpec.com.tw

Rev. A.4 - Aug., 2009

Free Datasheet http://www.datasheet4u.com/

APA2051

Typical Operating Characteristics

THD+N vs. Output Power THD+N vs. Output Power

10 10
VDD =5V VDD =5V
fin=1kHz RL=4Ω
Cin=2.2µF Cin=2.2µF
BW<80kHz BW<80kHz
AMP mode AMP mode
THD+N (%)

THD+N (%)
RL=8Ω RL=4Ω
1
1

fin=20kHz
fin=20Hz

0.1
fin=1kHz

0.05 0.1
0 0.5 1 1.5 2 2.5 3 0.01 0.1 1 2 5
Output Power (W) Output Power (W)

THD+N vs. Frequency Crosstalk vs. Frequency

10 +0
VDD =5V
VDD =5V
RL=4Ω -10 RL=4Ω
Cin=2.2µF
Cin=2.2µF
PO=1.5W -20 PO=1.5W
BW<80kHz
AMP mode
AMP mode -30
Crosstalk (dB)

-40
THD+N (%)

1 -50
Right to Left
-60

-70
Left to Right
Right Channel -80

-90
Left Channel
0.1 -100
20 100 1k 10k 20k 20 100 1k 10k 20k
Frequency (Hz) Frequency (Hz)

Output Noise Voltage vs. Frequency Frequency Response

100µ +11 +30
Gain
Output Noise Voltage (Vrms)

+25
+10
VDD =5V
Cin =2.2µF +20
Phase (deg)

RL=4Ω
Gain (dB)

+9 PO=0.2W
+15
AMP mode
10µ
Phase +10
+8

+5
VDD =5V
RL=4Ω +7
Cin=2.2µF +0
A-weighting
AMP mode
1µ +6 -5
20 100 1k 10k 20k 10 100 1k 10k 100k 200k
Frequency (Hz) Frequency (Hz)

Copyright  ANPEC Electronics Corp. 7 www.anpec.com.tw

Rev. A.4 - Aug., 2009

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APA2051

Typical Operating Characteristics (Cont.)

THD+N vs. Output Power THD+N vs. Frequency

10 10
VDD =5V VDD =5V
RL=8Ω RL=8Ω
Cin=2.2µF Cin=2.2µF
BW<80kHz PO=0.92W
AMP mode BW<80kHz
AMP mode
THD+N (%)

THD+N (%)
1 1

fin=20kHz
fin=20Hz

Left Channel
0.1 fin=1kHz 0.1
Right Channel
0.05 0.05
0.01 0.1 1 5 20 100 1k 10k 20k
Output Power (W) Frequency (Hz)

Crosstalk vs. Frequency Output Noise Voltage vs. Frequency

+0 100µ
VDD =5V
-10 RL=8 Ω
Cin=2.2µF
Output Noise Voltage (Vrms)

-20 PO=0.92W
AMP mode
-30
Crosstalk (dB)

-40

-50 10µ

-60

-70
Left to Right VDD =5V
-80 RL=8Ω
Right to Left Cin=2.2µF
-90 A-weighting
AMP mode
-100 1µ
20 100 1k 10k 20k 20 100 1k 10k 20k
Frequency (Hz) Frequency (Hz)

Frequency Response Crosstalk vs. Frequency

+11 +30 +0
VDD =5V
Gain
-10 RL=4Ohm (AMP)
+25 RL=10kΩ(HP)
-20 Cin=2.2µF (AMP)
+10
VDD =5V -30 PO=1.5W(AMP)
Cin =2.2µF +20 AMP (active) mode
Phase (deg)

Crosstalk (dB)

RL=8Ω
-40 HP Mode
Gain (dB)

+9 PO=0.13W -50
AMP mode +15 Right(AMP) to Right(HP)
-60 Left(AMP) to Left(HP)
+10 -70 Left(AMP) to Right(HP)
+8
-80
+5
-90
Phase
+7 -100
+0
-110
Right(AMP) to Left(HP)
+6 -5 -120
10 100 1k 10k 100k 200k 20 100 1k 10k 20k

Frequency (Hz) Frequency (Hz)

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APA2051

Typical Operating Characteristics (Cont.)

AMP Attenuation vs. Frequency AMP Attenuation vs. Frequency

+0 +0
-10 VDD =5V VDD =5V
RL=4Ω -10 RL=8Ω
-20 Cin=2.2µF -20 Cin=2.2µF
VO=2Vrms(f in=1kHz, AMP enable) VO=2Vrms(f in=1kHz,AMP enable)
-30
AMP Attenuation (dB)

AMP Attenuation (dB)

AMP mode (disable) -30 AMP mode (disable)
-40 -40
-50 -50
-60 -60
-70 -70
-80 -80
-90 -90
-100 -100
-110 -110
-120 -120
20 100 1k 10k 20k 20 100 1k 10k 20k
Frequency (Hz) Frequency (Hz)

Shutdown Attenuation vs. Frequency Shutdown Attenuation vs. Frequency

+0 +0
VDD =5V VDD =5V
-10 RL=4Ω
-10 RL=8Ω
Cin=2.2µF Cin=2.2µF
-20 -20
Shutdown Attenuation (dB)

VO=1Vrms(fin=1kHz)
Shutdown Attenuation (dB)

VO=1Vrms(fin=1kHz)
-30 Shutdown active -30 Shutdown active
AMP mode AMP mode
-40 -40
-50 -50
-60 -60
-70 -70
-80 -80
-90 -90
-100 -100
-110 -110
-120 -120
20 100 1k 10k 20k 20 100 1k 10k 20k
Frequency (Hz) Frequency (Hz)

Input Voltage vs. Output Voltage Input Voltage vs. Output Voltage
3.5 4
VDD =5V VDD =5V
RL=4Ω RL=8Ω
3 3.5 Cin=2.2µF
Cin=2.2µF
fin=1kHz fin=1kHz
Output Voltage (Vrms)
Output Voltage (Vrms)

AMP mode 3 AMP mode

2.5
2.5
2
2
1.5
1.5

1 1

0.5 0.5

0 0.3 0.6 0.9 1.2 1.5 0 0.3 0.6 0.9 1.2 1.5
Input Voltage (Vrms) Input Voltage (Vrms)

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APA2051

Typical Operating Characteristics (Cont.)

THD+N vs. Output Voltage THD+N vs. Output Power

10 T 10
VDD =5V VDD =5V
HVDD=3.3V HVDD=3.3V
fin=1kHz RL=16Ω
Cin=3.3µF Rin=39kΩ
1 BW<80kHz RL=300Ω Cin=3.3µF
HP mode BW<80kHz
1 HP mode
THD+N (%)

THD+N (%)
RL=32Ω
0.1 fin=20kHz

RL=16Ω
0.1
0.01 fin=20Hz

RL=10kΩ
fin=1kHz
0.001 0.01
0 0.5 1 1.5 2 2.5 3 1m 10m 100m 300m
Output Voltage (Volt) Output Power (W)

THD+N vs. Output Power THD+N vs. Frequency

10 10
VDD=5V VDD =5V
HVDD=3.3V HVDD=3.3V
RL=16Ω RL=16Ω
Rin=39kΩ Rin=39kΩ
Cin=3.3µF Cin=3.3µF
fin=1kHz PO=125mW
1 BW<80kHz 1
HP mode
HP mode
THD+N (%)
THD+N (%)

Stereo, in phase BW<80kHz

0.1
0.1
Stereo, 180O
out of phase
BW<22kHz
Mono 0.01
0.01 0.005
0 50m 100m 150m 200m 250m 20 100 1k 10k 20k
Output Power (W) Frequency (Hz)

Crosstalk vs. Frequency Output Noise Voltage vs. Frequency

+0 100µ
VDD=5V
-10 HVDD=3.3V
Output Noise Voltage (Vrms)

RL=16Ω
-20 Rin=39kΩ Right channel
Cin=3.3µF
-30 PO=125mW
Crosstalk (dB)

HP mode
Left channel
-40

-50 10µ

-60
VDD =5V
-70 Right to Left HVDD =3.3V
RL=16Ω
-80 Rin=39kΩ
Left to Right Cin=3.3µF
-90 A-weighting
HP mode
-100 1µ
20 100 1k 10k 20k 20 100 1k 10k 20k
Frequency (Hz) Frequency (Hz)

Copyright  ANPEC Electronics Corp. 10 www.anpec.com.tw

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APA2051

Typical Operating Characteristics (Cont.)

Frequency Response THD+N vs. Output Power

+0.2 +190 10
VDD=5V
HVDD=3.3V
RL=32Ω
Rin=39kΩ
+0.1 Gain +185 Cin=3.3µF
BW<80kHz
1

Phase (deg)
HP mode

THD+N (%)
Gain(dB)

Phase
-0 +180

fin=20kHz
VDD=5V
HVDD=3.3V 0.1
-0.1 RL=16Ω +175
Rin=39kΩ
Cin=3.3µF fin=20Hz
PO=28mW
HP mode fin=1kHz
-0.2 +170 0.01
10 100 1k 10k 100k 200k 1m 10m 100m 200m

Frequency (Hz) Output Power (W)

THD+N vs. Output Power THD+N vs. Frequency

10 10
VDD=5V VDD=5V
HVDD=3.3V HVDD=3.3V
RL=32Ω RL=32Ω
Rin=39kΩ Rin=39kΩ
Cin=3.3µF 1 Cin=3.3µF
fin=1kHz PO=88mW
1 BW<80kHz HP mode
THD+N (%)
THD+N (%)

HP mode

0.1 BW<80kHz

0.1 Stereo, 180o

out of phase
Stereo, in phase 0.01 BW<22kHz

Mono

0.01 0.001
0 50m 100m 150m 200m 20 100 1k 10k 20k
Output Power (W) Frequency (Hz)

Crosstalk vs. Frequency Output Noise Voltage vs. Frequency

+0 100µ
VDD=5V
-10 HVDD=3.3V
RL=32Ω
Output Noise Voltage (V)

-20 Rin=39kΩ
Cin=3.3µF Right channel
-30 PO=88mW
Crosstalk (dB)

HP mode
Left channel
-40

-50 10µ

-60
VDD =5V
-70 Right to Left HVDD=3.3V
RL=32Ω
-80 Rin=39kΩ
Cin=3.3µF
Left to Right
-90 A-weighting
HP mode
-100 1µ
20 100 1k 10k 20k 20 100 1k 10k 20k
Frequency (Hz) Frequency (Hz)

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APA2051

Typical Operating Characteristics (Cont.)

Frequency Response THD+N vs. Output Voltage

+0.2 +190 10
Gain VDD=5V
HVDD=3.3V
RL=300Ω
Rin=39kΩ
+0.1 +185 1 Cin=3.3µF
BW<80kHz

Phase (deg)
HP mode

THD+N (%)
Gain (dB)

Phase
-0 +180 0.1

fin=20kHz
VDD =5V
HVDD=3.3V
-0.1 RL=32Ω +175 0.01 fin=20Hz
Rin=39kΩ
Cin=3.3µF
PO=13mW fin=1kHz
HP mode
-0.2 +170 0.001
10 100 1k 10k 100k 200k 0 0.5 1 1.5 2 2.5 3
Frequency (Hz) Output Voltage (Vrms)

THD+N vs. Frequency Crosstalk vs. Frequency

10 +0
VDD=5V VDD=5V
HVDD=3.3V -10 HVDD=3.3V
RL=300Ω -20 RL=300Ω
Rin=39kΩ Rin=39kΩ
1 Cin=3.3µF -30 Cin=3.3µF
VO=1.7Vrms VO=1.7Vrms
-40 BW<80kHz
Crosstalk (dB)

BW<80kHz
THD+N (%)

HP mode -50 HP mode

0.1 -60
-70
-80

0.01 Right Channel -90 Right to Left

-100
Left Channel -110 Left to Right
0.001 -120
20 100 1k 10k 20k 20 100 1k 10k 20k
Frequency (Hz) Frequency (Hz)

Output Noise Voltage vs. Frequency Frequency Response

100µ +0.4 +195
Output Noise Voltage (Vrms)

Gain
Right channel +0.2 +190
Phase (deg)

VDD =5V
Gain (dB)

HVDD=3.3V
Left channel
RL=300Ω
Rin=39kΩ
10µ +0 Cin=3.3µF +185
VO=240mVrms
HP mode
VDD =5V
HVDD=3.3V Phase
RL=300Ω -0.2 +180
Rin=39kΩ
Cin=3.3µF
A-weighting
HP mode
1µ -0.4 +175
20 100 1k 10k 20k 10 100 1k 10k 100k 200k
Frequency (Hz) Frequency (Hz)

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APA2051

Typical Operating Characteristics (Cont.)

THD+N vs. Output Voltage THD+N vs. Frequency

10 10
VDD =5V VDD =5V
HVDD=3.3V HVDD=3.3V
RL=10kΩ RL=10kΩ
Rin=39kΩ Rin=39kΩ
1 Cin=3.3µF Cin=3.3µF
BW<80kHz
1
VO=1.7Vrms
HP mode BW<80kHz
THD+N (%)

THD+N (%)
HP mode

0.1 0.1

fin=20Hz

0.01 fin=20kHz Right channel

0.01

fin=1kHz Left channel

0.001 0.001
0 0.5 1 1.5 2 2.5 3 20 100 1k 10k 20k
Output Voltage (Volt) Frequency (Hz)

Crosstalk vs. Frequency Output Noise Voltage vs. Frequency

+0 100µ
VDD=5V
-10 HVDD=3.3V
-20 RL=10kΩ
Output Noise Voltage (Vrms)

Rin=39kΩ
-30 Cin=3.3µF Right channel
-40 VO=1.7Vrms
Crosstalk (dB)

BW<80kHz Left channel

-50 HP mode
-60
10µ
-70
-80
Left to Right VDD=5V
-90 HVDD=3.3V
RL=10kΩ
-100 Right to Left Rin=39kΩ
-110 Cin=3.3µF
A-weighting
-120
HP mode
-130 1µ
20 100 1k 10k 20k 20 100 1k 10k 20k

Frequency (Hz) Frequency (Hz)

Frequency Response Crosstalk vs. Frequency

+0.4 +195 +0
VDD =5V
-10 HVDD=3.3V
Gain RL=16Ω (HP)
-20 RL=8Ω(AMP)
+0.2 +190 Rin=39kΩ(HP)
VDD=5V
Crosstalk (dB)

-30 Cin=3.3µF (HP)

Phase (deg)

HVDD=3.3V
Gain (dB)

PO=125mW(HP)
RL=10kΩ
-40 AMP (active) mode
Rin=39kΩ
HP Mode
+0 Cin=3.3µF +185 -50
VO=240mVrms
HP mode
-60
Phase Left (HP) to Left (AMP) Right (HP) to Left (AMP)
-70
-0.2 +180
-80

-90 Left (HP) to Right (AMP)

Right (HP) to Right (AMP)
-0.4 +175 -100
10 100 1k 10k 100k 200k 20 100 1k 10k 20k
Frequency (Hz) Frequency (Hz)

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APA2051

Typical Operating Characteristics (Cont.)

HP Attenuation vs. Frequency HP Attenuation vs. Frequency

+0 +0
VDD =5V VDD =5V
-10 HVDD=3.3V -10 HVDD=3.3V
RL=32Ω RL=10kΩ
-20 Cin=3.3µF Cin=3.3µF
-20
-30 VO=1Vrms(fin=1kHz HP enable) VO=1Vrms(f in=1kHz HP enable)
HP attenuation (dB)

HP attenuation (dB)
HP mode (disable) -30 HP mode (disable)
-40
-50 -40

-60 -50

-70 -60
-80
-70
-90
-80 Right channel Left channel
-100 Left channel
-90
-110 Right channel

-120 -100
20 100 1k 10k 20k 20 100 1k 10k 20k
Frequency (Hz) Frequency (Hz)

Shutdown Attenuation vs. Frequency Shutdown Attenuation vs. Frequency

+0 +0
VDD =5V VDD =5V
-10 HVDD=3.3V -10 HVDD=3.3V
-20 RL=32Ω RL=10kΩ
-20
Cin=3.3µF Cin=3.3µF
Shutdown attenuation (dB)

-30
Shutdown attenuation (dB)

VO=1Vrms(fin=1kHz) -30 VO=1Vrms(f in=1kHz)

-40 Shutdown active Shutdown active
-40
-50 HP mode HP mode
-50
-60
-60
-70
-70
-80
-90 -80
Left channel
-100 -90

-110 Left channel -100

-120 -110
-130 -120 Right channel
Right channel
-140 -130
20 100 1k 10k 20k 20 100 1k 10k 20k
Frequency (Hz) Frequency (Hz)

Input Voltage vs. Output Voltage Input Voltage vs. Output Voltage
2.5 3
VDD =5V VDD =5V
HVDD=3.3V HVDD=3.3V Mono
RL=16Ω Mono RL=32Ω
2.5
Rin=39kΩ
Output Voltage (Vrms)

2 Rin=39kΩ
Output Voltage (Vrms)

Cin=3µF Cin=3µF
fin=1kHz fin=1kHz
HP mode 2 HP mode
1.5 Stereo, in phase Stereo, in phase

1.5

1
1

0.5
0.5

0 0
0 0.5 1 1.5 2 2.5 0 0.5 1 1.5 2 2.5 3

Input Voltage (Vrms) Input Voltage (Vrms)

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APA2051

Typical Operating Characteristics (Cont.)

Input Voltage vs. Output Voltage Input Voltage vs. Output Voltage
3 3
VDD =5V VDD =5V
HVDD=3.3V HVDD=3.3V
Mono
RL=300Ω RL=10kΩ
2.5 Rin=39kΩ 2.5 Rin=39kΩ
Output Voltage (Vrms)

Output Voltage (Vrms)

Cin=3µF Cin=3µF
fin=1kHz fin=1kHz
2 HP mode 2 HP mode
Stereo, in phase
Mono &
Stereo, in phase
1.5 1.5

1 1

0.5 0.5

0 0
0 0.5 1 1.5 2 2.5 3 0 0.5 1 1.5 2 2.5 3
Input Voltage (Vrms) Input Voltage (Vrms)

PSRR vs. Frequency PSRR vs. Frequency

+0 +0
VDD=5V VDD =5V
-10 RL=4Ω -10 RL=8Ω
Cin=2.2µF Cin=2.2µF
-20 Vrr=200mVrms -20 Vrr=200mVrms
AMP mode AMP mode
-30 -30
-40 -40
PSRR (dB)

PSRR (dB)

-50 -50
-60 -60
Right channel Right channel
-70 -70
-80 -80
Left channel Left channel
-90 Vrr: Ripple Voltage on VDD -90 Vrr: Ripple Voltage on VDD
-100 -100
20 100 1k 10k 20k 20 100 1k 10k 20k
Frequency (Hz) Frequency (Hz)

PSRR vs. Frequency PSRR vs. Frequency

+0 +0
VDD =5V VDD =5V
HVDD=3.3V HVDD=3.3V
-10 -10
RL=32Ω RL=10kΩ
Rin=39kΩ -20 Rin=39kΩ
-20 Cin=3.3µF
Cin=3.3µF
Vrr=200mVrms -30 Vrr=200mVrms
-30
HP mode
PSRR (dB)

HP mode
PSRR (dB)

-40 -40

-50 -50

-60 -60

-70 -70
Left channel -80 Left channel
-80

-90 -90
Right channel Vrr: Ripple Voltage on HVDD Right channel Vrr: Ripple Voltage on HVDD
-100 -100
20 100 1k 10k 20k 20 100 1k 10k 20k
Frequency (Hz) Frequency (Hz)

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APA2051

Typical Operating Characteristics (Cont.)

Supply Current vs. Supply Voltage Shutdown Current vs. Supply Voltage
20 50
Amp mode
18 No Load AMP Mode HP mode
No Load
40

Shutdown Current (µA)

16
Supply Current (mA)

ISD(VDD)
14 *HP Mode disable
HVDD=3.3V 30
12 IHVDD=0.15mA

10
20
8 **AMP Mode disable
VDD=5V
6 IVDD=12mA 10
4 HP Mode ISD(HVDD)
2 0
3.0 3.5 4.0 4.5 5.0 5.5 3.0 3.5 4.0 4.5 5.0 5.5
Supply Voltage (Volt) Supply Voltage (Volt)

Power Dissipation vs. Output Power Power Dissipation vs. Output Power
1.4 400

350 RL=16Ω
1.2 RL=4Ω
Power Dissipation (W)

Power Dissipation (mW)

300
1.0
250
0.8 RL=32Ω
200
0.6
RL=8Ω 150

0.4 100
VDD =5V
VDD =5V HVDD=3.3V
0.2 THD+N <1% 50
THD+N <1%
AMP mode HP mode
0.0 0
0.0 0.5 1.0 1.5 2.0 0 50 100 150 200
Output Power (W) Output Power (mW)
Output Power vs. Load Resistance &
Output Power vs. Load Resistance
Charge Pump Capacitance
300 350
VDD =5V VDD =5V
HVDD=3.3V CF=CCO=2.2µF fin=1kHz
fin=1kHz 300 THD+D=1%; Mono BW<80kHZ
250
BW<80kHZ & Stereo, in phase HP mode
Output Power (mW)

Output Power (mW)

HP mode
Mono, 250
200 THD+N=10%
CF=CCO=1µF
200 THD+N=1%; Mono
150
150

100
Mono, 100 CF=CCO=1µF
THD+N=1% THD+N=1%; Stereo, in phase
50 50
CF :Charge pump flying capacitor
CCO:Charge pump output capacitor
0 0
10 100 1000 10 20 30 40 50 60 70 80 90 100
Load Resistance (Ω) Load Resistance (Ω)

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APA2051

Typical Operating Characteristics (Cont.)

Input Resistance vs. Amplifier's Gain
37.5
VDD =5V
Input Resistance (kΩ)_AMP Mode

35.0 fin=1kHz
BW<80kHZ
32.5 No Load
AMP mode
30.0

27.5

25.0

22.5

20.0

17.5

15.0
-8 -6 -4 -2 0 2 4 6 8 10 12 14 16

Gain (dB)_AMP Mode

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APA2051

Operating Waveforms

Output Transient at Turn On Output transient at Shutdown Release

VDD 5V/div SD 5V/div

HP_Out 10mV/div HP_Out 10mV/div

AMP_Out AMP_Out
20mV/div 20mV/div
((Out+)-(Out-)) ((Out+)-(Out-))

20ms/div 20ms/div

Output Transient at Turn Off Output transient at Shutdown Active

VDD 5V/div SD 5V/div

HP_Out 10mV/div HP_Out 10mV/div

AMP_Out AMP_Out
20mV/div 20mV/div
((Out+)-(Out-)) ((Out+)-(Out-))

200ms/div 20ms/div

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APA2051

Pin Description
PIN
FUNCTION
NO. NAME
1 INL_A Left channel input terminal for speaker amplifier
2 INL_H Left channel input terminal for headphone driver
3,14 N.C. No Connection
4,20 PGND Power ground
5 LOUT+ Left channel positive output for speaker
6 LOUT- Left channel negative output for speaker
7,17 PVDD Power amplifier power supply
8 CVDD Charge pump power supply
9 CP+ Charge pump flying capacitor positive connection
10 CGND Charge pump ground
11 CP- Charge pump flying capacitor negative connection
12 HVSS Charge pump output and Headphone amplifier negative power supply pin
13 HP_R Right channel output for headphone
15 HV DD Headphone amplifier positive power supply
16 HP_L Left channel output for headphone
18 ROUT- Right channel negative output for speaker
19 ROUT+ Right channel positive output for speaker
21 HP_EN Headphone driver enable pin, pull high to enable headphone mode
22 BIAS Bias voltage generator
It has 19 steps gain setting control from 2.0~4.2V; pull high to 5V is 10.5dB fix gain and
23 SET
pull low to 0V, the APA2051 enter shutdown mode. ISD = 80µA
24 AMP_EN Speaker driver enable pin, pull low to enable speaker mode
25 VDD Power supply for control section
26 GND Ground
27 INR_A Right channel input terminal for speaker amplifier
28 INR_H Right channel input terminal for headphone driver

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APA2051

Block Diagram

ROUT+

INR_A

ROUT-
Internal
gain setting LOUT+

INL_A

LOUT-

SET
SET

BIAS
AMP_EN
SPK EN

Rf(HP_R)
HP_EN
HP EN
*40kΩ
INR_H
HP_R

Rf(HP_L)

*40kΩ
INL_H
HP_L

CVDD

CP+ HVDD
Charge Power Management
CP- PVDD
Pump
CGND VDD

, VSS PGND GND

* The internal Rf s value has
10% variation by process

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APA2051

Typical Application Circuit

ROUT+
Ci(AMP_R) R_CH
R_ch INR_A
for AMP 4Ω
2.2µF
Internal ROUT-
gain
setting LOUT+
Ci(AMP_L) L_CH
L_ch
INL_A
for AMP
2.2µF 4 Ω
VDD(5V)

10kΩ LOUT-
R1
10nF SET
SET
2.2µF
BIAS
Shutdown AMP_EN
R# SPK EN
CB
Rf(HP_R)
HP_EN Pull-high HP_EN to enable
SET HP EN
headohone driver
510kΩ *40kΩ Ring
0.47nF INR_H
HP_R
Recommended for
de-pop

3.3µF 39kΩ Rf(HP_L)

R_ch
for HP Ci(HP_R) Ri(HP_R) Sleeve
Tip
Ci(HP_L) Ri(HP_L) *40kΩ
INL_H Headphone Jack
L_ch
HP_L
for HP
3.3µF 39kΩ VDD(5V) HVDD(3.3V)
CVDD
VDD(5V)
CP+ HVDD
CCPB CCPF Power
Charge
1µF 1µF CP- Management PVDD
Pump
CGND VDD CS(PVDD) CS(HVDD)
10µF
CS(VDD) 0.1µF 0.1µF
PGND GND
VSS 0.1µF
#
R : For the gain setting of speaker driver that
,
you need, refer to the Gain Setting Table s VSS
CCPO
recommended voltage, and setting this voltage
, # #
at SET pin s voltage =5R /(R +10k).
1µF
R1<=25kΩ.

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APA2051

Application Information
Amplifier Mode Operation Headphone Mode Operation
The APA2051 has two pairs of operational amplifiers
HVDD
internally, which allows different amplifier configurations.
VOUT
HVDD/2
-
Pre-amplifier OUT+
Output signal +
OP1 GND

Conventional Headphone amplifier

Vbias

HVDD

-
+
DIFF_AMP_CONFIG
VOUT
OUT- GND
OP2

Figure 1. APA2051 Internal Configuration

(each channel)

The OP1 and OP2 are all differential drive configurations.

The differential drive configurations doubling the voltage
swing on the load. Compare with the single-ending
configuration, the differential gain for each channel is 2X
(Gain of SE mode).
By driving the load differentially through outputs OUT+
and OUT-, an amplifier configuration commonly referred
to all differential mode is established. All differential mode
operation is different from the classical single-ended SE
amplifier configuration where one side of its load is con-
nected to the ground.
A differential amplifier design has a few distinct advan-
tages over the SE configuration, as it provides differential
drive to the load, thus it is doubling the output swing for a
specified supply voltage. The output power can be 4 times
greater than the SE amplifier working under the same
condition. A differential configuration, similar as the one
used in APA2051, also creates a second advantage over
SE amplifiers. Since the differential outputs, ROUT+,
ROUT-, LOUT+, and LOUT- are biased at half-supply, it’s
not necessary for DC voltage to be across the load. This
eliminates the need for an output coupling capacitor which
is required in a single supply, SE configuration.
VSS
Cap-free Headphone amplifier
Figure 2. Cap-free Operation
The APA2051’s headphone amplifiers uses a charge
pump to invert the positive power supply (CVDD) to nega-
tive power supply (CVSS), see Figure 2. The headphone
amplifiers operate at this bipolar power supply (HVDD &
VSS), and the outputs reference refers to the ground. This
feature eliminates the output capacitor which is using in
conventional single-ended headphone amplifier. The
headphone amplifier internal supply voltage comes from
HVDD and VSS. For good AC performance, the HVDD con-
nected to 3.3V is recommended. It can avoid the output
over voltage for line out application.
Charge Pump Flying Capacitor
The flying capacitor (CCPF) affects the load transient of the
charge pump. If the capacitor’s value is too small, and
then that will degrade the charge pump’s current driver
capability and the performance of headphone amplifier.
Increasing the flying capacitor’s value will improve the
load transient of charge pump. It is recommended to use
the low ESR ceramic capacitors (X7R type is
recommended) above 1µF.

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APA2051
Application Information (Cont.)
Charge Pump Output Capacitor
The output capacitor (C CPO)’s value affects the power
ripple directly at CVSS(VSS). Increasing the value of output
capacitor reduces the power ripple. The ESR of output
capacitor affects the load transient of CVSS(VSS). Lower
ESR and greater than 1µf ceramic capacitor (X7R type is
recommended) is a recommendation.
Charge Pump Bypass Capacitor
The bypass capacitor (CCPB) relates with the charge pump
switching transient. The capacitor’s value is the same as
flying capacitor (1µF). Place it close to the CVDD and PGND.
Headphone Detection Input
HP_R
Control pin Ring
1KΩ
HPD_Switch
HP_EN
HP_L
1KΩ
Sleeve
Tip
Headphone Detection
Headphone Jack with swich
Figure 3. HPD Configurations
The HP_EN will detect the voltage. If the voltage is less
than 0.8V, the headphone amplifiers will be disabled; if
the voltage is greater than 2V, the headphone amplifier
will be enabled.
In Figure 3, phone-jack with the control pin is used and
connected to HP_EN input from control pin. When a head-
phone plug is inserted, the HP_EN will pull high inter-
nally which enables headphone amplifiers; without head-
phone plug, the HP_EN is pulled to the GND.
Operation Mode
The APA2051 amplifier has two pairs of independent
amplifier. One for stereo speaker is BTL structure, and
the other for headphone is cap-less structure. Each pair
has independent input pin; INR_A and INA_L are for ste-
reo speaker drivers, and INR_H and INL_H are for stereo
headphone drivers.
• Amplifier mode operation: Pull low the AMP_EN con-
trol pin can enable the stereo speaker driver.
• Headphone mode operation: Pull high the HP_EN
control pin can enable the cap-less headphone
Copyright  ANPEC Electronics Corp.
Rev. A.4 - Aug., 2009
drive.
• Both amplifier and headphone “ON” mode: Pull low
the AMP_EN and pull high the HP_EN control pins,
and then turn on both speaker drivers and head-
phone drivers
• Both amplifier and headphone “OFF” mode: Pull
high the AMP_EN and pull low the HP_EN control
pins, and then turn off both speaker drivers and
headphone drivers
If the AMP_EN and HP_EN are connected together, this
pin will be connected to headphone jack’s control pin
(Figure 3), the APA2051 is switchable between “Amplifier
mode (Headphone mute), or Headphone mode (Amplifier
mute).
Gain Setting
The gain for speaker drivers can be adjustable by apply-
ing DC voltage to the SET pin. The APA2051 control con-
sists of 19 step gain settings from 2.0V to 4.2V, and the
gain is from -7dB to 16dB. Each gain step corresponds to
a specific input voltage range, as shown in the “Gain Set-
ting Table”. To minimize the effect of noise on the gain
setting control, which can affect the selected gain level,
hysteresis and clock delay are implemented. For the high-
est accuracy, the voltage shown in the “recommended
voltage” column of the table is used to select a desired
gain. This recommended voltage is exactly halfway be-
tween the two nearest transitions. The amount of hyster-
esis corresponds to half of the step width, as shown in
Figure 4. Apply 0V to SET pin will place the APA2051 into
shutdown mode, and when SD =5V, it allows the speaker
driver at a fixed gain (AV=10.5dB).
20
10 Forward
0 Backward
-10
Gain (dB)
-20
-30
-40
-50
-60
-70
0.0 1.0 2.0 3.0 4.0 5.0
DC Volume (V)
Figure 4. APA2051 Gain setting vs. SET pin Voltage
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APA2051

Application Information (Cont.)

Gain Setting (Cont.) important to confirm the capacitor polarity in the
For headphone driver, the internal feedback resistor is application.
40kΩ (Rf(HP) external, 10% variation by process), therefore, Note: The headphone dirver’s input is ground reference,
the headphone driver’s gain is set by the input resistor so please check the Ci(HP)’s polarized at design.
(Ri(HP) external), the Table 1 lists the reference gain set- Effective Bias Capacitor, CB
tings with external resistor for headphone driver (HP
As with any power amplifier, proper supply bypassing is
Mode).
critical for low noise performance and high power supply
HP Mode Gain Setting Table for Reference
rejection.
Ri(HP),external *Rf(HP),internal
HP OUT (V/V) HP Gain(dB)
(kΩ) (kΩ) The capacitor location on both the bypass and power
62 40 0.65 -3.8
supply pins should be as close to the device as possible.
50 40 0.80 -1.9
39 40 1.03 0.2
The effect of a larger bypass capacitor is improved PSRR
30 40 1.33 2.5 due to increased 1.8V bias voltage stability. Typical appli-
24 40 1.67 4.4 cations employ a 5V regulator with 2.2µF and a 0.1µF
20 40 2.00 6.0 bypass capacitor, which aids in supply filtering. This does
*The internal Rf's value has 10% variation by process. not eliminate the need for bypassing the supply nodes of
Table 1. Gain Setting Table for Reference the APA2051. The selection of bypass capacitors, espe-
Input Capacitor, Ci cially CB, is thus dependent upon desired PSRR require-
In the typical application, an input capacitor, Ci, is required ments and click-and-pop performance.
to allow the amplifier to bias the input signal to the proper Power Supply Decoupling, Cs
DC level for optimum operation. In this case, Ci and the
The APA2051 is a high-performance CMOS audio ampli-
minimum input impedance Ri from a high-pass filter with
fier that requires adequate power supply decoupling to
the corner frequency are determined by the following
ensure the output total harmonic distortion (THD+N) is
equation:
1 as low as possible. Power supply decoupling also pre-
F C (highpass) = (1)
(2 πR i(MIN) ×C i ) vents the oscillations caused by long lead length between
The value of Ci must be considered carefully because it the amplifier and the speaker. The optimum decoupling
directly affects the low frequency performance of the is achieved by using two different types of capacitor that
circuit. Consider the example where Ri is 10kΩ and the target on different types of noise on the power supply
specification calls for a flat bass response down to 10Hz. leads. For higher frequency transients, spikes, or digital
The equation is reconfigured as below: hash on the line, a good low equivalent-series-resistance
1 (ESR) ceramic capacitor, typically 0.1µF, is placed as
Ci = (2)
(2 πR iFc) close as possible to the device VDD lead works best (the
When the input resistance variation is considered, the Ci pin1 (V DD) and pin2 (GND)’s capacitor must short less
is 1.6µF, so a value in the range of 2.2µF to 3.3µF would than 1cm). For filtering lower-frequency noise signals, a
be chosen. A further consideration for this capacitor is the large aluminum electrolytic capacitor of 10µF or greater
leakage path from the input source through the input net- is placed near the audio power amplifier is
work (Ri+Rf, Ci) to the load. This leakage current creates recommended.
a DC offset voltage at the input to the amplifier that re- Shutdown Function
duces useful headroom, especially in high gain
In order to reduce power consumption while not in use,
applications. For this reason, a low-leakage tantalum or
the APA2051 contains a shutdown pin to externally turn
ceramic capacitor is the best choice. When polarized
off the amplifier bias circuitry. This shutdown feature turns
capacitors are used, the positive side of the capacitor
the amplifier off when a logic low is placed on the SET
should face the amplifiers’input because the DC level of
pin. The trigger point between a logic high and logic low
the amplifiers’input is held at VDD/2. Please note that it is

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APA2051

Application Information (Cont.)

Shutdown Function (Cont.) Po (W) Efficiency (%) IDD(A) VPP(V) PD (W)
level is typically 2.0V. It is the best to switch between the 0.25 31.25 0.16 2.00 0.55
ground and the supply VDD to provide maximum device 0.50 47.62 0.21 2.83 0.55
performance.
1.00 66.67 0.30 4.00 0.5
By switching the SET pin to low, the amplifier enters a 1.25 78.13 0.32 4.47 0.35
low-current consumption state, I DD<80µA. In normal D+N
**High peak voltages cause the THD to increase
to increase.
operating, the SET pin is pulled to high level to keep the Table 2. Efficiency vs. Output Power in 5-V/8W Differential
IC out of the shutdown mode. The SET pin should be tied Amplifier Systems.
to a definite voltage to avoid unwanted state changing. A final point to remember about linear amplifiers is how
The wake-up time of shutdown is about 150ms, and the to manipulate the terms in the efficiency equation to the
shutdown release’s pop is caused by the operational utmost advantage when possible. Note that in equation,
amplifier’s offset. VDD is in the denominator. This indicates that as VDD goes
Speaker Driver Amplifier Efficiency down, efficiency goes up. In other words, using the effi-
ciency analysis to choose the correct supply voltage and
An easy-to-use equation to calculate efficiency starts out
speaker impedance for the application.
as being equal to the ratio of power from the power sup-
ply to the power delivered to the load. The following equa- Power Dissipation
tions are the basis for calculating amplifier efficiency. Whether the power amplifier is operated in BTL or SE
modes, power dissipation is a major concern. Teh equa-
PO
Efficiency = (3) tion 8 states the maximum power dissipation point for a
Psup
SE mode operating at a given supply voltage and driving
Where:
VOrms * VOrms (V * VP ) a specified load.
PO = = P (4) VDD 2
RL 2RL SE mode: PD,MAX = (8)
2π2RL
VP
VOrms = (5)
2 In BTL mode operation, the output voltage swing is
2VP doubled as in SE mode. Thus, the maximum power dis-
Psup = VDD * IDD (AVG) = VDD * (6)
πRL sipation point for a BTL mode operating at the same given
Efficiency of a Differential configuration: conditions is 4 times as in SE mode.
2
PO  (V * V )   2VP  πRL BTL mode: PD,MAX = 4V2DD (9)
=  P P  / VDD * = (7) 2π RL
Psup  2RL   πRL  4VDD
Since the APA2051 is a dual channel power amplifier, the
Table 1 calculates efficiencies for four different output maximum internal power dissipation is 2 times that both
power levels. Note that the efficiency of the amplifier is of equations depending on the mode of operation. Even
quite low for lower power levels and rises sharply as with this substantial increasing in power dissipation, the
power to the load is increased resulting in nearly flat in- APA2051 does not require extra heatsink. The power dis-
ternal power dissipation over the normal operating range. sipation from equation 9, assuming a 5V-power supply
Note that the internal dissipation at full output power is and an 8Ω load, must not be greater than the power dis-
less than in the half power range. Calculating the effi- sipation that results from the equation 9:
ciency for a specific system is the key to proper power
TJ,MAX - TA (10)
supply design. For a stereo 1W audio system with 8W PD,MAX =
θJA
loads and a 5V supply, the maximum draw on the power
supply is almost 3W.

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APA2051

Application Information (Cont.)

Power Dissipation (Cont.)
ThermalVia
For TQFN4x4-28 package with thermal pad, the thermal diameter
0.3mm X 9
resistance (θJA) is equal to 45oC/W.
1.0mm
Since the maximum junction temperature (TJ,MAX) of 0.25mm

APA2051 is 150°C and the ambient temperature (TA) is

defined by the power system design, the maximum power
0.45mm

3.2mm
2.2mm
dissipation that the IC package is able to handle can be
obtained from equation10. Once the power dissipation
is greater than the maximum limit (PD,MAX), either the sup-
ply voltage (VDD) must be decreased, the load impedance
(R L) must be increased or the ambient temperature 2.2mm
should be reduced. Solder Mask Ground plane
to Prevent for
Thermal Pad Consideration Short Circuit ThermalPAD

The thermal pad must be connected to the ground. The

Figure 5. TQFN4X4-28 Land Pattern Recommendation
package with thermal pad of the APA2051 requires spe-
cial attention on the thermal design. If the thermal design Thermal Consideration
issues are not properly addressed, the APA2051 4Ω will Linear power amplifiers dissipate a significant amount
go into thermal shutdown when driving a 4Ω load. The of heat in the package under normal operating conditions.
thermal pad on the bottom of the APA2051 should be In the Power Dissipation vs. Output Power graph, the
soldered down to a copper pad on the circuit board. Heat APA2051 is operating at a 5V supply and a 4Ω speaker
can be conducted away from the thermal pad through the that 2W output power peaks are available. The vertical
copper plane to ambient. If the copper plane is not on the axis gives the information of power dissipation (PD) in the
top surface of the circuit board, 8 to 10 vias of 15 mil or IC with respect to each output driving power (PO) on the
smaller in diameter should be used to thermally couple horizontal axis.
the thermal pad to the bottom plane. For good thermal
This is valuable information when attempting to estimate
conduction, the vias must be plated through and solder
the heat dissipation of the IC requirements for the ampli-
filled. The copper plane used to conduct heat away from
fier system.
the thermal pad should be as large as practical.
Using the power dissipation curves for a 5V/4Ω system,
If the ambient temperature is higher than 25°C, a larger
the internal dissipation in the APA2051 and maximum
copper plane or forced-air cooling will be required to keep
ambient temperatures is shown in Table 3.
the APA2051 junction temperature below the thermal shut-
Average Power Max. TA (°C)
down temperature (150°C). Peak output
output dissipation
power (W)
power (W) (W/channel) With thermal pad
In higher ambient temperature, higher airflow rate and/or
larger copper area will be required to keep the IC out of 2 1.95 1.25 37

the thermal shutdown. See Demo Board Circuit Layout 2 1.17 1.25 37

as an example for PCB layout. 2 0.74 1.19 43

2 0.43 1.05 55
2 0.19 0.8 78
Table 3. APA2051 Power information, 5V/4Ω, Stereo, Differential mode

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APA2051

Application Information (Cont.)

Thermal Consideration (Cont.)

Package θJA
TQFN4x4 -28 45°C/W
Table 4. Thermal resistance Table

This parameter is measured with the recommended cop-

per heat sink pattern on a 2-layer PCB, 23cm 2 in
5.7mmx4mm in PCB, 2oz. Copper, 100mm2 coverage.
Airflow 0 CFM the maximum ambient temperature de-
pends on the heat sink ability of the PCB system.
To calculate maximum ambient temperatures, first con-
sideration is that the numbers from the dissipation graphs
are per channel values, so the dissipation of the IC heat
needs to be doubled for two-channel operation.
Given θJA, the maximum allowable junction temperature
(TJ,Max), and the total intemal dissipation (PD), the maxi-
mum ambient temperature can be calculated with the
following equation. The maximum recommended junc-
tion temperature for the APA2051 is 150°C. The internal
dissipation figures are taken from the Power Dissipation
vs. Output Power graph.

TA,Max = TJ,Max - θJAPD (11)

150 - 45(0.8*2) = 78°C (with thermal pad)

NOTE: Internal dissipation of 0.8W is estimated for a 2W system
with 15-dB headroom per channel.

Table 3 shows that for some applications, no airflow is

required to keep junction temperatures in the specified
range. The APA2051 is designed with a thermal shut-
down protection that turns the device off when the junc-
tion temperature surpasses 150°C to prevent IC from
damaging. The information in table 3 was calculated for
maximum listen volume with limited distortion. When the
output level is reduced, the numbers in the table change
significantly. Also, using 8Ω speakers will dramatically
increase the thermal performance by increasing ampli-
fier efficiency.

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APA2051

Package Information
TQFN4x4-28

A
D

E
Pin 1

b
A1
D2
A3

Pin 1
Corner
E2
L K

S TQFN4x4-28
Y
M MILLIMETERS INCHES
B
O
L MIN. MAX. MIN. MAX.
A 0.70 0.80 0.028 0.031
A1 0.00 0.05 0.000 0.002
A3 0.20 REF 0.008 REF
b 0.17 0.27 0.007 0.011
D 3.90 4.10 0.154 0.161
D2 2.10 2.50 0.083 0.098
E 3.90 4.10 0.154 0.161
E2 2.10 2.50 0.083 0.098
e 0.45 BSC 0.018 BSC
L 0.35 0.45 0.014 0.018
K 0.20 - 0.008 -

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APA2051

Carrier Tape & Reel Dimensions

OD0 P0 P2 P1 A

E1
F

W
B0

K0 A0 OD1 B A
B

SECTION A-A

T
SECTION B-B

d
H
A

T1

Application A H T1 C d D W E1 F
12.4+2.00 13.0+0.50
330.0±2.00 50 MIN. 1.5 MIN. 20.2 MIN. 12.0±0.30 1.75±0.10 5.5±0.05
-0.00 -0.20
TQFN4x4-28 P0 P1 P2 D0 D1 T A0 B0 K0
1.5+0.10 0.6+0.00
4.0±0.10 8.0±0.10 2.0±0.05 1.5 MIN. 4.30±0.20 4.30±0.20 1.30±0.20
-0.00 -0.40

(mm)

Devices Per Unit

Package Type Unit Quantity
TQFN 4x4-28 Tape & Reel 3000

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APA2051

Taping Direction Information

TQFN4x4-28

USER DIRECTION OF FEED

Classification Profile

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APA2051

Classification Reflow Profiles

Profile Feature Sn-Pb Eutectic Assembly Pb-Free Assembly
Preheat & Soak
100 °C 150 °C
Temperature min (Tsmin)
150 °C 200 °C
Temperature max (Tsmax)
60-120 seconds 60-120 seconds
Time (Tsmin to Tsmax) (ts)

Average ramp-up rate

3 °C/second max. 3°C/second max.
(Tsmax to TP)
Liquidous temperature (TL) 183 °C 217 °C
Time at liquidous (tL) 60-150 seconds 60-150 seconds
Peak package body Temperature
See Classification Temp in table 1 See Classification Temp in table 2
(Tp)*
Time (tP)** within 5°C of the specified
20** seconds 30** seconds
classification temperature (Tc)
Average ramp-down rate (Tp to Tsmax) 6 °C/second max. 6 °C/second max.

Time 25°C to peak temperature 6 minutes max. 8 minutes max.

* Tolerance for peak profile Temperature (Tp) is defined as a supplier minimum and a user maximum.
** Tolerance for time at peak profile temperature (tp) is defined as a supplier minimum and a user maximum.

Table 1. SnPb Eutectic Process – Classification Temperatures (Tc)

3 3
Package Volume mm Volume mm
Thickness <350 ≥350
<2.5 mm 235 °C 220 °C
≥2.5 mm 220 °C 220 °C

Table 2. Pb-free Process – Classification Temperatures (Tc)

3 3 3
Package Volume mm Volume mm Volume mm
Thickness <350 350-2000 >2000
<1.6 mm 260 °C 260 °C 260 °C
1.6 mm – 2.5 mm 260 °C 250 °C 245 °C
≥2.5 mm 250 °C 245 °C 245 °C

Reliability Test Program

Test item Method Description
SOLDERABILITY JESD-22, B102 5 Sec, 245°C
HOLT JESD-22, A108 1000 Hrs, Bias @ 125°C
PCT JESD-22, A102 168 Hrs, 100%RH, 2atm, 121°C
TCT JESD-22, A104 500 Cycles, -65°C~150°C
HBM MIL-STD-883-3015.7 VHBM≧2KV
MM JESD-22, A115 VMM≧200V
Latch-Up JESD 78 10ms, 1tr≧100mA

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APA2051

Customer Service

Anpec Electronics Corp.

Head Office :
No.6, Dusing 1st Road, SBIP,
Hsin-Chu, Taiwan
Tel : 886-3-5642000
Fax : 886-3-5642050

Taipei Branch :
2F, No. 11, Lane 218, Sec 2 Jhongsing Rd.,
Sindian City, Taipei County 23146, Taiwan
Tel : 886-2-2910-3838
Fax : 886-2-2917-3838

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