TN KTS-Altera DE1 B mn i n T - HBK Tp HCM

Kit th nghi m K thu t s Altera DE1

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TN KTS-Altera DE1 B mn i n T - HBK Tp HCM

CC B C TH NGHI M K THU T S

TRN KIT ALTERA DE1

Nh p file thi t k dng m Verilog

Bin d ch

M ph ng ch c nng

No

Thi t k

ng? Yes

Gn chn

Phn tch v m ph ng th i gian

No

t yu c u th i gian? Yes N p kit v th m ch

Hnh 1: Cc b c th c hi n

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TN KTS-Altera DE2 B mn i n T - HBK Tp HCM

B c 1. Ch y chng trnh Quartus II:

Hnh 2: Mn hnh chnh Quartus II.

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TN KTS-Altera DE1 B mn i n T - HBK Tp HCM

B c 2. T o project m i:
1. Ch n File > New Project Wizard:

Hnh 3: File menu.

2. Ch n th m c lm vi c,

t tn cho project r i nh n Next:

Hnh 4: T o 1 project m i.

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TN KTS-Altera DE1 B mn i n T - HBK Tp HCM

Nh n Yes.

Hnh 5: Quartus II t o th m c m i cho project.

3. Khng c n ph i ch n thm file no, nh n NEXT:

Hnh 6: Thm file thi t k 4.

c s n.

Ch n chip Cyclone II EP2C20F484C7N, nh n NEXT.

Hnh 7: Ch n chip FPGA. Trang 5

TN KTS-Altera DE1 B mn i n T - HBK Tp HCM

5. Khng c n ch n EDA TOOL no, nh n Next:

Hnh 8: Ch n EDA tools.

6. B ng tm t t cc thng s ci

t cho project nh hnh 9. Nh n Finish

Hnh 9: Tm t t cc thng s ci

t cho project.

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TN KTS-Altera DE1 B mn i n T - HBK Tp HCM

Chng trnh s quay tr v mn hnh chnh:

Hnh 10: Mn hnh Quartus II cho project m i c t o.

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TN KTS-Altera DE2 B mn i n T - HBK Tp HCM

B c 3. Nh p file thi t k dng m Verilog:

3.1. Ch n File > New, ch n Verilog HDL File, r i nh n OK.

Hnh 13: Ch n Verilog HDL file.

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3.2. T o file thi t k m i: ch n File > Save As, ch n Save as type = Verilog HDL File. t tn cho file. Ch n Add file to current project. Nh n Save

Hnh 14:

t tn file.

3.3 Nh p chng trnh dng m Verilog vo khung Text Editor. Lu file: File > Save, ho c nh n Ctrl-S.

Hnh 15: Mn hnh Quartus II sau khi t o file.

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TN KTS-Altera DE1 B mn i n T - HBK Tp HCM

C th ty ch n cc tnh nng c a Text Editor b ng cch ch n: Tools > Options > Text Editor.

Hnh 16: Cc ty ch n cho Text Editor.

C th dng template

nh p chng trnh: Edit > Insert Template > Verilog HDL

3.4. a file thi t k vo project: ch n Assignments > Settings, ch n Files ho c ch n Project > Add/Remove Files in Project N u dng Quartus II Text Editor v ch n Add file to current project nh trong ph n 3.2 th file thi t k s c n p th ng vo project.

Hnh 17: Ty ch n cc thng s cho project. Trang 10

TN KTS-Altera DE1 B mn i n T - HBK Tp HCM

N u cha c th ph i n p nh sau: 1. Copy file thi t k vo th m c lm vi c. 2. Nh n nt ... ch n file

Hnh 18: Ch n file

3. Ch n file c n thi t r i nh n Open. Sau nh n Add, OK.

B c 4. Bin d ch chng trnh thi t k :

4.1 Ch n Processing > Start Compilation, ho c nh n nt . Ch bin d ch chng trnh cho n khi bo Successful (ho c unsuccessful) r i nh n OK

Hnh 19: Mn hnh sau khi bin d ch thnh cng. Trang 11

TN KTS-Altera DE1 B mn i n T - HBK Tp HCM

4.2 Khi bin d ch xong chng trnh s t ng hi n th Compilation Report. Report ny cng c th c m b ng cch ch n Processing > Compilation Report ho c nh n nt .

Hnh 20: K t qu bin d ch.

Thng bo l i:

Hnh 25: Thng bo bin d ch c l i.

Hnh 26: N i dung l i.

Hnh 27: Xc

nh v tr l i Trang 12

TN KTS-Altera DE1 B mn i n T - HBK Tp HCM

B c 5. Gn chn c a project cho kit Altera DE 1:

5.1 Ch n Assignments > Import Assignments. Ch n file DE1_pin_assignments.csv Nh n OK.

Hnh 24. Mn hnh Import Assignments

5.2 Ch n Assignments > Assignment Editor. Ch n Category = Pin. Double-click vo v t sng highlight mu xanh dng c t To. R i gn cc chn vo, ra tng ng.

Hnh 25. Drop-down menu hi n th tn cc ng vo, ra.

Lu file thi t k .

Hnh 27. Hon t t vi c gn chn

B c 6. M ph ng m ch thi t k :
1. Ch n File > New - Ch n Vector Waveform File - Nh n OK. 2. Mn hnh Waveform Editor nh Hnh 32. Lu vector waveform file (.vwf) Ch n th i gian th c hi n m ph ng t 0 nh p 200 ns. Ch n View > Fit in Window

n 200 ns b ng cch ch n Edit > End Time r i

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TN KTS-Altera DE1 B mn i n T - HBK Tp HCM

Hnh 33. Mn hnh Waveform Editor

3. Ch n Edit > Insert Node or Bus.

Hnh 34. H p tho i Insert Node or Bus.

Nh n nt Node Finder.

Hnh 35. Ch n nodes

a vo Waveform Editor.

Ch n Filter = Pins: all r i nh n nt List. Ch n nt >> r i nh n OK. Nh n OK trong c a s hnh 34. th . Lu vector waveform file.

4. Ch n cc gi tr logic c a cc ng vo

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TN KTS-Altera DE1 B mn i n T - HBK Tp HCM

Hnh 37. Ch n cc gi tr logic c a cc ng vo

th

6.1 Th c hi n m ph ng: (Functional Simulation) Ch n Assignments > Settings ch n Simulation mode = Functional r i nh n OK.

Hnh 38. Ch n Simulation mode = Functional.

Ch n Processing > Generate Functional Simulation Netlist. B t u th c hi n m ph ng b ng cch ch n Processing > Start Simulation, ho c nh n nt .

Hnh 39. K t qu m ph ng.

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TN KTS-Altera DE1 B mn i n T - HBK Tp HCM

B c 7. L p trnh cho FPGA trn kit Altera DE1:

Trn kit DE2 t SW19 = RUN (JTAG mode) K t n i USB cp t my tnh v i USB-Blaster trn kit DE1. C p ngu n cho kit. Ch n Tools > Programmer. Ch n Mode = JTAG. Ch n Hardware = USB-Blaster theo nh Hnh 42. Ch n Check box Program/Configure.

Hnh 41. Mn hnh programing.

Hnh 42. Mn hnh ch n hardware.

Nh n nt Start

b t

u n p project vo kit DE1.

B c 8. Th project v a thi t k :
Ti n hnh th project v a c n p trn kit DE1. N u mu n thay i thi t k tr c h t ph i t t mn hnh Programmer r i th c hi n project m i t b c 2.

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Bi th nghi m 1
Switches, Lights, Multiplexers
1. Th nghi m 1.1: Th c hi n m ch th nghi m c ng vo l 10 cng t c SW 90 , v ng ra l 10 n LED mu thi c a cc ng vo. // Chung trnh Verilog n gi n cho bi TN 1.1: module tn1_1 (SW, LEDR); input [9:0] SW; // toggle switches output [9:0] LEDR; // red LEDs assign LEDR = SW; endmodule Cc b c c n th c hi n: 1. 2. 3. 4. T o project m i. Vi t chng trnh Verilog cho bi TN Gn chn & bin d ch project. N p project vo kit TN. Th m ch. LEDR 90 dng c tr ng

2. Th nghi m 1.2: Cho m ch multiplexer 2 sang 1 nh hnh 2 v i ng vo ch n knh s. N u s = 0 ng ra m s b ng ng vo x, v n u s = 1 th ng ra m = y.

x

m s y

a) S

m ch
s

s 0 1

m x y x y
0 1

b) B ng s th t

c) K hi u

Hnh 2. M ch multiplexer 2 sang 1. M ch c th m t dng m Verilog nh sau: assign m = ( s & x) (s & y); Dng 4 b multiplexer 2 sang 1 nh hnh 2 th c hi n m ch multiplexer 2 sang 1 - 4 bit nh hnh 3a. M ch c 2 ng vo nh phn 4 bit X v Y, v ng ra 4 bit M. N u s = 0 th M = X , cn s = 1 th M = Y.

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TN KTS-Altera DE1 B mn i n T - HBK Tp HCM

x3 y3

0 1

m3

X3 Y3

0 1

m2

s
4

X Y
4

0 1

x0 y0

m0

a) s

m ch

b) k hi u

Hnh 3. M ch multiplexer 2 sang 1, 4 bit. Cc b c c n th c hi n: 1. T o project m i. 2. Vi t chng trnh Verilog v i: s = SW9 v n i v i LEDR9 X = SW3-0 v n i v i LEDR3-0 Y = SW7-4 v n i v i LEDR7-4 M = LEDG3-0 3. Gn chn 4. Bin d ch project. 5. N p project vo kit TN. 6. Th m ch b ng cch thay 3. Th nghi m 1.3: Dng 3 b multiplexer 2 sang 1 nh hnh 2 th c hi n m ch multiplexer 4 sang 1 nh hnh 4a. M ch c 4 ng vo u, v, w v x; 1 ng ra m; 2 ng vo ch n knh s1 s0

i cc cng t c SW r i theo di cc n LED xanh,

s1 s0

u v

0 1

0 1

w x

0 1

a) s

m ch

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TN KTS-Altera DE1 B mn i n T - HBK Tp HCM

s1 s0 0 0 1 1 0 1 0 1

m u v w x

s1 s0 u x v w x

00 01 10 11

b) b ng s th t

c) k hi u Hnh 4. M ch multiplexer 4 sang 1 th c hi n m ch multiplexer 4 1 - 2 bit nh

Tng t dng 2 m ch multiplexer 4 1 nh hnh 4a hnh 5

s1 s0 U V W X
2 2 2 2 00 01 10 11

Hnh 5. M ch multiplexer 4 sang 1 - 2 bit

Cc b c c n th c hi n: 1. T o project m i. 2. Vi t chng trnh Verilog v i: s 1 s 0 = SW9-8 v n i v i LEDR9-8 U-X = SW7-0 v n i v i LEDR7-0 M = LEDG1-0 3. Gn chn 4. Bin d ch project. 5. N p project vo kit TN. 6. Th m ch b ng cch thay

i cc cng t c SW r i theo di cc n LED xanh,

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TN KTS-Altera DE1 B mn i n T - HBK Tp HCM

4. Th nghi m 1.4: Th c hi n b gi i m c 2 ng vo c1 c0 v 7 ng ra t 0 n 6 dng hi n th cc k t trn b hi n th 7 o n nh hnh 6. B ng 1 li t k cc k t c n hi n th (g m H,E,L v k t O) tng ng v i cc ng vo c1 c0 . Cc ng ra tch c c m c logic 0.

0 5 c1 c0 7-segment decoder 4 3 6 1 2

Hnh 6. B gi i m 7 o n c1 c0 00 01 10 11 K t H E L O

B ng 1. B ng m ch Cc b c c n th c hi n: 1. T o project m i. 2. Vi t chng trnh Verilog v i: o Cc ng vo c1 c0 n i v i cc cng t c SW1-0 o Cc ng ra 0 6 n i v i HEX00, HEX01..HEX06 3. Gn chn 4. Bin d ch project. 5. N p project vo kit TN. 6. Th m ch b ng cch thay

i cc cng t c SW10 r i quan st b hi n th 7 o n.

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TN KTS-Altera DE1 B mn i n T - HBK Tp HCM

5. Th nghi m 1.5: Th c hi n m ch i n hi n th ch xoay nh hnh 7 ho t ng theo b ng 2. Cc cng t c SW 70 dng t o k t v SW 98 dng ch n k t hi n th .

SW 9 SW 8 SW 7 6 SW 5 4 SW 3 2 SW 1 0
2 2 2 2 00 01 10 11

0
2

7-segment decoder

5 4

1 2

Hnh 7. M ch c th ch n & hi n th 1 trong 4 k t . SW9 SW8 00 01 10 11 Hi n th H E L O

B ng 2. Hi n th ch xoay HELLO. module part5 (SW, HEX0); input [9:0] SW; // toggle switches output [0:6] HEX0; // 7-seg displays wire [1:0] M; mux 2bit 4to1 M0 (SW[9:8], SW[7:6], SW[5:4], SW[3:2], SW[1:0], M); char 7seg H0 (M, HEX0); endmodule // implements a 2-bit wide 4-to-1 multiplexer module mux 2bit 4to1 (S, U, V, W, X, M); input [1:0] S, U, V, W, X; output [1:0] M; . . . code not shown endmodule // implements a 7-segment decoder for H, E, L and O module char 7seg (C, Display); input [1:0] C; // input code output [0:6] Display; // output 7-seg code . . . code not shown endmodule Hnh 8. Chng trnh g i cho m ch i n hnh 7.

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TN KTS-Altera DE1 B mn i n T - HBK Tp HCM

Bi th nghi m 2
Numbers & Displays
y l bi th nghi m thi t k m ch t h p c ng hai s BCD. 1. Th nghi m 2.1: Dng cc n 7 o n HEX1 v HEX0 hi n th cc s th p phn t 0 b ng cc cng t c SW74 v SW 30 tng ng.

th c hi n b bi n

i s nh phn sang s th p phn v m ch

n 9. Gi tr hi n th thay

i c

1. 2. 3. 4.

Cc b c c n th c hi n: T o project m i. Vi t chng trnh Verilog cho bi TN Gn chn & bin d ch project. N p project vo kit TN. Th m ch b ng cch thay i cc cng t c v quan st cc n hi n th .

2. Th nghi m 2.2: Th c hi n 1 ph n c a m ch chuy n i s nh phn 4 bit V = v 3 v2 v1 v0 thnh s th p phn D = d1 d0 n h hnh 1, b ng 1. M ch bao g m m ch so snh ( ki m tra V > 9), m ch multiplexer v m ch A (cha c n th c hi n m ch B v b gi i m 7 o n). M ch s c ng vo V 4 bit, ng ra M 4 bit v ng ra z. Binary value 0000 0001 0010 ... 1001 1010 1011 1100 1101 1110 1111 B ng 1. B ng gi tr chuy n Cc b c c n th c hi n: 1. T o project m i. Vi t chng trnh 2. 3. 4. 5. Bin d ch project v th c hi n m ph ng Vi t thm o n chng trnh cho m ch B v m ch gi i m 7 o n. Dng cc cng t c SW30 nh p s nh phn V v cc n 7 o n HEX1, HEX0 hi n th s th p phn d 1 d0 Bin d ch l i r i n p project vo kit TN. Th m ch: thay i gi tr V v quan st cc n hi n th . Decimal digits 0 0 0 ... 0 1 1 1 1 1 1 0 1 2 ... 9 0 1 2 3 4 5 i nh phn th p phn.

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TN KTS-Altera DE1 B mn i n T - HBK Tp HCM

d1 z Comparator Circuit B
7

0 5 4 6 1 2 3

v3 0

0 1

m3

d0 v2
0 1

m2 7-segment decoder
7

0 5 4 6 1 2 3

v1

0 1

m1

v0

0 1

m0

Circuit A

Hnh 1. M ch chuy n 3. Th nghi m 2.3:

i nh phn-th p phn.

Cho m ch c ng ton ph n (FA) nh hnh 2a v i cc ng vo a, b, and ci , cc ng ra s v co . c o s = a + b + ci . Dng 4 m ch c ng FA nh trn th c hi n m ch c ng 4 bit nh hnh 2d.

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TN KTS-Altera DE1 B mn i n T - HBK Tp HCM

ci a b s ci a
0 1

s FA co

co

a) M ch c ng FA
b3 a3 c 3

b) K hi u
b2 a2 c 2 b1 a1 c 1 b 0 a 0 c in

b a ci 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1

co s 0 0 0 1 0 1 1 1 0 1 1 0 1 0 0 1

FA

FA

FA

FA

c out s 3

s2

s1

s0

c) B ng s th t

d) M ch c ng 4 bit Hnh 2. M ch c ng.

Cc b c c n th c hi n: 1. T o project m i v vi t chng trnh Verilog cho m ch c ng: N i cc ng vo A, B v cin v i cc cng t c tng ng SW74 , SW 30 v SW8 v v i cc n LED mu LEDR N i cc ng ra c out v S v i cc n LED mu xanh LEDG 2. 3. Gn chn, bin d ch v n p project vo kit TN Th m ch b ng cch thay i cc gi tr khc nhau c a A, B v c in, quan st cc n hi n th .

4. Th nghi m 2.4: Th c hi n m ch c ng 2 s BCD. Ng vo c a m ch l 2 s A, B v ng vo cho s nh c in . Ng ra l s BCD t ng S1 S0 v s nh c out.

Cc b c c n th c hi n: 1. T o project m i cho m ch c ng s BCD. Ph i th c hi n m ch c ng 2 s 4 bit A, B (th nghi m 2.3) v 1 m ch chuy n i 5 bit t ng s3s2s1s0co thnh 2 s BCD S1 S0 (th nghi m 2.2) 2. Vi t chng trnh Verilog: N i cc ng vo A, B v cin v i cc cng t c tng ng SW74 , SW 30 v SW8 v v i cc n LED mu LEDR70 N i cc ng ra c out v S v i cc n LED mu xanh LEDG40 Dng cc n 7 o n HEX3, HEX2 hi n th gi tr c a 2 s A v B v HEX1, HEX0 hi n th k t qu S1 S0 . 3. 4. Gn chn, bin d ch v n p project vo kit TN Th m ch b ng cch thay i cc gi tr khc nhau c a A, B v c in, quan st cc n hi n th .

5. Th nghi m 2.5: Thi t k m ch t h p chuy n i 1 s nh phn 6 bit thnh s th p phn d i d ng 2 s BCD. Dng cc cng t c SW 50 nh p s nh phn v cc n 7 o n HEX1 v HEX0 hi n th s th p phn.

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Bi th nghi m 3
Latches, Flip-flops, Registers
1. Th nghi m 3.1: Hnh 1 m t m ch RS latch dng c ng logic. C 2 cch dng Verilog m t m ch ny: dng c ng logic (hnh 2a) v dng cng th c logic (hnh 2b).
R R_g Qa (Q) Clk Qb S S_g

Hnh 1. M ch RS latch dng c ng logic. // A gated RS latch module part1 (Clk, R, S, Q); input Clk, R, S; output Q; wire R_g, S_g, Qa, Qb /* synthesis keep */ ; and (R_g, R, Clk); and (S_g, S, Clk); nor (Qa, R_g, Qb); nor (Qb, S_g, Qa); assign Q = Qa; endmodule Hnh 2a. Dng c ng logic m t m ch RS latch.

// A gated RS latch module part1 (Clk, R, S, Q); input Clk, R, S; output Q; wire R_g, S_g, Qa, Qb /* synthesis keep */ ; assign R_g = R & Clk; assign S_g = S & Clk; assign Qa = (R_g Qb); assign Qb = (S_g Qa); assign Q = Qa; endmodule Hnh 2b. Dng cng th c logic m t m ch RS latch.

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TN KTS-Altera DE1 B mn i n T - HBK Tp HCM

C 2 cch th c h n: dng 1 LUT 4 ng vo (hnh 3a) v dng 4 LUT 2 ng vo (hnh 3b).

Clk

Qa (Q)
4-LUT

(a) RS latch ch dng 1 b ng tham chi u 4 ng vo.

R
4-LUT

R_g
4-LUT

Qa (Q)

Clk S_g
4-LUT

4-LUT

Qb

(b) RS latch dng 4 b ng tham chi u 2 ng vo. Hnh 3. Cc cch th c hi n m ch RS latch Cc b c c n th c hi n: 1. 2. 3. 4. T o project RS latch Vi t chng trnh Verilog theo hai cch 2a v 2b. Bin d ch. Dng ti n ch RTL Viewer so snh v i s m ch hnh 1. Dng ti n ch Technology Viewer so snh v i s m ch hnh 3b. T o Vector Waveform File (.vwf) cho cc ng vo/ra. T o d ng sng cho cc ng vo R v S r i dng ti n ch Quartus II Simulator quan st cc d ng sng R_g, S_g, Qa v Qb

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2. Th nghi m 3.2: Cho m ch D latch dng c ng nh hnh 4.

D S S_g Qa (Q) Clk Qb R_g

Hnh 4. M ch D latch dng c ng logic.

Cc b c c n th c hi n: 1. 2. 3. 4. 5. 6. T o project m i v i chng trnh Verilog d ng 2b cho m ch D latch. Bin d ch chng trnh. Dng ti n ch Technology Viewer kh o st m ch. M ph ng ki m tra ho t ng c a m ch. Dng cng t c SW0 cho ng vo D, v SW1 cho ng vo Clk. N i ng ra Q n LEDR 0 . Bin d ch chng trnh l i v n p project vo kit TN. Th m ch b ng cch thay i cc ng vo D, Clk v quan st ng ra Q.

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TN KTS-Altera DE1 B mn i n T - HBK Tp HCM

3. Th nghi m 3.3: Cho m ch master-slave D flip-flop hnh 5.

Master D Clock D Q Qm

Slave D Q Qs Q Q

Clk Q

Clk Q

Hnh 5. M ch master-slave D flip-flop. Cc b c c n th c hi n: 1. 2. 3. 4. 5. T o project m i dng 2 D flip-flop c a th nghi m 3.2. Dng cng t c SW 0 cho ng vo D, v SW 1 cho ng vo Clk. N i ng ra Q n LEDR 0 . Bin d ch chng trnh. Dng ti n ch Technology Viewer kh o st m ch. M ph ng ki m tra ho t ng c a m ch. Th m ch b ng cch thay i cc ng vo D, Clk v quan st ng ra Q.

4. Th nghi m 3.4: Cho m ch i n hnh 6 v i D latch, D flip- flop kck c nh ln v D flip- flop kck c nh xu ng.

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TN KTS-Altera DE1 B mn i n T - HBK Tp HCM

D Clock

Qa Qa

Clk Q

Q Q

Qb Qb

Q Q

Qc Qc

(a) S

m ch

Clock D Qa Qb Qc

(b) Gi n d th i gian

Hnh 6. S

m ch v d ng sng c a th nghi m 3.4.

Cc b c c n th c hi n: 1. 2. 3. 4. 5. T o project m i. Vi t chng trnh d a trn o n chng trnh g i nh hnh 7. Bin d ch chng trnh. Dng ti n ch Technology Viewer kh o st m ch. M ph ng ki m tra ho t ng c a m ch. So snh ho t ng c a cc ph n t trong m ch. module D_latch (D, Clk, Q); input D, Clk; output reg Q; always @ (D, Clk) if (Clk) Q = D; endmodule Hnh 7. Chng trnh g i cho D latch.

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TN KTS-Altera DE1 B mn i n T - HBK Tp HCM

Bi th nghi m 4
Counters
1. Th nghi m 4.1: Cho m ch m ng b 4 bit dng 4 T flip-flops nh hnh 1.

Enable Clock

Q Q

Q Q

Q Q

Q Q

Clear

Hnh 1. B Cc b c c n th c hi n:

m 4 bit.

1. T o project m i th c hi n b m 16 bit dng 4 m ch m nh hnh 1. Bin d ch chng trnh. Ghi nh n s ph n t logic (LEs) c dng? T n s ho t ng t i a (Fmax) c a m ch m l bao nhiu? 2. M ph ng ho t ng c a m ch. 3. Gn thm nt nh n KEY0 lm ng vo Clock, cc cng t c SW 1, SW0 lm ng vo Enable, Reset v cc n 7 o n HEX3-0 hi n th gi tr th p l c phn c a ng ra m ch m. 4. Bin d ch l i v n p project vo kit TN. 5. Th ho t ng c a m ch b ng cch thay i cc cng t c v quan st cc n 7 o n. 6. Th c hi n m ch m 4 bit r i dng ti n ch RTL Viewer quan st m ch v so snh v i m ch i n hnh 1. 2. Th nghi m 4.2: Th c hi n l i th nghi m 4.1 dng m Verilog sau: Q <= Q + 1; Bin d ch chng trnh. So snh s ph n t logic (LEs) c dng, t n s ho t ng t i a (Fmax) c a m ch Dng RTL Viewer kh o st v nh n xt nh ng khc bi t so v i th nghi m 4.1. m.

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TN KTS-Altera DE2 B mn i n T - HBK Tp HCM

3. Th nghi m 4.3: Dng module c s n trong th vi n LPM (Library of Parameterized Modules) Thay i LPM cho ph h p, nh Enable, Reset. 4. Th nghi m 4.4: Th c hi n m ch ng h m giy t 0 n 9s hi n th trn n 7 o n HEX 0. Ph i th c hi n 1 m ch m t o th i gian 1s t xung clock 50 MHz c s n trn kit TN. 5. Th nghi m 4.5: Th c hi n m ch hi n th ch HELLO ln 4 n 7 o n HEX 3 0, d ch t ph i sang tri v i th i kho ng 1s theo m u nh b ng 1. Clock cycle 0 1 2 3 4 5 6 7 8 ... B ng 1. Displayed pattern H E L L O H E L L O th c hi n m ch m 16 bit.

H E L L O

H E L L O

H and so on n ch ch y HELLO.

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