22. Digital Circuits ET aT -13 ‘There are two types of mem 01 wee ry elements based on the type of triggering that Is sultable + Latches + Flip-flops Latches operate with enable signal, which is level sei sensitive, We will discuss about flip-flops in next chi Latch & D Latch one by one. nsitive. Whereas, flip-flops are edge lapter. Now, let us discuss about SR ; SR Latch SR Latch is also called as Set Reset Latch. This latch affects the outputs as long as the enable, E is maintained at ‘1’, The circuit diagr i i Bree gram of SR Latch is shown in the following Qt) ey i : This circuit has two inputs S & R and two outputs Q(t) & Q(t). The upper NOR gate has two inputs R & complement of present state, Q(t)’ and produces next state, Q(t+1) when’ enable, E is ‘1' Similarly, the lower NOR gate has two inputs S & present state, Q(t) and produces complement of next state, Q(t+1) when enable, E is ‘2’ We know that 4 2-input NOR gate produces an output, which is the condieal gnother Input when one of the input is ‘0’. Similarly, it produces ‘0’ output, when on the input is "1. 1¢$e1, then next state Q(t+1) will be equal tot’ irrespective of present values. i es If Re 1, then next state Q(t+ 1) will be equal to 0’ irrespective o values.At any time, only of those two inputs should be * state Q(t+1) value is undefined. ‘The following table shows the state table of SR latch. s R (ted) 0 0 0) 0 T 0 T 0 T z T T = Therefore, SR Latch performs three types of functions such as Hold, Set & Reset based on the input conditions. DLatch There is one drawback of SR Latch. That is the next state value can’t be predicted when both the Inputs S & R are one. So, we can overcome this difficulty by D Latch. It is also called as Data Latch. The circuit diagram of D Latch is shown in the following figure. ey ity > This circuit has single input D and two outputs Q(t) & Q(t)’. D Latch is obtained Latch by placing an inverter between S & R inputs and connect D input to S. we eliminated the combinations of S & R are of same value. 8 If: Present state, Q( state table. Present state, Q(t) values. This is corresponding to ttTherefore, D Latch Hold the information that is availabl ‘output of D Latch is sensitive to the changes in the input, In this chapter, we implemented various Latches by providing NOR gates. Similarly, you can implement these Latches usingre the basic building blocks of In previous chapter, we discussed about Latches. Those are the basi 9 flip-flops. We can implement flip-flops in two methods. BP ela id extend twolntcies in such @ way that the ist Iateni Ie a a every positive clock pulse and second latch is enabled for every negative clock pi that the combination of these two latches become a flip-flop. In second method, we can directly implement the flip-flop, which is edge sensitive. In this chapter, let us discuss the following flip-flops using second method. + SR Flip-Flop + DFilip-Fiop q + 3K Flip-Flop , + T Flip-Flop SR FlipFlop SR flip-flop operates with only positive cl Whereas, SR latch operates with en: shown in the following figure. lock transitions or negative clock transitions, ble signel. The circuit diagram of SR flip-flop is a | ‘ >a —, 7: \, Anis circult has two inputs $ & R and two outputs Q(t) & Q(t)’. The operation of SR flip- {op is similar to SR Latch. But, this flip-flop affects the outputs only when positive transition of the clock signal is applied instead of active enable, ‘The following table shows the state table of SR flip-flop. s R Q(t+i) Qt)By using three variable K-Map, we can get the simplified expression for ne The three variable K-Map for next state, Q(t+1) Is shown in the folloy The maximum possible groupings of adjacent ones are al ‘Therefore, the simplified expression for next state QD re p fe to the changes in the input, D except for active transition ‘diagram of D flip-flop is shown in the following figure. This circuit has single input D and two outputs Q(t) & Q(t)’. The operation of D flip- similar to D Latch, But, this flip-flop affects the outputs only when positive tra the clock signal is applied instead of active enable. ‘The following table shows the state table of D flip-flop. accom ala = earlier positive tra the next state equ:This circuit has two inputs J & K and two outputs Q(t) & Q(t)’. is similar to SR flip-flop. Here, we considered the inputs of SR flip R=KQ(t) in order to utilize the modified SR flip-flop for 4 combi The following table shows the state table of JK flip-flop. Here, Q(t) & Q(t+1) are present state & next state respectiv used for one of these four functions such as Hold, Reset, state based on the input conditions, when positive transitior following table shows the characteristic table of JK flip-flKat) 308) le groupings of adjacent ones are already shown in the Therefore, the simplified expression for next state Q(t+1) is Q(t + 1) = JEW’ + KA) Mllp-flop is the simplified version of 3K flip-flop. It is obtained by connecting the $3 input 'T’ to both inputs of JK flip-flop. It operates with only positive clock transitions Regative clock transitions. The circuit diagram of T flip-flop is shown in the follo figure. This circuit has single input T and two outputs Q(t) & Q(t)’. The oper ‘same as that of JK flip-flop. Here, we considered the Inputs of J in order to utilize the modified JK flip-flop for 2 combination: the other two combinations of J & K, for which those two val ‘other in T flip-flop.From the above characteristic table, we can directly write QE+ D = TH + TQM)’ => Qt+1) =TS Aw The output of T flip-flop always toggles for every positive transiti when input T remains at logic High (1). Hence, T flip-flop can be In this chapter, we implemented various flip-flops by providing the NOR gates. Similarly, you can implement these flip-flops by using