CAMELLIA INSTITUTE OF TECHNOLOGY

Assignment-1

Odd semester-2022

Year: 2nd semester: 3rd Stream: CSE/IT

Sub: Analog & Digital Electronics Sub code: ESC-301

GROUP-A
(Multiple Choice Type)

1) Answer any all of the following: [1*21=21]

(i) Minimum number of NAND gates are required to implement an EX-OR gate are
(a) 4 (b) 5
(c) 6 (d) 3
(ii) Each cell in K-MAP represents
(a) minterm (b) maxterm
(c) both minterm and maxterm (d) none of these
(iii) Which logic gate is called equality detector?
(a) EX-OR (b) EX-NOR
(c) NAND (d) NOR
(iv)Which combinational circuit is called data selector?
(a) Demux (b) MUX
(c) Adder (d) Subtractor
(v) Decoder with enable input is called
(a) Encoder (b) MUX
(c) DE-MUX (d) Comparator
(vi) Bubbles AND gate is called
(a) NOR Gate (b) NAND Gate
(c) EX-OR Gate (d) EX-NOR Gate
(vii) Toggle mode of J-K flip flop is when
(a) J = K = 0 (b) J = K = 1
(c) J=1, K=0 (d) none of these
(viii) The minimum number of NOR gates required to design one XOR gate is
(a) 4 (b) 5
(c) 6 (d) 7
(ix) How many flip flops are required to design MOD 10 Asynchronous counter?
(a) 1 (b) 2
(c) 3 (d) 4
(x) A latch is a
(a) 1-bit memory cell (b) 2-bit memory cell
(c) 3-bit memory cell (d) none of these
(xi) The output of a logic gate is 1 when all its inputs are at logic zero. The gate is either
(a) a NAND or an EX-OR (b) an OR or an EX-OR
(c) an AND or an EX-OR (d) a NOR or an EX-NOR
(xii) Which logic gate is called the data distributor?
(a) Encoder (b) MUX
(c) DE-MUX (d) Comparator
(xiii) In which code do the successive code characters differ in only one position?
(a) Hamming code (b) Excess-3 code
(c) Gray code (d) ASCII code
(xiv) Race around condition occurs in
(a) SR flip flop (b) JK flip flop
(c) Flip flop (d) none of these
(xv) Parity checker is used to detect
(a) 1-bit error (b) 2-bit error
(c) 3-bit error (d) 4-bit error
 (xvi) Which of the following combination is not allowed in an SR flip flop?
(a) S=0, R=0 (b) S=0, R=1
(c) S=1, R=0 (d) S=1, R=1
(xvii) The number of 2:1 MUX required to implement 8:1 MUX is
(a) 6 (b) 7
(c) 8 (d) 9
(xviii) BCD code of decimal number( 36)10 is
(a) 0000 1110 (b) 0011 0110
(c) 0010 1110 (d) none of these
(xix) Gray code of binary number (10011) 2 is
(a) 10110 (b) 00110
(c) 11010 (d) none of these
(xx) A flip flop has two outputs which are
(a) always 0 (b) always 1
(c) always complementary (d) both outputs are same
(xxi) How many selection line inputs are in 8:1 MUX?
(a) 2 (b) 5
(c) 4 (d) 3

GROUP-B
(Short Answer Type)

Answer all of the following: [5*10=50]

2) Design a full adder using two half adder and an external OR gate.

3) Design a 4:16 decoder using two 3:8 decoder.

4) Design a 8:1 MUX using two 4: 1 MUX and one 2:1 MUX.

5) Implement the following Boolean function using one 8:1 MUX only

F(A,B,C,D) = ∑m(0,2,5,8,10,13,15)

6) Write down characteristic table and characteristic equation of JK and D flip flop.

7) Draw the output waveform of J-K flip-flop for input sequences J = 1011010 and K = 0110110
(a) The flip-flop is positive edge-triggered
(b) The flip-flop is negative edge-triggered

8) What do you mean by race around condition? How can it be overcome?

9) Design a MOD 8 synchronous counter using JK flip flops.

10) Design full adder using 3:8 decoder with all active high output. Take extra logic gate if necessary.

11) Design 3 bit asynchronous counter using JK flip flop and also write down its truth table.