Professional Documents
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Rev. EC21_Hardware_Design_V1.4
Date: 2017-03-01
www.quectel.com
LTE Module Series
EC21 Hardware Design
Our aim is to provide customers with timely and comprehensive service. For any
assistance, please contact our company headquarters:
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http://www.quectel.com/support/salesupport.aspx
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For technical support, or to report documentation errors, please visit:
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http://www.quectel.com/support/techsupport.aspx
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Or email to: Support@quectel.com
GENERAL NOTES
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QUECTEL OFFERS THE INFORMATION AS A SERVICE TO ITS CUSTOMERS. THE INFORMATION
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PROVIDED IS BASED UPON CUSTOMERS’ REQUIREMENTS. QUECTEL MAKES EVERY EFFORT
TO ENSURE THE QUALITY OF THE INFORMATION IT MAKES AVAILABLE. QUECTEL DOES NOT
MAKE ANY WARRANTY AS TO THE INFORMATION CONTAINED HEREIN, AND DOES NOT ACCEPT
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ANY LIABILITY FOR ANY INJURY, LOSS OR DAMAGE OF ANY KIND INCURRED BY USE OF OR
RELIANCE UPON THE INFORMATION. THE INFORMATION SUPPLIED HEREIN IS SUBJECT TO
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CHANGE WITHOUT PRIOR NOTICE.
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COPYRIGHT
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THE INFORMATION CONTAINED HERE IS PROPRIETARY TECHNICAL INFORMATION OF
QUECTEL CO., LTD. TRANSMITTING, REPRODUCTION, DISSEMINATION AND EDITING OF THIS
DOCUMENT AS WELL AS UTILIZATION OF THE CONTENT ARE FORBIDDEN WITHOUT
PERMISSION. OFFENDERS WILL BE HELD LIABLE FOR PAYMENT OF DAMAGES. ALL RIGHTS
ARE RESERVED IN THE EVENT OF A PATENT GRANT OR REGISTRATION OF A UTILITY MODEL
OR DESIGN.
Copyright © Quectel Wireless Solutions Co., Ltd. 2017. All rights reserved.
History
Revision Date
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Author Description
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1.0 2016-04-15 Yeoman CHEN Initial
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1. Updated frequency bands in Table 1.
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2. Updated transmitting power, supported maximum
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baud rate of main UART, supported internet
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protocols, supported USB drivers of USB interface,
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and temperature range in Table 2.
3. Updated timing of turning on module in Figure 12.
4. Updated timing of turning off module in Figure 13.
Yeoman CHEN/ 5. Updated timing of resetting module in Figure 16.
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1.1 2016-09-22 Frank WANG/ 6. Updated main UART supports baud rate in Chapter
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Lyndon LIU 3.11.
7. Added notes for ADC interface in Chapter 3.13.
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8. Updated GNSS Performance in Table 21.
9. Updated operating frequencies of module in Table
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23.
10. Added current consumption in Chapter 6.4.
11. Updated RF output power in Chapter 6.5.
12. Added RF receiving sensitivity in Chapter 6.6.
1. Added SGMII and WLAN interfaces in Table 2.
2. Updated function diagram in Figure 1.
3. Updated pin assignment (Top View) in Figure 2.
4. Added description of SGMII and WLAN interfaces in
Table 4.
Lyndon LIU/
1.2 2016-11-04 5. Added SGMII interface in Chapter 3.17.
Michael ZHANG
6. Added WLAN interface in Chapter 3.18.
7. Added USB_BOOT interface in Chapter 3.19.
8. Added reference design of RF layout in Chapter
5.1.4.
9. Added current consumption of EC21-V in Chapter
6.4.
10. Added note about SIMO in Chapter 6.6.
1. Updated frequency bands in Table 1.
2. Updated function diagram in Figure 1.
3. Updated pin assignment (top view) in Figure 2.
4. Added BT interface in Chapter 3.18.2.
5. Updated reference circuit of wireless connectivity
interfaces with FC20 module in Figure 29.
Lyndon LIU/
1.3 2017-01-24 6. Updated GNSS performance in Table 24.
Rex WANG
7. Updated module operating frequencies in Table 26.
8. Added EC21-AUV current consumption in Table 38.
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9. Updated EC21-A conducted RF receiving sensitivity
of in Table 42.
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10. Added EC21-J conducted RF receiving sensitivity in
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Table 48.
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1.4 2017-03-01 Geely YANG Deleted the LTE band TDD B41 of EC21-CT
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Contents
1 Introduction ..................................................................................................................................... 10
1.1. Safety Information ..................................................................................................................11
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2.1. General Description .............................................................................................................. 12
2.2. Key Features ......................................................................................................................... 13
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2.3. Functional Diagram ............................................................................................................... 16
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2.4. Evaluation Board ................................................................................................................... 16
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3 Application Interfaces ..................................................................................................................... 17
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3.1. General Description .............................................................................................................. 17
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3.2. Pin Assignment ..................................................................................................................... 18
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3.3. Pin Description ...................................................................................................................... 19
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3.4. Operating Modes .................................................................................................................. 28
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3.5. Power Saving ........................................................................................................................ 28
3.5.1. Sleep Mode.................................................................................................................. 28
3.5.1.1. UART Application ............................................................................................... 28
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3.5.1.2. USB Application with USB Remote Wakeup Function ....................................... 29
3.5.1.3. USB Application with USB Suspend/Resume and RI Function .......................... 30
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3.5.1.4. USB Application without USB Suspend Function............................................... 31
3.5.2. Airplane Mode.............................................................................................................. 32
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3.6. Power Supply ........................................................................................................................ 32
3.6.1. Power Supply Pins....................................................................................................... 32
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3.6.2. Decrease Voltage Drop ................................................................................................ 33
3.6.3. Reference Design for Power Supply ............................................................................ 34
3.6.4. Monitor the Power Supply ............................................................................................ 35
3.7. Turn on and off Scenarios ..................................................................................................... 35
3.7.1. Turn on Module Using the PWRKEY ........................................................................... 35
3.7.2. Turn off Module ............................................................................................................ 37
3.7.2.1. Turn off Module Using the PWRKEY Pin ........................................................... 37
3.7.2.2. Turn off Module Using AT Command ................................................................. 37
3.8. Reset the Module .................................................................................................................. 38
3.9. USIM Card Interface ............................................................................................................. 39
3.10. USB Interface ........................................................................................................................ 41
3.11. UART Interfaces.................................................................................................................... 43
3.12. PCM and I2C Interfaces ........................................................................................................ 45
3.13. ADC Function ........................................................................................................................ 48
3.14. Network Status Indication ..................................................................................................... 49
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5 Antenna Interfaces .......................................................................................................................... 60
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5.1. Main/Rx-diversity Antenna Interface ..................................................................................... 60
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5.1.1. Pin Definition................................................................................................................ 60
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5.1.2. Operating Frequency ................................................................................................... 60
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5.1.3. Reference Design of RF Antenna Interface ................................................................. 61
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5.1.4. Reference Design of RF Layout................................................................................... 62
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5.2. GNSS Antenna Interface ....................................................................................................... 64
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5.3. Antenna Installation .............................................................................................................. 65
5.3.1. Antenna Requirement .................................................................................................. 65
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5.3.2. Recommended RF Connector for Antenna Installation ................................................ 66
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6.2. Power Supply Ratings ........................................................................................................... 68
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6.3. Operating Temperature ......................................................................................................... 69
6.4. Current Consumption ............................................................................................................ 70
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6.5. RF Output Power .................................................................................................................. 76
6.6. RF Receiving Sensitivity ....................................................................................................... 76
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6.7. Electrostatic Discharge ......................................................................................................... 80
7 Mechanical Dimensions.................................................................................................................. 81
7.1. Mechanical Dimensions of the Module.................................................................................. 81
7.2. Recommended Footprint....................................................................................................... 83
7.3. Design Effect Drawings of the Module .................................................................................. 84
Table Index
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TABLE 9: PIN DEFINITION OF THE USIM CARD INTERFACE ...................................................................... 39
TABLE 10: PIN DESCRIPTION OF USB INTERFACE ..................................................................................... 41
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TABLE 11: PIN DEFINITION OF THE MAIN UART INTERFACE ..................................................................... 43
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TABLE 12: PIN DEFINITION OF THE DEBUG UART INTERFACE ................................................................. 43
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TABLE 13: LOGIC LEVELS OF DIGITAL I/O .................................................................................................... 44
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TABLE 14: PIN DEFINITION OF PCM AND I2C INTERFACES ....................................................................... 46
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TABLE 15: PIN DEFINITION OF THE ADC ...................................................................................................... 48
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TABLE 16: CHARACTERISTIC OF THE ADC .................................................................................................. 48
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TABLE 17: PIN DEFINITION OF NETWORK CONNECTION STATUS/ACTIVITY INDICATOR...................... 49
TABLE 18: WORKING STATE OF NETWORK CONNECTION STATUS/ACTIVITY INDICATOR ................... 49
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TABLE 19: PIN DEFINITION OF STATUS ........................................................................................................ 50
TABLE 20: BEHAVIOR OF THE RI ................................................................................................................... 51
TABLE 21: PIN DEFINITION OF THE SGMII INTERFACE .............................................................................. 52
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TABLE 22: PIN DEFINITION OF WIRELESS CONNECTIVITY INTERFACES ................................................ 54
TABLE 23: PIN DEFINITION OF USB_BOOT INTERFACE ............................................................................. 57
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TABLE 24: GNSS PERFORMANCE ................................................................................................................. 58
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TABLE 25: PIN DEFINITION OF THE RF ANTENNA ....................................................................................... 60
TABLE 26: MODULE OPERATING FREQUENCIES ........................................................................................ 60
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TABLE 27: PIN DEFINITION OF GNSS ANTENNA INTERFACE..................................................................... 64
TABLE 28: GNSS FREQUENCY ....................................................................................................................... 64
TABLE 29: ANTENNA REQUIREMENTS.......................................................................................................... 65
TABLE 30: ABSOLUTE MAXIMUM RATINGS .................................................................................................. 68
TABLE 31: POWER SUPPLY RATINGS ........................................................................................................... 68
TABLE 32: OPERATING TEMPERATURE........................................................................................................ 69
TABLE 33: EC21-A CURRENT CONSUMPTION ............................................................................................. 70
TABLE 34: EC21-AUT CURRENT CONSUMPTION ........................................................................................ 71
TABLE 35: EC21-E CURRENT CONSUMPTION ............................................................................................. 72
TABLE 36: EC21-KL CURRENT CONSUMPTION ........................................................................................... 73
TABLE 37: EC21-V CURRENT CONSUMPTION ............................................................................................. 74
TABLE 38: EC21-AUV CURRENT CONSUMPTION ........................................................................................ 74
TABLE 39: GNSS CURRENT CONSUMPTION OF EC21 SERIES MODULE ................................................. 75
TABLE 40: RF OUTPUT POWER ..................................................................................................................... 76
TABLE 41: EC21-E CONDUCTED RF RECEIVING SENSITIVITY .................................................................. 76
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TABLE 53: DESCRIPTION OF DIFFERENT CODING SCHEMES .................................................................. 92
TABLE 54: GPRS MULTI-SLOT CLASSES ...................................................................................................... 93
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TABLE 55: EDGE MODULATION AND CODING SCHEMES ........................................................................... 94
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Figure Index
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FIGURE 9: REFERENCE CIRCUIT OF POWER SUPPLY .............................................................................. 34
FIGURE 10: TURN ON THE MODULE USING DRIVING CIRCUIT ................................................................. 35
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FIGURE 11: TURN ON THE MODULE USING KEYSTROKE .......................................................................... 36
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FIGURE 12: TIMING OF TURNING ON MODULE ........................................................................................... 36
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FIGURE 13: TIMING OF TURNING OFF MODULE ......................................................................................... 37
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FIGURE 14: REFERENCE CIRCUIT OF RESET_N BY USING DRIVING CIRCUIT ...................................... 38
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FIGURE 15: REFERENCE CIRCUIT OF RESET_N BY USING BUTTON ...................................................... 38
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FIGURE 16: TIMING OF RESETTING MODULE ............................................................................................. 39
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FIGURE 17: REFERENCE CIRCUIT OF USIM CARD INTERFACE WITH AN 8-PIN USIM CARD
CONNECTOR .................................................................................................................................................... 40
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FIGURE 18: REFERENCE CIRCUIT OF USIM CARD INTERFACE WITH A 6-PIN USIM CARD CONNECTOR
........................................................................................................................................................................... 40
FIGURE 19: REFERENCE CIRCUIT OF USB APPLICATION ......................................................................... 42
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FIGURE 20: REFERENCE CIRCUIT WITH TRANSLATOR CHIP ................................................................... 44
FIGURE 21: REFERENCE CIRCUIT WITH TRANSISTOR CIRCUIT .............................................................. 45
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FIGURE 22: PRIMARY MODE TIMING ............................................................................................................ 46
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FIGURE 23: AUXILIARY MODE TIMING .......................................................................................................... 46
FIGURE 24: REFERENCE CIRCUIT OF PCM APPLICATION WITH AUDIO CODEC .................................... 47
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FIGURE 25: REFERENCE CIRCUIT OF THE NETWORK INDICATOR .......................................................... 50
FIGURE 26: REFERENCE CIRCUITS OF STATUS ......................................................................................... 50
FIGURE 27: SIMPLIFIED BLOCK DIAGRAM FOR ETHERNET APPLICATION ............................................. 52
FIGURE 28: REFERENCE CIRCUIT OF SGMII INTERFACE WITH PHY AR8033 APPLICATION................. 53
FIGURE 29: REFERENCE CIRCUIT OF WIRELESS CONNECTIVITY INTERFACES WITH FC20 MODULE
........................................................................................................................................................................... 55
FIGURE 30: REFERENCE CIRCUIT OF USB_BOOT INTERFACE ................................................................ 57
FIGURE 31: REFERENCE CIRCUIT OF RF ANTENNA INTERFACE ............................................................. 61
FIGURE 32: MICROSTRIP LINE DESIGN ON A 2-LAYER PCB ...................................................................... 62
FIGURE 33: COPLANAR WAVEGUIDE LINE DESIGN ON A 2-LAYER PCB .................................................. 62
FIGURE 34: COPLANAR WAVEGUIDE LINE DESIGN ON A 4-LAYER PCB (LAYER 3 AS REFERENCE
GROUND) .......................................................................................................................................................... 63
FIGURE 35: COPLANAR WAVEGUIDE LINE DESIGN ON A 4-LAYER PCB (LAYER 4 AS REFERENCE
GROUND) .......................................................................................................................................................... 63
FIGURE 36: REFERENCE CIRCUIT OF GNSS ANTENNA ............................................................................. 64
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1 Introduction
This document defines the EC21 module and describes its air interface and hardware interface which are
connected with your application.
This document can help you quickly understand module interface specifications, electrical and
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mechanical details, as well as other related information of EC21 module. Associated with application note
and user guide, you can use EC21 module to design and set up mobile applications easily.
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The following safety precautions must be observed during all phases of the operation, such as usage,
service or repair of any cellular terminal or mobile incorporating EC21 module. Manufacturers of the cellular
terminal should send the following safety information to users and operating personnel, and incorporate
these guidelines into all manuals supplied with the product. If not so, Quectel assumes no liability for the
customer’s failure to comply with these precautions.
Full attention must be given to driving at all times in order to reduce the risk of an
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accident. Using a mobile while driving (even with a handsfree kit) causes
distraction and can lead to an accident. You must comply with laws and regulations
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restricting the use of wireless devices while driving.
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Switch off the cellular terminal or mobile before boarding an aircraft. Make sure it is
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switched off. The operation of wireless appliances in an aircraft is forbidden, so as
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to prevent interference with communication systems. Consult the airline staff about
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the use of wireless devices on boarding the aircraft, if your device offers an
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Airplane Mode which must be enabled prior to boarding an aircraft.
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Switch off your wireless device when in hospitals, clinics or other health care
facilities. These requests are designed to prevent possible interference with
sensitive medical equipment.
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Cellular terminals or mobiles operating over radio frequency signal and cellular
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network cannot be guaranteed to connect in all conditions, for example no mobile
fee or with an invalid USIM/SIM card. While you are in this condition and need
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emergent help, please remember using emergency call. In order to make or
receive a call, the cellular terminal or mobile must be switched on and in a service
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area with adequate cellular signal strength.
Your cellular terminal or mobile contains a transmitter and receiver. When it is ON,
it receives and transmits radio frequency energy. RF interference can occur if it is
used close to TV set, radio, computer or other electric equipment.
In locations with potentially explosive atmospheres, obey all posted signs to turn
off wireless devices such as your phone or other cellular terminals. Areas with
potentially explosive atmospheres include fuelling areas, below decks on boats,
fuel or chemical transfer or storage facilities, areas where the air contains
chemicals or particles such as grain, dust or metal powders, etc.
2 Product Concept
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EC21 is a series of LTE-FDD/LTE-TDD/WCDMA/GSM wireless communication module with receive
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diversity. It provides data connectivity on LTE-FDD, LTE-TDD, DC-HSPA+, HSPA+, HSDPA, HSUPA,
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WCDMA, EDGE and GPRS networks. It also provides GNSS1) and voice functionality2) for your specific
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applications. EC21 contains ten variants: EC21-E, EC21-A, EC21-V, EC21-AUT, EC21-AU, EC21-AUV,
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EC21-AUTL, EC21-J, EC21-CT and EC21-KL. You can choose a dedicated type based on the region or
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operator. The following table shows the frequency bands of EC21 series module.
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Table 1: Frequency Bands of EC21 Series Module
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Rx-
Modules2) LTE Bands 3G Bands GSM GNSS1)
diversity
WCDMA:
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EC21-E FDD: B1/B3/B5/B7/B8/B20 900/1800 Y
B1/B5/B8
WCDMA:
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EC21-A FDD: B2/B4/B12 N Y GPS,
B2/B4/B5
GLONASS,
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EC21-V FDD: B4/B13 N N Y BeiDou/
Compass,
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WCDMA:
EC21-AUT FDD: B1/B3/B5/B7/B28 N Y Galileo,
B1/B5
QZSS
FDD: B1/B2/B3/B4/B5/B7/B8/
3) WCDMA: 850/900/
EC21-AU B28 Y
B1/B2/B5/B8 1800/1900
TDD: B40
NOTES
1)
1. GNSS function is optional.
2)
2. EC21 series module (EC21-E, EC21-A, EC21-V, EC21-AUT, EC21-AU, EC21-AUV, EC21-AUTL,
EC21-J, EC21-CT and EC21-KL) includes Data-only and Telematics versions. Data-only version
does not support voice function, while Telematics version supports it.
3)
3. B2 band on EC21-AU module does not support Rx-diversity.
4. Y = supported (including LTE and WCDMA). N = Not supported.
With a compact profile of 32.0mm × 29.0mm × 2.4mm, EC21 can meet almost all requirements for M2M
applications such as automotive, metering, tracking system, security, router, wireless POS, mobile
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computing device, PDA phone, tablet PC, etc.
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EC21 is an SMD type module which can be embedded into applications through its 144-pin pads,
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including 80 LCC signal pads and 64 other pads.
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2.2. Key Features
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The following table describes the detailed features of EC21 module.
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Table 2: EC21 Key Features of EC21 Module
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Features Details
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Power Supply Supply voltage: 3.3V~4.3V Typical supply voltage: 3.8V
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Class 4 (33dBm±2dB) for GSM900
Class 1 (30dBm±2dB) for DCS1800
Class 1 (30dBm±2dB) for PCS1900
Class E2 (27dBm±3dB) for GSM850 8-PSK
Transmitting Power Class E2 (27dBm±3dB) for GSM900 8-PSK
Class E2 (26dBm±3dB) for DCS1800 8-PSK
Class E2 (26dBm±3dB) for PCS1900 8-PSK
Class 3 (24dBm+1/-3dB) for WCDMA bands
Class 3 (23dBm±2dB) for LTE-FDD bands
Class 3 (23dBm±2dB) for LTE-TDD bands
Support up to non-CA CAT1
Support 1.4 to 20MHz RF bandwidth
LTE Features
Support MIMO in DL direction
FDD: Max 5Mbps (UL), 10Mbps (DL)
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Maximum of four Rx time slots per frame
GSM Features
EDGE:
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Support EDGE multi-slot class 12 (12 by default)
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Support GMSK and 8-PSK for different MCS (Modulation and Coding
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Scheme)
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Downlink coding schemes: CS 1-4 and MCS 1-9
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Uplink coding schemes: CS 1-4 and MCS 1-9
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Support TCP/UDP/PPP/FTP/HTTP/NTP/PING/QMI/HTTPS*/SMTP*/
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MMS*/FTPS*/SSL* protocols
Internet Protocol Features Support PAP (Password Authentication Protocol) and CHAP (Challenge
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Handshake Authentication Protocol) protocols which are usually used for
PPP connections
Text and PDU mode
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Point to point MO and MT
SMS
SMS cell broadcast
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SMS storage: ME by default
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USIM Interface Support USIM/SIM card: 1.8V, 3.0V
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GSM: HR/FR/EFR/AMR/AMR-WB
Audio Features WCDMA: AMR/AMR-WB
LTE: AMR/AMR-WB
Support echo cancellation and noise suppression
Used for audio function with external codec
Support 8-bit A-law*, μ-law* and 16-bit linear data formats
PCM Interface Support long frame synchronization and short frame synchronization
Support master and slave modes, but must be the master in long frame
synchronization
Compliant with USB 2.0 specification (slave only); the data transfer rate
can reach up to 480Mbps
USB Interface Used for AT command communication, data transmission, GNSS NMEA
output, software debugging, firmware upgrade and voice over USB*
Support USB drivers for Windows XP, Windows Vista, Windows 7,
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Wireless Connectivity Support a low-power SDIO 3.0 interface for WLAN and UART/PCM
Interfaces interface for Bluetooth*
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Rx-diversity Support LTE/WCDMA Rx-diversity
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Gen8C Lite of Qualcomm
GNSS Features
Protocol: NMEA 0183
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Compliant with 3GPP TS 27.007, 27.005 and Quectel enhanced AT
AT Commands
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commands
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Two pins including NET_MODE and NET_STATUS to indicate network
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Network Indication
connectivity status
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Including main antenna interface (ANT_MAIN), Rx-diversity antenna
Antenna Interface
interface (ANT_DIV) and GNSS antenna interface (ANT_GNSS)
Size: (32.0±0.15) × (29.0±0.15) × (2.4±0.2)mm
Physical Characteristics
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Weight: approx. 4.9g
Operation temperature range: -35°C ~ +75°C1)
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Temperature Range
Extended temperature range: -40°C ~ +85°C2)
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Firmware Upgrade USB interface and DFOTA*
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RoHS All hardware components are fully compliant with EU RoHS directive
NOTES
1)
1. Within operating temperature range, the module is 3GPP compliant.
2)
2. Within extended temperature range, the module remains the ability to establish and maintain a
voice, SMS, data transmission, emergency call, etc. There is no unrecoverable malfunction. There
are also no effects on radio spectrum and no harm to radio network. Only one or more parameters
like Pout might reduce in their value and exceed the specified tolerances. When the temperature
returns to normal operating temperature levels, the module will meet 3GPP specifications again.
3. “*” means under development.
The following figure shows a block diagram of EC21 and illustrates the major functional parts.
Power management
Baseband
DDR+NAND flash
Radio frequency
Peripheral interfaces
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ANT_MAIN ANT_GNSS ANT_DIV
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Switch
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SAW Switch
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Duplex LNA
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SAW
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VBAT_RF
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PA
APT
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PRx DRx
Tx
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NAND
Transceiver DDR2
SDRAM
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IQ Control
VBAT_BB
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PMIC
Control
PWRKEY
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RESET_N
Baseband
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ADCs
STATUS 19.2M
XO
In order to help you develop applications with EC21, Quectel supplies an evaluation board (EVB), USB
data cable, earphone, antenna and other peripherals to control or test the module.
3 Application Interfaces
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EC21 is equipped with 80-pin SMT pads plus 64-pin ground pads and reserved pads that can be
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connected to cellular application platform. Sub-interfaces included in these pads are described in detail in
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the following chapters:
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Power supply
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USIM interface
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USB interface
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UART interfaces
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PCM interface
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ADC interface
Status indication
SGMII interface
Wireless connectivity interfaces
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USB_BOOT interface
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EC21_Hardware_Design Confidential / Released 17 / 94
LTE Module Series
EC21 Hardware Design
RESERVED
RESERVED
RESERVED
USB_VBUS
VBAT_RF
VBAT_BB
VBAT_BB
VBAT_RF
USB_DM
USB_DP
STATUS
GND
GND
DCD
RXD
DTR
CTS
TXD
RTS
RI
114
113
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
WAKEUP_IN1) 1 54 GND
AP_READY 2 53 GND
129 117
RESERVED 3 52 GND
108 103 99 95 90 85
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W_DISABLE# 4 130 118 51 GND
NET_MODE1) 5 131 119 50 GND
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NET_STATUS 6 49 ANT_MAIN
132 120
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VDD_EXT 7 109 104 100 96 91 86 48 GND
141 133 144 RESERVED
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RESERVED 121
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RESERVED 142 82 79 76 73 143 RESERVED
134 122
GND 8 110 105 83 80 77 74 92 87 47 ANT_GNSS
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GND 9 135 123 46
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84 81 78 75 GND
USIM_GND 10 45 ADC0
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136 124
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DBG_RXD 11 44 ADC1
111 106 101 97 93 88
DBG_TXD 12 137 125 43 RESERVED
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USIM_PRESENCE 13 42 I2C_SDA
138 126
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USIM_VDD 14 41 I2C_SCL
USIM_DATA 15 139 127 112 107 102 98 94 89 40 BT_CTS
USIM_CLK 16 39 BT_RXD
140 128
USIM_RST 17 38 BT_TXD
RESERVED 18 37 BT_RTS
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116 RESERVED
115 USB_BOOT
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
RESET_N
PCM_IN※
PCM_OUT※
PCM_SYNC※
PCM_CLK※
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
GND
GND
PWRKEY2)
GND
ANT_DIV
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WLAN Pins Power Pins Bluetooth Pins
NOTES
1)
1. means that these pins cannot be pulled up before startup.
2)
2. PWRKEY output voltage is 0.8V because of the diode drop in the Qualcomm chipset.
3. Pads 119~126 are SGMII function pins.
4. Pads 37~40, 118, 127 and 129~139 are wireless connectivity interfaces, among which pads 127 and
129~138 are WLAN function pins, and others are Bluetooth (BT) function pins. BT function is under
development.
5. Pads 24~27 are multiplexing pins used for audio design on EC21 module and BT function on FC20
module.
6. Keep all RESERVED pins and unused pins unconnected.
7. GND pads 85~112 should be connected to ground in the design, and RESERVED pads 73~84
should not be designed in schematic and PCB decal.
※
8. “ ” means these interface functions are only supported on Telematics version.
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The following tables show the pin definition of EC21 module.
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Table 3: I/O Parameters Definition
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Type Description
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IO Bidirectional
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DI Digital input
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DO Digital output
PI Power input
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PO Power output
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AI Analog input
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AO Analog output
OD Open drain
Pin Name
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Table 4: Pin Description
Power Supply
Vmax=4.3V
Comment
Turn on/off
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The output voltage is
VIHmax=2.1V
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Turn on/off the 0.8V because of the
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PWRKEY 21 DI VIHmin=1.3V
module diode drop in the
l
VILmax=0.5V
c
Qualcomm chipset.
a
VIHmax=2.1V
e i
RESET_N 20 DI Reset the module VIHmin=1.3V
t
VILmax=0.5V
u n
Status Indication
Q ide
Pin Name Pin No. I/O Description DC Characteristics Comment
f
operating status
0.9mA. keep it open.
n
1.8V power domain.
Indicate the module
VOHmin=1.35V Cannot be pulled up
o
NET_MODE 5 DO network registration
VOLmax=0.45V before startup.
mode
If unused, keep it open.
C
Indicate the module
NET_ VOHmin=1.35V 1.8V power domain.
6 DO network activity
STATUS VOLmax=0.45V If unused, keep it open.
status
USB Interface
USIM Interface
l
Vmin=2.7V
e
IOmax=50mA
t
For 1.8V USIM:
c l
VILmax=0.6V
VIHmin=1.2V
e ia
VOLmax=0.45V
t
VOHmin=1.35V
u
Data signal of USIM
USIM_DATA 15 IO
n
card
For 3.0V USIM:
Q ide
VILmax=1.0V
VIHmin=1.95V
VOLmax=0.45V
f
VOHmin=2.55V
For 1.8V USIM:
n
VOLmax=0.45V
VOHmin=1.35V
o
Clock signal of USIM
USIM_CLK 16 DO
card
For 3.0V USIM:
C
VOLmax=0.45V
VOHmin=2.55V
For 1.8V USIM:
VOLmax=0.45V
VOHmin=1.35V
Reset signal of
USIM_RST 17 DO
USIM card
For 3.0V USIM:
VOLmax=0.45V
VOHmin=2.55V
VILmin=-0.3V
USIM_ USIM card insertion VILmax=0.6V 1.8V power domain.
13 DI
PRESENCE detection VIHmin=1.2V If unused, keep it open.
VIHmax=2.0V
UART Interface
l
VILmax=0.6V 1.8V power domain.
RTS 65 DI Request to send
VIHmin=1.2V If unused, keep it open.
e
VIHmax=2.0V
t
1.8V power domain.
l
VILmin=-0.3V
c
Pull-up by default. Low
Data terminal ready, VILmax=0.6V
a
DTR 66 DI level wakes up the
e i
sleep mode control VIHmin=1.2V
module.
t
VIHmax=2.0V
u
If unused, keep it open.
n
VOLmax=0.45V 1.8V power domain.
TXD 67 DO Transmit data
VOHmin=1.35V If unused, keep it open.
Q ide
VILmin=-0.3V
VILmax=0.6V 1.8V power domain.
RXD 68 DI Receive data
VIHmin=1.2V If unused, keep it open.
f
VIHmax=2.0V
n
Debug UART Interface
o
Pin Name Pin No. I/O Description DC Characteristics Comment
C
DBG_TXD 12 DO Transmit data
VOHmin=1.35V If unused, keep it open.
VILmin=-0.3V
VILmax=0.6V 1.8V power domain.
DBG_RXD 11 DI Receive data
VIHmin=1.2V If unused, keep it open.
VIHmax=2.0V
ADC Interface
General purpose
Voltage range:
ADC0 45 AI analog to digital If unused, keep it open.
0.3V to VBAT_BB
converter
General purpose
Voltage range:
ADC1 44 AI analog to digital If unused, keep it open.
0.3V to VBAT_BB
converter
PCM Interface
VILmin=-0.3V
VILmax=0.6V 1.8V power domain.
PCM_IN 24 DI PCM data input
VIHmin=1.2V If unused, keep it open.
VIHmax=2.0V
VOLmax=0.45V 1.8V power domain.
PCM_OUT 25 DO PCM data output
VOHmin=1.35V If unused, keep it open.
VOLmax=0.45V 1.8V power domain.
l
VOHmin=1.35V In master mode, it is an
PCM data frame
VILmin=-0.3V output signal.
PCM_SYNC 26 IO synchronization
e
VILmax=0.6V In slave mode, it is an
t
signal
VIHmin=1.2V input signal.
c l
VIHmax=2.0V If unused, keep it open.
a
VOLmax=0.45V 1.8V power domain.
e i
VOHmin=1.35V In master mode, it is an
t
VILmin=-0.3V output signal.
u
PCM_CLK 27 IO PCM clock
VILmax=0.6V In slave mode, it is an
n
VIHmin=1.2V input signal.
Q ide
VIHmax=2.0V If unused, keep it open.
I2C Interface
f
Pin Name Pin No. I/O Description DC Characteristics Comment
n
External pull-up
I2C serial clock.
resistor is required.
I2C_SCL 41 OD Used for external
o
1.8V only.
codec
If unused, keep it open.
C
External pull-up
I2C serial data.
resistor is required.
I2C_SDA 42 OD Used for external
1.8V only.
codec
If unused, keep it open.
SGMII Interface
For 1.8V:
VOLmax=0.45V
1.8V/2.85V power
VOHmin=1.4V
domain.
EPHY_RST_N 119 DO Ethernet PHY reset
If unused, keep it
For 2.85V:
open.
VOLmax=0.35V
VOHmin=2.14V
VILmin=-0.3V
1.8V power domain.
Ethernet PHY VILmax=0.6V
EPHY_INT_N 120 DI If unused, keep it
interrupt VIHmin=1.2V
open.
VIHmax=2.0V
For 1.8V:
VOLmax=0.45V
VOHmin=1.4V
VILmax=0.58V
1.8V/2.85V power
SGMII MDIO VIHmin=1.27V
SGMII_ domain.
121 IO (Management Data
MDATA If unused, keep it
Input/Output) data For 2.85V:
l
open.
VOLmax=0.35V
VOHmin=2.14V
t e
VILmax=0.71V
l
VIHmin=1.78V
c
For 1.8V:
e a
VOLmax=0.45V
i
1.8V/2.85V power
t
SGMII MDIO VOHmin=1.4V
SGMII_ domain.
u
122 DO (Management Data
MCLK If unused, keep it
n
Input/Output) clock For 2.85V:
open.
Q ide
VOLmax=0.35V
VOHmin=2.14V
Configurable power
source.
f
1.8V/2.85V power
n
SGMII MDIO pull-up domain.
USIM2_VDD 128 PO
power source External pull-up for
o
SGMII MDIO pins.
If unused, keep it
C
open.
SGMII transmission If unused, keep it
SGMII_TX_M 123 AO
- minus open.
SGMII transmission If unused, keep it
SGMII_TX_P 124 AO
- plus open.
SGMII receiving If unused, keep it
SGMII_RX_P 125 AI
- plus open.
SGMII receiving If unused, keep it
SGMII_RX_M 126 AI
- minus open.
VILmin=-0.3V open.
VILmax=0.6V
VIHmin=1.2V
VIHmax=2.0V
VOLmax=0.45V
VOHmin=1.35V
1.8V power domain.
SDC1_ VILmin=-0.3V
130 IO SDIO data bus D2 If unused, keep it
DATA2 VILmax=0.6V
open.
VIHmin=1.2V
VIHmax=2.0V
VOLmax=0.45V
l
VOHmin=1.35V
1.8V power domain.
SDC1_ VILmin=-0.3V
e
131 IO SDIO data bus D1 If unused, keep it
t
DATA1 VILmax=0.6V
open.
l
VIHmin=1.2V
c
VIHmax=2.0V
e a
VOLmax=0.45V
t i
VOHmin=1.35V
1.8V power domain.
u
SDC1_ VILmin=-0.3V
132 IO SDIO data bus D1 If unused, keep it
n
DATA0 VILmax=0.6V
open.
Q ide
VIHmin=1.2V
VIHmax=2.0V
1.8V power domain.
VOLmax=0.45V
SDC1_CLK 133 DO SDIO clock If unused, keep it
f
VOHmin=1.35V
open.
n
1.8V power domain.
VOLmax=0.45V
SDC1_CMD 134 DO SDIO command If unused, keep it
o
VOHmin=1.35V
open.
1.8V power domain.
C
External power VOLmax=0.45V
PM_ENABLE 127 DO If unused, keep it
control VOHmin=1.35V
open.
VILmin=-0.3V 1.8V power domain.
Wake up the host
WAKE_ON_ VILmax=0.6V Active low.
135 DI (EC21 module) by
WIRELESS VIHmin=1.2V If unused, keep it
FC20 module.
VIHmax=2.0V open.
1.8V power domain.
WLAN function
VOLmax=0.45V Active high.
WLAN_EN 136 DO control via FC20
VOHmin=1.35V If unused, keep it
module
open.
VILmin=-0.3V
1.8V power domain.
COEX_UART_ LTE/WLAN VILmax=0.6V
137 DI If unused, keep it
RX coexistence signal VIHmin=1.2V
open.
VIHmax=2.0V
l
data VOHmin=1.35V
open.
e
VILmin=-0.3V
1.8V power domain.
t
BT UART receive VILmax=0.6V
BT_RXD* 39 DI If unused, keep it
l
data VIHmin=1.2V
c
open.
VIHmax=2.0V
e ia
1.8V power domain.
BT UART clear to VOLmax=0.45V
t
BT_CTS* 40 DO If unused, keep it
u
send VOHmin=1.35V
open.
n
1.8V power domain.
BT function control VOLmax=0.45V
Q ide
BT_EN* 139 DO If unused, keep it
via FC20 module VOHmin=1.35V
open.
RF Interface
f
Pin Name Pin No. I/O Description DC Characteristics Comment
n
Diversity antenna If unused, keep it
ANT_DIV 35 AI 50 ohm impedance
o
pad open.
C
If unused, keep it
ANT_GNSS 47 AI GNSS antenna pad 50 ohm impedance
open.
GPIO Pins
el
Pin Name Pin No. I/O Description DC Characteristics Comment
t
VILmin=-0.3V
l
1.8V power domain.
c
Force the module to VILmax=0.6V
USB_BOOT 115 DI If unused, keep it
boot from USB port. VIHmin=1.2V
a
open.
e i
VIHmax=2.0V
u t
RESERVED Pins
n
Pin Name Pin No. I/O Description DC Characteristics Comment
Q ide
3, 18, 23,
28~34,
43, 55,
f
Keep these pins
RESERVED 73~84, Reserved
unconnected.
n
113, 114,
116, 117,
o
140~144
C
NOTES
The table below briefly summarizes the various operating modes referred in the following chapters.
Mode Details
Software is active. The module has been registered on the network, and
Idle
Normal it is ready to send and receive data.
l
Operation Network connection is ongoing. In this mode, the power consumption is
Talk/Data
decided by network setting and data transfer rate.
t e
Minimum
AT+CFUN command can set the module to a minimum functionality mode without
l
Functionality
c
removing the power supply. In this case, both RF function and USIM card will be invalid.
Mode
e ia
Airplane AT+CFUN command or W_DISABLE# pin can set the module to airplane mode. In this
t
Mode case, RF function will be invalid.
u
In this mode, the current consumption of the module will be reduced to the minimal level.
n
Sleep Mode During this mode, the module can still receive paging message, SMS, voice call and
Q ide
TCP/UDP data from the network normally.
In this mode, the power management unit shuts down the power supply. Software is not
Power down
active. The serial interface is not accessible. Operating voltage (connected to VBAT_RF
Mode
and VBAT_BB) remains applied.
n f
o
3.5. Power Saving
C
3.5.1. Sleep Mode
EC21 is able to reduce its current consumption to a minimum value during the sleep mode. The following
section describes power saving procedure of EC21 module.
If the host communicates with module via UART interface, the following preconditions can let the module
enter into sleep mode.
The following figure shows the connection between the module and the host.
Module Host
RXD TXD
TXD RXD
RI EINT
DTR GPIO
AP_READY GPIO
l
GND GND
t e
Figure 3: Sleep Mode Application via UART
c a l
e
Driving the host DTR to low level will wake up the module.
i
t
When EC21 has URC to report, RI signal will wake up the host. Refer to Chapter 3.16 for details
u
about RI behavior.
n
AP_READY will detect the sleep state of the host (can be configured to high level or low level
detection). Please refer to AT+QCFG=“apready” command for details.
NOTE
Q ide
f
AT+QCFG=“apready” command is under development.
o n
3.5.1.2. USB Application with USB Remote Wakeup Function
C
If the host supports USB suspend/resume and remote wakeup functions, the following three preconditions
must be met to let the module enter into sleep mode.
The following figure shows the connection between the module and the host.
Module Host
USB_VBUS VDD
USB_DP USB_DP
USB_DM USB_DM
AP_READY GPIO
GND GND
t el
Figure 4: Sleep Mode Application with USB Remote Wakeup
c a l
e
Sending data to EC21 through USB will wake up the module.
i
t
When EC21 has URC to report, the module will send remote wake-up signals via USB bus so as to
u
wake up the host.
Q ide n
3.5.1.3. USB Application with USB Suspend/Resume and RI Function
If the host supports USB suspend/resume, but does not support remote wake-up function, the RI signal is
f
needed to wake up the host.
n
There are three preconditions to let the module enter into the sleep mode.
o
Execute AT+QSCLK=1 command to enable sleep mode.
C
Ensure the DTR is held in high level or keep it open.
The host’s USB bus, which is connected with the module’s USB interface, enters into suspended
state.
The following figure shows the connection between the module and the host.
Module Host
USB_VBUS VDD
USB_DP USB_DP
USB_DM USB_DM
AP_READY GPIO
RI EINT
GND
l
GND
t e
Figure 5: Sleep Mode Application with RI
c a l
e
Sending data to EC21 through USB will wake up the module.
i
t
When EC21 has URC to report, RI signal will wake up the host.
u
Q ide n
3.5.1.4. USB Application without USB Suspend Function
If the host does not support USB suspend function, you should disconnect USB_VBUS with additional
control circuit to let the module enter into sleep mode.
n f
Execute AT+QSCLK=1 command to enable sleep mode.
Ensure the DTR is held in high level or keep it open.
o
Disconnect USB_VBUS.
C
The following figure shows the connection between the module and the host.
Module Host
GPIO
Power
USB_VBUS Switch VDD
USB_DP USB_DP
USB_DM USB_DM
RI EINT
AP_READY GPIO
GND GND
Switching on the power switch to supply power to USB_VBUS will wake up the module.
NOTE
Please pay attention to the level match shown in dotted line between the module and the host. Refer to
document [1] for more details about EC21 power management application.
When the module enters into airplane mode, the RF function does not work, and all AT commands
l
correlative with RF function will be inaccessible. This mode can be set via the following ways.
t e
Hardware:
c l
The W_DISABLE# pin is pulled up by default; driving it to low level will let the module enter into airplane
mode.
e t ia
Software:
u n
AT+CFUN command provides the choice of the functionality level.
Q ide
AT+CFUN=0: Minimum functionality mode; both USIM and RF functions are disabled.
AT+CFUN=1: Full functionality mode (by default).
AT+CFUN=4: Airplane mode. RF function is disabled.
n f
NOTES
o
1. The W_DISABLE# control function is disabled in firmware by default. It can be enabled by
AT+QCFG=“airplanecontrol” command. This command is under development.
C
2. The execution of AT+CFUN command will not affect GNSS function.
EC21 provides four VBAT pins for connection with the external power supply. There are two separate
voltage domains for VBAT.
The following table shows the details of VBAT pins and ground pins.
el
3.6.2. Decrease Voltage Drop
t
The power supply range of the module is from 3.3V to 4.3V. Please make sure that the input voltage will
c l
never drop below 3.3V. The following figure shows the voltage drop during burst transmission in 2G
a
network. The voltage drop will be less in 3G and 4G networks.
u e t i
Burst Burst
Transmission Transmission
Q ide n
f
VBAT Ripple
Drop
Min.3.3V
o n
Figure 7: Power Supply Limits during Burst Transmission
C
To decrease voltage drop, a bypass capacitor of about 100µF with low ESR should be used, and a
multi-layer ceramic chip (MLCC) capacitor array should also be used to provide the low ESR. The main
power supply from an external application has to be a single voltage source and can be expanded to two
sub paths with star structure. The width of VBAT_BB trace should be no less than 1mm; and the width of
VBAT_RF trace should be no less than 2mm. In principle, the longer the VBAT trace is, the wider it will be.
Three ceramic capacitors (100nF, 33pF, 10pF) are recommended to be applied to the VBAT pins. These
capacitors should be placed close to the VBAT pins. In addition, in order to get a stable power source, it is
suggested that you should use a zener diode of which reverse zener voltage is 5.1V and dissipation
power is more than 0.5W. The following figure shows the star structure of the power supply.
VBAT
VBAT_RF
VBAT_BB
+ +
D1 C1 C2 C3 C4 C5 C6 C7 C8
Module
l
Figure 8: Star Structure of the Power Supply
t e l
3.6.3. Reference Design for Power Supply
c a
Power design for the module is very important, as the performance of the module largely depends on the
e i
power source. The power supply is capable of providing sufficient current up to 2A at least. If the voltage
t
drop between the input and output is not too high, it is suggested that you should use an LDO to supply
u n
power for the module. If there is a big voltage difference between the input source and the desired output
(VBAT), a buck converter is preferred to be used as the power supply.
Q ide
The following figure shows a reference design for +5V input power source. The typical output of the power
supply is about 3.8V and the maximum load current is 3A.
f
MIC29302WU
n
DC_IN VBAT
2 4
o
IN OUT
GND
ADJ
EN
100K
C
51K 1%
1
4.7K 470R
470uF 100nF
470uF 100nF
47K
VBAT_EN 47K 1%
NOTE
In order to avoid damaging internal flash, please do not switch off the power supply when the module
works normally. Only after the module is shut down by PWRKEY or AT command, the power supply can
be cut off.
AT+CBC command can be used to monitor the VBAT_BB voltage value. For more details, please refer to
document [2].
l
The following table shows the pin definition of PWRKEY.
t e
Table 7: PWRKEY Pin Description
c l
Pin Name Pin No. Description DC Characteristics Comment
e ia
VIHmax=2.1V The output voltage is 0.8V
u t
PWRKEY 21 Turn on/off the module VIHmin=1.3V because of the diode drop in
n
VILmax=0.5V the Qualcomm chipset.
Q ide
When EC21 is in power down mode, it can be turned on to normal mode by driving the PWRKEY pin to a
low level for at least 100ms. It is recommended to use an open drain/collector driver to control the
PWRKEY. After STATUS pin (require external pull-up) outputting a low level, PWRKEY pin can be
f
released. A simple reference circuit is illustrated in the following figure.
n
PWRKEY
o
≥100ms
C
4.7K
Turn on pulse
47K
The other way to control the PWRKEY is using a button directly. When pressing the key, electrostatic
strike may generate from finger. Therefore, a TVS component is indispensable to be placed nearby the
button for ESD protection. A reference circuit is shown in the following figure.
S1
PWRKEY
TVS
Close to S1
l
Figure 11: Turn on the Module Using Keystroke
t e
The turn on scenario is illustrated in the following figure.
c a l
NOTE
u e t i
VBAT ≥100ms
n
VIH≥1.3V
Q ide
PWRKEY VIL≤0.5V
RESET_N
≥2.5s
f
STATUS
n
(OD)
≥12s
o
UART Inactive Active
C
≥13s
NOTE
Please make sure that VBAT is stable before pulling down PWRKEY pin. The time between them is no
less than 30ms.
Normal power down procedure: Turn off the module using the PWRKEY pin.
Normal power down procedure: Turn off the module using AT+QPOWD command.
Driving the PWRKEY pin to a low level voltage for at least 650ms, the module will execute power-down
l
procedure after the PWRKEY is released. The power-down scenario is illustrated in the following figure.
t e l
VBAT
c a
≥650ms ≥29.5s
u e t i
PWRKEY
n
STATUS
Q ide
(OD)
n f
Figure 13: Timing of Turning off Module
Co
3.7.2.2. Turn off Module Using AT Command
It is also a safe way to use AT+QPOWD command to turn off the module, which is similar to turning off the
module via PWRKEY pin.
NOTE
In order to avoid damaging internal flash, please do not switch off the power supply when the module
works normally. Only after the module is shut down by PWRKEY or AT command, the power supply can
be cut off.
The RESET_N pin can be used to reset the module. The module can be reset by driving RESET_N to a
low level voltage for time between 150ms and 460ms.
VIHmax=2.1V
l
RESET_N 20 Reset the module VIHmin=1.3V
VILmax=0.5V
t e l
The recommended circuit is similar to the PWRKEY control circuit. An open drain/collector driver or button
c
can be used to control the RESET_N.
e t ia
RESET_N
u n
TBD
Q ide
4.7K
Reset pulse
f
47K
o n
Figure 14: Reference Circuit of RESET_N by Using Driving Circuit
C
S2
RESET_N
TVS
Close to S2
VBAT
≤460ms
≥150ms
RESET_N VIH≥1.3V
VIL≤0.5V
Module
Running Resetting Restart
l
Status
t e
Figure 16: Timing of Resetting Module
NOTES
e c ia l
u t
1. Use RESET_N only when turning off the module by AT+QPOWD command and PWRKEY pin failed.
n
2. Ensure that there is no large capacitance on PWRKEY and RESET_N pins.
Q ide
3.9. USIM Card Interface
n f
The USIM card interface circuitry meets ETSI and IMT-2000 SIM interface requirements. Both 1.8V and
o
3.0V USIM cards are supported.
C
Table 9: Pin Definition of the USIM Card Interface
EC21 supports USIM card hot-plug via the USIM_PRESENCE pin. The function supports low level and
high level detections, and is disabled by default. Please refer to document [2] about AT+QSIMDET
command for details.
The following figure shows a reference design for USIM card interface with an 8-pin USIM card connector.
VDD_EXT USIM_VDD
51K 15K
USIM_GND 100nF USIM Card Connector
USIM_VDD
l
VCC GND
USIM_RST 22R
RST VPP
Module USIM_CLK
e
CLK IO
USIM_PRESENCE
t
22R
l
USIM_DATA 22R
c a
GND
33pF 33pF 33pF
u e n t i GND GND
Q ide
Figure 17: Reference Circuit of USIM Card Interface with an 8-Pin USIM Card Connector
f
If USIM card detection function is not needed, please keep USIM_PRESENCE unconnected. A reference
circuit for USIM card interface with a 6-pin USIM card connector is illustrated in the following figure.
o n
USIM_VDD
15K
C
USIM_GND 100nF
USIM Card Connector
USIM_VDD
VCC GND
USIM_RST 22R
RST VPP
Module USIM_CLK
CLK IO
22R
USIM_DATA 22R
GND GND
Figure 18: Reference Circuit of USIM Card Interface with a 6-Pin USIM Card Connector
In order to enhance the reliability and availability of the USIM card in your application, please follow the
criteria below in USIM circuit design:
Keep layout of USIM card as close to the module as possible. Keep the trace length as less than
200mm as possible.
Keep USIM card signals away from RF and VBAT traces.
Assure the ground between the module and the USIM card connector short and wide. Keep the trace
width of ground and USIM_VDD no less than 0.5mm to maintain the same electric potential.
To avoid cross-talk between USIM_DATA and USIM_CLK, keep them away from each other and
shield them with surrounded ground.
In order to offer good ESD protection, it is recommended to add a TVS diode array whose parasitic
l
capacitance should not be more than 50pF. The 22 ohm resistors should be added in series between
the module and the USIM card so as to suppress EMI spurious transmission and enhance ESD
e
protection. The 33pF capacitors are used for filtering interference of GSM900. Please note that the
t
USIM peripheral circuit should be close to the USIM card connector.
c l
The pull-up resistor on USIM_DATA line can improve anti-jamming capability when long layout trace
a
and sensitive occasion are applied, and should be placed close to the USIM card connector.
u e n t i
Q ide
EC21 contains one integrated Universal Serial Bus (USB) transceiver which complies with the USB 2.0
specification and supports high-speed (480Mbps) and full-speed (12Mbps) modes. The USB interface is
f
used for AT command communication, data transmission, GNSS NMEA sentences output, software
debugging, firmware upgrade and voice over USB*. The following table shows the pin definition of USB
n
interface.
Co
Table 10: Pin Description of USB Interface
Require differential
USB_DP 69 IO USB differential data bus (positive)
impedance of 90Ω
Require differential
USB_DM 70 IO USB differential data bus (minus)
impedance of 90Ω
GND 72 Ground
For more details about the USB 2.0 specifications, please visit http://www.usb.org/home.
The USB interface is recommended to be reserved for firmware upgrade in your design. The following
figure shows a reference circuit of USB interface.
Test Points
Minimize these stubs
Module R3 NM_0R
MCU
VDD R4 NM_0R
R1 0R USB_DM
USB_DM
R2 0R
USB_DP USB_DP
l
Close to Module GND
GND
c t e l
a
Figure 19: Reference Circuit of USB Application
u e t i
In order to ensure the integrity of USB data line signal, components R1, R2, R3 and R4 must be placed
n
close to the module, and also these resistors should be placed close to each other. The extra stubs of
Q ide
trace must be as short as possible.
In order to ensure the USB interface design corresponding with the USB 2.0 specification, please comply
with the following principles:
f
It is important to route the USB signal traces as differential pairs with total grounding. The impedance
n
of USB differential trace is 90 ohm.
o
Do not route signal traces under crystals, oscillators, magnetic devices or RF signal traces. It is
important to route the USB differential traces in inner-layer with ground shielding on not only upper
C
and lower layers but also right and left sides.
Pay attention to the influence of junction capacitance of ESD protection components on USB data
lines. Typically, the capacitance value should be less than 2pF.
Keep the ESD protection components to the USB connector as close as possible.
NOTES
The module provides two UART interfaces: the main UART interface and the debug UART interface. The
following shows their features.
The main UART interface supports 4800, 9600, 19200, 38400, 57600, 115200, 230400, 460800,
921600 and 3000000bps baud rates, and the default is 115200bps. The interface is used for data
transmission and AT command communication.
The debug UART interface supports 115200bps baud rate. It is used for Linux console and log
output.
l
The following tables show the pin definition of the main UART interface.
c t e l
Table 11: Pin Definition of the Main UART Interface
e ia
Pin Name Pin No. I/O Description Comment
u t
RI 62 DO Ring indicator
n
DCD 63 DO Data carrier detection
Q ide
CTS 64 DO Clear to send
f
DTR 66 DI Sleep mode control
n
TXD 67 DO Transmit data
o
RXD 68 DI Receive data
C
Table 12: Pin Definition of the Debug UART Interface
VOL 0 0.45 V
l
VOH 1.35 1.8 V
t e
The module provides 1.8V UART interface. A level translator should be used if your application is
l
equipped with a 3.3V UART interface. A level translator TXS0108EPWR provided by Texas Instrument is
c
recommended. The following figure shows a reference design.
e t ia
VDD_EXT VCCA VCCB
u
VDD_MCU
0.1uF
0.1uF
n
OE GND
Q ide
RI A1 B1 RI_MCU
DCD A2 B2 DCD_MCU
CTS A3 Translator B3 CTS_MCU
A4 B4
f
RTS RTS_MCU
DTR A5 B5 DTR_MCU
n
TXD A6 B6 TXD_MCU
RXD A7 B7 RXD_MCU
o
51K 51K
A8 B8
C
Figure 20: Reference Circuit with Translator Chip
Another example with transistor translation circuit is shown as below. The circuit design of dotted line
section can refer to the design of solid line section, in terms of both module input and output circuit
designs; but please pay attention to the direction of connection.
4.7K
VDD_EXT VDD_EXT
1nF
MCU/ARM Module
10K
TXD RXD
RXD TXD
1nF
10K
VDD_EXT
VCC_MCU 4.7K
RTS RTS
CTS CTS
GPIO DTR
EINT RI
l
GPIO DCD
GND GND
c t e l
Figure 21: Reference Circuit with Transistor Circuit
NOTE
u e t ia
n
Transistor circuit solution is not suitable for applications with high baud rates exceeding 460Kbps.
Q ide
f
3.12. PCM and I2C Interfaces
n
EC21 provides one Pulse Code Modulation (PCM) digital interface for audio design, which supports the
o
following modes:
C
Primary mode (short frame synchronization, works as both master and slave)
Auxiliary mode (long frame synchronization, works as master only)
In primary mode, the data is sampled on the falling edge of the PCM_CLK and transmitted on the rising
edge. The PCM_SYNC falling edge represents the MSB. In this mode, PCM_CLK supports 128, 256, 512,
1024 and 2048kHz for different speech codecs.
In auxiliary mode, the data is also sampled on the falling edge of the PCM_CLK and transmitted on the
rising edge. But the PCM_SYNC rising edge represents the MSB. In this mode, PCM interface operates
with a 128kHz PCM_CLK and an 8kHz, 50% duty cycle PCM_SYNC only.
EC21 supports 8-bit A-law* and μ-law*, and also 16-bit linear data formats. The following figures show the
primary mode’s timing relationship with 8kHz PCM_SYNC and 2048kHz PCM_CLK, as well as the
auxiliary mode’s timing relationship with 8kHz PCM_SYNC and 128kHz PCM_CLK.
125us
PCM_SYNC
PCM_OUT
l
PCM_IN
t e
Figure 22: Primary Mode Timing
e c ia l
125us
u t
PCM_CLK 1 2 15 16
Q ide n
PCM_SYNC
MSB LSB
f
PCM_OUT
MSB LSB
n
PCM_IN
Co
Figure 23: Auxiliary Mode Timing
The following table shows the pin definition of PCM and I2C interfaces which can be applied on audio
codec design.
Clock and mode can be configured by AT command, and the default configuration is master mode using
short frame synchronization format with 2048kHz PCM_CLK and 8kHz PCM_SYNC. Please refer to
document [2] about AT+QDAI command for details.
The following figure shows a reference design of PCM interface with external codec IC.
l
MICBIAS
t e
INP
BIAS
PCM_CLK BCLK
l
INN
PCM_SYNC
c
LRCK
PCM_OUT DAC
e ia
PCM_IN ADC
u t
LOUTP
n
I2C_SCL SCL
I2C_SDA SDA LOUTN
Q ide
4.7K
4.7K
Module Codec
1.8V
f
Figure 24: Reference Circuit of PCM Application with Audio Codec
NOTES
o n
C
1. “*” means under development.
2. It is recommended to reserve RC (R=22 ohm, C=22pF) circuit on the PCM lines, especially for
PCM_CLK.
3. EC21 works as a master device pertaining to I2C interface.
The module provides two analog-to-digital converters (ADC). AT+QADC=0 command can be used to
read the voltage value on ADC0 pin. AT+QADC=1 command can be used to read the voltage value on
ADC1 pin. For more details about these AT commands, please refer to document [2].
In order to improve the accuracy of ADC, the trace of ADC should be surrounded by ground.
l
Pin Name Pin No. Description
e
ADC0 45 General purpose analog to digital converter
t l
ADC1 44 General purpose analog to digital converter
e c ia
The following table describes the characteristic of the ADC function.
u n t
Table 16: Characteristic of the ADC
Q ide
Parameter Min. Typ. Max. Unit
f
ADC1 Voltage Range 0.3 VBAT_BB V
n
ADC Resolution 15 bits
NOTES
1.
2.
3.
Co
ADC input voltage must not exceed VBAT_BB.
It is prohibited to supply any voltage to ADC pins when VBAT is removed.
It is recommended to use resistor divider circuit for ADC application.
The network indication pins can be used to drive network status indication LEDs. The module provides
two pins which are NET_MODE and NET_STATUS. The following tables describe the pin definition and
logic level changes in different network status.
l
Indicate the module’s network registration
NET_MODE1) 5 DO
status
e
1.8V power domain
t
Indicate the module’s network activity
NET_STATUS 6 DO
l
status
NOTE
e c t ia
u
1)
n
means that this pin cannot be pulled up before startup.
Q ide
Table 18: Working State of Network Connection Status/Activity Indicator
f
Pin Name Logic Level Changes Network Status
n
Always High Registered on LTE network
NET_MODE
o
Always Low Others
C
Flicker slowly (200ms High/1800ms Low) Network searching
VBAT
Module
2.2K
Network 4.7K
Indicator
47K
l
Figure 25: Reference Circuit of the Network Indicator
c t e l
a
3.15. STATUS
u e t i
The STATUS pin is an open drain output for indicating the module’s operation status. You can connect it
n
to a GPIO of DTE with a pull up resistor, or as the LED indication circuit shown below. When the module is
Q ide
turned on normally, the STATUS will present the low state. Otherwise, the STATUS will present
high-impedance state.
f
Table 19: Pin Definition of STATUS
n
Pin Name Pin No. I/O Description Comment
o
STATUS 61 OD Indicate the module’s operation status Require external pull-up
C
The following figure shows different circuit designs of STATUS, and you can choose either one according
to your application demands.
VBAT
VDD_MCU
10K
2.2K
Module Module
No matter on which port URC is presented, URC will trigger the behavior of RI pin.
NOTE
URC can be output from UART port, USB AT port and USB modem port by AT+QURCCFG command.
The default port is USB AT port.
el
In addition, RI behavior can be configured flexibly. The default behavior of the RI is shown as below.
c t l
Table 20: Behavior of the RI
e t ia
State Response
u n
Idle RI keeps in high level
Q ide
URC RI outputs 120ms low pulse when new URC returns
The RI behavior can be changed by AT+QCFG=“urc/ri/ring” command. Please refer to document [2]
f
for details.
o n
3.17. SGMII Interface
C
EC21 includes an integrated Ethernet MAC with an SGMII interface and two management interfaces, key
features of the SGMII interface are shown below:
IEEE802.3 compliance
Full duplex at 1000Mbps
Half/full duplex for 10/100Mbps
Support VLAN tagging
Support IEEE1588 and Precision Time Protocol (PTP)
Can be used to connect to external Ethernet PHY like AR8033, or to an external switch
Management interfaces support dual voltage 1.8V/2.85V
l
SGMII_MCLK 122 DO 1.8V/2.85V power domain
Input/Output) clock
e
Configurable power source.
t
SGMII MDIO pull-up power 1.8V/2.85V power domain.
USIM2_VDD 128 PO
l
source External pull-up power source for
c
SGMII MDIO pins.
e ia
SGMII Signal Part
u t
Connect with a 0.1uF capacitor,
SGMII_TX_M 123 AO SGMII transmission-minus
n
close to the PHY side.
Q ide
Connect with a 0.1uF capacitor,
SGMII_TX_P 124 AO SGMII transmission-plus
close to the PHY side.
Connect with a 0.1uF capacitor,
SGMII_RX_P 125 AI SGMII receiving-plus
close to EC21 module.
f
Connect with a 0.1uF capacitor,
SGMII_RX_M 126 AI SGMII receiving-minus
n
close to EC21 module.
o
The following figure shows the simplified block diagram for Ethernet application.
C
SGMII
MDI Ethernet
Module AR8033 RJ45
Transformer
Control
The following figure shows a reference design of SGMII interface with PHY AR8033 application.
Close to Module
SGMII_RX_P C1 0.1uF SOP
l
SGMII Data
SGMII_TX_P 0.1uF C3 SIP
e
0.1uF C4
t
SGMII_TX_M SIN
l
Close to AR8033
e c ia
Figure 28: Reference Circuit of SGMII Interface with PHY AR8033 Application
u n t
In order to enhance the reliability and availability in your application, please follow the criteria below in the
Q ide
Ethernet PHY circuit design:
Keep SGMII data and control signals away from RF and VBAT trace.
Keep the maximum trace length less than 10inch and keep skew on the differential pairs less than
f
20mil.
n
The differential impedance of SGMII data trace is 100ohm±10%.
To minimize crosstalk, the distance between separate adjacent pairs that are on the same layer must
o
be equal to or larger than 40mil.
C
NOTE
For more information about SGMII application, please refer to document [5] and document [7].
EC21 supports a low-power SDIO 3.0 interface for WLAN and a UART/PCM interface for BT.
The following table shows the pin definition of wireless connectivity interfaces.
l
WLAN Part
t e
SDC1_DATA3 129 IO SDIO data bus D3 1.8V power domain
c l
SDC1_DATA2 130 IO SDIO data bus D2 1.8V power domain
e ia
SDC1_DATA1 131 IO SDIO data bus D1 1.8V power domain
u t
SDC1_DATA0 132 IO SDIO data bus D0 1.8V power domain
n
SDC1_CLK 133 DO SDIO clock 1.8V power domain
Q ide
SDC1_CMD 134 IO SDIO command 1.8V power domain
f
WLAN_EN 136 DO 1.8V power domain
FC20 module. Active high.
n
Coexistence and Control Part
o
PM_ENABLE 127 DO External power control 1.8V power domain
C
135 DI 1.8V power domain
WIRELESS by FC20 module.
BT Part*
el
NOTES
t
1. “*” means under development.
c l
2. 1) Pads 24~27 are multiplexing pins used for audio design on EC21 module and BT function on FC20
a
module.
u e t i
The following figure shows a reference design of wireless connectivity interfaces with Quectel FC20
n
module.
Q ide
Module FC20 Module
SDC1_DATA3 SDIO_D3
SDC1_DATA2 SDIO_D2
f
SDC1_DATA1 SDIO_D1
WLAN SDC1_DATA0 SDIO_D0
n
SDC1_CLK SDIO_CLK
SDC1_CMD SDIO_CMD
o
WLAN_EN WLAN_EN
WLAN_SLP_CLK 32KHz_IN
C
WAKE_ON_WIRELESS WAKE_ON_WIRELESS
COEX_UART_RX LTE_UART_TXD
COEX & Control
COEX_UART_TX LTE_UART_RXD
BT_EN BT_EN
BT_RTS BT_UART_RTS
BT_CTS BT_UART_CTS
BT_TXD BT_UART_RXD
BT BT_RXD BT_UART_TXD
PCM_IN PCM_OUT
PCM_OUT PCM_IN
PCM_CLK PCM_CLK
PCM_SYNC PCM_SYNC
Figure 29: Reference Circuit of Wireless Connectivity Interfaces with FC20 Module
NOTES
EC21 provides a low power SDIO 3.0 interface and control interface for WLAN design.
l
SDIO interface supports the following modes:
t e
l
Single data rate (SDR) mode (up to 200MHz)
c
Double data rate (DDR) mode (up to 52MHz)
e ia
As SDIO signals are very high-speed, in order to ensure the SDIO interface design corresponds with the
u t
SDIO 3.0 specification, please comply with the following principles:
n
It is important to route the SDIO signal traces with total grounding. The impedance of SDIO signal
Q ide
trace is 50 ohm (±10%).
Protect other sensitive signals/circuits (RF, analog signals, etc.) from SDIO corruption and protect
SDIO signals from noisy signals (clocks, DCDCs, etc.).
f
It is recommended to keep matching length between CLK and DATA/CMD less than 1mm and total
routing length less than 50mm.
n
Keep termination resistors within 15~24 ohm on clock lines near the module and keep the route
o
distance from the module clock pins to termination resistors less than 5mm.
Make sure the adjacent trace spacing is 2x line width and bus capacitance is less than 15pF.
C
3.18.2. BT Interface*
EC21 supports a dedicated UART interface and a PCM interface for BT function application.
Further information about BT interface will be added in future version of this document.
NOTE
EC21 provides a USB_BOOT pin. During development or factory production, USB_BOOT pin can force
the module to boot from USB port for firmware upgrade.
l
Force the module to boot from USB
USB_BOOT 115 DI Active high.
port
If unused, keep it open.
t e l
The following figure shows a reference circuit of USB_BOOT interface.
e c ia
Module
u n t
Q ide
VDD_EXT
Test point
10K
USB_BOOT
f
Close to test point
TVS
o n
C
Figure 30: Reference Circuit of USB_BOOT Interface
4 GNSS Receiver
l
EC21 includes a fully integrated global navigation satellite system solution that supports Gen8C-Lite of
e
Qualcomm (GPS, GLONASS, BeiDou, Galileo and QZSS).
t l
EC21 supports standard NMEA-0183 protocol, and outputs NMEA sentences at 1Hz data update rate via
c
USB interface by default.
e t ia
By default, EC21 GNSS engine is switched off. It has to be switched on via AT command. For more
u
details about GNSS engine technology and configurations, please refer to document [3].
Q ide
4.2. GNSS Performance
n
f
The following table shows the GNSS performance of EC21.
o n
Table 24: GNSS Performance
C
Parameter Description Conditions Typ. Unit
Autonomous 35 s
Cold start
@open sky
XTRA enabled 18 s
TTFF
(GNSS)
Autonomous 26 s
Warm start
@open sky
XTRA enabled 2.2 s
Autonomous 2.5 s
Hot start
@open sky
XTRA enabled 1.8 s
Accuracy Autonomous
CEP-50 <1.5 m
(GNSS) @open sky
NOTES
1. Tracking sensitivity: the lowest GNSS signal value at the antenna port on which the module can keep
on positioning for 3 minutes.
l
2. Reacquisition sensitivity: the lowest GNSS signal value at the antenna port on which the module can
fix position again within 3 minutes after loss of lock.
e
3. Cold start sensitivity: the lowest GNSS signal value at the antenna port on which the module fixes
t
position within 3 minutes after executing cold start command.
e c ia l
u t
4.3. Layout Guidelines
Q ide n
The following layout guidelines should be taken into account in your design.
Maximize the distance among GNSS antenna, main antenna and the Rx-diversity antenna.
Digital circuits such as USIM card, USB interface, camera module, display connector and SD card
f
should be kept away from the antennas.
n
Use ground vias around the GNSS trace and sensitive analog signal traces to provide coplanar
isolation and protection.
o
Keep 50 ohm characteristic impedance for the ANT_GNSS trace.
C
Please refer to Chapter 5 for GNSS antenna reference design and antenna consideration.
5 Antenna Interfaces
EC21 antenna interfaces include a main antenna interface, an Rx-diversity antenna interface which is
used to resist the fall of signals caused by high speed movement and multipath effect, and a GNSS
antenna interface. The antenna interfaces have an impedance of 50 ohm.
el
5.1. Main/Rx-diversity Antenna Interface
c t l
5.1.1. Pin Definition
e ia
The pin definition of main antenna and Rx-diversity antenna interfaces is shown below.
u n t
Table 25: Pin Definition of the RF Antenna
Q ide
Pin Name Pin No. I/O Description Comment
f
ANT_DIV 35 AI Receive diversity antenna pad 50 ohm impedance
o n
5.1.2. Operating Frequency
C
Table 26: Module Operating Frequencies
l
B40 2300~2400 2300~2400 MHz
t e l
5.1.3. Reference Design of RF Antenna Interface
c a
A reference design of ANT_MAIN and ANT_DIV antenna pads is shown as below. It should reserve a
e i
π-type matching circuit for better RF performance. The capacitors are not mounted by default.
u n t
Main
Module antenna
Q ide
R1 0R
ANT_MAIN
C1 C2
f
NM NM
Diversity
n
antenna
R2 0R
o
ANT_DIV
C3 C4
C
NM NM
NOTES
1. Keep a proper distance between the main antenna and the Rx-diversity antenna to improve the
receiving sensitivity.
2. ANT_DIV function is enabled by default.
3. Place the π-type matching components (R1, C1, C2, R2, C3, C4) as close to the antenna as
possible.
For user’s PCB, the characteristic impedance of all RF traces should be controlled as 50 ohm. The
impedance of the RF traces is usually determined by the trace width (W), the materials’ dielectric constant,
the distance between signal layer and reference ground (H), and the clearance between RF trace and
ground (S). Microstrip line or coplanar waveguide line is typically used in RF layout for characteristic
impedance control. The following are reference designs of microstrip line or coplanar waveguide line with
different PCB structures
t el
.
e c ia l
u n t
Figure 32: Microstrip Line Design on a 2-layer PCB
Q ide
n f
Co Figure 33: Coplanar Waveguide Line Design on a 2-layer PCB
l
Figure 34: Coplanar Waveguide Line Design on a 4-layer PCB (Layer 3 as Reference Ground)
c t e l
u e t ia
Q ide n
n f
Figure 35: Coplanar Waveguide Line Design on a 4-layer PCB (Layer 4 as Reference Ground)
o
In order to ensure RF performance and reliability, the following principles should be complied with in RF
C
layout design:
Use impedance simulation tool to control the characteristic impedance of RF traces as 50 ohm.
The GND pins adjacent to RF pins should not be hot welded, and should be fully connected to
ground.
The distance between the RF pins and the RF connector should be as short as possible, and all the
right angle traces should be changed to curved ones.
There should be clearance area under the signal pin of the antenna connector or solder joint.
The reference ground of RF traces should be complete. Meanwhile, adding some ground vias around
RF traces and the reference ground could help to improve RF performance. The distance between
the ground vias and RF traces should be no less than two times the width of RF signal traces (2*W).
The following tables show the pin definition and frequency specification of GNSS antenna interface.
el
Table 28: GNSS Frequency
c t l
Type Frequency Unit
e ia
GPS/Galileo/QZSS 1575.42±1.023 MHz
u t
GLONASS 1597.5~1605.8 MHz
n
BeiDou 1561.098±2.046 MHz
Q ide
A reference design of GNSS antenna is shown as below.
f
VDD
n
GNSS
0.1uF
o
Antenna 10R
Module
C
47nH
100pF
ANT_GNSS
NM NM
NOTES
1. An external LDO can be selected to supply power according to the active antenna requirement.
2. If the module is designed with a passive antenna, then the VDD circuit is not needed.
The following table shows the requirements on main antenna, Rx-diversity antenna and GNSS antenna.
Type Requirements
l
Frequency range: 1561~1615MHz
Polarization: RHCP or linear
e
VSWR: <2 (Typ.)
t
Passive antenna gain: >0dBi
l
GNSS
c
Active antenna noise figure: <1.5dB
Active antenna gain: >-2dBi
e ia
Active antenna embedded LNA gain: 20dB (Typ.)
t
Active antenna total gain: >18dBi (Typ.)
u
VSWR: ≤2
n
Gain (dBi): 1
Q ide
Max input power (W): 50
Input Impedance (ohm): 50
Polarization type: Vertical
f
Cable insertion loss: <1dB
GSM/WCDMA/LTE
(GSM850, GSM900, WCDMA B5/B8,
n
LTE B5/B8/B12/B13/B18/B19/B20/B26/B28)
Cable insertion loss: <1.5dB
o
(GSM1800, GSM1900, WCDMA B1/B2/B4, LTE B1/B2/B3/B4)
Cable insertion loss <2dB
C
(LTE B7/B40)
t el
e c ia l
u n t
Q ide
Figure 37: Dimensions of the UF.L-R-SMT Connector (Unit: mm)
n f
U.FL-LP serial connectors listed in the following figure can be used to match the UF.L-R-SMT.
Co
Figure 38: Mechanicals of UF.L-LP Connectors
t el
e c ia l
u n t
Q ide
Figure 39: Space Factor of Mated Connector (Unit: mm)
n f
Co
l
6.1. Absolute Maximum Ratings
t e
Absolute maximum ratings for power supply and voltage on digital and analog pins of the module are
c l
listed in the following table.
e t ia
Table 30: Absolute Maximum Ratings
u n
Parameter Min. Max. Unit
Q ide
VBAT_RF/VBAT_BB -0.3 4.7 V
f
Peak Current of VBAT_BB 0 0.8 A
n
Peak Current of VBAT_RF 0 1.8 A
o
Voltage at Digital Pins -0.3 2.3 V
C
Voltage at ADC0 0 VBAT_BB V
VBAT VBAT_BB and Voltage must stay within the 3.3 3.8 4.3 V
el
6.3. Operating Temperature
c t l
The operating temperature is listed in the following table.
u e t ia
Table 32: Operating Temperature
n
Parameter Min. Typ. Max. Unit
Q ide
Operation Temperature Range1) -35 +25 +75 ºC
NOTES
n f
o
1)
1. Within operation temperature range, the module is 3GPP compliant.
C
2)
2. Within extended temperature range, the module remains the ability to establish and maintain a
voice, SMS, data transmission, emergency call, etc. There is no unrecoverable malfunction. There
are also no effects on radio spectrum and no harm to radio network. Only one or more parameters
like Pout might reduce in their value and exceed the specified tolerances. When the temperature
returns to the normal operating temperature levels, the module will meet 3GPP specifications again.
l
AT+CFUN=0 (USB disconnected) 1.0 mA
e
WCDMA PF=64 (USB disconnected) 2.8 mA
c t l
Sleep state WCDMA PF=128 (USB disconnected) 2.3 mA
e ia
LTE-FDD PF=64 (USB disconnected) 2.2 mA
u t
LTE-FDD PF=128 (USB disconnected) 2.2 mA
n
WCDMA PF=64 (USB disconnected) 21.6 mA
Q ide
WCDMA PF=64 (USB connected) 31.6 mA
Idle state
(GNSS OFF)
LTE-FDD PF=64 (USB disconnected) 23.7 mA
f
LTE-FDD PF=64 (USB connected) 36.5 mA
n
IVBAT
WCDMA B2 HSDPA @22.09dBm 542.0 mA
o
WCDMA B2 HSUPA @22.28dBm 681.0 mA
C
WCDMA B4 HSDPA @21.94dBm 550.0 mA
WCDMA data transfer
(GNSS OFF)
WCDMA B4 HSUPA @21.81dBm 547.0 mA
l
WCDMA PF=64 (USB disconnected) 2.1 mA
t e
Sleep state WCDMA PF=128 (USB disconnected) 1.7 mA
c l
LTE-FDD PF=64 (USB disconnected) 2.9 mA
e ia
LTE-FDD PF=128 (USB disconnected) 2.4 mA
u t
WCDMA PF=64 (USB disconnected) 22.0 mA
Q ide n
WCDMA PF=64 (USB connected) 32.0 mA
Idle state
LTE-FDD PF=64 (USB disconnected) 23.6 mA
f
LTE-FDD PF=64 (USB connected) 33.6 mA
n
IVBAT WCDMA B1 HSDPA @22.59dBm 589.0 mA
o
WCDMA data WCDMA B1 HSUPA @22.29dBm 623.0 mA
(GNSS OFF) WCDMA B5 HSDPA @22.22dBm 511.0 mA
C
WCDMA B5 HSUPA @21.64dBm 503.0 mA
l
FDD-LTE PF=128 (USB disconnected) TBD mA
e
WCDMA PF=64 (USB disconnected) TBD mA
t l
WCDMA PF=64 (USB connected) TBD mA
c
Idle state
a
(GNSS OFF) LTE-FDD PF=64 (USB disconnected) TBD mA
e t i
LTE-FDD PF=64 (USB connected) TBD mA
u n
GSM900 4DL/1UL @32.3dBm 220 mA
Q ide
GSM900 3DL/2UL @32.18dBm 387 mA
f
GPRS data transfer GSM900 1DL/4UL @29.4dBm 555 mA
n
(GNSS OFF) DCS1800 4DL/1UL @29.6dBm 185 mA
o
DCS1800 3DL/2UL @29.1dBm 305 mA
C
DCS1800 2DL/3UL @28.8dBm 431 mA
l
LTE-FDD B1 @23.45dBm 807 mA
t e
LTE-FDD B3 @23.4dBm 825 mA
c l
LTE data transfer LTE-FDD B5 @23.4dBm 786 mA
e ia
(GNSS OFF) LTE-FDD B7 @23.86dBm 887 mA
u t
LTE-FDD B8 @23.5dBm 675 mA
n
LTE-FDD B20 @23.57dBm 770 mA
Q ide
GSM900 PCL=5 @32.8dBm 336 mA
GSM voice call
PCS1800 PCL=0 @29.3dBm 291 mA
f
WCDMA B1 @23.69dBm 683 mA
n
WCDMA voice call WCDMA B5 @23.61dBm 741 mA
o
WCDMA B8 @23.35dBm 564 mA
C
Table 36: EC21-KL Current Consumption
l
Parameter Description Conditions Typ. Unit
t e
OFF state Power down 20 uA
c l
AT+CFUN=0 (USB disconnected) 1.0 mA
e ia
Sleep state LTE-FDD PF=64 (USB disconnected) 2.5 mA
u t
LTE-FDD PF=128 (USB disconnected) 2.0 mA
n
IVBAT
Q ide
Idle state LTE-FDD PF=64 (USB disconnected) 22.0 mA
(GNSS OFF) LTE-FDD PF=64 (USB connected) 32.0 mA
f
LTE data transfer
(GNSS OFF) LTE-FDD B13 @23.26dBm 534.0 mA
o n
Table 38: EC21-AUV Current Consumption
C
Parameter Description Conditions Typ. Unit
l
WCDMA B8 HSUPA @21.78dBm 555.0 mA
t e
LTE-FDD B1 @23.12dBm 721.0 mA
c l
LTE-FDD B3 @23.04dBm 734.0 mA
e a
LTE data transfer
i
LTE-FDD B5 @23.16dBm 669.0 mA
t
(GNSS OFF)
u
LTE-FDD B8 @23.21dBm 698.0 mA
n
LTE-FDD B28 @23.57dBm 790.0 mA
Q ide
WCDMA B1 @22.72dBm 640.0 mA
f
WCDMA B8 @23.27dBm 626.0 mA
o n
Table 39: GNSS Current Consumption of EC21 Series Module
C
Parameter Description Conditions Typ. Unit
l
DCS1800/PCS1900 30dBm±2dB 0dBm±5dB
e
GSM850/GSM900 (8-PSK) 27dBm±3dB 5dBm±5dB
t l
DCS1800/PCS1900 (8-PSK) 26dBm±3dB 0dBm±5dB
c a
WCDMA bands 24dBm+1/-3dB <-50dBm
e t i
LTE-FDD bands 23dBm±2dB <-44dBm
u n
LTE-TDD bands 23dBm±2dB <-44dBm
Q ide
NOTE
f
In GPRS 4 slots TX mode, the maximum output power is reduced by 3.0dB. The design conforms to the
GSM specification as described in Chapter 13.16 of 3GPP TS 51.010-1.
o n
6.6. RF Receiving Sensitivity
C
The following tables show the conducted RF receiving sensitivity of EC21 series module.
l
LTE-FDD B20 (10M) -97.5dBm -99.0dBm -102.5dBm -93.3dBm
t e l
Table 42: EC21-A Conducted RF Receiving Sensitivity
c a
Frequency Primary Diversity SIMO 3GPP (SIMO)
e t i
WCDMA B2 -110.0dBm / / -104.7dBm
u n
WCDMA B4 -110.0dBm / / -106.7dBm
Q ide
WCDMA B5 -110.5dBm / / -104.7dBm
f
LTE-FDD B4 (10M) -97.5dBm -99.0dBm -101.0dBm -96.3dBm
n
LTE-FDD B12 (10M) -96.5dBm -98.0dBm -101.0dBm -93.3dBm
C
LTE-FDD B4 (10M)
o
Table 43: EC21-V Conducted RF Receiving Sensitivity
Frequency
-97.5dBm
-95.0dBm
Diversity
-99.0dBm
-97.0dBm
SIMO
-101.0dBm
-100.0dBm
3GPP (SIMO)
-96.3dBm
-93.3dBm
el
Table 45: EC21-AUTL Conducted RF Receiving Sensitivity
t l
Frequency Primary Diversity SIMO 3GPP (SIMO)
c a
LTE-FDD B3 (10M) -98.0dBm -96.0dBm -100.0dBm -93.3dBm
e t i
LTE-FDD B7 (10M) -97.0dBm -95.0dBm -98.5dBm -94.3dBm
u n
LTE-FDD B28 (10M) -97.0dBm -99.0dBm -102.0dBm -94.8dBm
Q ide
Table 46: EC21-KL Conducted RF Receiving Sensitivity
f
Frequency Primary Diversity SIMO 3GPP (SIMO)
n
LTE-FDD B1 (10M) -98.0dBm -99.5dBm -100.5dBm -96.3dBm
o
LTE-FDD B3 (10M) -97.0dBm -97.5dBm -99.5dBm -93.3dBm
C
LTE-FDD B5 (10M) -98.0dBm -99.5dBm -100.5dBm -94.3dBm
l
LTE-FDD B8 (10M) -98.4dBm -99.0dBm -101.2dBm -93.3dBm
e
LTE-FDD B18 (10M) -99.5dBm -99.0dBm -101.7dBm -96.3dBm
t l
LTE-FDD B19 (10M) -99.2dBm -99.0dBm -101.4dBm -96.3dBm
c a
LTE-FDD B26 (10M) -99.5dBm -99.0dBm -101.5dBm -93.8dBm
u e n t i
Table 49: EC21-AUV Conducted RF Receiving Sensitivity
Q ide
Frequency Primary Diversity SIMO 3GPP (SIMO)
f
WCDMA B5 -111.0dBm / / -104.7dBm
n
WCDMA B8 -111.0dBm / / -103.7dBm
o
LTE-FDD B1 (10M) -97.2dBm -97.2dBm -100.2dBm -96.3dBm
C
LTE-FDD B3 (10M) -98.2dBm -98.7dBm -100.7dBm -93.3dBm
NOTES
1)
1. SIMO is a smart antenna technology that uses a single antenna at the transmitter side and two
antennas at the receiver side, which can improve RX performance.
2. “*” means under development.
The module is not protected against electrostatic discharge (ESD) in general. Consequently, it is subject
to ESD handling precautions that typically apply to ESD sensitive components. Proper ESD handling and
packaging procedures must be applied throughout the processing, handling and operation of any
application that incorporates the module.
l
Table 50: Electrostatic Discharge Characteristics
e
Tested Points Contact Discharge Air Discharge Unit
t l
VBAT, GND ±5 ±10 kV
c a
All Antenna Interfaces ±4 ±8 kV
e t i
Other Interfaces ±0.5 ±1 kV
u
Q ide n
n f
Co
7 Mechanical Dimensions
This chapter describes the mechanical dimensions of the module. All dimensions are measured in mm.
l
7.1. Mechanical Dimensions of the Module
c t e l
(32+/-0.15)
e a
2.4+/-0.2
u n t i
Q ide
(29+/-0.15)
n f
Co Figure 40: Module Top and Side Dimensions
0.8
32.0
1.30 3.85
1.90
3.5
3.35 1.30
5.96
2.0
2.0
0.82
1.8 3.0 1.8
l
1.15
2.8
29.0
2.15
e
4.88
t
1.10
l
1.05
1.10
c
1.6
e ia
6.75
u n t 4.8
1.7
0.8
Q ide
3.2 3.4 3.2 3.4 3.2
3.5
4.4
2.49
n f
Figure 41: Module Bottom Dimensions (Bottom View)
Co
1.90
3.40
1.10 2.00
3.00
1.10
2.00
7.80
2.00
4.80
el
1.80 3.00 1.80
t
0.50 4.80
2.80 0.50
c l
Keepout area
e ia
0.50 4.80
0.50
t
15.60
u n
4.80
3.40
f
1.90 2.50
1.00
n
1.30 0.80
32.0
NOTES
t el
e c ia l
t
Figure 43: Top View of the Module
u
Q ide n
n f
Co Figure 44: Bottom View of the Module
NOTE
These are design effect drawings of EC21 module. For more accurate pictures, please refer to the
module that you get from Quectel.
l
8.1. Storage
t e
EC21 is stored in a vacuum-sealed bag. The storage restrictions are shown as below.
c a l
1. Shelf life in the vacuum-sealed bag: 12 months at <40ºC/90%RH.
u e t i
2. After the vacuum-sealed bag is opened, devices that will be subjected to reflow soldering or other
n
high temperature processes must be:
Q ide
Mounted within 72 hours at the factory environment of ≤30ºC/60%RH
Stored at <10%RH
f
3. Devices require baking before mounting, if any circumstances below occurs:
n
When the ambient temperature is 23ºC±5ºC and the humidity indicator card shows the humidity
is >10% before opening the vacuum-sealed bag.
o
Device mounting cannot be finished within 72 hours at factory conditions of ≤30ºC/60%RH.
C
4. If baking is required, devices may be baked for 48 hours at 125ºC±5ºC.
NOTE
As the plastic package cannot be subjected to high temperature, it should be removed from devices
before high temperature (125ºC) baking. If shorter baking time is desired, please refer to
IPC/JEDECJ-STD-033 for baking procedure.
Push the squeegee to apply the solder paste on the surface of stencil, thus making the paste fill the
stencil openings and then penetrate to the PCB. The force on the squeegee should be adjusted properly
so as to produce a clean stencil surface on a single pass. To ensure the module soldering quality, the
thickness of stencil for the module is recommended to be 0.18mm. For more details, please refer to
document [4].
It is suggested that the peak reflow temperature is from 235 to 245ºC (for SnAg3.0Cu0.5 alloy). The
absolute maximum reflow temperature is 260ºC. To avoid damage to the module caused by repeated
l
heating, it is suggested that the module should be mounted after reflow soldering for the other side of
PCB has been completed. Recommended reflow soldering thermal profile is shown below:
t e l
ºC
c
Preheat Heating Cooling
a
250
e i
Liquids Temperature
t
217
u
200ºC
n
200
40s~60s
Q ide
160ºC
Temperature
150
70s~120s
n f
100
o
Between 1~3ºC/s
50
Time
250
NOTE
During manufacturing and soldering, or any other processes that may contact the module directly, NEVER
wipe the module label with organic solvents, such as acetone, ethyl alcohol, isopropyl alcohol,
trichloroethylene, etc.
8.3. Packaging
EC21 is packaged in tape and reel carriers. One reel is 11.53m long and contains 250pcs modules. The
figure below shows the packaging details, measured in mm.
1.75±0.1
44.00±0.1 .1
±0 0.35±0.05
2.00±0.1 4.00±0.1 50
1.
20.20±0.15
l
29.3±0.15
30.3±0.15
30.3±0.15
44.00±0.3
c t e l
e ia
32.5±0.15 4.2±0.15
t
33.5±0.15 3.1±0.15
u
Q ide n
32.5±0.15
33.5±0.15
f
48.5
Cover tape
o n
13
Direction of feed
C
100
44.5+0.20
-0.00
9 Appendix A References
l
EC21 Power Management Application
[1] Quectel_EC21_Power_Management_Application_Note
e
Note
t
[2] Quectel_EC25&EC21_AT_Commands_Manual EC25 and EC21 AT Commands Manual
c l
EC25 and EC21 GNSS AT Commands
a
[3] Quectel_EC25&EC21_GNSS_AT_Commands_Manual
e
Manual
t i
[4] Quectel_Module_Secondary_SMT_User_Guide Module Secondary SMT User Guide
u n
[5] Quectel_EC21_Reference_Design EC21 Reference Design
Q ide
[6] Quectel_RF_Layout_Application_Note RF Layout Application Note
n f
Table 52: Terms and Abbreviations
o
Abbreviation Description
C
AMR Adaptive Multi-rate
CS Coding Scheme
DL Downlink
l
FR Full Rate
e
GLONASS
t
Navigation Satellite System
c l
GMSK Gaussian Minimum Shift Keying
e a
GNSS Global Navigation Satellite System
u t i
GPS Global Positioning System
n
GSM Global System for Mobile Communications
Q ide
HR Half Rate
f
HSDPA High Speed Downlink Packet Access
n
HSUPA High Speed Uplink Packet Access
o
I/O Input/Output
C
Inorm Normal Current
MO Mobile Originated
MT Mobile Terminated
l
RF Radio Frequency
e
RHCP Right Hand Circularly Polarized
t l
Rx Receive
c a
SGMII Serial Gigabit Media Independent Interface
e t i
SIM Subscriber Identification Module
u n
SIMO Single Input Multiple Output
Q ide
SMS Short Message Service
f
TDMA Time Division Multiple Access
n
TD-SCDMA Time Division-Synchronous Code Division Multiple Access
o
TX Transmitting Direction
C
UL Uplink
l
VOHmin Minimum Output High Level Voltage Value
e
VOLmax Maximum Output Low Level Voltage Value
t l
VOLmin Minimum Output Low Level Voltage Value
c a
VSWR Voltage Standing Wave Ratio
e t i
WCDMA Wideband Code Division Multiple Access
u n
WLAN Wireless Local Area Network
Q ide
n f
Co
l
Code Rate 1/2 2/3 3/4 1
t e
USF 3 3 3 3
c l
Pre-coded USF 3 6 6 12
e t ia
Radio Block excl. USF and BCS 181 268 312 428
u n
BCS 40 16 16 16
Q ide
Tail 4 4 4 -
f
Punctured Bits 0 132 220 -
n
Data Rate Kb/s 9.05 13.4 15.6 21.4
Co
l
number of slots the GPRS device can use simultaneously for both uplink and downlink communications.
t e
The description of different multi-slot classes is shown in the following table.
e c a l
Table 54: GPRS Multi-slot Classes
u t i
Multislot Class Downlink Slots Uplink Slots Active Slots
n
1 1 1 2
Q ide
2 2 1 3
3 2 2 3
f
4 3 1 4
o n
5 2 2 4
6 3 2 4
C
7 3 3 4
8 4 1 5
9 3 2 5
10 4 2 5
11 4 3 5
12 4 4 5
l
Table 55: EDGE Modulation and Coding Schemes
e
Coding Scheme Modulation Coding Family 1 Timeslot 2 Timeslot 4 Timeslot
t l
CS-1: GMSK / 9.05kbps 18.1kbps 36.2kbps
c a
CS-2: GMSK / 13.4kbps 26.8kbps 53.6kbps
u e t i
CS-3: GMSK / 15.6kbps 31.2kbps 62.4kbps
n
CS-4: GMSK / 21.4kbps 42.8kbps 85.6kbps
Q ide
MCS-1 GMSK C 8.80kbps 17.60kbps 35.20kbps
f
MCS-3 GMSK A 14.8kbps 29.6kbps 59.2kbps
n
MCS-4 GMSK C 17.6kbps 35.2kbps 70.4kbps
o
MCS-5 8-PSK B 22.4kbps 44.8kbps 89.6kbps
C
MCS-6 8-PSK A 29.6kbps 59.2kbps 118.4kbps