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DESCRIPTION FEATURES
The MP1474 is a high-frequency, synchronous, Wide 4.5V-to-16V Operating Input Range
rectified, step-down, switch-mode converter 100mΩ/40mΩ Low RDS(ON) Internal Power
with built-in power MOSFETs. It offers a very MOSFETs
compact solution to achieve a 2A continuous High-Efficiency Synchronous Mode
output current with excellent load and line Operation
regulation over a wide input supply range. The Fixed 500kHz Switching Frequency
MP1474 has synchronous mode operation for Synchronizes from a 200kHz-to-2MHz
higher efficiency over the output current load External Clock
range. Power-Save Mode at Light Load
Current-mode operation provides fast transient Internal Soft-Start
response and eases loop stabilization. Power Good Indicator
Full protection features include over-current OCP Protection and Hiccup
protection and thermal shut down. Thermal Shutdown
Output Adjustable from 0.8V
The MP1474 requires a minimal number of Available in an 8-pin TSOT-23 Package
readily-available standard external components,
and is available in a space-saving 8-pin APPLICATIONS
TSOT23 package. Notebook Systems and I/O Power
Digital Set-Top Boxes
Flat-Panel Television and Monitors
Distributed Power Systems
All MPS parts are lead-free and adhere to the RoHS directive. For MPS green
status, please visit MPS website under Quality Assurance. “MPS” and “The
Future of Analog IC Technology” are Registered Trademarks of Monolithic
Power Systems, Inc.
TYPICAL APPLICATION
Efficiency vs.
4.5V-16V 5
R3
20
Output Current
2
VIN IN BST VOUT=3.3V, IOUT=0.01A-2A
100
C1 C4
95
22 MP1474
3 3.3V/2A 90 VIN=5V
6 SW
EN/SYNC L1 85 VIN=12V
EN/ C2 80
SYNC 47 R1
7 R6 75 VIN=16V
VCC 40.2k
8 16k 70
C5 R5 FB
65
0.1 100k
1 R2 60
PG
GND 13k
55
4
50
0.0 0.4 0.8 1.2 1.6 2.0
OUTPUT CURRENT (A)
ORDERING INFORMATION
Part Number* Package Top Marking
MP1474DJ TSOT-23-8 ADK
PACKAGE REFERENCE
TOP VIEW
PG 1 8 FB
IN 2 7 VCC
SW 3 6 EN/SYNC
GND 4 5 BST
TYPICAL CHARACTERISTICS
VIN = 12V, VOUT = 3.3V, L=5.5μH, TA = 25°C, unless otherwise noted.
Load Regulation Line Regulation Peak Current
VIN=5-16V, IOUT=0-2A VIN=5V-16V vs. Duty Cycle
0.3 0.5 4.3
IOUT=0A
0.2 VIN=12V 0.3 4
VOUT/AC
VOUT 20mV/div.
2V/div.
VPG VIN/AC VOUT/AC
5V/div. 50mV/div.
200mV/div.
VIN
5V/div.
VSW
VSW 10V/div.
5V/div.
IOUT
IL 1A/div.
IINDUCTOR
2A/div.
2A/div.
PIN FUNCTIONS
Package
Name Description
Pin #
Power Good Output. The output of this pin is an open drain that goes high if the output
1 PGvoltage exceeds 90% of the normal voltage. There is a 0.4ms delay between when
FB≥90% to when the PG pin goes high.
Supply Voltage. The IN pin supplies power for internal MOSFET and regulator. The
MP1474 operates from a +4.5V to +16V input rail. Requires a low-ESR, and low-
2 IN
inductance capacitor (C1) to decouple the input rail. Place the input capacitor very close to
this pin and connect it with wide PCB traces and multiple vias.
Switch Output. Connect to the inductor and bootstrap capacitor. This pin is driven up to VIN
by the high-side switch during the PWM duty cycle ON time. The inductor current drives
3 SW the SW pin negative during the OFF time. The ON resistance of the low-side switch and
the internal body diode fixes the negative voltage. Connect using wide PCB traces and
multiple vias.
System Ground. Reference ground of the regulated output voltage. PCB layout Requires
4 GND
extra care. For best results, connect to GND with copper and vias.
Bootstrap. Requires a capacitor connected between SW and BST pins to form a floating
5 BST
supply across the high-side switch driver.
Enable. EN=high to enable the MP1474. Apply an external clock change the switching
6 EN/SYNC
frequency. For automatic start-up, connect EN pin to VIN with a 100kΩ resistor.
Internal 5V LDO output. Powers the driver and control circuits. Decouple with 0.1μF-to-
7 VCC
0.22μF capacitor. Do not use a capacitor ≥0.22μF.
Feedback. Connect to the tap of an external resistor divider from the output to GND to set
the output voltage. The frequency fold-back comparator lowers the oscillator frequency
8 FB when the FB voltage is below 400mV to prevent current limit runaway during a short circuit
fault. Place the resistor divider as close to the FB pin as possible. Avoid placing vias on
the FB traces.
Bootstrap
Regulator BST
Oscillator HS
Driver
+
SW
- Comparator
1pF On Time Control VCC
Current Limit Logic Control
50pF
Comparator
EN/SYNC Reference 400k
LS
6.5V 1MEG
Driver
+
+
FB -
OPERATION
The MP1474 is a high-frequency, synchronous, The EN pin is clamped internally using a 6.5V
rectified, step-down, switch-mode converter series-Zener-diode as shown in Figure 2.
with built-in power MOSFETs. It offers a very Connecting the EN input pin through a pullup
compact solution that achieves a 2A continuous resistor to the voltage on the IN pin limits the
output current with excellent load and line EN input current to less than 100µA.
regulation over a wide input supply range. For example, with 12V connected to IN, RPULLUP
The MP1474 operates in a fixed-frequency, ≥ (12V – 6.5V) ÷ 100µA = 55kΩ.
peak-current–control mode to regulate the Connecting the EN pin is directly to a voltage
output voltage. An internal clock initiates a source without any pullup resistor requires
PWM cycle. The integrated high-side power limiting the amplitude of the voltage source to
MOSFET turns on and remains on until the ≤6V to prevent damage to the Zener diode.
current reaches the value set by the COMP
voltage. When the power switch is off, it
remains off until the next clock cycle starts. If,
within 95% of one PWM period, the current in
the power MOSFET does not reach the value
set by the COMP value, the power MOSFET is
forced off. Figure 2: 6.5V Zener Diode Connection
Internal Regulator
A 5V internal regulator powers most of the For external clock synchronization, connect a
internal circuitries. This regulator takes VIN and clock with a frequency range between 200kHz
operates in the full VIN range. When VIN and 2MHz 2ms after the output voltage is set:
exceeds 5.0V, the output of the regulator is in The internal clock rising edge will synchronize
full regulation. When VIN is less than 5.0V, the with the external clock rising edge. Select an
output decreases, and the part requires a 0.1µF external clock signal with a pulse width less
ceramic decoupling capacitor. than 1.7μs.
Thermal Shutdown
Thermal shutdown prevents the chip from
operating at exceedingly high temperatures.
When the silicon die reaches temperatures that
exceed 150°C, it shuts down the whole chip.
When the temperature drops below its lower
threshold, typically 130°C, the chip is enabled
again.
Floating Driver and Bootstrap Charging
Figure 3: Adjustable UVLO An external bootstrap capacitor powers the
Internal Soft-Start floating power MOSFET driver. This floating
The soft-start prevents the converter output driver has its own UVLO protection. This
voltage from overshooting during startup. When UVLO’s rising threshold is 2.2V with a
the chip starts, the internal circuitry generates a hysteresis of 150mV. The bootstrap capacitor
soft-start voltage (VSS) that ramps up from 0V to voltage is regulated internally by VIN through
1.2V. When VSS is less than VREF, the error D1, M1, R3, C4, L1 and C2 (Figure 4). If (VIN-
amplifier uses VSS as the reference. When VSS VSW) exceeds 5V, U1 will regulate M1 to
exceeds VREF, the error amplifier uses VREF as maintain a 5V BST voltage across C4. A 20Ω
the reference. The SS time is internally set to resistor placed between SW and BST cap. is
1.2ms. strongly recommended to reduce SW spike
voltage.
Power Good Indicator
D1
MP1474 has an open drain pin as the power- VIN
good indicator (PG). Pull this up to VCC or
another external source through a 100kΩ M1
BST
resistor. When VFB exceeds 90% of VREF, PG
switches goes high with 0.4ms delay time. If VFB 5V U1 R3
goes below 85% of VREF, an internal MOSFET C4
pulls the PG pin down to ground. VOUT
SW L1
The internal circuit keeps the PG low once the C2
input supply exceeds 1.2V.
Over-Current-Protection and Hiccup Figure 4: Internal Bootstrap Charging Circuit
The MP1474 has a cycle-by-cycle over-current Startup and Shutdown
limit when the inductor current peak value If both VIN and VEN exceed their respective
exceeds the set current limit threshold. thresholds, the chip starts. The reference block
Meanwhile, the output voltage drops until VFB is starts first, generating stable reference voltage
below the Under-Voltage (UV) threshold— and currents, and then the internal regulator is
typically 50% below the reference. Once UV is enabled. The regulator provides a stable supply
triggered, the MP1474 enters hiccup mode to for the remaining circuitries.
periodically restart the part. This protection
mode is especially useful when the output is Three events can shut down the chip: VEN low,
dead-shorted to ground, and greatly reduces VIN low, and thermal shutdown. During the
the average short circuit current to alleviate shutdown procedure, the signaling path is first
thermal issues and protect the regulator. The blocked to avoid any fault triggering. The
MP1474 exits the hiccup mode once the over- COMP voltage and the internal supply rail are
current condition is removed. then pulled down. The floating driver is not
subject to this shutdown command.
APPLICATION INFORMATION
Setting the Output Voltage Where ΔIL is the inductor ripple current.
The external resistor divider sets the output
Choose the inductor ripple current to be
voltage (see Typical Application on page 1). The
approximately 30% of the maximum load current.
feedback resistor R1 also sets the feedback loop
The maximum inductor peak current is:
bandwidth with the internal compensation
capacitor (see Typical Application on page 1). IL
Choose R1 around 40kΩ. R2 is then given by: IL(MAX) ILOAD
2
R1 Use a larger inductor for improved efficiency
R2 under light-load conditions—below 100mA.
VOUT
1 Selecting the Input Capacitor
0.807V The input current to the step-down converter is
The T-type network—as shown in Figure 5—is discontinuous, therefore requires a capacitor is to
highly recommended when VOUT is low. supply the AC current to the step-down converter
while maintaining the DC input voltage. Use low
Cf
ESR capacitors for the best performance. Use
Rt R1 ceramic capacitors with X5R or X7R dielectrics
8
FB VOUT for best results because of their low ESR and
small temperature coefficients. For most
R2 applications, use a 22µF capacitor.
Since C1 absorbs the input switching current, it
Figure 5: T-Type Network requires an adequate ripple current rating. The
Table 1 lists the recommended T-type resistors RMS current in the input capacitor can be
value for common output voltages. estimated by:
Table 1: Resistor Selection for Common Output VOUT VOUT
I C1 ILOAD 1
Voltages VIN VIN
VOUT
R1 (kΩ) R2 (kΩ) Rt (kΩ) Cf(pF) L(μH) The worse case condition occurs at VIN = 2VOUT,
(V)
1.0 20.5 84.5 82 15 2.2 where:
1.2 30.1 61.9 82 15 2.2 ILOAD
IC1
1.8 40.2 32.4 33 15 4.7 2
2.5 40.2 19.1 33 15 4.7 For simplification, choose an input capacitor with
3.3 40.2 13 16 15 5.5 an RMS current rating greater than half of the
5 40.2 7.68 16 15 5.5 maximum load current.
Selecting the Inductor The input capacitor can be electrolytic, tantalum
or ceramic. When using electrolytic or tantalum
Use a1µH-to-10µH inductor with a DC current capacitors, add a small, high quality ceramic
rating of at least 25% percent higher than the capacitor (e.g. 0.1μF) placed as close to the IC
maximum load current for most applications. For as possible. When using ceramic capacitors,
highest efficiency, use an inductor with a DC make sure that they have enough capacitance to
resistance less than 15mΩ. For most designs, provide sufficient charge to prevent excessive
the inductance value can be derived from the voltage ripple at input. The input voltage ripple
following equation. caused by capacitance can be estimated as:
VOUT (VIN VOUT ) ILOAD V V
L1 VIN OUT 1 OUT
VIN IL fOSC fS C1 VIN VIN
4
7.68k
GND
GND
13k
GND
GND
19.1k
GND
GND
R3
20
VIN 2 5
IN BST
C1A C1
0.1uF C4
22uF
25V 25V MP1474 0.1uF
L1
GND GND 4.7uH VOUT
7 3
1.8V/2A
VCC VCC SW
C5 C2 C2A
0.1uF 22uF 22uF
R5
100k
GND
GND GND
1
PG PG C3
15pF
R4
100k
R6
33k
6 8
EN/SYNC EN/SYNC FB
R1
GND
40.2k
R2
4
32.4k
GND
GND
61.9k
GND
GND
84.5k
GND
GND
PACKAGE INFORMATION
TSOT23-8
NOTICE: The information in this document is subject to change without notice. Users should warrant and guarantee that third
party Intellectual Property rights are not infringed upon when integrating MPS products into any application. MPS will not
assume any legal responsibility for any said applications.