A Complete Model for Glitch Analysis in Logic Circuits

Ki-Seok Chung Synopsys Inc. 700 E. Middlefield Rd. Mountain View, CA, USA Taewhan Kim
Dept. of EECS and

C. L. Liu
Dept. of Computer Science

Adv. Information Tech. Research Center National Tsing Hua Univ. Korea Adv. Institute of Sci. & Tech. Hsinchu, Taiwan R.O.C. Taejon, Korea

Abstract: One of the major factors which contribute to the power consumption in CMOS combinational logic circuits is the switching activities in the circuits. Many of such switching activities are due to spurious pulses, called glitches. Recently, a new model of glitch analysis, called G-vector[7]has been proposed. The power of the model is that, unlike the existing ones which model only the propagation of glitches to count the number of glitches in the circuits, it allows to model the generation, propagation and elimination of glitches to be able to not only count the number of glitches but also locate the glitches. In this paper, we complete the concept of G-vector by providing a set of efficient solutions to the two important practical issues: (1) extending to signals over multiple clock cycles, and (2) extending to a logic decomposition utilizing the model. Integrating the solutions all together enables G-vector to be practically very efficient. A set of experimental results is provided to show the effectiveness of the proposed solutions.
I. INTRODUCTION

Low power circuit design is one of the major topics of research in design automation. The power consumed in CMOS combinational logic circuits is heavily dependent on the switching activities in a circuit. Such switching activities are largely determined by the input switching pattems and the structure of the circuit. Many researches have studied how switching activities are to be modeled and the determination of optimal circuit structure for power reduction [ 1,2]. Signal switching in combinational circuits occurs for different reasons. Input signal transitions take place at different times in a clock cycle. Different logic gates are sensitive to different types of transitions in the inputs. Also propagation delays of the gates may differ. All of these mean that a signal might go through several state changes before it reaches its steady state within a clock cycle. These spurious transitions are often called glitches. For low power design, glitching should be minimized because it causes power dissipation. To estimate the power consumption of a circuit, we need to determine the number and locations of the glitches in order to minimize the power dissipathat in a combinational tion due to glitches. It was reported ( [ 3 ] ) circuit the power dissipation due to glitches could be as high as 20% of the total power consumption, and can be much more in some circuits such as combinational adders. Unfortunately, most of the approaches for reducing glitch power dissipation have not been successful. The lack of good synthesis systems for reducing

glitch power dissipation is due largely to the lack of a good model to describe signals that contain glitches. In [3], the exact power estimation of a given combinational logic circuits is carried out by a method called symbolic simulation. This method is accurate but the complexity of the method is a exponential. In [4], model which counts the number of glitches based on the assumption that every input makes a transition, and every transition at the input will cause a transition at the output of a gate was used. Clearly, this is a worst case scenario and might not be close to the average behavior of a circuit at all. In [5],the notion of transition dens@ was introduced. Transition density is the average number of transitions in a signal over a period of time. The concept of transition density is capable of modeling the propagation of input transitions to the output. However, it cannot model the generation of glitches. In [ 6 ] ,several techniques for power estimation using probabilistic methods were proposed. Their model for glitch activity was based on glitch sensitivity which is computed from the arrival sequence of input signals. Recently, in [7] a new analytic glitch analysis model at the gate level, called G-vector, is proposed. The attraction of the model is that it is able to represent the glitches efficiently and accurately with the capability of modeling the generation, propagation, and elimination of glitches. In fact, in this paper we complete the concept of G-vector by providing a set of efficient solutions to the two important practical issues: (i) extending to signals over multiple clock cycles (Sec. ID), and (ii) extending to a logic decomposition utilizing the model (Sec. N ) . Combining the solutions all together enables G-vector to be very efficient and powerful in practice.
11. REVIEW: GLITCHES AND G-VECTOR

An electrical signal which appears in an input line will be referred to as a physical signal. The value of a physical signal is sampled N times in a clock cycle through 0/1 signal sampling. By 0/1 signal sampling, we mean that we probe a signal line and determine the state of the line as either 0 or 1. By probing a signal line N times in a clock cycle, we obtain a sequence of 0s and 1s of length N which is a representation of the waveform of the phys1 ical signal. The 0 1 sequence representation of a physical signal is called a 0/1 sampled signal, and each interval for one probing is called a frame. Clearly,. a 0/1 sampled signal may not capture every transition in a physical signal. However, our assumption is that the sampling rate is fast enough so that there is at most one transition or one glitch in a frame. It is clear that many different

0-7803-6598-4/00/$10.00 0 2000 IEEE

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physical signals will yield the same 0/1 sampled signal. Such a many-to-one relationship between physical signals and 011 sampled signals means that, in general, we cannot identify uniquely a physical signal from its corresponding 0/1 sampled signal. Consequently, for a given 0/1sampled signal, we assume that each of its corresponding physical signals has equal probability of occurrence. In a clock-cycle, a physical signal may assume one of the following different states: (i) 0(1) at the start, and 0(1) at the end of the clock cycle, and (ii) 0(1) at the start, and l(0) at the end of the clock cycle. If there is no spurious transition in a clock cycle, the first two cases should not contain any transition in the clock cycle(referred to as stable 0, and stable 1, respectively), and the last two cases should contain exactly one transition. Since glitches do not exist in the steady state behavior, we assume that in our multi-frame representation, the states of the first and the last frames cannot contain any glitch. In a 0/1 sampled signal, a transition is detected by any subsequence of Ol(0+ 1 transition) or 10 (1 + 0). Since a glitch-free signal can have at most one transition in a clock cycle, any additional transition implies the existence of a glitch. In the previous section, we discussed how we can detect the existence of glitches from a 0/1 sampled signal. However; 0/1 sampled signals are not sufJicient to handle logic composition of signals because a O/I sampled signal does not provide explicit information on the dependency among the sampled states of successive frames. Figure 1 shows an example. Suppose two 0/1 sampled signals are combined by an A N D gate. The first input 0/1 sampled signal corresponds to a unique physical signal, and the second input 0/1 sampled signal corresponds to two possible physical signals, say, B 1 and B2. Consequently, there are two possible output signals in the output, A*B1 and A*B2. Both of them are signals with glitches. However, because the 0/1 sampled signal representation does not differentiate a clean state from a glitch state, the output 0/1 sampled signal will be [ l,O,O,O,O]which is a glitch-free signal. This example illustrates that 011 sampled signals cannot handle logic compositions properly.

U1, or G where

The rule for obtaining a G-vector V from a 0/1 sampled signal S can be found in [7]. Definition (Valid G-Vector)[7]: A G-vector is valid i and only f if it does not have any of the following subsequences: OIO, IOl, l U ~ l , OUIO. or
Note that a G-vector is an encoded representation of a set of physical signals. We perform logic compositions of G-vectors instead of performing the compositions on the corresponding sets of physical signals. Thus, we need to verify that the output Gvector is equivalent to the set of physical signals which can appear in the output of a gate. By equivalence, we mean that the output G-vector is the correct encoded representation of all possible physical signals that may appear in the output, and nothing else. [7]derived the following important results which verify the correctness of G-vector compositions. Theorem 1The valid output G-vector in a logic compositionfrom two valid input G-vectors is equivalent to the set ofphysical signals which can be obtained in the logic compositions of every pair of physical signals in the expansions of the two input G-vectors. In other words, the expansion of the output G-vector will generate the same set of physical signals that are obtained from the pairwise logic composition in the two input expansions. This is true for AND,OR,NAND,NOR,and NOT gates, and any network which is composed of these logic gates. From Theorem 1 , we can conclude that G-vector compositions generate the correct output G-vector in the logic gates. Thus, we can-count the number of glitches in a logic network using the Gvectors which represent the signals in the network. Here is an example illustrating how G-vectors can be utilized in analyzing the behavior of logic networks. Example 1: Lets go back to Figure 1 which shows that 0/1 sampled signals are inadequate representations for logic composition. Now we want to show how G-vectors work. Figure 2 shows how G-vectors are composed for the same set of physical signals at the input as in Figure 1. The G-vector for the first input vector [1,0,1,0,1] is [l,G,l,G,l], and the G-vector for the second input vector [1,1,0,1,0]is [l,l,Uo,U1,0]. The corresponding outwhich exput G-vector from the A N D operation is [l,G,Uo,G,O] actly implies two output physical signals [ l,G,G,G,O] (A * B l ) and [ l,G,O,G,O](A * B2). This example illustrates that G-vectors can handle logic compositions efficiently.

0 1 G
U 0

: Non-glitch 0 state

U 1

: Non-glitch 1 state : Glitch state : Either non-glitch 0 state or glitch state : Either non-glitch 1 state or glitch state

.
1

.
1 ; o

.
, l

,:

0;

HI. G-MATRIX: PROBABILISTIC G-VECTOR

Figure 1: Limitation of 0/1 sampled signals.

Definition (G-Vector): A G-Vector is a sequence of length N where N is the number of sampling frames. The components of a G-Vector are defined as follows:
0

II1.A Motivation

The first and last frames can only be either 0 or 1. The rest of the frames in the middle can be either 0, 1, UO,

In Sec. II, we have discussed how to model a set of signals containing glitches using a G-vector. It was shown that G-vectors can be used for counting the number of glitches and for logic composition in many standard logic gates. Thus, using G-vectors, we will be able to find a good circuit structure with a minimum number of glitches assuming that each input line contains the set of

272

G-vector

Frame 2 3

# of

Instances

1 U0

U1 0 , .
1 0

1 1 0

Figure 2: Example of logic composition using G-vectors.

signals represented by a single G-vector over multiple clock cycles. Unfortunately, this is not the case in general. The inputs of a circuit usually carry many different signals over multiple clock cycles. Hence, the glitch analysis based on a single G-vector per input may not be accurate in practice. Thus, we extend the Gvector model to a statistical model of glitches, called G-matrix.

lII.B G-Matrix and Compressed G-Matrix Definition (G-Matrix): A G-matrix is a 5 X N matrix. Each column in the matrix represents a frame, and the entries in the 5 rows will be used to represent the occurrence probability of 0, 1, G, UQ, U1 in that frame, respectively. and Suppose we sample each input signal line over multiple clock cycles and obtain a G-vector for each clock cycle. We can count the number of instances of each distinct G-vector in the input line. Then for each frame, we can compute the occurrence probability of each component. The following shows an example of how we obtain a G-Matrix from input sampling. Example2: Suppose we sample the signal which appear in an input line over 100cycles, and obtain 100 corresponding G-vectors. Suppose there are 6 distinct G-vectors with the number of instances of each given as in Table 1-(a). From this table, we can determine the corresponding G-matrix by computing the probability of the state in each frame. For example, in 80 out of the 100G-vectors, the first frame is in 0 state (30 in G-vector 1,20 in G-vector 2, and so on.). So the occurrence probability of 0 in the first frame is 0.8. Table 1-(b) shows the corresponding G-matrix. Note that U0 represents either 0 or G, and U1 represents 1 or G. We assume that they are equally probable. To simplify the evaluation procedure, we compress the G-matrices by eliminating the rows for U0 and U l , and splitting the probabilities equally, and adding them to the corresponding rows. The new G-matrix so obtained is called a Compressed G-matrix.Table l(c) shows the CGM for the G-matrix in Table 1-(b). Then, we have the following theorem. Theorem 2 The expected number of glitches in a CGM for a signal line is simply the sum of the values in the row for G. Let us call this number the weight of a CGM. When a CGM is obtained from the set o G-vectors which appeared in a signal line, f f the weight o the CGM is exactly the average weight of each Gvector in the signal line. Therorm 2 tells us that the expected number of glitches from a CGM is exactly the same as the average by dividing the total number of glitches by the total number of G-vectors. For exam-

State 0

1
I

0 0.8 0.2 0

1 0.35 0.25 0.4

Frame 2 3 0.2 0.575 0.175 0.15 0.625 0.275

4 0.3 0.7 0

Table 1: (a) Signal sampling. (b) Its G-matrix. (c) Its compressed G-Matrix.
ple, from Table 1-(a), the average estimated number of glitches from G-vectors is 1.5.0.3+ 2.0.2 + 1.0.25+ 1.0.1+ 1.0.1 + 0.0.05 = 1.3, and the weight of the corresponding CGM (Table l(c)) is 0.4 + 0.625 + 0.275 = 1.3. IILC Logic Composition Using Compressed G-Matrix We have seen that a G-matrix for a signal line is an accurate summary of the set of G-vectors that appear in the signal line. Now we have to look at the logic composition using CGM's. Obtaining the output CGM in a logic operation between two input CGM's is a two step procedure:

Step 1: Compute the probability of each state in the output CGM using the corresponding G-vector composition table'. Let T[p][q] the composition table entry (output state) when input be states are p and q. Let I j ( k ) be the probability of being state k (k E {0,1, G}) in frame j in input CGM i. Let Oj"l"'(k)be the probability of being state k (k E {0,1, G } )of frame j in the output CGM from two input CGMs, Imand I". Then,

Step 2: Since the result obtained from Step 1 contains only the probabilities for glitch propagation and elimination, we need to
'For CGM, we use only the portion of the table which is related to 0,1, and G only.

273

compute the probabilities of generation of new glitches, and adjust the output CGM accordingly. The adjustment is done as follows: Let O j ( k ) be the probability of being state IC (IC E { 0 , 1 , G}) in frame j (0 5 j 5 N - 1) in the original output CGM. Let 0; (IC) be the probability of being state k (IC E ( 0 , 1, G}) at frame j (0 5 j 1 N - 1) in the new CGM. Let Aj(k) be the adjustment . (1 for Oj(k) 5 j 5 N - 2). Then, b'j (1 5 j 5 N - 2), Aj(1) = Oo(0) O j ( 1 ) . 0 ~ - 1 ( 0 ) Then, Aj(0) = Oo(1) . Oj(0) . O ~ - l ( l ) Aj(G) = - (Aj(1) Aj(0)) V j , k, O;(k) Oj(lc) - Aj(k). = Aj(1) and Aj(0) are the portions of probabilities that are to be glitch in frame j rather than values 1 and 0, respectively. The following example shows an example of a CGM composition.

0 1 G

0.3 0.7 0

0.3 0.2 0.5

0.4 0.3 0.3

0.4 0.05 0.55

0.45 0.15 0.4

0.3 0.7 0

I
State 0 1 G

II
0 0.4 0.6 0
1 0.1 0.45 0.45

Frame 3 2 0.3 0 0.45 0.1 0.25 0.9

I
4 0.25 0.25 0.5
5

0.6 0.4 0

Frame State 0 1 G 0 0.12

0.88

Example 3: Let's consider the computation of the output CGM from an OR operation between two input CGM's shown in Table 2-(a) and (b). Let I j ( k ) be the probability of being state k in frame j in the input CGM i. Let Oj(lc) be the probability of being state k in frame j . Let us show some partial computations for Step 1. Oo(0) = I l ( 0 ) P ( 0 ) = 0.12
@(O) Ol(1)
0 (C) 1

1 0.03 0.56 0.41

0.12 0.62 0.27

0 0.15 0.86

4 0.11 0.36 0.53

0.42
0.58

= =

8 ( 0 ) .19(0) = 0.03 I I ( 1 ) . I h (0) I i ( 0 ) .I?(1) + I ? ( l ) . I,2(1)+ Ii(l). $(C) I i ( G ) . 12(1) = 0.56 0.41

= -

I (G) .I;(O) i ,

+ +

+ I, . I t ( G ) + Zi ( G ) . If(") (0)

State 0 1 G

0 0.12 0.88 0

1 0.01 0.53 0.45

Frame 3 2 0 0.06 0.58 0.14 0.36 0.86 (4

...
From Step 1, we obtain Table 2-(c). And here are partial computations for A j ( k ) in Step 2.
Al(0) Al(1) Al(G)

= =
=

A2(0)
A2(l) Az(G)

=
= =

0.88 x 0.58 x 0.03 0.12 x 0.42 x 0.56 -(Al(O)+Al(l)) 0.69 x 0.73 x 0.02 0.24 x 0.27 x 0.631 -(A2(0) Az(1))

...

The final output CGM is shown in Table 2-(d).

w. TECHNOLOGY DECOMPOSITION MINIMIZING FOR

GLITCHES The existence of glitches in a circuit may do much harm to both the correct operation and power consumption of the circuit. Thus, we always try to minimize the occurrence of glitches. As an application of the concept of G-vectors, we present a heuristic algorithm for decomposing an n input logic gate into a network of 2 input gates of the same type. The goodness of a decomposition is measured by the total number of glitches in the outputs of all the 2 input gates in the decomposition. It is well-known that an exhaustive algorithm for technology decomposition has complexity of O(n!. nn). O(n!

[ : Thus, we suggest a heuristic )).

\ /

algorithm for minimizing the total number of glitches. Suppose we are given the n G-vectors corresponding to the n input signals of the gate. The heuristic is a similar procedure of constructing a Huffman tree[8]. The procedure BUILD-UP finds the best input pair which generates an output signal with the minimum number of glitches and replace the two inputs with

274

4 0.06 0.34 0.60

5 0.42 0.58 0

=
=

=
= = =

0.0153 0.0282 -0.0435 0.01007 0.04889 -0.058954

Table 2: An example of CGM composition: (a) Input CGM 1,

(c) Input CGM 2, (c) Output CGM from Step 1 for OR, and (d) The final output CGM.

the output, and then repeat this procedure until a single output is is generated. The complexity of procedure BUILD-UP O ( n 3 ) .
I

'
I

I* F:Boolean Function */ /* S: CGMs of input G-vectors on multiple cycles *I

Procedure BuILD-UP(F,S) if ISI = 1, return; else { 0 Obtain the output CGM for every pair of CGMs in S according to F ; 0 Find the pair whose output CGM has the minimum number of glitches; 0 Create a gate of type 7 and connect the two input signals; 0 Delete the corresponding two CGMs from S ; 0 Add the new output CGM to S ; 0 return BUILD-UP(^, S); endProcedure

F represents the type of gate used in technology decomposition,

and S is the set of compressed G-matrixes that are initially derived from the input G-vectors on the multiple clock cycles.

V. EXPERIMENTAL RESULTS

A variety of experiments was carried out to verify the accuracy and effectiveness of our proposed solutions. Our program was written in C++ and executed on a Sun Sparc20 workstation. Our experiments were performed in two folds to show (1) the accuracy of the compressed G-matrix (CGM) in estimating the number of glitches and (2) the effectiveness of CGM in technology decomposition.

circuit

logic sim. #glitch I run

11

11

#glitch

CGM run time

error

Accuracy of CGM in estimating the number of glitches: To test the accuracy of the CGM composition, we implemented a simulation program and tested on MCNC benchmark circuits shown in the first colum of Table 3. We generate 1000 random input vectors and propagate each of them from circuit inputs to circuit outputs, from which the exact number of glitches is computed. The second and third columns of Table 3 show the aveage number of glitches so obtained by simulating each of the circuits 1000 times, one for each input vector, and the total simulation time, respectively. On the other hand, the fourth and fifth columns of Table 3 show the estimated number of glitches produced by compressing the 1000 random input vectors into one CGM and propagating it from the circuit inputs to circuit outputs according to the 2-step logic composition in Sec. IILC, and the simulation time, respectively. The comparison of the simulation results indicates that by using CGM we obtain significant speed up over the explicit simulation method with an average error of only 4.2%. Effectiveness of CGM in technology decomposition: To show the effectiveness of the heuristic, we compare the results from the heuristic with the optimal results from the exhaustive search. Table 4 shows the results from a variety of experiments. The comparison shows that our proposed heuristic based on the CGM produces near-optimal results while reducing the run time significantly.
VI. CONCLUSIONS In this paper, we studied a new model for glitch analysis, called G-Vector. Unlike models studied in the past, the model was capable of modeling the generation, propagation, and elimination of glitches in logic networks with many standard logic gates. To complete the model to be practically effective, we proposed a set of solutions to two important problems, namely, (1) supporting signals over multiple clock cycles, and (2) supporting a logic decomposition utilizing the model. From the experiments, we confirmed that using the proposed solutions were able to estimate the number of glitches efficiently and accurately, and more importantly to generate logic circuits with significantly less number of glitches.

cm163a cm42a cm82a cm85a

732 356 472 1050

320 291 298 311

760 370 481 1102

lO(32) 9 (32) 8(37) 1 1 (28)

3.8 3.9 1.9 4.5

Table 3: Results of glitch estimation using CGM for MCNC benchmark circuits.

I #inout/ II
#Tkst 6/100 71100 8/20

Outimal Glitch (time) 3.69 (3.5 min) 4.37 (1.5 hr) 3.70 (8.0 hr)

BUILD-UP Glitch (time) 3.71 (< 1 sec) 4.41 (< 1 sec) 3.72 (< 1 sec)

Worst Glitch 10.4 13.1 14.2

Table 4: Comparison of BUILD-UPagainst the optimaVworst

results.

Acknowledgments: This work was partially supported by the Korea Science and Engineering Foundation (KOSEF) through the Advanced Information Technology Research Center (AITrc).

References
[l] A. P. Chandrakasan and R. W. Broderson, Low Power Digizul CMOS Design, Kluwer Academic Publishers, pp. 473-484, 1995. We first convert the initial benchmark circuits into ones with 2-input AND/OR gates by using tech-decomp -a 2 -0 2 command in SIS package.

M. Pedram, Power Minimization in IC Design: Principles and Apf plications, ACM Truns. on Design Automution o Electronic Systems, vol. 1, no. 1, pp. 3-56, 1996. A. Ghosh, S . Devadas, K. Keutzer, and J. White, Estimation of Average Switching Activity in Combinational and Sequential Circuits, Pmc. ofDesign Automution Con$, pp. 68-73, 1992. R. Murgai, R. K. Brayton, A. Sangiovanni-Vincentelli, Decomposition of Logic Functions for Minimum Transition Activity, Pmc. o Eumpeun Design urd Test C o f , pp. 404-410, 1995. f E Najm, Transition Density, a Stochastic Measure of Activity in f Digital Circuits, Pmc. o Internutiom1 Con$ on Computer-Aided Design, pp. 644-649, 1991. H. Mehta, M. Borah, R. M. Owens, and M. J. Irwin, Accurate Estimation of Combinational Circuit Activity, P m . o Design Auf tomution C o f , pp. 618-622, 1995. K. S. Chung, T. Kim, and C. L. Liu, G-Vector: A New Model for Glitch Analysis, Pmcc. o Internutionul ASIUSOC Cot$, 1999. f D. A. Huffman, A Method for the Construction of Minimum Ref dundancy Codes, Proceedings o the IRE, vol. 40, pp. 1098-1101, Sept. 1952.

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