Subject: Computer architecture

Code: 17834
Institution: Escuela Politécnica Superior
Degree: Computer Science Engineering
Level: Graduate
Type: Compulsory
ECTS: 6

COMPUTER ARCHITECTURE SYLLABUS

This document includes the set of rules that regulates the Computer Architecture
subject, which is part of the Degree in Computer Science Engineering. The academic
board of the Escuela Politecnica Superior has approved this set of rules. The
document is valid for the academic course 2014-2015 and is available to all students
in the web page of the Escuela Politecnica Superior. This document can be
considered as a contract for registered students.

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 Subject: Computer architecture
Code: 17834
Institution: Escuela Politécnica Superior
Degree: Computer Science Engineering
Level: Graduate
Type: Compulsory
ECTS: 6

1. COURSE TITLE
Computer Architecture
1.1. Course number
17834 Degree in Computer Science Engineering

1.2. Course area

Computer Engineering

1.3. Course type

Compulsory

1.4. Course level

Graduate

1.5. Year
3º

1.6. Semester
1º

1.7. Credit allotment

6

1.8. Prerequisites
It is highly recommended to have completed the courses Computer Fundamentals and
Computer Structure.

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 Subject: Computer architecture
Code: 17834
Institution: Escuela Politécnica Superior
Degree: Computer Science Engineering
Level: Graduate
Type: Compulsory
ECTS: 6

1.9. Minimum attendance requirement

In this subject students can choose between two different assessment methods (see
section 4). Based on the selected assessment method, the minimum required
attendance is:

CONTINUOUS ASSESSMENT
Attendance is highly advisable but not mandatory.

FINAL EXAM
Attendance is highly advisable but not mandatory.

1.10. Faculty data

Note: Add @uam.es to all emails.

Ivan Gonzalez Martínez (English Group)

Department of Electronic and Communications Technology
Faculty: Escuela Politecnica Superior
Office: Building C room C-223
Phone: +34 91 497 6212
Email: ivan.gonzalez
Office hours: Request an appointment by email.

Francisco Javier Gómez Arribas (Coordinator)

Department of Electronic and Communications Technology
Faculty: Escuela Politecnica Superior
Office: Building C room C-226
Phone: +34 91 497 2255
Email: francisco.gomez
Office hours: Request an appointment by email.

Sergio López Buedo

Department of Electronic and Communications Technology
Faculty: Escuela Politecnica Superior
Office: Building C room C-223
Phone: +34 91 497 2249
Email: sergio.lopez-buedo
Office hours: Request an appointment by email.

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 Subject: Computer architecture
Code: 17834
Institution: Escuela Politécnica Superior
Degree: Computer Science Engineering
Level: Graduate
Type: Compulsory
ECTS: 6

Laboratory:
Víctor Moreno Martínez (Laboratory Coordinator)
Departamento de Tecnología Electrónica y de las Comunicaciones
Faculty: Escuela Politecnica Superior
Office: Building C room C-118
Phone: +34 91 497 2268
Email: victor.moreno
Office hours: Request an appointment by email.

1.11. Course objectives

In this course you learn the architecture and design of some conventional and
advanced processors. Returning to the subject studied in the first year "The structure
of computers," it examines more advanced concepts in processor design. The content
of the course discusses the design techniques that improve the performance of
computer systems. Shows the evolution of the main innovations in architecture and
computer technology and explains the incorporation of these advances in current
processors, justifying its usefulness in terms of performance improvement.

The competencies to be acquired with this subject are:

Basic:
B5. Knowledge of the structure, organization, operation and interconnection of
Computer Systems, the fundamentals of their programming and the application of
this knowledge in solving engineering problems.

Common:
C9. Ability to understand and evaluate computer structures and architectures, as
well as the basic components that make them up.

Specifics:
IC1. Ability to design and construct digital systems, including computers,
microprocessor based systems and communications systems.
IC3. Ability to analyze and evaluate computer architecture, including parallel and
distributed platforms, as well as develop and optimize software for them.

At the end of each unit, the student should be capable of:

UNIT BY UNIT SPECIFIC OBJECTIVES

UNIT 1.- Abstractions, Technology and Performance of Computers.
Describe the main aspects that influence technological evolution in today’s computer
1.1. systems.
1.2. Recognize the basic vocabulary of computer architecture.

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 Subject: Computer architecture
Code: 17834
Institution: Escuela Politécnica Superior
Degree: Computer Science Engineering
Level: Graduate
Type: Compulsory
ECTS: 6

1.3. Identify the components of a computer system.

1.4. Understand the concept of runtime in a system.
1.5. Determine the causes and effects on the growth performance in part on the whole.
UNIT 2.- Pipelined Processors.
Understand the basic concepts of computer architecture. Arithmetic Logic Unit (ALU),
2.1. register banks, registers and flip-flop latch, clock period, and Harvard RISC
architecture.
Understand the concept of pipeline (segmentation) and the concepts associated
2.2. latency and throughput.
Indicate how the pipeline processor works based on the execution of overlapping
2.3. instructions.
2.4. Understanding the limitations of pipelining and causes of loss of productivity.
2.5. Understand how to eliminate or mitigate structural, control and data hazards.
Describe techniques to avoid halts. Internal forwarding and branch prediction using
2.6. static and dynamic BTB.

UNIT 3 .- Memory Organization and Structure: caches and virtual memory

Understand the concept of memory hierarchy. Reasons why the different storage
3.1. levels are organized into hierarchy.
Recognize the need and utility of cache memories and the organization in fully
3.2. associative, direct mapped and set associative.
Indicate operating schemes of caches. Write Through with assignment in writing and
3.3. without writing assignment. Post-write or writeback.
Understand replacement algorithms and cache coherence problems on multiprocessor
3.4.
systems.
Understand the operation of virtual memory: paging, segmentation and paged
3.5. segmentation.
3.6. Indicate steps in the translation of virtual addresses to physical or real addresses.
Understand the necessary hardware support in the memory management unit (MMU)
3.7. and translation look-aside buffer (TLB).
Understanding the integration of memory system between cache and TLB (cache
3.8.
system with virtual addresses cache or real addresses cache.)
UNIT 4 .- Storage and other aspects of the input / output (I / O).
4.1. Understand and differentiate the concepts of reliability and availability.
4.2. Recognize the key features of storage in disks and flash memory.
4.3. Indicate the main performance metrics in the input-output systems.
4.4. Identify the main possibilities that can be applied to parallelize the input / output.
UNIT 5.- Advanced Techniques of parallelism.
Understanding the instruction level parallelism (ILP) and the base of the superscalar
5.1. processors.
Knowing the basics of superscalar processors: policies of instructions issued, renaming
5.2. registers, reordering buffer, retirement unit.
5.3. Design a superscalar processor based on the previously studied under item 2.
Understanding processors where the parallelism is solved by the compiler instead of
5.4. hardware (VLIW processors).

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 Subject: Computer architecture
Code: 17834
Institution: Escuela Politécnica Superior
Degree: Computer Science Engineering
Level: Graduate
Type: Compulsory
ECTS: 6

Identify problems and understand parallel programming models of multicore

5.5. processors, multiprocessors.
5.6. Knowing the architecture of clusters and other message-passing multiprocessors.
5.7. Recognize the main characteristics of graphics processors.

1.12. Course contents

Synthetic program
UNIT 1. Abstractions, Technology and Performance Computers.
UNIT 2. Pipelined processor.
UNIT 3. Memory Organization and Structure: caches and virtual memory.
UNIT 4. Storage and other aspects of I / O
UNIT 5. Advanced techniques of parallelism.

Detailed Program
1. Abstractions, Technology and Performance Computer
1.1. introduction
1.2. Architecture of a computer system. Basics
1.3. Performance in a computer system
1.4. Perspective and evolution of technology
2. segmented processors
2.1. fundamentals of designing a processor
2.1.1. The instruction set
2.1.2. single cycle
2.1.3. Data path and control
2.2. The technique of segmentation (pipeline)
2.2.1. ideal operation
2.2.2. Associated Concepts: Latency and Performance (Throughput)
2.3. Design a processor with pipeline
2.4. Limitations of the pipelined instructions channel
2.4.1. Causes of performance loss due to stop of pipeline
2.4.1.1. Conflicts structural constraints
2.4.1.2. Conflicts over control risks
2.4.1.3. Data dependency conflicts
2.4.2. Techniques to avoid halts
2.4.2.1. Internal forwarding
2.4.2.2. Branch prediction
3. Memory Organization and Structure: caches and virtual memory
3.1. Memory Hierarchy
3.2. Basic principles of the cache
3.2.1. Multi-level cache
3.2.2. Organizations: fully associative, direct mapped and set associative
3.2.3. Operating schemes. Write Through with assignment in writing (Fetch on-
write) and no assignment in writing. Post-write or writeback

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 Subject: Computer architecture
Code: 17834
Institution: Escuela Politécnica Superior
Degree: Computer Science Engineering
Level: Graduate
Type: Compulsory
ECTS: 6

3.2.4. Replacement algorithms

3.2.5. cache coherence
3.2.6. Examples of caches
3.3. Virtual Memory
3.3.1. Operation of virtual memory: paging, segmentation, paged segments
3.3.2. Translation of virtual addresses to physical or real addresses
3.3.3. Memory Management Unit (MMU)
3.3.4. Translation Look-aside Buffer (TLB)
3.4. Integration of the memory: the TLB and cache
3.4.1. Cache system with real or virtual cache
4. Storage and other aspects of the I / O
4.1. Reliability and availability
4.2. Flash disk storage
4.3. Measures of performance in I / O
4.4. Parallelism and I / O
5. Advanced techniques of parallelism
5.1. Instruction level parallelism (ILP)
5.2. superscalar processors
5.2.1. Policies in Instruction Issue
5.2.2. Register renaming.
5.2.3. Superscalar Implementation, reorder buffer, unit retirement
5.3. VLIW processors.
5.3.1. Planning by the compiler
5.3.2. Comparison Superscalar vs. VLIW processor.
5.4. Multicore, multiprocessors and clusters
5.4.1. The difficulty of parallel programs
5.4.2. Shared memory multiprocessors
5.4.3. Clusters and other message-passing multiprocessor
5.4.4. Introduction to graphics processors

Bibliography available at
1.13. Course bibliography the library’s catalogue
(click here)
Basic:
1. Estructura y diseño de computadores: La interfaz software/hardware. D.A.
Patterson y J.L. Hennessy. Ed. Reverte 2011. ISBN: 978-84-291-2620-4.
Ref_UAM: INF/681.32.3/PAT.
2. Computer Organization And Design: The Hardware/Software Interface. D.A.
Patterson y J.L. Hennessy. Morgan Kaufmann. 4ª Ed. 2009. ISBN: 978-01-237-
4493-7. Ref_UAM: INF/681.3.06/PAT.
Additional:
3. Estructura Y Diseño De Computadores: interficie circuitería- programación. D.A.
Patterson y J.L. Hennessy. Vols. 1 y 2. Ed. Reverte 2000.

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 Subject: Computer architecture
Code: 17834
Institution: Escuela Politécnica Superior
Degree: Computer Science Engineering
Level: Graduate
Type: Compulsory
ECTS: 6

4. Organización y Arquitectura De Computadores. W. Stallings. 7ª Ed. Pearson

Prentice Hall 2006.
5. Computer Architecture: A Quantitative Approach. J.L. Hennessy y D.A. Patterson.
Morgan Kaufmann. 4ª Ed. 2007.
6. Digital Design and Computer Architecture. D.M. Harris y S.L. Harris. Elsevier.
2007.
7. Arquitectura de computadores: Fundamentos de los Procesadores Superescalares,
J.P. Shen, M.H. Lipasti. McGraw-Hill. 2006.
8. Arquitectura de Computadores: de los Microprocesadores a las
Supercomputadoras. B. Parhami. McGraw Hill. 2007.
9. The Student’s Guide to VHDL. P. Ashenden. Morgan Kaufman Pub. 1998. ISBN:
1558605207. Ref_UAM: INF/681.3.062/ASH.
10. The designer's guide to VHDL". P.J. Ashenden. Morgan Kaufmann. 2ª Ed. 2002.

2. Teaching methodology
See next section.

3. Student workload

Nº de hours Percentage
Presence Lectures (3h x 14 weeks) 42 h (28%)
Laboratory (2h x13 weeks) 26 h (17%)
Tutorships 4 h (3%) 78 h (52%)
Final Exam (ordinary) 3 h (2%)
Final Exam (extraordinary) 3 h (2%)
No
Weekly study (3 h x 14 weeks) 42 h (28%)
presence
72 h (48%)
Prepare the exam (ordinary) 12 h (8%)
Prepare the exam (extraordinary) 18 h (12%)
Total hours: 25 hours x 6 ECTS credits 150 h

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 Subject: Computer architecture
Code: 17834
Institution: Escuela Politécnica Superior
Degree: Computer Science Engineering
Level: Graduate
Type: Compulsory
ECTS: 6

4. Evaluation procedures and weight of components

in the final grade
Grading for the continuous assessment method is the defined by the following
equation:
Grade = 0,3*Not_Lab + 0,7*Not_Teo
Not_Lab and Not_Teo must be 5 or higher. Otherwise, the final grade will be
Grade: (0,3*Min(5,Not_Lab) + 0,7*Min(5,Not_Teo))
1. CONTINUOUS ASSESMENT grade is defined by the following rules:
A. Theory grade (Not_Teo) is:
Not_Teo: MAX([0,2*ExP1 + 0,2*ExP2 + 0,6*ExFinal], ExFinal)
- ExP1 and ExP2 are two modular exams that students will do during the
semester.
- ExFinal is the final exam and it will cover all the topics of this subject.

B. Laboratory grade (Not_Lab) is obtained from all practical exercises and test of
the subject. Practical exercises and tests require a min of 4. Fail one exercise
or test will suppose to fail the current session.

2. FINAL EXAM grade is defined by the following rules:

A. Theory grade (Not_Teo) is:
Not_Teo = ExFinal
- ExFinal is the final exam and it will cover all the topics of this subject.

B. Laboratory grade (Not_Lab) is obtained from final practical exam that

evaluates all the knowledge and skills learnt in the laboratory:

Not_Lab = Practical ExFinal

For both assessment methods (CONTINUOUS or FINAL EXAM):

Not_Teo will be only valid for the extraordinary session of the same academic
year.
Not_Lab will be only valid for the extraordinary session of the same academic year
and the next two ones, only if the grade is 7,0 or higher. The grade each next
session will be (5+Old_grade)/2.

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 Subject: Computer architecture
Code: 17834
Institution: Escuela Politécnica Superior
Degree: Computer Science Engineering
Level: Graduate
Type: Compulsory
ECTS: 6

5.
Course calendar*

Semana Actividades Presenciales Actividades No Presenciales

 Presentación de la asignatura.
 U1. Abstracciones, Tecnología y Rendimiento de los
1ª Ordenadores.  Estudio del material propuesto sobre U1.
Temas: 1.1
 P0. Repaso VHDL
 U1. Abstracciones, Tecnología y Rendimiento de los
Ordenadores.
 Estudio del material propuesto sobre U1
2ª Temas: 1.2, 1.3, 1.4
 Resolución de problemas de U1.
 Tutoría Conjunta U1.
 P1. Micro Segmentado (I).
 U2. Procesadores segmentados
Temas: 2.1, 2.2  Estudio del material propuesto sobre U2.
3ª
 Tutoría Conjunta U2.
 P1. Micro Segmentado (II).
 U2. Procesadores segmentados
Temas: 2.3, 2.4  Resolución de problemas de U2.
4ª
 Tutoría Conjunta U2.  Estudio del material propuesto sobre U2.
 P1. Micro Segmentado (III).
 U2. Procesadores segmentados  Entrega P1.
Tema: 2.4  Estudio del material propuesto sobre U2.
5ª
 Tutoría Conjunta U2.  Resolución de problemas de U2.
 P2. Soporte de riesgos (I).
 U3. Organización y Estructura de la Memoria: Cachés y
Memoria Virtual.  Estudio del material propuesto sobre U3.
6ª Temas: 3.1, 3.2  Resolución de problemas de U3.
 Tutoría Conjunta U3.
 P2. Soporte de riesgos (II).
 U3. Organización y Estructura de la Memoria: Cachés y
Memoria Virtual.  Resolución de problemas de U3.
7ª Temas: 3.2 y 3.3  Estudio del material propuesto sobre U3.
 Tutoría Conjunta U3.
 P2. Soporte de riesgos (III).
 U3. Organización y Estructura de la Memoria: Cachés y  Entrega P2.
Memoria Virtual.  Estudio del material propuesto sobre U3.
8ª
Temas: 3.3 y 3.4  Resolución de problemas de U3.
 Tutoría Conjunta U3.
 U4. Almacenamiento y otros Aspectos de la E/S
 Estudio del material propuesto sobre U4.
9ª  Tutoría Conjunta U4.
 Resolución de problemas de U4.
 Pex1. Primer examen de prácticas.
 U4. Almacenamiento y otros Aspectos de la E/S
 Resolución de problemas de U4.
10ª  Tutoría Conjunta U4.
 Estudio del material propuesto sobre U4.
 P3. Memoria Cache (I).
 U5. Técnicas avanzadas de paralelismo.
Temas: 5.1, 5.2  Resolución de problemas de U5.
11ª  Estudio del material propuesto sobre U5
 Tutoría Conjunta U5.
 P3. Memoria Cache (II).
 U5. Técnicas avanzadas de paralelismo.
 Entrega P3.
Temas: 5.3
12ª  Resolución de problemas de U5.
 Tutoría Conjunta U5.
 P4. Sistemas Multiprocesador/Multicore (I).  Estudio del material propuesto sobre U5
 U5. Técnicas avanzadas de paralelismo.
Temas: 5.4  Estudio del material propuesto sobre U5.
13ª
 Tutoría Conjunta U5.  Resolución de problemas de U5.
 P4. Sistemas Multiprocesador/Multicore (II).
 Entrega P4.
 U5. Técnicas avanzadas de paralelismo.  Entrega Opcional.
14ª
 Tutoría Conjunta U5.  Estudio del material propuesto sobre la U5.
 Resolución de problemas de las U5.

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 Subject: Computer architecture
Code: 17834
Institution: Escuela Politécnica Superior
Degree: Computer Science Engineering
Level: Graduate
Type: Compulsory
ECTS: 6

Semana Actividades Presenciales Actividades No Presenciales

15ª  Pex2. Segundo examen de prácticas.
XX/12/2014  Examen Final Ordinario  Preparación del Examen final.
XX/06/2015  Examen Final Extraordinario  Preparación del Examen final.

The calendar is for guidance only. Future modifications can be made based on the academic calendar and
the development of the subject.

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