A Low Power Hard Decision Decoder for BCH
Codes
2021 10th International Conference on Advances in Computing and Communications (ICACC) | 978-1-6654-3919-0/21/$31.00 ©2021 IEEE | DOI: 10.1109/ICACC-202152719.2021.9708303
Pranitha Garlapati
Department of Electronics and Communication Engineering, Department of Electronics and Communication Engineering,
Amrita School of Engineering, Coimbatore,
Amrita Vishwa Vidyapeetham, India.
Karthi Balasubramanian
Department of Electronics and Communication Engineering,
Amrita School of Engineering, Coimbatore,
Amrita Vishwa Vidyapeetham, India.
Abstract—In decoding of Bose-Chaudhuri-Hocquenghem
codes, Peterson’s algorithm is more efficient for codes with
single, double and triple error correcting capabilities. Numerous
methods were proposed to reduce the hardware complexity
caused due to the inversion operation involved in the Peterson’s
algorithm. In this paper, a low complex hardware BCH decoder
using inversion-less Peterson’s algorithm presented in literature is
designed and its performance is verified with the Matlab results.
An attempt is made to design a low power version of this low
complex BCH decoder by replacing the parallel Chien search
architecture in the decoder with the two-step p-parallel Chien
search approach that is originally used in literature with the
Berlekamp-Massey Algorithm. For use with the inversion-less
Peterson’s algorithm the parallel Chien search architecture has
been modified and the resultant decoder has shown a power
reduction of up to 42 percentage with a moderate increase in
area by 10 percentage.
Index Terms—BCH codes, Hard decision decoding, Low com-
plex decoder, BER performance.
I. I NTRODUCTION
Error correcting codes are an integral part in most of the dig-
ital communication systems. Bose-Chaudhuri-Hocquenghem
(BCH) codes, turbo codes and convolutional codes are some
of the widely used error correcting codes [1]. Binary BCH
codes belong to a class of multiple error correcting cyclic
codes constructed from a generator polynomial whose roots
are from the extended Galois Field (GF). BCH codes with
single, double and triple error correcting capability finds wide
applications in optical communication, digital storage systems
and random access memory applications [2]–[5].
Algorithms and architectures for Hard Decision Decoding
(HDD) and Soft Decision Decoding (SDD) of BCH codes
have been proposed in literature [6], [7]. Berlekamp-Massey
algorithm (BMA) and Peterson’s algorithm are the two com-
monly used HDD algorithms. Both the algorithms involve
generation of error location polynomial and solving it for
determining the positions of errors. In the BCH decoding
process, the step involving determining the error locations by
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B. Yamuna
Amrita School of Engineering, Coimbatore,
Amrita Vishwa Vidyapeetham, India,
*Email:b yamuna@cb.amrita.edu.
solving the error location polynomial demands high hardware
complexity, which in turn affects the speed of the decoder.
Peterson’s decoder is used for determining the error location
polynomial when the error correcting capability is small. The
algorithm employs GF multiplications and inversions [8], [9].
The throughput and complexity of the algorithm are mainly
dependent on GF inversion since the size of the inversion
circuit is almost double the size of the multiplier [9]. Jurgen
Freudenberger et al., in [10] have proposed an inversion-less
Peterson’s algorithm to reduce the complexity of the decoding
process.
Solving the error location polynomial involves search for its
roots. Chien search algorithm is commonly used for finding
the roots of the error location polynomial. This root searching
step is the highest power consuming step in the decoding
process. Power efficient Chien search approaches like early
termination scheme [11], [12] and polynomial order reduction
[13] have been proposed to reduce the power consumption.
The early termination scheme and polynomial order reduction
techniques save power significantly when the errors are located
at the beginning of the codeword but they fail to do so when
the errors are located at other positions of the codeword.
To overcome the above drawback, a two step Chien search
approach has been proposed in [14] which leads to power
saving, regardless of the location of the errors.
In this work, we propose a low power version of the low
complex BCH decoder introduced by Jurgen Freudenberger
et al. [10]. The proposed low power architecture makes use
of the two-step p-parallel Chien search approach proposed in
[14] in place of the parallel Chien search architecture in the
low complex decoder proposed by Jurgen Freudenberger et al..
The two-step p-parallel Chien search approach involves two
steps: the first step involves processing q bits for each clock
cycle, the second step involves processing the remaining f-q
bits only when the first step is successful, where f represents
the field dimension. This leads to a reduction in the number
of computations and hence the esulting power saving.
The paper is organized as follows. Sections II and III
 give a brief introduction to the BCH encoder and decoder
respectively. The low complex BCH decoder using inversion-
less Peterson’s algorithm and its hardware architecture are
briefed in section IV. The proposed low power architecture
is presented in section V followed by the simulation results in
section VI. The conclusions are summarized in section VII.
II. BCH ENCODER
An (n, k, t) binary BCH code exists for any positive integer
f ≥ 3 and t < 2f −1 where t is the error correcting capability,
n is the length of the codeword that is output by the BCH
encoder and k is the length of input message to the encoder
[15].
BCH encoder generates a BCH code of length n and error
correcting capability t using generator polynomial g(x) for
k message bits. The hardware implementation of the BCH
encoder proposed in [15], is carried out using the Linear
Feedback Shift Register (LFSR) as shown in Fig. 1, where
the coefficients of the generator polynomial act as feedback to
the LFSR. To generate the codeword, k message bits are fed
as input to the LFSR and parity bits are generated using the
LFSR. The output of the LFSR is the BCH codeword.
Fig. 1. An (n,k) BCH encoder [15]
III. BCH DECODER
The three main steps in HDD of BCH codes are syndrome
computation, generation of the error location polynomial and
solving the error location polynomial. Fig. 2 shows the block
diagram of the hard decision BCH decoder [10].
Fig. 2. Block diagram of the BCH decoder [10]
The input to the syndrome generator is the received word
from which the most likely transmitted codeword is to
be decoded, The syndrome computation module generates
S1 , S2 , ...., S2t−1 syndromes. The generated syndromes de-
pend only on the error vector. Peterson’s algorithm is more
efficient than BMA for decoding of BCH codes with low
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error correcting capability [10], [16]. Chien search algorithm
determines the roots of the error location polynomial that gives
the decoded error positions.
IV. LOW COMPLEX BCH DECODER
The conventional Peterson’s algorithm uses inversion oper-
ations for generating the error location polynomial. Inversion-
less Peterson’s algorithm is used to reduce the complexity
caused due to the inversion operation. To achieve inversion-
less operation, all the f bit coefficients of the error location
polynomial are multiplied using a non zero factor without
changing the roots of the polynomial. The pipelined hardware
architecture of the inversion-less Peterson’s algorithm in [10],
that increases the speed of the low complex decoder is shown
in Fig. 3.
Fig. 3. Hardware architecture for Inversion-less Peterson’s algorithm [10]
The error positions are determined by solving the error loca-
tion polynomial using the Chien search root finding algorithm.
To increase the decoder throughput, the parallel Chien search
architecture has been employed in place of the conventional
Chien search architecture [2] as shown in Fig. 4. In every
computation involving solving the error location polynomial,
all the f bits of each of the coefficients are accessed.
The low complexity decoder design proposed in [10] uses
inversion-less Peterson’s algorithm for generating the error
location polynomial and parallel Chien search approach for
determining the error positions. However there always exists

Fig. 4. Conventional parallel Chien search architecture [2]
a possibility of further reduction in power consumption and
hence provide more power efficient decoders.
V. PROPOSED LOW POWER DECODER
ARCHITECTURE
The proposed work attempts to reduce the power consumed
in the low complex BCH decoder design presented in [10]. The
Chien search module is the highest power consuming step in
the decoding process. The proposed BCH decoder architecture
uses a two-step p-parallel Chien search architecture proposed
by Hoyoung Yoo et al. [14] in the low complex decoder [10]
in place of the parallel Chien search architecture.
The BCH decoder presented in [14] uses Berlekamp-Massey
algorithm to generate the error location polynomial but the
proposed design uses the inversion-less Peterson’s algorithm
as in [10]. Hence the hardware architecture for the two-step p-
parallel Chien search used in [14] is modified as shown in Fig.
5 in accordance to the error location polynomial generated by
the inversion-less Peterson’s algorithm.
In the two step p-parallel Chien search approach, each
computation is divided into two steps: In the first step the
occurrence of errors is determined by accessing only q of
the f bits, and not all the f bits and in the second step, the
remaining f-q bits are accessed only when the output of the
first step is zero i.e., λ(αyp+j )(f −q−1:0) is accessed only when
λ(αyp+j )(f −1:f −q) is zero, where j ranges from 1 to p, λ(x) is
the error location polynomial, yj denotes the registers used to
store the intermediate values obtained during the computation
and p denotes the number of αj computations at every clock
cycle. In this two-step approach, power reduction is observed
since the second step is performed only when the output of
the first step is zero.
Each of the computation in the two-step approach results
in an increase in the critical path length. To resolve this
issue, delay elements are inserted so that the computations
works in a pipelined manner. The hardware requirement for
the proposed decoder and the low complex BCH decoder in
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Fig. 5. Modified two-step p-parallel Chien search architecture
[10] is almost same except that the two-step p-parallel Chien
search architecture requires additional p, one bit registers and
(p − 1)t buffers of length f bits.
VI. EXPERIMENTAL RESULTS
The BCH encoder is designed in Matlab and used to encode
an input data of length 10,00,000 bits. BPSK scheme is used
to modulate the enoded message bits and sent through an
AWGN channel. The resultant received words are decoded
using the low complex BCH decoder [10] designed in Matlab.
The hardware designs of both the low complex BCH decoder
and the proposed low power decoder are done in Verilog.
Simulations for the Bit Error Rate (BER) performance is
carried out for both the decoders using the same test vec-
tors generated from Matlab, for (15,5,3), (15,7,2), (15,11,1),
(63,45,3), (63,51,2), (63,57,1), (255,231,3), (255,239,2) and
(255,247,1) BCH codes.
The low power BCH decoder designed based on the inversion-
less Peterson’s algorithm and the two-step p-parallel Chien
search approach is compared with the low complex decoder
based on inversion-less Peterson’s algorithm and parallel
Chien search approach for field dimensions of 4, 6 and 8 and
error correcting capabilities of one, two and three. The BER
simulation results of both the hardware designs are compared
with that of the decoder designed in Matlab for the above
mentioned BCH codes and the same are presented in Fig. 6 -
Fig. 14. It is observed that there is no difference in the Matlab
and Verilog outputs in all the cases.
To analyse the resource utilization of the decoders, the
designs were implemented on Basys 3 Artix-7 FPGA trainer
board. Tables I and II show the resource utilization summaries
for the low complex and the proposed low power BCH
decoders respectively for field dimensions of f = 4, 6 and
8.
To analyse the power consumed by the proposed low
power approach and the original design, the decoders were
synthesised in Synopsys using 90nm CMOS technology. Fig.
15 shows the percentage reduction in the power dissipation
of the proposed architecture with respect to the bit width of
 Fig. 6. Comparative BER performance of (15,5,3) BCH decoders(low Fig. 8. Comparative BER performance of (15,11,1) BCH decoders(low
complex and low power) complex and low power)

Fig. 7. Comparative BER performance of (15,7,2) BCH decoders(low Fig. 9. Comparative BER performance of (63,45,3) BCH decoders(low
complex and low power) complex and low power)

TABLE I TABLE II
FPGA RESOURCE UTILIZATIONS OF THE LOW COMPLEX BCH DECODER FPGA RESOURCE UTILIZATIONS OF THE PROPOSED LOW POWER BCH
DECODER
BCH decoder LUTs Flip-flops Throughput:
utilized utilized codewords BCH decoder LUTs Flip-flops Throughput:
per second utilized utilized codewords
BCH decoder (15,5,3) 180 263 90 ∗ 106 per second
BCH decoder (15,7,2) 121 207 111 ∗ 106 BCH decoder (15,5,3) 198 289 82 ∗ 106
BCH decoder (15,11,1) 94 159 125 ∗ 106 BCH decoder (15,7,2) 133 227 104 ∗ 106
BCH decoder (63,45,3) 445 636 83 ∗ 106 BCH decoder (15,11,1) 105 175 112 ∗ 106
BCH decoder (63,51,2) 287 478 91 ∗ 106 BCH decoder (63,45,3) 485 690 74 ∗ 106
BCH decoder (63,57,1) 181 248 95 ∗ 106 BCH decoder (63,51,2) 315 525 83 ∗ 106
BCH decoder (255,231,3) 934 651 69 ∗ 106 BCH decoder (63,57,1) 189 272 87 ∗ 106
BCH decoder (255,239,2) 798 586 71 ∗ 106 BCH decoder (255,231,3) 1027 715 62 ∗ 106
BCH decoder (255,247,1) 630 539 76 ∗ 106 BCH decoder (255,239,2) 880 640 64 ∗ 106
BCH decoder (255,247,1) 696 590 70 ∗ 106

the first stage of the two-step p-parallel Chien approach and

the field dimension f. It can seen that the power reduction is

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 Fig. 10. Comparative BER performance of (63,51,2) BCH decoders(low
complex and low power)
Fig. 11. Comparative BER performance of (63,57,1) BCH decoders(low
complex and low power)
directly proportional to the field dimension. It is also observed
that the maximum power reduction is obtained when smaller
bit width is used at the first stage of the two-step p-parallel
Chien search approach. It is observed that the optimal width
for processing the first step that can yield maximum power
saving is q = 2, for (15,5,3), (15,7,2), (15,11,1) BCH codes;
q = 3 for (63,45,3), (63,51,2), (63,57,1) BCH codes and q =
3 for (255,231,3), (255,239,2), (255,247,1) BCH codes. The
corresponding maximum power reduction that can be achieved
are 20.40%, 31.98% and 41.62% respectively.
VII. CONCLUSIONS
This paper proposes a hardware decoder that uses the two
step p-parallel Chien search architecture in the low complex
BCH decoder to reduce the power consumption.
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Fig. 12. Comparative BER performance of (255,231,3) BCH decoders(low
complex and low power)
Fig. 13. Comparative BER performance of (255,239,2) BCH decoders(low
complex and low power)
Simulation results show that there is a power saving of
upto 42% when compared to the low complex BCH decoder
designed in [10] with a 10% increase in resource utilization
and 10% decrease in throughput. Power savings due to the
designed architecture improves with the increase in field
dimension. It is envisaged that future work on high speed
and area-efficient architectures will be able to overcome the
speed and area trade-offs incurred by the proposed low power
architecture.
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Fig. 15. Percentage of power savings versus bit width of the first stage for
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