Stochastic Computing based BCH Decoder for
WBAN Systems
Kaining Han, Junchao Wang, and Warren J. Gross
Department of Electrical and Computer Engineering, McGill University, Montreal, Quebec, Canada
Email: kaining.han@mail.mcgill.ca; junchao.wang@mail.mcgill.ca; warren.gross@mcgill.ca
Abstract—BCH codes have been accepted as the error correc-
tion coding scheme by the IEEE 802.15.6 standard for wireless
body area networks (WBAN). Soft-decision BCH decoders are
attractive for the reason that the decoding gains result in signif-
icant transmitting energy reduction. An approximate computing
technology called stochastic computing is a promising low power
and low hardware cost implementation candidate for BCH soft
decision decoders. In this paper, a stochastic computing based
soft decision decoder is presented for the BCH code defined in
the IEEE 802.15.6 standard. According to the evaluation results,
the proposed design has the advantages of energy consumption
and hardware cost while approaching the decoding performance
in terms of block error rate (BLER) compared to existing BCH
soft decision decoders. In addition, the proposed design requires
no noise power estimation for the soft decision demodulation
module, which could further reduce the hardware cost and energy
consumption of the WBAN receiver.
Index Terms—Stochastic Computing, BCH Codes, Wireless
Body Area Network, Soft-Decision Decoding
I. I NTRODUCTION
In recent years, wireless body area networks (WBAN) have
attracted significant academic and industrial research attention
since they provides a low power, reliable, and efficient net-
work supporting wireless communications between biometric
sensors and centralized devices. In 2012, the IEEE 802.15.6
standard [1] was released for the specifications of WBAN
systems. According to this standard, in order to improve
the reliability of the communications, the Bose-Chaudhuri-
Hocquenghem (BCH) code has been specified as the error
correcting code (ECC) scheme.
In terms of BCH decoding methods, the hard-decision
decoder (HDD) is commonly used in WBAN due to the
simple hardware implementation structure. However, in view
of system power consumption, a soft-decision decoder (SDD)
is more attractive since the better bit-error rate (BER) perfor-
mance leads to power reduction in the transmitting side. Based
on the evaluation performed by [2], maximum likelihood (ML)
decoding provides the best BER performance for SDD, while
the huge complexity results in impractical hardware cost. Re-
garding the BCH SDD in WBAN, multiple architectures with
acceptable hardware cost have been proposed [3],[4]. However,
the BER performance gap between published decoders and the
ML decoder is still relatively large.
As an implementation technique, stochastic computing can
carry out complex computations with simple logic and has the
advantages of low implementation complexity, short critical
path, and high fault tolerance. Several stochastic computing
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based decoders have been proposed in prior literature for
various codes such as such as Reed-Solomon codes [5] [6],
LDPC codes [7],[8], Turbo codes[9], and Polar codes [10]. The
advantages of lower hardware cost, shorter critical path, and
higher throughput are observed for stochastic computing based
decoders compared to conventional binary decoder designs.
In this paper, a novel stochastic computing based BCH de-
coder is proposed. The proposed stochastic BCH decoder has
approximately the same BER performance as ML decoding.
Furthermore, a fully combinational logic architecture of the
HDD kernel is proposed which saves the hardware cost of
control logic and memory. A noise dependent scaling (NDS)
method has been applied to further optimize the decoding
latency.
II. P RELIMINARIES
In this section, the basis of BCH code and stochastic
computing are introduced.
A. BCH codes
A binary BCH code with code length N = 2m − 1 is de-
signed based on the Galois field GF(2m ), where the informa-
tion length K > N − mt is selected according to the required
error correcting capacity t. In the IEEE 802.15.6 standard, the
(N = 63, K = 51, t = 2) BCH code is designed over GF(26 ),
which encodes the information bits uK 1 = {u1 , u2 , ..., uK } to
codeword bits xN 1 = {x 1 , x2 , ..., x N }.
One of the most attractive features of a binary BCH code is
the analyzable error correcting capacity, while another is the
efficient architecture of hard decision (HD) decoding resulting
from the simple binary implementation structure of additions
and multiplications over GF(2m ).
The commonly used HD decoding (HDD) algorithm for
BCH is Berlekamp-Massey [11]. However, once the error
correcting capacity t is low such as the BCH code specified
in IEEE 802.15.6, where t = 2, the look-up-table (LUT) [12]
and Peterson Rule based [13] HDD kernel are more suitable
[3]. Benefiting from the efficient architecture of HDD kernel,
the HDD based soft-decision decoding (SDD), such as the
type-II Chase-based SDD [14], shows advantages for hardware
compared to the Maximum Likelihood (ML) decoding [15]
and Generalized Minimum Distance (GMD) [16]. In this
paper, a stochastic BCH decoder is based on a LUT based
HDD kernel.
729

Fig. 1. The hardware architecture of the proposed stochastic BCH decoder:
(a) Top level architecture of the stochastic BCH decoder; (b) The BCH HDD
kernel architecture.
B. Stochastic Computing
In stochastic computing, a number is represented with a
random bit stream by comparing it with a uniformly distributed
random number R(t)∼U (0, 1). Using a stochastic represen-
tation can map complex arithmetic functions to simple bit
wise logical operation. For example, multiplication, which
has high hardware cost in the conventional binary system,
is mapped to a single AND gate in stochastic computing. In
this paper, stochastic computing has been utilized to represent
and randomize the decoder soft input, while the decoding is
processed in GF(2m ) with binary logic.
III. S TOCHASTIC BCH D ECODING
The proposed stochastic BCH decoder consists of three
modules: Bit stream generator (BSG), HDD kernel, and CRC
check module, illustrated in Fig. 1. The bit-stream generator
produces test patterns to be used in a Chase-like scheme based
on a HDD decoder [5][6].
A. Stochastic Bit Stream Representation
The first step of the proposed stochastic BCH decoder is to
transform the input log-likelihood ratios LLRn to probabilities
Pn , P (yn |xn = 1) and then represent them with bit streams:
(t) (t)
{Yn |P r(Yn = 1) = Pn }, where n = 1, 2, ..., N .
 
P (yn | xn = 0)
LLRn = log (1)
P (yn | xn = 1)
1
P (yn | xn = 1) = (2)
1 + exp (LLRn )
( C. Noise Dependent Scaling
1, P (yn | xn = 1) ≥ R(t);
Yn(t) = (3)
0, otherwise;
The bit stream generator based on (1), (2) and (3) involves
a large number of exponential operations, resulting in large
( 0
1, LLRn ≤ R (t) ;
Yn(t) = (5)
0, otherwise,
0
where R (t) , ln [1/R (t) − 1] can be calculated with the
uniformly distributed random number R (t). The random num-
ber sharing scheme is also applied in this work to reduce
the amount of random number engines (RNE) [17]. Even
though the bit stream generator adds slight hardware overhead,
the proposed stochastic BCH decoder still illustrates lower
hardware cost compared to conventional binary based BCH
SDD since it does not contain the multiple bits represented
test syndrome calculation module and sorting module.
Regarding the main reason why the proposed stochastic
BCH decoder can approximate to the performance of ML
decoder, it is worthy to note that the bit stream representation
of the input LLRs can be considered as random searching,
(t)
while the combination of the bit streams: Y1∼N could be any
codeword of the BCH codeword space. Therefore, with enough
bit stream length, the whole codeword space can be covered
by the random searching.
B. Combinational Logic based HDD Kernel
In HDD kernel, the first step is to compute the syndrome
(t) (t) (t)
based on vector-formated bit streams y = [Y1 , Y2 , ..., YN ]
and parity check matrix H as,
s = y · HT = [s1 , s3 ], (6)
where s is the syndrome vector. The second step is calculating
the error location polynomial (ELP). For the BCH code when
t = 2 in WBAN, the ELP can be calculated as,
δ(x) = 1 + δ1 x + δ2 x2 , (7)
where δ1 = s1 and δ2 = (s31 + s3 )/s1 . The third step is to
utilize Chien search module to allocate the error bits. All the
possible values of x = αi are tried in (7) to check whether it
holds, where i = 0, 1, ..., n − 1 and α is the primitive element
of GF(2m ). If δ(αi ) = 0, the (n − i)-th bit of the error mask
vector is 1.
In the proposed design, the second and third step can be
implemented with a LUT, which could shorten the critical
path and increase the clock frequency. Benefiting from the
combinational logic based syndrome module and LUT based
ELP computation module and Chien search module, each bit
in the input bit stream can be processed in one clock cycle,
which contributes to higher throughput.
For many of the stochastic computing based decoders, in
order to reduce the number of hold states, NDS [7] is used to
reduce the error floor and speed up convergence:
0

hardware cost. The direct LLR-to-Stochastic (L2S) method LLRn = α · LLRn , (8)
[17] is applied to remove the exponential operations. where α = λ · N0 is the scaling factor obtained through
simulation, and N0 is the noise power, while usually α < 1.
 
1
P (yn | xn = 1) ≥ R(t) ⇒ LLRn ≤ ln −1 (4) The scaling result is demonstrated as red curve in Fig. 2.
R (t)

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 Fig. 2. The scaling operation with scaling factor α = 0.5, 1, 2. Fig. 3. BLER simulation results for the (63,51,2) BCH code in IEEE 802.15.6.

The scaling operation on the soft input is used to narrow the

searching range and reduce the decoding latency. As illustrated
in Fig. 2 (blue curve), the linear scaling operation on the
LLRn results in a non-linear scaling operation on the original
probability. The highly reliable inputs, such as Pn > 0.9 and
Pn < 0.1, are scaled close to 1 and 0, respectively. Based
on the fact that the error bits usually occurs at low reliable
positions, smaller searching range leads to a lower decoding
latency. Moreover, by using the NDS method, there is no
need for noise power estimation for soft decision demodulation
module [7].
D. CRC aided Early Stopping Criteria Fig. 4. Decoding performance comparison with the existing soft-decision
BCH decoders
In order to improve the decoding performance and reduce
the decoding latency, CRC aided early stopping criteria is
applied in the proposed stochastic BCH decoder. Based on As demonstrated in Fig. 4, a comparison between proposed
the simulation results, the trade off between the CRC error stochastic BCH decoder and existing soft-decision BCH de-
detection capability and effective SNR loss is evaluated. De- coders [4], [3] has been illustrated. It can be observed that the
spite the increment in code rate and loss in effective SNR, proposed stochastic BCH decoder outperforms the existing SD
the better coding gain is observed by using the CRC check. decoders by 1 dB in terms of Eb/N 0. Moreover, the proposed
Therefore, the 8 bit CRC is applied in proposed design. design provides 1.75 dB coding gain compared to HDD.
IV. E VALUATION AND I MPLEMENTATION B. Decoding Latency
In this section, the simulation results on decoding perfor- Benefiting from the CRC aided early stopping criteria, the
mance, decoding latency analysis, and hardware implementa- proposed stochastic BCH decoder illustrates a significantly
tion results are presented.
A. Decoding Performance
The proposed stochastic BCH decoder is simulated based on
a BPSK modulated communication system with the (63,51,2)
BCH code specified in the IEEE 802.15.6 standard. The
floating point ML and HDD [2] are also plotted in Fig.
3 for comparison. The length of the bit streams L in the
proposed stochastic BCH decoder is set to 32, 64, 128, and
256 respectively. It can be observed that the performance of
the proposed stochastic BCH decoder improves significantly
with the increasing of bit stream length. Eventually, it approx-
imates to the performance of floating point ML decoder when
L = 256, with only 0.1 dB loss. In the rest of the simulation
and implementation, the bit stream length L is selected to be Fig. 5. Average decoding latency of the proposed stochastic BCH decoder
256. with CRC aided early stopping criteria, where L = 32, 64, 128, 256.

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 TABLE I
C OMPARISON OF (63,51,2) BCH CODE IN IEEE 802.15.6 HARDWARE IMPLEMENTATIONS .
Design Hard-Decision [3]
CMOS Technology (nm) 90d
Code (N , K, t) (63,51,2)
Coding Gainsb 0 dB
Frequency (MHz) 143
Logic Gates 9618
Area (um2 ) 35140
Average Latencyc (clock cycles) 1 1.4
Throughputc (Mbps) 7283
Hardware Efficiency (Mbps/K Gates) 432
a The parallelism level is selected as 7 (defined as decoding bits in one clock cycle), which is reported the highest hardware efficiency in [4]. b Measured at
BLER=10−2 compared with HDD performance. c Measured at EbN 0 = 5dB. d The CMOS technology is not detailed in [3].
reduced decoding latency at high signal-to-noise ratio region.
The IEEE 802.15.6 standard requires the frame error rate lower
than 10%. Thus, in a practical WBAN system, the proposed
stochastic BCH decoder would work at the EbN 0 > 4.5
dB region (BLER < 10−2 ), where it takes lower than 4
clocks latency on average shown as Fig. 5. In addition, the
stochastic BCH decoders with L = 32, 64, 128, 256 show a
similar average decoding latency when EbN 0 > 4.5 dB which
means a longer bit stream length would leads to much better
decoding performance with little deterioration on decoding
latency.
C. Hardware Implementation
Form Table I, it can be observed that the area consumption
and logic gates of the proposed design is lower than the exist-
ing SDD [3] as a result of the simple architecture of stochastic
computing. The SDD in [4] shows the lowest hardware cost
due to its lower parallelism level (P = 7). The design in [3]
and [4] used a test syndrome calculation and sorting module
with complex structure and longer delay, resulting a lower
throughput than proposed work. Consequently, compared to
conventional binary system based SDD, the proposed design
illustrates advantages on both coding gains and the hardware
efficiency defined as the ratio of throughput to logic gates.
V. C ONCLUSION
This paper presents a novel stochastic computing based
decoder for BCH codes in WBAN systems. A combinational
logic based hard decision decoding kernel and noise dependent
scaling are characterized in the proposed design to further
reduce the hardware cost and improve the throughput, which
contributes to high hardware efficiency. The proposed decoder
significantly improves the decoding performance with respect
to the existing art in soft decision decoders, while achieves
higher area efficiency. The proposed stochastic BCH decoding
scheme could be a good implementation candidate for practical
WBAN systems.
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