A New Approach to Fast Gate Design A unique sampii 1g gate offers the highes George Frye Project Engineer, Sampling Fig 1 shows a section of delay line with switches inserted at point A and point C. A nonloading voltmeter placed at point B, measures the average of the voltage between the switches when the switch section is opened. When a fast step is applied to the line and the switches then opened, the following observations may be made, IE the step propagating down the line is at point A when the switch opens, 0 volts are observed. If the switches are reclosed and a second observation made at a later time, when the wavefront has reached point C, the voltage is 1. When the step is just entering the switch at point A, we observe 0; if it i just leaving the switeh at point C, we observe 1. Thus, we may state that the system 0-100S¢ risetime is determined by the length of the switch scetion or C-A. Since we know the line has capacitance and voltage, we have effectively “trapped” a quantity of charge (Q=CE). If we now apply this concept 10 the model shown in fig 2, we can note some very important observations ‘The model in fig 2 illustrates a simplified form of the tes risetime dependency upon strobe width. This new development ‘speed sampling system to date and offers promise for even faster gates. new sampling gate used in the Tektronix Type Set Sampling Head. Diodes replace the switches and instead of opening the switches simultaneously, we tur the diodes off one after another. Although it is a balanced system, only one half of the system will be deseribed, ‘The leading edge of the strobe pulse turns the diodes fon and the signal propagates into the conducting diodes and transmission line. The diodes remain on for the duration of the strobe pulse, being turned off by the tailing edge of the wave shape. The strobe pulse is designed to be longer than the transit time between the diodes. Gate action begins when the strobe trailing edge turns D2 off. At the same time, suppose a signal front enters through conducting diode DI. When the front reaches D2, it is off since the strobe arrived there prior to the front, The signal front reflects and reaches D1 which is now off since the strobe tailing edge has preceded the front. Thus, the signal front has been effectively tapped in the transmission line between the two diodes, Note, howover, that the gate characteristics are deter- mined by the strobe tailing edge (only one transition)TIMeE—> |. DIODE JUNCTION sl 50ps Le — | a VOLTAGE DROP 5 g ---- tn S DIODE BACK Fa BIAS a g a IDENTICAL -Gt CONVENTIONAL NEW TYPE $-4 STROBE STROBE ‘The conventionst sampling gate must take the diode from 2 fully off condition, turn fully-on, and return it 08 fully. off condition. The ine between the two {uly-off conetione, ys the sooo wlth an determines the reste Of the aystam, In the Type S-4 got, the diodes {ullvon as te ection egies, and oniy ane transition is mended. Risetime is determined by the length ofthe transmsion lin a8 pointes ou the text. The conventional strobe for 3 fest sampling gate te very narrow since the robe width determines the system resting. The Type {sess wide stab and minimizes the probleme inherent in narrow strobe generators ‘Only one transition is required for the gate action (gate my In this system, the 0-100%6 risetime is determined by [——~ 1 tosice the propagation time between D1 and D2, since | both the front and the strobe must traverse the distance. | ‘The important points to note are the following: (1) | =r _stoe a —————: 4 Gif condition). Using one aration offers aubwantal seis reduetion possibile, (2) "The setine of the Sten ih not dependent spon the abe wdkh (3) The propacedon tne eevee des sm thie ate (15 pt fe much lest than the noe pod of appre rraly 200 pr. (4) Beease the dies currently ed may be turned. in B10 po they do not pov a Fig 2, Simplified mode of sampling gate for Type 8-4 | Fi | Non-Loaoine vit @) 8 Fig 2. 25-08 hybrid gate, 6 Tektronix-manutactured diode chips are Pisces ona ceramic substrate The substrate Is focmed with slots {010301 which remove high dielectric constant material ear the tie to fede shun captions, The dade chip are et 0 Be, fxtending over the slot, to minimize lead Inductencs. Dp ts in the iret to correc for signals capactvely caupled through the gate ‘odes when they are not conducting Tolonby! Fig 1. Delaytine ection