IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. SC-12, NO.

6, DECEMBER 1977 685

A Low-Distortion Monolithic Wide-Band Amplifier

KAM H. CHAN AND ROBERT G. MEYER, SENIOR MEMBER , IEEE

Abstract –A wide-band monolithic amplifier is described which real- R,=75 RO=75

.+ RF
izes 20-dB gain and 250-MHz bandwidth using an 800-MHz integrated-
circuit process. At O-dBm signal levels, second- and third-order inter-
modulation distortion levels are below –55 and –42 dB, respectively,
across the band. Terminal impedances are matched to 75 Q with
VSWR better than 1.7. Both circuit and process design are: described
as well as computer optimization of circuit performance. (a)

I. INTRODUCTION R, =75 fio~75

w
tions.
IDE-BAND
communication
In communication
low-distortion
systems and instrumentation
amplifiers
applica-
systems, for example, amplifiers are
are widelly used in

often required with bandwidths of several hundred nnegahertz

and very low distortion levels. At present, amplifiers of this ‘F1

type are generally realized as thin-film hybrids [1] .

(b)
In this paper, a wide-band monolithic amplifier with char-
acteristics comparable to many hybrid units, but with much
Fig. 1. Shunt and series feedback circuits. (a) Single stage. (b) Two
lower manufacturing cost, is described. The circuit require- stage.
ments are first described, followed by a discussion of the
circuit configuration. Next the monolithic process is de-
although later versions of the circuit could use higher values,
scribed and finally the measured circuit data are presented.
and achieve even lower distortion values.
The noise performance of the amplifier is important for
II. AMPLIFIER REQUIREMENTS
several reasons. First, the amplifier itself can be used as a pre-
The choice of amplifier specifications involves compromises, amplifier in many applications if its noise performance is
and this is reflected in the amplifier requirements listed below. adequate. Second, if very low noise is required, a low-noise
A gain of 20 dB was chosen as a compromise value that could preamplifier can be added and the noise of the main amplifier
be realized in a single package. It is high enough to overcome should then be low enough to make a negligible contribution.
the noise of the following stages and also high enough that The compromise here is that the high bias currents needed for
the input signal requirements to the amplifier are moderate. A low distortion generally lead to a degradation in circuit-noise
bandwidth greater than 200 MHz was specified, and this en- performance. A specification of 9 dB was set for the circuit-
ables the amplifier to be used in many common applications. noise figure.
Most applications of these amplifiers are in systems designed Finally, in order to reduce the cost of fabrication, the circuit
around matched impedances of 50 or 75 fJ. The amplifier was was designed for realization using fairly standard bipolar mono-
designed for input and output impedance matches to 75 S2, lithic processing. The process, to be described later, incorpo-
although 50 fl could equally well be used. rates shallow diffusion but uses standard diffused isolation
Three important specifications that are related are amplifier techniques and regular single-level aluminum metallization.
distortion, noise figure, and power requirements. Since many
applications of these amplifiers require very low distortion III. CIRCUIT CONFIGURATION
levels, a design aim was to achieve second- and third-order The realization of the amplifier specifications previously
intermodulation distortion below -50 dB at signal levels of described requires careful choice of the amplifier-circuit con-
O dBm across the frequency band [2] . As will be shown later, figuration. The simultaneous requirements of wide bandwidth,
low distortion generally requires use of high bias currents in matched terminal impedances, low noise, and low distortion
the active devices with consequent high-power requirements. are difficult to achieve, particularly when realized in a mono-
A limit of 2 W was set for power dissipation in this design, lithic integrated circuit (IC). One possible configuration is
shown in Fig. 1(a). This incorporates simultaneous shunt and
series feedback via RF and RE [1] , [3] . It can be shown that
Manuscript received May 20, 1977. This work was supported by the the terminal impedances of this circuit are resistive and broad-
U.S. Army Research Office under Grant DAHC04 -74 -G-151.
band and can be designed for ‘75-Q operation by a suitable
The authors are with the Department of Electrical Engineering and
Computer Sciences, University of California, Berkeley, CA 94720. choice of RF and RE. The gain characteristic is broad-band,
686 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. SC-12, NO. 6, DECEMBER 1977

.
,=)70 I I Vcc
(10-16V)
the circuit
are bias
distortion
resistors common
and high-frequency
to both
gain.
half-circuits.
Resistors REE
Transistor
R2

R, R
‘u
400

80
Qcc

.
100

IL
t
‘c2A

T ,
QCCis connected as a VBE-multiplier and sets the bias voltage
at the collectors of Ql~ and QIB. Other important compo-
nents in the bias circuit are Zener diodes Z1 and Zz which
have a 5.5-V dc voltage drop and allow direct connection of
Q3A ~,
o
‘IA R RP2 to the output.
t I .,” 230 RBfl 70 ~:2A

1~”- L Although the Zener diodes greatly facilitate biasing in the

‘EIA 8 RF2AI’5 amplifier, they must be carefully designed to minimize their

v,

vi ‘EEI 60 REE2 40
distortion and noise contributions. The noise is minimized by
‘EIB 8
designing the devices to operate at high-current densities, as
‘F2B 125
RE2B described in the next section. Distortion is minimized by
19
operating the Zeners well beyond the knee of the Zener char-
v ‘FIB 230 RBB 70
s. 22
QIZI ,
0.. acteristic. In addition, series resistance in the Zeners must be
I minimized since this causes errors in the values of RF2A and
I H7; RC,8 c“ 100j Rc2B
—
~~ ‘;: ~~ L
( RF2B . In the final circuit, the Zeners made no measurable
contribution to the distortion performance and added only
Fig. 2. Complete schematic of the wide-band monolithic amplifier.
about 1 dB to the circuit-noise figure.
The distortion performance of the circuit of Fig. 2 was also
simulated by computer using the program SPICE [4] , and the
but computer simulation showed that the gain and bandwidth bias currents in the various stages were set largely on the basis
requirements for this design could not be met in a single-stage of computer prediction of best distortion performance. At
circuit of this type using monolithic technology. low frequencies, the distortion is due almost entirely to non-
The advantages of the circuit of Fig. l(a) can be retained linearity in Q3A and Q3B. At the upper end of the frequency
while the gain-bandwidth product is increased if a two-stage range, the output devices are still the most important, but
version of the circuit [1] is used. This is shown schematically distortion due to the input stage is significant because of the
in Fig. l(b), where simultaneous shunt and series feedback is decrease in gain of the output stage.
applied over two stages to realize resistive terminal impedances
of 75 S2, together with a much larger gain-bandwidth product. IV. MONOLITHIC PROCESS AND DEVICE STRUCTURE
Since feedback is applied over two stages, substantial feed-
The distortion specification of the amplifier is one of the
back-loop gain is realized for the minimization of distortion.
most important characteristics and is heavily dependent on
In the final circuit a balanced version of this configuration
the characteristics of the monolithic transistors used. In
was used, and input and output signals were taken differen-
addition, realization of the gain and bandwidth requirements
tially. This eases the biasing problem in the IC and also gives
of the amplifier requires transistors with f~ in the region
a large amount (20-30 dB) of second-order distortion can-
of 1 GHz.
cellation.
The design of low-distortion transistors requires optimiza-
The complete circuit of the monolithic amplifier is shown in
tion of device geometry and epitaxial (epi) layer character-
Fig. 2. The input and output signals appear differentially at
istics. The effects of device geometry can be seen by an
~ and VO, respectively. The differential terminal impedances
approximate analysis of high-frequency distortion in the
are 75 !2 and the terminal impedances of the half-circuits are
transistor. It can be shown [5] that third-order intermodu-
37.5 Q. The component values in the circuit were optimized
Iation distortion in a bipolar transistor at high frequencies
by computer to yield 20-dB gain with maximum bandwidth
is given approximately by
and adequate input and output impedance matches. This is
achieved by minimizing a figure of merit M where ~~ cjEQ VT 11 1
+CjCQRL; ;+l Y
4 R~I~ () VQ
ml, = (2)
~j~Q VT
1+ ~ cjCQRL

+B~[~~(Ui)- 1]2}. (1) IQ

where
Coefficients At and Bi are weighting functions at different
frequency points, G is the circuit gain, PI and p2 are input K
Cjc . (3)
and output voltage standing-wave ratios (VSWR), and ~i is
(% + VcB)”n
the frequency.
The circuit is biased from a single supply Vcc which can and
have values from 10 to 16 V. Resistors RF1 and RE2 provide
VT . LT. (4)
shunt-series feedback and RF1 also provides dc bias to the
q
input base. Resistors RE1 and RF2 provide series-shunt feed-
back. A Darlington output connection is used to improve In these equations IQ is the collector current, ~Q the collector-
CHAN AND MEYER: MONOLITHIC WIDE-BAND AMPLIFIER 687

DEEP n+ (COLLECTOR)
~~

A A

1-E
~ \ I
DEEP p+ (BASE) EMITTER n+

(a)

“\E’B; E[B c
--- ,,
...
P+ P+ P+
—-*FU ‘P- \~
3pm n+
n
L!!L
“+
BURIED LAYER

p SUBSTRATE
(b)

Fig. 3. Monolithic transistor structure. (a) Plan. (b) Section At.

base voltage, RL the load resistance, PO the peak output t f.

THIRO-OROER
IN TERM OVULATION
VOkage per Signal, cjEQ the emitter depletion Ca[)aCkUICe, DISTORTION (dB)

and CjcQ the collector depletion capacitance. If two sinu- IM3

soidal signals of frequencies m ~ and C.02are applied to the

600; \ -lo
transistor to produce equal output
the ratio of the distortion component at (202 - u ~) to the
voltages F’., then IM3 is
J ‘, I
+–20
fundamental signal at u ~ or Uz. Second-order intermodu- 400 J
\
1-30
lation distortion IM2 is the ratio of the distortion ccjmponent Pred, cted IM3

at (a ~ + Wz ) to the fundamental signal.

200;
j ‘“J
‘,
----
1-40

Equation (2) shows that IM3 increases as IQ is reduced

1
-- -50
L Mess.red IM3
because of the presence of cjEQ in the transistor. The pres- -60
j
ence of cjfJQ also causes the device ~~ to fall at low ]Q. In 0+ 1 I I
order to minimize this source of distortion, the device must o 10 20 30 40
COLLECTOR CURRENT (mA)
be designed for minimum cj~Q and operation at moder-
ately high IQ k WRntid. Fig. 4. Transistor distortion and .fT versus collector current.
This also minimizes second-order
intermodulation.
An additional source of distortion not considered. in (2) is used to reduce the base resistance and improve the high-
high-current ~T falloff due to the Kirk effect [5]. This can frequency gain and noise figure. The base diffusion is about
be minimized by the choice of epi layer characteristics. Be- l-~m deep and the active basewidth about 0.4 Mm. The pro-
cause of difficulty in controlling out-diffusion of the buried cess uses eight masks and standard aluminum metallization.
layer, no attempt was made to operate with the epi region In Fig. 4 measured curves of~~ and IM3 (at 200 MHz) versus
depleted, and epi thickness and doping of 3 Urn and 1 Q . cm collector current are shown for a typical device. Distortion
were used to minimize the Kirk effect. predicted for the device by SPICE is also shown and is close
The monolithic device structure used is shown in Fig. 3. to the measured value. The behavior predicted earlier is
An interdigitated base and emitter structure is employed to observed in that as IQ is reduced
distortion increases rapidly
maximize the emitter periphery which is the active region and ~T becomes dependent on IQ. Thus typical bias currents
of the emitter at high-current levels. In order to minimize the in the output devices of the circuit are in excess of 20 mA
total emitter area (and thus CjE Q ), the minimum possible where the device j_T is approximately constant and equal to
emitter contact opening is used. In this process, an emitter 800 MHz.
contact opening of 2.5 pm was used with an emitter-wash The amplifier circuit of Fig. 2 utilizes Zener diodes Z1 and
technique. Developments in lithography allowing submicrcrn Zj as part of the bias circuit. In order to reduce the noise
dimensions should allow significant further improvements contribution of the Zener diodes, the devices are designed for
in distortion in devices of this type. small geometries [6] and high-current density. An additional
A cross section of the device is shown in Fig. 3(b). A deep requirement in this application is that 21 and Z2 should be
n+-diffusion is used to contact the buried layer anld reduce reasonably well matched and this precludes the use of mini-
the collector series resistance. A deep p+-diffusicm is also mum-area devices. The Zener is fabricated using the n+- and
688 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. SC-12, NO. 6, DECEMBER 1977

n+ d, ff. $,on —

A ---- –--–– –––---–––A

‘.3 ‘p+ “’’US’””
P’ conloct

uj-
1 1

(a)

;~, “*’’””W
15pm P’

“-

n+ Buried Ioyer

P Subs frafe

(b)

Fig. 5. Low-noise Zener-diode structure. (a) Plan. (b) Section AA.

10’14 VoltsZ/H,

I
Fig. 7. Die photograph.

10 (mA)
+
V.
Fig. 6. Measured noise-voltage spectral density versus bias current
for the Zener diodes.

p’”- diffusions, and the device structure is shown in Fig. 5. The Fig. 8. Typical external connections to the IC.

breakdown voltage is 5.5 V and the mismatch between ZI and

Z:! is typically 50 mV. The measured noise-voltage density
is shown in Fig. 6. This is essentially flat over the amplifier Fig. 8. Wide-band balun transformers T1 and T2 maintain
bamdwidth, and is inversely proportional to operating current. balanced operation of the circuit and allow significant second-
At 5-mA bias current, the noise density is 10-16 V2/Hz. order int ermodulation distortion cancellation. Amplifiers can
be cascaded with negligible interaction, and if this is done an
V. CIRCUIT PERFORMANCE interstage transformer is not required. The IC has six pins
A die photograph of the final circuit is shown in Fig. 7. and operates from a single power supply. Distortion per-
The output devices can be seen on the right, and the layout formance can be traded against power dissipation by varying
is symmetrical along the centerline to minimize thermal the supply voltage.
imbalance. This is important for the nulling of second-order The measured gain of the amplifier is compared with com-
distortion in the amplifier. The die size is 40 X 60 roil. puted values in Fig. 9, and both show a value of about 20 dB
Typical external connections to the amplifier are shown in with a bandwidth of 250 MHz. Measurements at 100 and
CHAN AND MEYER: MONOLITHIC WIDE-BAND AMPLIFIER 689

b
o----o Measured
— Computed
_25-

&--- --- -----0 -----0-----0-” -

t ~
; lo-
3
~5
1
ok- ,~
Frequency (MHz)

Fig. 9. Amplifier gain versusfrequency.

Frequency (MHz) 100 MHz. The high-frequency discrepancy could be due to

-50-
inaccuracies in modeling capacitive parasites in the IC.
The noise figure of the amplifier has a worst case value of
9 dB at 250 MHz. Reverse transmission in the amplifier is
-37 dB and measured input and output VSWR was less than
1.7 in a 75-Q system. Total power dissipation was 1.65 W
from a 14-V supply.

VI. FURTHER DEVELOPMENTS

The results just described were obtained using an 800-MHz

IC process and a circuit optimized around those process
(a) parameters. However, computer simulation showed the
circuit to be close to optimum for a range of ~T values. This
Frequency ( MHz) was confirmed by fabricating circuits with the same mask
5 10 20 50 100 200300
-40 set but using a more advanced IC process. This process uses
,. @
.-5 ,’ shallower diffusions to achieve ~T = 1.7 GHz and gave ampli-
~ J
;- -50- ,’ fiers with gain characteristics similar to those of Fig. 9 but
.m ,L
E-a
,6’
with 370-MHz bandwidth. Measured values of IM2 and IM3
~-
.-= ~ ’60
,’ were below -60 and -44 dB, respectively, below 300 MHz.
.- ,“
$: ,’~
For frequencies below 200 MHz all distortion is below -53
: z .70 ,/ *,’ dB.
!V .-
:.- -x--o. - ------ Measured
~ 1
— Computed
i=
-80
VII. CONCLUSIONS

(b) A wide-band monolithic amplifier has been described.

Computer optimization has yielded 20-dB gain and 250-MHz
Fig. 10. Computed distortion in the monolithic circuit compared
with measured values. (a) Second-order intermodulation. (b) Third- bandwidth using an 800-MHz integrated-circuit process. The
order intermodulation. process incorporates eight masks and also includes low-noise
Zener diodes for bias purposes. Appropriate choice of device
geometry and operating conditions, circuit topology, and
200 MHz showed gain sensitivity to a temperature of 0.004 epitaxial characteristics has yielded low distortion across
and 0.02 dB/°C, respectively. the amplifier bandwidth. The circuit performance improves
Fig. 10 shows measured circuit distortion compared with when more advanced IC processes are used for fabrication.
computed values at signal levels of O dBm. In Fig. 10(a)
measured and computed values of IMZ show good agreement REFERENCES

and IM2 is below -55 dB across the amplifier bamdwidth. [1] R. G. Meyer, R. Eschenbach, and R. Chin, “A wideband ultra-
The distortion becomes worse as frequency increases because linear amplifier from 3 to 300 MHz,” IEEE J. Solid-State Cir-
cuits, vol. SC-9, pp. 167-175, Aug. 1974.
the feedback-loop gain of the amplifier diminishes. Below [2] K. A. Simons, “The decibel relationship between amplifier dis-
20 MHz the measured IMZ increases because the coupling tortion products,” F’roc. IEEE, vol. 58, pp. 1071-1086, July
transformers become unbalanced and the second- order can- 1970.
[3] J. B. Couglin, R. J. Gelsing, P. J. Jochems, and H. J. M. van der
cellation degrades. This can be improved by using larger cores Laak, “A monolithic silicon wideband amplifier from DC to 1
on the transformers. GHz,” IEEE J. Solid-State Circuits, vol. SC-8, pp. 414-419,
Measured and computed values of IM3 in Fig. 10(b) are Dec. 1973.
[4] S. H. Chishohn and L. W. Nagel, “Efficient computer simulation
fairly close except at high frequencies. The measured values of distortion in electronic circuits,” IEEE Trans. Circuit Theory,
are below -42 dB across the band and below -55 {cIBbelow VOL CT-20, pp. 742-745, NOV. 1973.
690 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. SC-12, NO. 6, DECEMBER 1977

[5] H. E. Abraham and R. G. Meyer, “Transistor design for low dis- Universities and Colleges” in 1971-1972. He is a member of Sigma
tortion at high frequencies,” IEEE Trans. Electron Devices, Tau and Phi Kappa Phi.
vol. ED-23, pp. 1290-1297, Dec. 1976.
[6] W. F. Davis, “A five-terminal *15 V monolithic voltage regu-
lator,” IEEE J. Solid-State Circuits, vol. SC-6, PP. 366-376,
Dec. 1971.
Robert G. Meyer (S’64-M’68-SM’74) was
born in Melbourne, Australia, on JUIY 21,
1942. He received the B. E., M. Eng. Sci.,
and Ph.D. degrees, all in electrical engineering
from the University of Melbourne, Australia,
Kam H. Chan was born in Macau, South in 1963, 1965, and 1968, respectively.
China, on February 20, 1949. He received In 1968 he was employed as an Assistant
the B.S. degree in electrical engineering from Lecturer in Electrical Engineering at the Uni-
the California State University, Fresno, in versity of Melbourne. Since September 1968,
1972, and the M.S. and Ph.D. degrees in elec- he has been employed in the Department of
—. .-.
tronics from the University of California, blectrlcai kmgmeermg and Computer Sciences,
Berkeley, in 1974 and 1977, respectively. University of California, Berkeley, where he is now an Associate Pro-
He has been employed as a Research Assis- fessor. His current research interests are in integrated-circuit design
tant at the Electronics Research Laboratory and device fabrication. He has been a Consultant to Hewlett-Packard,
in the University of California, Berkeley, IBM, Exar, and Signetics. He is coauthor of the book Analysis and
since 1973. In 1974 he was a Co-op Student Design of Analog Integrated Circuits (Wiley, 1977).
at Motorola Semiconductor, Inc., in Phoenix, AZ. In 1977 he was Dr. Meyer is secretary of the Solid-State Circuits Council of the IEEE
employed as an Acting Instructor at the University of California, and is an Associate Editor of the IEEE JOURNALOFSOLID-STATECIRCUITS.
Berkeley. His interests are in device modeling, analysis and design He is a member of the ADCOM of the IEEE Circuits and Systems Society
of high-frequency integrated circuits, and process development. and is an Associate Editor of the IEEE TRANSACTIONSON CIRCUITS AND
Dr. Chan was elected to “Who’s Who Among Students in American SYSTEMS. He is a member of Sigma Xi.

Special Correspondence

A Vertical Injection Logic Watch IC with CMOS Equivalent 1 55V

~.—
-—-—-+ -—-—-—--
Current Drain I I
!
CURRENT SUPPLY
Y. HORIBA, T. NOGUCHI, AND K. KIJIMA I
i i i 4 ‘------ + ‘ !i
CRYSTAL
CURRENT
OSCIL- BUFFER FF 9 CONTROL
Oy LATOR
Abstract–Vertical injection logic (V~L), an improved structure of 12L,
-T: G
was applied to an anafog watch IC with a 1.5-V supply voltage, which
resulted in a CMOS equivalent current drain of 2 PA and half the chip
size of CMOS. The design consideration and experimental work that WAVE MOTOR
SHAPING ORIVER pa
support the characteristics are described. I
RESET
I i~oi
L. —._. —._. _.— .*.J
12 L watch chips have been realize
developed recently [ 1 ] to
CMOS comparable current drain, but the current was still Fig. 1. Block diagram of VIL analog watch chip.
larger than CMOS. The current drain in watch circuits such as
dividers is mainly determined by the power-delay product of
12L gates. ye rtical injection logic (VIL) [2] is superior to con- cillator/buffer, frequency dividers, a step-motor driver, and a
ventional I L in the power-delay product, and was applied suc- current supply, as shown in Fig. 1. Logic circuits, including
cessfully to an analog watch IC with CMOS equivalent current the 16-stage divider, were composed of VIL gates. Analog cir-
drain. This correspondence will describe the experimental re- cuits such as an oscillator or a current amplifier in the output
sults of an IC designed with the following considerations: stage were constructed by using the conventional p+-diffusion
isolated n-p-n/p-n-p transistors.
1 ) lower power-delay product in the logic circuits; VIL has a buried p+-injector [2] under the base of the n-p-n
2) less current loss in the linear circuits; transistor to obtain high current gain in the p-n-p transistor.
3) optimum current distribution among the circuit blocks. The power-delay product of 12L gates may be expressed as
[3]
The chip was composed of a 32-kHz crystal-controlled os-

Manuscript
The authors
received March 7, 1977; revised July 29, 1977.
are with the LSI Detielopment
Electric Corporation, Itami, Japan.
Laboratory, Mitsubishi
where
pOwer-delayprOduc
(l-::’2)cv2
CYn and ~i are the normal and inverse current gain, re-