a OA 8086 16-Bit Microprocessor iAPX86 Family FINAL DISTINCTIVE CHARACTERISTICS '© Directly addresses up to 1 Mbyte of memory © 24 operand addressing modes Efficient implementation of high level ianguages Intruction sot compatible wih 8080 software BBA, byte, word, and block operations iid 16-0 signed and unsigned arithmetic in binary or decimal © MULTIBUS® systom interface © Three speed options = SMH for 2086 = @MHz for 8086-2 = 1OMH2 for 8086-1 GENERAL DESCRIPTION | “The 8086 is a general purpose 16-bit microprocessor CPU. Its architecture is bull around thinean 16-bi rogistrs and rine ‘-bitflage. The CPU operates on 16-bit address ‘spaces and can directly address up to 1 mogabyte using coffeet addresses within four distinct memory segments, ‘dosignatod ae code, dala, stack and extra code. The 8006 implements powerful instruction set with 24 operand ‘addressing modes, This instruction set is compatblo with that of the 8080 and 8085. In addtion, the 8086 is particulary effective in executing high level languages. ‘The 8086 can operate in minimum and maximum modes. Maximum mode offloads certain bus control functions to & peripheral device and allows tho CPU to operat efficiently, ina multi-processor system. The CPU and its high perfor: ‘mance peripherals aro MULTIBUS compatibie, The 8086 is. implemented in N-channel, depletion load, silcon gate technology and is contained ina 40-pin CERDIP package, Molded DIP packaga, or Plastic Leaded Chip Carrier. BLOCK DIAGRAM 0003740 ec Ament oe 7 Iosue Deve August 1988 13Daw oP SEBRESEEESEEEE Note: Pin 1 is mathod for orintaton, CONNECTION DIAGRAMS Top View om we om om, am ccooterot 14AMD. ORDERING INFORMATION Commercial AMO commercial products ar avaiable in several packages and operating ranges. The order number (Vaid Combination i formed bya combination of a. Temperature Range i. Package Type © Device Number 4. Speed Option ©. Optional Processing - Products | Valid Combinations. st configurations planned to be supported in volume fortis device. Consult the local AMD Seles office to contlem availabilty of specific valid Combinations, to check on newly eleasod vaké combinations, fd to oblain additonal dala on AMO'S standard itary grade products 16Dino ORDERING INFORMATION Mittary Products ‘AMO products for Aerospace and Defense sppications are avaiable in several packages and operating ranges. APL (Approved Product List) products are fly complant with MIL:STD-889C requirements. The oer number (Valid Combination) foc APL product is trmed by a combinaton of a. Device Number 'b Speed Option {i appicebie) © Device Class. 4. Package Type © Load Finis L_. ere 4 PACKAGE TYPE ON Aae Coamic OF (C0 040) 6 Dever c1ass {________ speto omnon | Bones ne “Er ne — NUMBER /OESCRIPTION Ux ary Valid Combinations Valid Combinations list configurations planned to be Group A Teste Group A tosts consist of Subgroups 12,9, 7,6.8, 10, 11 14au ON PIN DESCRIPTION Ww | FREE cs heh eI A ae Pred | all a be He HEH | aeehtltys of GH zbfuley lesz Ufa | | | s a i i fi Hall sey abedee Ta Ge |p i eo, cll dee tae el UL} Hee aide Uae SHU UvDy ae THE Sula ieeieslleke 8 he sides HEE EHF be ne Hay Pg PORE HAG eal aa OUT aE Tea ae ee anal LAE lees i eo bk Bh feb le ith : Fakes he raw corenpond © OE omyDivo PIN DESCRIPTION (continued) Name vo | Description BSS ‘SS Ave ang Fay. and Tp and ftaved wo a save a 11) arta Tao Oana Tw jason READY a Hom ‘Tad sas ‘x moe by tu 0200 Bos Conse’ fo Giarate Non ae io wee convo! sees us yt. ara rou tote passe ea Bett ater co i ete aerate iE aa yon Se Sewage Leweytanns eames Eon ae ei nay oa erase cas Stee ete Sack Gt mt et st me sra's 2 args ich tia env tw ter at fake Laer cit ae noe areca nie Sion oes rare sage cetera imo b nase ca tr mre et it te ions Shtannowriare serene 2 en meanest tg gape © er Tt oe exons no oat ta SSreeaeateees escesarygee om tot me eng pmpriannras cesar tT msoraee geet . SSS SEN sn GES Sa Se es te USURIS RR ESSE tena vo oa ie not mt + cal bs wil be rlenand eng the nt cock. 2 Arama ect wi sat we 8 ake. Now De fer Res fora cuenty act memory ele ir carlin rate" amsy seis oe wey ‘© | TREE ona incsis Bat oer ayer bus nasi wa ol 9 gan Sokol fhe een ba we [LOCK acre LOW. The LOEX seals ecieles by be “LOCK prehenercann 3 roma te srt te corgioton cttw next evcton The Sree actve LOW, and hawt fo tree ware OFF in a ehrewiedge ‘O[Oueus Ste The qinue naa @ vad cng he GOK Sle ater WRGh te Goo epuaion W FOr ‘Some 1251 wr O60 rovie sats w slow eral racking of he is £086 ineucson mut © Teerani?0 steae, MG tatones'aisp Ts crcsong'a ba Goss St rare wank out Fe tat [Tuo tho eyes 0 = HIG, 1O= LOW). M/ID Real to Trew sate OFF” in al bw "hols acknowoage’ |i. ingcates rat * ‘we rary & wie 70 one at of wiS nga Wm ate fot Tt To ay ta Ce. 8 te COMO hows fo |ieo-sute OFF rice! bua “nad ackndeton™ ‘|INTA is sed a «road wbe ter iterintscnowooge jos We aire LGW daira Ta Tu ond Tw ot wach itront actrowonse ose. ‘0 [Adres Laten Enea Proviea by tha povenor to ich fe addons ip OS8TRIED odioss CR Wp JeSHiGH pase aclve aug Tr of arm Bex cya: Note a ALE ave ate a om, rene, Rao mea enon at ures fn an CHER a Ta Pane §) ‘ha ramam made, and te Unig s the sama ee for MG. (F=TAGHE R~-LOW) The ogra dats fo eo.nate OFF inca! bur "hold sexed: "BEN's cave LOW aun ecn memory and 10 acon an fr NTA eyoue, Fo" ad oF inl Tonge tie WT me 8 wr cy, ee rm tro bognneg 2 Tz wal bo mca of EN tous to tweets OFF eee bis “hol 1avo PIN DESCRIPTION (continued) Pin Wo | Name | VO. ‘Description ] Fr 5 | Hous] OHO, ctor Bat mia nasi roqeting alee! ts OR To be aarawdped HOLD rut Bae te sce niet ee provera rcavag the “hl runt wi eave HOR Quit as an a [ina same we a for FEV apa roping when te os bus wt be rlese HOLD © nt eymtroneus in Esra ercronason shou be Orde Se Sst cat che ia rane Soreapond t OPE oh DETAILED DESCRIPTION “The 8088 CPU is internally organized into two processing Unis, These two units are the Bus Interface Uit IU) and the Exacuton Unit (EU). A block dlagram of tis organization is showa. on age t “The BU pertoms instruction fetch and queuing, operand fetch and stor, adress relocation, and basic bus conto. Tho EU Feooives operands and insructons tom the BIU and process- fs them on & 16 ALU. The EU accesses memory and Denphoral devices through requests to the BIU. The BU ‘deneretos physical addresses in mamory using the segment registers and offset values. “The BIU and EU usualy operate asynchronously. This permits the 8086 to overlap execution felch and execution. Up 10 6 instruction bya can be queued. The struction queue ects as ‘FIFO butler for instructions, trom which the EU extracts instruction bytes as requred, Memory Organization ‘Tne 8086 addresses up to 1 megabyte of mamory, The address spacd is organized as a hear aray, trom 00000 to [FFFFF in hexadecimal. Memory is subdivided into segments ‘of 64K bytes each. Thore ae 4 sogrents: code, stack, data {nd extra (usually employed as an ecra data sogmont). Each ‘segment thus contains information ofa similar ype. Selection ‘of destination segment is automaticaly performed using the ‘les in the table bolow. Tis segmentation makes memory tore easly relocetable and suppors a more stuctured programming ste Physica addresses in memery are generated by selecting the appropriate segment obtaining the segment "base adress tem the sogment register, sting the base aderess& digits to the let and nen adcing this basa to the “ose adress. For programming code, the offset adcress is obtsned from the Insttuction pointer. For operands, the cfet adores is cal. lated in several ways, depending upon information contained ‘nthe addressing made. Memory organization and address ‘Generation are shown in Figure 1a (Certain memory focaions are reserved for specite CPU operations. ‘These are shown in Figure tb. Addresses FEFFOH through FFFFFH are reserved for operations which include @ jump to the intial program loading routne. After RESET, te CPU wil always begin execution a location FFFFOH, where the jump must be located. ‘Aderosees 00000H through OOOFFH a79 reserved fo inerupt ‘operations. The service rovine of each of the 256 possible imervpt types ts signaled by a 4/0 pointer. The poiter ‘loments, must be stored in reserved momory addresses betore the interupts ae invoked, i -- | .- cer | Sa | a te | Figure ta. Memory Organization Figure 1b, Reserved Memory Locations: ory‘AMD Memory ]Seoment Register ener aes ey Segment Selection Fule Traore ‘CODE (C5) [Asai oe a pathing of Ravi is 4 Nick poshas and pons, anal raroyvlrocas roa To BP basa Toor = = a ean c iim eae ‘DATA (05) [OWE rons win arabe he Hack Be Gosizaion oa ag epealon oF oy Dama es) [Destnton of song Speen, whan Tay we Sey eolacld wag & RRO Minimum and Maximum Modes ‘Tho 8086 has. to systom conigurations, minimum and ‘maximum mode. The CPU has a strap pin, MN/MR, wich Gefines the system configurator. The situs of this strap pin Sefines the function of pin numbers 24 tough 31 ‘When MN/NR is strapped to GND, the 8096 operates in rmaxirum mode. The operations of pins 26 though 31 ae {adotined. in maximum modo, savera bus ting and contol functions are “oftloaded" to the 6288 bus controler, thus frooing up the CPU, The CPU communicates status informa: tion 10 the 8288 through pins Sq. S, and Sp, In maxmum ‘mode the 8088 can operate a multiprocessor system, using the LOCK signa! within a Mulibus format. When MN/NUR is sapped to Voo. the 8086 operates In minimum mode. The CPU sends bus contol signals ise trough pins 28 wough 31. Th is shown in tho Connection ‘Diagrams (in parentheses). Examples of miriam and max mum mode systems are shown i Figue 2 Figure 2a. Minimum Mode 8088 Typical Configuration 1410aio OA i aa eee ict re — = 3 me rows 2, Maxum Mode S08 Type! Contato ous operation PLE Characteristics rhe te anton sams eden nn srmony RET TS ea Tpemneccrpmtemmenanre cores Fett mews ee atnactereacee stir ais = Se enc ance tees tte Sete western cate many aes provided on memory and I/O modules. The bus can also be swat) [0 | 0 | insmevon Fetch demultiplexed at the processor with a single set of address 7 © Tt J Read Data trom Meenory eons pe renmgiem e aaetes (it bet wares van pt eee Each bus cycle consist of at aast four CLK cytes. Those are totorrd to a8 Ts, Tz, Tg and Ta (S00 Figure 5), The across is ‘sen fom the procossor during Ty. Data transler occurs onthe bus during Ts and Ty. Ts used for changing the direction of the bus Guing reed operations. In the evant that a "NOT READY” indication is given bythe eddressod device, "Wit States (Ty) a7 inserted betwoon Tg and Ta, Each inserted "Wat state is of the same duration as a CLK oye. "id ‘sates (T1) oF activ CLK cycles can occur between 8086 bus cycles. Tho processor Uses these cycles for intemal housokeoping. During Ty of ay bus cycle, the ALE (Address Latch Enable) ‘Sgnal is emitted (by ether the processor or the 8288 bus controle, dependieg on the MN/MK strap). At the wating fodge of tis pulse, a valid address and contain status informa: tion for the eyole may be latched. ‘satus bits 85, Bj, and Bar used, masimum mode, by tho bus controller to entity the typ of bus Wansaction according 10 the following table ‘Stas bis Sp though $7 are multolexed with high-ordor ‘address bs andthe BHE signal, and ae thorefora vabd during ‘Te ttrough Ta. S9 and Sq indicate which segment register (908 Instructon Sot descrption) was used for this bus cycle i forming the address, according to the fotowing table: se | Se (characteristics BLOM | 9 | Moris Data (oa segment oft] Sacx ‘Gro | coow oF Rone = 6 sa rolection of he PSW interupt enable bit, $5 = 0 and Sy is a sparo status bit MO Addressing £2026 1/0 operations can adcress up to 8 maximum of 64K 1/0 bye rogisters or 32K 1/0 word registers, The VO address ‘appears in the sare format as the memory adcress on bus Ties AygrAp. The address tnes Ato~Ayg are 60 In 1/0 ‘peratons. 70 instructions whieh us register OX as a pointer fave full aderess capably. Det 1/0 instructions drecty ‘addres one oF two of th 258 V/O byte locations in page Oot the /0 address space. /O ports are adéressed in he same manner as momory locations.Do —. — w]e | lw) st ups |. |w] on ae m Xe = Figure 3. Basic System Timing EXTERNAL INTERFACE Processor Reset and Initialization ‘Processor intalization or start up is socomplihed wit activa tion (HIGH) of the RESET pin. The 8086 RESET is requred to bbe HIGH for grestor than 4 CLK cycles. The 8086 wil terminate operations on the high going eago of RESET and wilromain dormant as log as RESET le HIGH, The low-going transtion of RESET viggers an inleral reset sequence for approximately 10 CLK cyces. Aftor this iniral the 6086 operates normaly beginning with the instucton in absolute locaton FFFFOH (soe Figure 1b). The details of his operation are explained inthe instruction Set description of tho MCS-28 Family User's Manual The RESET inputs internally synctvo- rized othe processor clock. Atintalzation the HIGH-t0-LOW tvansiion of RESET must occur no sooner than Sus afer power-up, 10 allow compete inialzaton of the 6086, [NMI may not be asserted prior to the 2nd CLK cyto following the ond of RESET, Interrupt Operations Interupt operations fall into two claseas: software ox hardware bated. The software iat intorupts and software as pects of haraware Intrupts are described inthe Insiucon Set description Hardware interupts are ether nonsmaskable oF maskabie. Interts transfor conto to a now program location, A 256- lement table containing adcross pointers to the interupt service program locations resides in absolute locations 0 through 3FFH (s00 Figure 1b), which are reserved for tis ‘purpose. Each element inthe tabio is 4 bytes In size and ‘corresponds to an interrupt "type." An interupting device supplies an 8b type number ding the slerupt acknow' ledge sequence, which is used to "vector" trough the ‘appropriate element to the new inlerupt service program toomion Non-Maskable Interrupt (NMI) ‘The processor provides a single non-masksble interrupt pin (NM which nas highor pronty than the maskableinleript fequest pin INTA).A typical use would be 0 achvale a power 12so OA ‘ahire routine, The NMI odge-tiggered on @ LOW10 HIGH ‘tension. The activation of ths pin causes a type 2 interup. (See Instcton Set description) TNMs roqied o havea duration i the HIGH stato ot greater than two CLK eyes, Bus not requred tobe synchronized 12 the clock Any high-going tranaiion of NMI latchod on-chip land wil bo aeniced at te end of the curent instruction or [between whole moves ofa bock-ype instruction, Worst case ‘response to NMI woul be to mulipy, vide, and variable sit Instuctions, There sno specication on tho occurrence ofthe tow-going edge: may occur belore, during, of ator the sorving of NMI. Another highgoing edge tiggers another fesponee # occurs ater the stat ofthe NMI procedzo. The ‘Sgnal must be free of logical spikes in genoral and be fee of bounces onthe low-going @d90 to ave triggering extraneous responses Maskable Interrupt (INTR) ‘The 06/10 provides a single intrrupt request input (INT) which ean be masked interaly by software wit the eseting ofthe inerupt enable FLAG status bt. The iniorupt request ‘Signal is lveltiggered. 1 Intemally synchvonized dung ‘ach clock cycle. on the high-going adge of CLK. To be ‘esponded to, INTA must be present (HIGH) during the clock Derod preceding the and ofthe current instruction or the end ot a whole move for a block-ype instuction, Dung the interpt response sequence, futher intorupts aro dsable. ‘The enabo bit reset as part of th response to any iferupt AONTR, NMI, software interupt. or single-step), although the FLAGS regiter, which s automaticaly pushed ono the stack. Feflocts the stato ofthe processor prot tothe Interrupt. Unt the old FLAGS rogeter i rastored, the arable bt willbe 2610 Unless spocticaly sat by an insvucton During the response sequence (Fgure 4), the processor cutee two suscessive (back o-back) interupt acknow!. ‘cdge cytes. The 8006 omits the LOK signal trom Ta ofthe fst bus cycle ntl Tz of the second, A local bus old” request wil not be honored unbl the end of tho second bus tyce, In the socond bus cycle, a byte is fetched from the ‘external ntruptsystom (e.g, 82594 PIC) which ides the ‘Source (ype) of Be Inter. This byte is maltpled by four land used as a ponte into the intoupt vector lookup table. An INTR signal ltt HIGH wil 69 contaualy responded to within the limfations of the enable bit and. sample period. The INTERRUPT RETURN instructon includes @ FLAGS pop. ‘which retume the stats of the original rapt enable bit ‘when it rostores the FLAGS. HALT When a software "HALT" instruction is executed, the proces: sor indicates that is entrng the "HALT" sate in one of two ways depending upon which mode is strapped. In minum Tredo, the processor leeues one ALE wan no qualiong bus Contol signal. In Maximum Mode, the processor issues fappropiate HALT status on 5281S, and the 6288 bus Contraler issues one ALE. The 8086 wil not leave the "HALT atte whon @ local bus "hol!" is entered whie in "HALT." In this ease, the procossor reissues tho HALT indeator, An interrupt request © RESET wit force the 8086 out of te "HALT" stata, Read/Modity/Write (Semaphore) Operation Via Lock’ ‘Tho COCR status information is provided by the processor nen drecty consecutive bus oycles are required during the ‘xecuton of an sastracton. Ths prowdes the processor wth the capebity of performing read/modity write operations on momory (va the Exchange Regier With Memory Instruction, for examole) wihout te possbiity of another system bus ‘maslorrecaing intewening memory oyles. This i usel in tmotiprocessorsystom configuraors © accomplish "test and ‘Set lock" operations. The LOCK signal i actvatod (forced LOW) in the clock cycle following the one in which the software "LOCK" profi instruction is docoded bythe EU. Its deactivated atthe end of the last bus cycie ofthe insructon folowing the "LOCK" prefix instruction. While LOCK i active, ‘a roquest on a RO/GT pn wil be racorded and then honored ft the end of the LOCK External Synchronization Via Test ‘As anatternatvo toto interrupts and general /O capabities, the 8086 provides 8 single softwarottable input known as tho TEST signal At any tie, the program may axocute & WATT instruction, at that time the TEST signal is inactive (HIGH), program execution becomes suspended while the processor waits for TEST to bacome activo. Ht must remain ete for at last § CLK cycies, The WAIT instructon i610. ‘executed repastedyy unt that time. This actviy doos not ‘consume bus cyoles. The processor remains in an ile state wre wating. Al 8086 crvers go to tWvoestalo OFF H bus HOLD’ is enero If iterupts are enabled, they may occur wie the processor ie wating, When this occurs, the proces: Sorfetches the WAIT intucton one extra me, processes the interrupt. and then refetehes and ro-oxecutos. the WAIT Instruction upon retuing fom the interupt Basic System Timing “Typical system configurations forthe processor operating in rmikmm mode and in maximum mode are shown i Figures 2a and 20, rospectvely. In minimum mode, the processor ‘omits bus contol signal na manner sia’ tothe 8085, In maximum mde, the processor eras coded status formation ‘wich the 6268 bus controler uses to ganerato MULTIBUS ‘Compatiio bus contol signal. Figure 9 ausratos the signal timing relationships. System Timing ~ Minimum System “The read cyclo begins in T; wih te assertion of the Adds Latch Enable (ALE) signal. Tho traling (ow-going) edge of tis ‘signal is used folate the addrss information, whch is vad fo the local bus at this ima, into the 6262/8283 latch. The [BRE and Ap signals address tho ow, hig or both bytes. From 7 t0 Ty ho M/TO signal indicat a momar or /0 operation, [A To the adcres fs removed fom tha local Bus ard the bus (9008 to argh impedance state. The road contol signals also fssoried at Tz The road (RD) signal causes tne adorossed ‘devs to enable Rs data bus deers to the local bus. Some time lator vabd data wil be avaiable on tho bus and the ‘addressed devion wit ve the READY line HIGH. When the Drocessor rotumns the read signal 10 @ HIGH lovel, the ‘addressed dovce veil again stato ts bus divers. It & transceiver (8286/8287) ls required to butter the 8086 local bus, sgnais OT/F and DEN are provided by the 8026 [A wite cycle ato bogins wih the assorton of ALE and the ‘mission ofthe address. The M/IO signa is again assertod to Incite a memory 1/0 wie operation. Inthe Ta immadiate- Iy fotowng the address emission, the processor orsts the ata fo be writen into the adcressed locaton. Ths d Fomains vakd ntl th mda oT Dring To, T3, and Ty, the Drocessor asserts tho wito contol signal The wie (WR) ‘Signal becomes actvo atthe Bogining of Te as opposed to the read which is delayed somewhat to Ta to provide timo for the bus to fat. ‘The BRE and Ap signals aroused to select he proper byte(s) ofthe momory/1O word tobe read or wetan according 1 he following table 8086 143(Characteriticn Whole word Upper byte Kom/te od adress Lower byte tom/to even address None. =lel-lele VO pons are addressed in the same manner as memory location. Even adoressed byte are tansirred on the O7-Dp bus lines and odd addressed bytes on Ds5-Ds. ‘The basic stlerence between the intent acknowledge cycle and a read cycle is thatthe inlorupt ackrowiedge signal ARTA) is asserted in place of the read (RD) slgnal and the | address bus i flted. (See Figure 6) Inthe second of two successive INTA cycles, a bya of information i read rom bus oes Dy-Dp 8 supplied by the intorupt system loge io. 82504 Prony Interpt Controlen. This byl ientiies the s0ur08 (ype) ofthe inerupt tis mult by fou ard used |88 4 pointer ino a interupt vector lookup able, 9 described carter. ‘Bus Timing —Medium Size Systems. For medium size systoms, tho MN/RIR pin is connected 1 Vas, | and te 8288 Bus Controle added othe system aa well ‘an 8282/8260 latch for latching the ayatom adorose and a 8286/6287 transcover to alow for bus loading greater than ‘he 6086 ' capable of handing. Signals ALE, DEN, and OT/F ‘are generated by the 8268 instead ofthe processor in tis configuration, afthough their ting remains rolabvly the sama. Tho 8086 statis Sa, 81, and So) provide ype-ot cycle information and become 8286 inputs. Ths bus cyie informa tion speci read (code, data. or 1/0), wrte (Sata 1/0), interupt ackrowiedge, or software halt. The 8288 thu esues ontot signals spectying memory read or wrt, 1/0 read of wrt, oF iforupt acknowledge. The 8288 proves two types of write stobes, normal and advanced, to be. applied as required. The normal wite stiobes have data vad at the leading edge of write. The advanced wito srobes have the ‘The pointer into the inferugt vector table, whichis passed ‘uring the second INTA cycle, can derive trom an 8250 located on ether he local us o the system bus. H the mastor {82594 Prot Interupt Controle Is postioned on tha local bus, a TTL gato is requred to sable tho 6265/8267 \rantceiver whon reading trom tho master 8259A ding the intomupt acknowledge sequence and software "pol rn an a \ =e Figure 4. Interrupt Acknowledge Sequence wrooears AE nee ‘orcoseaa Figure 5. 8088 Register Model 14awo A ABSOLUTE MAXIMUM RATINGS OPERATING RANGES Storage Temperance €5 10 +150 Commo (6) Devices ‘Ambient Temperature Under Bis. 30706 Temperate (Ta ow 470% Vatage on any Pn Sippy Votage ec) wih Respect o Ground “110 +70 Ses ee Power Dissptation zw one, 60862 vs Indust () Devos ‘Stesses above tose ited under ABSOLUTE MAXIMUM - [RATINGS may cause paranont dovce faire Functnanty —— Tomearahre (Ta). 1010 +056 ator above these hfs not mplod Exposure lo abso vply Voage (Vcc) ae ee ee cae ee ee ee 00s 80862. ove 5% operating ranges define those Sots between which the tunetoraity ofthe device is guaranteed. | DC CHARACTERISTICS over COMMERCIAL operating range Parameters Deserption Test Conations [win | Mex | Unite r" Te Vo =o [roa Ti in ah Von 20 | verros |v. WoL Supt tow Vote Tass 38 |v = {bow Noe TGR [READY Setup Tim rs @ = nm TEHAVE [READE WoT 88 2 = 7s amc | RAD mare OX “2 10 7 ea note 7 Fone] RR TEST Saran we . 5 w Thon (ee noe 2 e ¢ | on] eee om Fon 081020 2 = =[ = (Craw {Crist ——T rest Fa Tn acer cog [Fon Bo wow = 7 t= Neuf Sa BAA wow or rrene ony 2 Sin queer 1 tyrone glo 1 gain scons pet CL 5. dopae ony to 13 mn oe eo To) 006 148Dw SWITCHING CHARACTERISTICS over COMMERCIAL operating range (continued) TIMING RESPONSES 2008 2086-2 ‘2006-1 Tost Parameters Deseripton Conditions win [aax| win [max min [stax] Unies aay ‘ins Vi Daly vo [wo] Te] 0] =] = To Aesres Hold Tre 10 70 0 = Ton ‘Aéstos Foe! Ooty So A "Toa TALE wih Teucn-2 | | Taoe- | [Weer oe 7) TALE Aesve Dey o = a [oe oH (AE teeta co = aa ‘sree Ho Te Tuk fas rox | [rowi-10] | toHa-10 5 Teiov ‘Dats vate One [we] ee] ee To Deus Held Tine 7 7 0 ne THHOX ‘Dans Hols Tine Afar WA Teon=so | | Teton-we | Fearne oy TEVETV | Gort Acve Daley 7 so [wo] ow] 0] | ve ToHGTY | tat hae ey @ | 2 2000 oF vo [wo [10 ee [10a ve TeVER "| Conor nace Delay 7 woo] 19 | 10 90 fre TAL ‘Ado Feat © eos Seeaa o ° Ai - READ ace Simca C= 00 GAC TD seve Delay woe | 0 ee | 0 9 TAR TD sci Ooty 10 [190] 10] we | 10] fre TRHAY Ti mechs io Het Touc. 4s Tac -40 ‘ToLcL-35 5 TEA [HDA vate Dea 7 [es eo Tee | 0 oe TLR 0 wa [Foon prensa m= “wow | — WH wor zrcie.-<0 | —farexc-«0] | 0c. a6 ne TAAL odes Vaid ALE Law Touor=00 | | rexr-«o |} roven-as me TOL Gaal Fie Tine Fon 980 20 = = [ne TORO. ‘Supa Fal Tre From 2070 08-V 2 2 zie ‘SWITCHING TEST INPUT/OUTPUT WAVEFORM SWITCHING TEST LOAD CIRCUIT pevice {S—-Test PoNTS—= 15 aos ows. reer hee ope wrooeae: roo0es69 [AC Testing inputs aro driven at 24 V for a logic "1" and ©) includes fg capactance 045 V for a logic "0." Timing measurements are made at 15 V for both a logic “1” and "0."SWITCHING CHARACTERISTICS over COMMERCIAL operating range (continued) MAX MODE SYSTEM (USING 8288 BUS CONTROLLER) TIMING REQUIREMENTS. or Descrot 3 a — Unte rameters fon [—"* se oe Conaions [win [ax] win [mex] man [bax Taek os ree 0 | so. | ves —f 500 | eo 50 TaGe [ak toe Tie : a o = me FoRGL | GH Tire 3 a = mI TMG | CUE Ros Tere Fontowssv[ we 7 eects | Gx Fa Tore From 351 10V 70 we 0 | Tovct | Ons Setup Tae % = z mo sniven | RDY Setee Tie io Bam Se - - river | on note 1° Fie] ROY Ho Tove aio ak > a = Tou (Boe Note 9 TAVRGH | READY Sone Tne ne 8H we = = TGR | READE Ha Ti no 686 % 2. oe Tarte | READY hactre 1o COK Te 7 (Boe note _ won | (wre nate TEST » 6 % ms {Sor hate 2 Taven —[ROVEY sere Tae = = 7 = ToRGK [RS roa Tne ne 2 = 2 om Tu int Rie Tove Fam 08% 20¥ = = »| | eg x = Tat Fa Te Fem 2010 08 ¥ 2 @ ef Twos 1 Salat €2048 oF 6068 arom for felronce ory 2 Setuorequremant for asyctronou agra ony 1 quae recognition at reat CLK. 5. Aap oly wo T3 and wa tas 4 papi ony 1 12 Sate (Bs to T3) 17Daw SWITCHING CHARACTERISTICS over COMMERCIAL and INDUSTRIAL ranges (continued) TIMING RESPONSES Paar Description Lend a ee sere at meters ita Conamione min [wax] tin [tex] man | max| eae Ae Dat we jel o fs; «© [alo rem | een 1 m | Saran naive Dar we [=] wo [wl] « [ala Tem | Geo Not ee v0 e elo ToHSY | Sine Active Detny_ |] wee] oe es Tosh | Sine iacive ot no [00 | 19 [0 [vo [ss |e Town | Aaeess vata Ooty 1 wo 10 Po | 050 oe TouAK | Aas Hold Tov 0 10 0 ve Toinz | Adare Fost Doi Feu ef Tear | we] | Sin Yai fo AE High 16 15 | Tew | (eee note x ‘Sia Vase 12 ME 6 8 sf revue | ioe not 1) ron | okies) a 15 lo x GOK on CE Fh a 16 sf rower | (Soe Nae Ton | Ae heey 40.10 oF 6 15 |= 7 {Seo howe i ar oo ce anes Oa ‘Gages ty ation roe. | MEE kactie (2S saxlous 5 15 | TeLoy | Oat Vand Dole we [re] ee eo oe ToHOX | Oat Hot Toe 10 0 8 7 Tovy) GBreo Ave Dalay * > fel > [«l= {Seo Now 1) ee eed 10 wo fs] oo [ol = {Soo Not Torn | FB dative Oy Toes | eee | 0 me TURK | RD rcv Doty fo [sof [oo | 0 oo | ne rnay | Roache fo Next ony Tow —0 you. -26 | ‘sree heb Towra | Breeton Const Act = 2 ul Bet Gow Not 1 J Tawar | Breeton Cont asive ~ a xl Baty Gow Now 1 : Tere | GT Aawe One ope [sf oe TeLGH | GT tact Dou ope oof es oe Rn | FO wa wea] [arenes] | recat ne TOLOH | Owe Rss Tne Fon Gee av = = [oe ToHOL | Oso Fal Tne Fron 20 08-V 2 bre tee: 1. Salat BZEAA or 8200 shown fo lence cy | 2. Setup requremest fr anyon spr ony To gurante recopiton at nt CLK 4. hop oy to 79 and wat states 4 popin ony to T2 tate (ne te 3).ABSOLUTE MAXIMUM RATINGS ‘Storage Temperature 65 10 + 150°C Ambont Temporature Under Bias 8 t 70°C Voltage on any Pin wit Respect to Ground nt to +70 omer Dssiptation 250 ‘Stresses above those listed under ABSOLUTE MAXIMUM RATINGS may cause pormanon! dovcefalure. Functionality at oF above those mts fe not imped. Exposure 10 absolute ‘maximum ratngs tor extended parods may attect device ‘ebay. DC CHARACTERISTICS over MILITARY operating range (lor APL Products, Group A, Subgroups 1, 2. 9 {are tested unless otherwise noted) OPERATING RANGES Maitary (M) Devices “Temperature (Te) 50 +1250 Sopply Volage (ec) BV 10% Operating ranges define those limits between which the funesonalty of the device 8 guaranteed. Paramoter Parameter ] T ‘Symbol Deverption Test conditions | win | tawx_| vot vet Tapa TOW Waage Togrin kim} wos [se Wer Trou HGH Votoge Voo= Min 8 Wx 20 [Won vam ow ve a T ca You ‘sat LOW Votuae wa Vou ‘at HGH vonage pe a v Tee Tower Spy Carer Wei 1 Tg= 25° Vega a | “ae ost Laaage Carer Wetiacy |e | | im hott ‘htt Loakage Carer Wrvacwv| | | om wat Geek pt (OW Voge Yoo" Fas. | =o} vee JV Yor Geek np HGH Vota Woon & as 39 |v tv ian ceeareng ope Eo OF Fo ee cee wo |e To He Copacarca f V0 Bir Hoe ADs ROVE) eat = 1419Fo 9, 10, 11 are tested unless otherwise noted) MINIMUM COMPLEXITY SYSTEM TIMING REQUIREMENTS SWITCHING CHARACTERISTICS over MILITARY operating range (or APL Products, Group A, Subgroups ‘Sop feurement lc asyrcrcns sgn ony furantee recogrton at next CLK, iy Ty and wat sas omy 12 Sate (moo 13. a by he erayre 41 oe Hina Be mtn ioe Se mine eos ees Va SRR Test 2006 06-2 Parameter Conditions Symbol (ete 6) min [Max | min [Max | unit TeLct | LK Cio Paros ie 1 Ea Teich | GX LOW Tere 1a @ =| Tene. [Gk GH Tore oy “ ro TORO [CK Ase Te ia 5) Fon 10350 7 a Touaeut [ae Fa Tew ote 5) Fon 3516 10 9 10 | ne Tovct_ | Onn = Setup Tene = # 7s Teuox | an Hoi Tee 7 “8 7s TRIVEL | ROY Sev Tire io G2E4A (aes 7 8A) 3 35 ry TouREK | ROY Hols Time ot 254A (vows 1 2 ¢ ° = TRYHGH | READY Sohp Toe ms 8006 = Tour | READY Ho Tie ro 6068 7 TaYLcL [READY acne fo CUE ote s THYGH | HOLD Satin Tine = ea rs TT Tip Rise Tove face CUR) (Noto 6) | From Bw 20V ¥ wre “Ta Tet Fal Teo (sep! Ld ete 6 Fron 200 08 2 2 [we Noles 1 Spal a 82648 ang B2Hb shown fr rterance oni +20 8086awo &A SWITCHING CHARACTERISTICS over MILITARY oporating range (continued) ‘TIMING RESPONSES: Tost 2005 2006-2 | Parameter Parameter Conditions. ‘Symbol Description (ote 6), win. | Max | min. | max | uni Tou | asror va Dey [| wo | | | re TCX | Aare Hot Tie (sos 7B) 7. 0 7 ee vo] eae TToRL [ALE War the 10 oe = ne TCL [ALE Ace Dey oto) fe o wom TOL | ALE waco Deir Wet 8 [ss [ws TAC | Address Hol Tine © ALE facie Wot 7) at a oe T.DY | Date Vai Oia (ts 8) fo ef [oe TGROX | Oat Hots Tene ot 10) 10 0 ne “WOK | Bain Fld Tine Ae WR Oe) oy Ey oe TVCTV | Coot Asive Ova 1 ow 8 0 50 | oe TEN] Conte Ace Doty 2 (ie 8 Perr 0 vo [ oo] TEVETK | Conver racine Dewy (2 8) Sareea of TATA | ndoress Fett READ Acie (6) 125006 Sera oes) [0 3 ‘ Teta | A Ace Deiy ote 8) so[ es | 0 ee fre Tota | AB inastve Onoy (oe 8) ce a “TanAV | FE actve 10 hon Assess Ave (ste 10) 15 cs ve TCU:AT | HDA Vai Oatay (te 8) 1 A TLR | FO We ow 1 mes EI =| TTwEW [WH wt ow 1 7 300 200 re TAVAL | Aderovs vats ALE LOW Ooi 8) = 28 re TOLOW | Ouput Rise Tne (le 9) Fon ose a0v = a Toro. | Ove Fat Teno ole 3) Fron 208 08¥ 2 2 [es Noles: 1 Sgnal at €204A ane 8286 shown Sr sterance ony. 2. Setup recuremert for smncrraous si ny 10 guaran recogion a nxt CLK 5 Apples sry 1019 ard a see 1 Afolos aay fo 12 Stef moo 19 Neon pce Cred by he Tee Jet tte 2, Moonen Spee tast at Voc Mae (55 Vey ira ee re tn HV 9096 421Dw MAX MODE SYSTEM (USING 6: SWITCHING CHARACTERISTICS over Mi ITARY operating range (continued) BUS CONTROLLER) TIMING REQUIREMENTS Test e008 006-2 Parameter Conditions Description (Note 6) ax. [ie [Max | unit TIX Gye Farad Wolo 1 ‘o_[ tas [500 | ow ‘GUE Rise Te fle 5 Fon 10 35V 7 oe ‘GLK Fat Tine Not 5) From 35 18V 0 [oe Outs Soup Tine % e ny I ‘Date ot Tse @ 10. = ROY Setup Tene io SERA (ows 1A 35 25 m= TADY Hols Timp io €260A tots 7 & 2) @ ° = READY Seup Tne mo 89 we co s READY Inactive to CUE te =e =8 me ‘ep Tie fr Rocognien (NTR. Nu, ET 5 ms = ino 2) Teor ROVGT Seip Tene - = a TOG FE Hit Tore S055 @. 2 oe Tar Toot Fis Tie (Excoot COR Note Fonda 20 om Tr Tepu Fal Tine Secoot CLM (Note 9 Fon 206 08 2 [om Notes: 1 Spal 9264A and 8289 shown fo cterence ony ‘Soup rourement fx asyncences sg! ony to gurete reagan at next CLK ‘opine ay fo Tard ar ses ‘Spins oy fo 2 sn 8 wt 9) eu ay ect we Sonata by We Tey Jo tate Tete St VGE Ma 3 0) ‘en sosatn fr TE 7 f f F 5; 3 422 8086aw OA SWITCHING CHARACTERISTICS over MILITARY operating range (continued) TIMING RESPONSES ] Test nee ‘Parameter | Parameter Conditions: — Sybot Sener hoe) | wan | wax | wn | Max | Unt | Teun | Coad Ace Onay ae a “ew | corms race Day 1 woes eas) RVG | READY Acie Sun Pave (2 i ee Tee | Sata Ave Ooty eter #8) a eis | Sat Face Oo eee] TEA Aes Vaud Doty [oe —[ eo TAK hres Ho Tre 7 7 2 eae arse Fost Bai jo [ee svc | Sia Ve YALE WOH eT 7s [a TSWiGH [Satur Va WE GH Be 1 7 [oe Teun [Gk Cow ALE Vaid ot a 7s TENG | GLOW io EE WOH Oe a cn Tox | ALE ice Doty (om 3) See 1 =f Tec | MCE iacive Oway Woie 1) | 8008 etna! tne 6 1s | eis | ona vad Oty eo TEiOK | bat Tee 72 2 oI Temi oe a Oy SS T ef ep TER | Gove rave Gna pope ee AER | nae Fo Ro Ae @ ° TexRL | ae Day wee 09 TEER FE rare a a Tay | FO eae et Aa ae 78 a oI TOHOTL ‘Drection Control Active Delay (Note 1) 0 Ea rm TE=OTH | DreconCova acne a Ba 1 2% 2 TELGi [OF ae Say (tw 8 a YL] GT act Oty ie ore [2 Tuer [RO wi cs EA v2 YOLOH | a ies Te Fanon eID 2 a Toren [op Fat Tene Fon 3016 08 7% te. Notes 4 Sila 2004 on 9288 aan or rlrnce Miimum epee tested at Voc Max. (55 ¥) ont 3 0 oa Seas Ee SS came mie GRIN 128Daw SWITCHING WAVEFORMSaw &N — SWITCHING WAVEFORMS (continued) MINIMUM MODE - ¥ = # Notes: 1. Al signals switch between Voy and Vox unless otherwise specified 2. ADY is sampled near the end of Ta, Ta, Tw 10 determine Tw machines states are to be snsoned, 3, Two INTA cyclas run backto-back. The 6086 LOCAL ADDA/DATA BUS is floating during both INTA cycles. Contol signals are shown for second INTA cycle. 4. Signals at 82644 aro shown for reference only 5. Al timing measurements are made at 1.5 V unless otherwise noted. 8006 125Dao ‘SWITCHING WAVEFORMS (continued)ao OA SWITCHING WAVEFORMS (continued) MAXIMUM MODE (continued) Notes: 1. All signals switch betweon Von and Vou unless otherwise speciiog 2. RDY is sampled near the ond of Tg, Ta. Tw to determine if Tw machines states ere to bo insert, 2, Cascade address & vald betwoon fest and second INTA cycle. 4 Two INTA cycles run becko-beck. The 8086 LOCAL ADDR/DATA BUS ie floating dung both INTA cycles. Contot for pointr adeross is shown for second INTA cyte 5. Signals at 8204A or 8288 aro shown for reference ony. {6 The issuance of the 8268 command and coro! sgnale (UI, MWTC, ARWC, TORC, TOW, ‘IONE, INTA and DEN) lags the active tigh 8288 CEN. 7. Ai ining measurements aro mada at 1.5 V unless otherwise noted 8. Stas inactive in stato just prot 10 4Daw SWITCHING WAVEFORMS (continued) BUS LOCK SIGNAL TIMING ASYNCHRONOUS SIGNAL RECOGNITION cere evox cee :|~ (MAXIMUM MODE ONLY) Note RESET TIMING — = Vt a rma Wro08s00 REQUEST/GRANT SEQUENCE TIMING (MAXIMUM MODE ONLY) AEA DOA “7 ES a ee wevosri0 Note: The Coprocessor may not dive the buses outside the region shown without raking contention, HOLD/HOLD ACKNOWLEDGE TIMING (MINIMUM MODE ONLY) 1.28DATA TRANSFER Regtermenor to Irom reier mediate to regitrmemary Immediate to repetr Memery to ecumsator Acoust 16 memory egitewamary 1 segment regster Segment agate 1 rgsier/memen) egitermamery gate Sogrent rege PoP = Pop: Regtarinameny eater ‘Segment register HoHa= Exchange: Regate/mamecy wh reper gist wt accuser (We opt Home Fed pot vn prt UT = ut: Fd port ara por XLAT = Tanna bp 0 AL LEA Lond EA to reper LDS - Loud pointer 10 0S LES = Lond potter t ES LANE = Lond Ai we tags SANE = Stove A eo ags PUSH = Pash tgs POPE = Pop tage 8086/2088 INSTRUCTION SET SUMMARY rasesaie resaazte resaaese ToeoT TOO | malo mgm : Tee | med Oe ToedoT Te or Toot ow ‘ ‘ : (teetee[ et) Citrecre] pon } Tevoiee| wodearm Tootroe Tooter ne Teseazr0 1209Divo INSTRUCTION SET SUMMARY (continued) ARITHMETIC A00= ade 7osea21e reseaz10 7eseaas0 reseszi0 Imm t reget /memery TooCo0sw] maloooum | am | wiv teweor ‘ADC = At wth ae: fe/amen i sw eter Tees Ta) Inet may S01 om [ana roe mnt (eosreree] ae [amt] even er Bee] AAA ASCH aut for acd Goa] DAA Decimal aus for ad (eoreoi} sue= seat payne wt oe ee Sa) | sansa fon nec ie ae a evra ag er (me to preart Tee ee ae ore fom mdr —— aT eT ‘Nea nang sgn Tiitettw] msotiae ] carsomeen Aepennonry wi gee oe ere] Pajero Immediate wih regstrnemony (jeee0ew] motive | om | aetew=or ] ae Samaiee rec 18 A808 wat wont (OAS Cosma edu fr aubeat [eer] tw. sate cnn (UL ineger muna (sora: (ot 1901 eat may Torsise [sess Tors] 0 Oe na 10 in on et Cope Pai] sno ash st one a comer oye wr Co Cova wrt a wt 190 008io OA INSTRUCTION SET SUMMARY (continued) Loaic SHL/SAL Si operetta ‘Sem Sim open ht SAR Si etre Hoh ROL Rota lt ROR oat ron RCL Rotate tough cary ag tt RR Rotate ough cay Gh Req/menary an reget 10 etter rent orogeny Inet to acoumustor ‘TEST = And function Yo flaps, no amt: Pegster/memory and register meade cata and rogitor memory ono Regimamery and rpatr te other immed to reget mamery HOR #exctnve or eg/meneny an rg to ter ‘STRING MANIPULATION: REP epot MOVs = Move nye wore (cus = Compare arwort {SCAS = Scan bord {L008 = Lona bye 1 ALIAX [5708 = Sor btn Hom ALIA (eiooee | meteor | TroTOo ew | met oI | Tore eee Lear ie (Crereovw | maoeom } (eater Peer] aaa (ivooovoe | meatoomm | aw waded aaootee | ame Tate ae a] Toioieoe[ aa | ates naira Ra a) mort ove | ae [ae tent) Daitoiow ae outa Gear) 181AMO. ‘CONTROL TRANSFER CALL = can Inset tne sepent Dect nrsogrent Inaret iteragmn MP = Uncondons! ane: rect wine sogman shod indroct wink segment Ines arose RET= Return tom CALL: Winn sognent wine 9 ang inn to SP ntarsegment Inersegrent acing made 10 SP JENE= hme on eai/er0 AUANGE = Jump on lea/nh rir oF oun E/ING = Juno on lot equine pte BE/INA = Jump on blow o equine stove JP1SPE = hare on pntyipaty ven 40 = Jp on ovrtow J8= sump on 99 IL/JOE = Juno on net lst/rroFenut NLE/IG = Jump on et 88 of eal rater | aMa/JAE = taro on not blow/above oF cust INBE/JA = Jump on el baow oF eal sove INO = sme 09 at ovatow NS = te on rot Sgn LOOP = Loop Cx nes LOCPE/LOOPE = Loop wee serfecia LOOPNZ/LOOPME = Loop wnto ot 260/equ 202 = ue 09 OF 290 INSTRUCTION SET SUMMARY (continued) Tesaagre resesz10 resesate os | i : 4 Taeeete é 3 e ) | (rose, a] Gren Ditiooor a Se Tiieoott a. ‘| 192INSTRUCTION SET SUMMARY (continued) CONTROL TRANSFER (Cont'd) In = ote resenase reseaszie reseszi0 ressazt0 Type speciied ITO = tempt on everton Tees ET = rt rate Teer PROCESSOR CONTROL, (2 = Complement cary sto~set com CLD = Cow docton STD Set secon (CU= wr intent ‘s11=Setnerupt lal A SC = Proceso: Extension Escape LOOK = Bs ack orate Footnotes: AL =p accomsatoy I tim =i then EA(BX) +P DIG Totows 2nd be of meteor feo dete required) ca! r= 00 and tm = 110 tan EA pig pow ifs 01 ten 16 bts of irate aa form te operand ERSTE BS w Since Site Spree om we AE Spee eat =: vet ten “count nL) SEGMENT OVERRIDE PREF eG is eagped exergy ie sean eno) ‘eament ooo Ax 0 AL es oor oor ae Sie ox oo 1 $8 on ar i Bt ios io Br for Se Instone wich retrace te fag raga: Hes a8 16 objet ef aybl FLAGS toro FLAGS = 000108 OFT SA ZF) X(AF)CPPICA) 133