A 320×240 I-ToF CMOS Image Sensor with 2-Tap

5.6μm Pixel and Mismatch-Nonlinearity

Suppression
Youze Xin1, Bing Zhang1,2, Congzhen Hu1, Li Dong1, Dan Li1, Yunsong Wang2, Lijun Zhang2, Shuyu Lei2 and Li Geng1
1
School of Microelectronics, Xi’an Jiaotong University, Xi’an, 710049, China
2
ABAX Sensing Electronic Technology, Ningbo, China
Email: gengli@xjtu.edu.cn, bing_zhang1982@xjtu.edu.cn
2021 IEEE International Symposium on Circuits and Systems (ISCAS) | 978-1-7281-9201-7/20/$31.00 ©2021 IEEE | DOI: 10.1109/ISCAS51556.2021.9401247

Abstract—This paper presents a 320×240 indirect time of

flight (I-ToF) image sensor with 5.6μm×5.6μm 2-Tap pixel in
110nm process. The readout channel offset cancellation and
nonlinearity suppression techniques are proposed to achieve
high-precision detection. The measured relative precision is 1%
at a 5m target distance and non-linearity is below 1.02%. The
chip also integrates LVDS and I2C interface for data
transmission and Laser control. This work effectively improved
the ranging accuracy with a simple method.

Keywords—Time of flight, nonlinearity suppression, offset

cancellation, 3D camera.

I. INTRODUCTION
With the increasing demands of machine vision, motion
sensing games, and gesture recognition, the research on high-
precision 3D sensors has become more and more important
and urgent. To enhance the detection accuracy of indirect time
of flight (I-ToF) sensors, some works have been done. The
relationship between the measurement accuracy and the noise
and modulation contrast has been proposed in [1]. The ranging
accuracy is increased by decreasing the system circuit noise
and improving the modulation contrast. Similarly, a 4-tap
pixel structure could eliminate the kTC noise through the
correlated double sample (CDS) technique to improve the
ranging accuracy [2][3].
Fig. 1. 2-TAP pixel schematic and operating principle with proposed toggle
Furthermore, the offset and nonlinearity of readout circuit technique in I-ToF.
also have a crucial impact on ranging accuracy. In
conventional design, algorithm module is used to calibrate A. Readout channel offset Cancellation Technique
these negative effects in post data processing. However, the Fig. 1 shows schematic of a 2-TAP pixel and a timing
algorithm calibration increases the complexity of the system diagram for the 4-phase sampling, which could eliminate the
and reduce the frame rate of I-ToF sensor. In this work, we effect of background light. As shown in frame 1 in Fig. 1, the
proposed a technique without algorithm to increase the 0° and 90° samplings are readout by A, and the 180° and 270°
ranging accuracy influenced by offset and nonlinearity. Using samplings are readout by B. The measured distance L can be
this technique, the measured relative precision is 1% at a 5m written in (1), where c is the speed of light, fmod is the
target distance and non-linearity is below 1.02%. modulation frequency, V0°~V270° are the different phase
output voltages. However, because of SF mismatch, SS-ADC
II. CIRCUIT DESIGN offset and transmission line delay. A and B have different
In the I-ToF pixel, the charges stored in the floating channel offset errors which causes the measurement distance
diffusion (FD) are transmitted to the ADC by source follow error, which can be illustrated by α’ in (2), where VosA and
(SF). Because of the non-linearity and mismatch of SF and FD VosB are the readout channel offset. In order to solve this
capacitor, respectively. The output voltage of different readout problem, A and B are toggled in frame 2. In this frame, the
channel generate large errors, which reduce the ranging cα V90° -V270°
accuracy of I-ToF. In order to solve these issues, in this work, L= , α= at ideal case 1
we propose a toggle technique to cancel different readout 4fmod V0° -V180° + V90° -V270°
channel offset and a new SS-ADC structure to reduce the
V90° +VosA - V270° +VosB
influence of FD capacitor mismatch and SF nonlinearity, α' = (2)
respectively. V0° +VosA - V180° +VosB + V90° +VosA - V270° +VosB

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 Fig. 2. FD Capacitor mismatch and SF nonlinearity suppression ramp with
timing diagram and floor planning.

0° and 90° samplings are readout by B, while the 180° and

270° samplings are readout by A. When the distance is
calculated, the signals of 0°, 90°, 180° and 270° are sampled
by A and B, respectively. Due to the proposed toggle
technique, the coefficient can be written as (3). As result, the
error caused by the readout channel offset is eliminated. Also,
the toggle mode does not reduce the frame rate.
V90° +VosA - V270° +VosB
α''=
V0° +VosA - V180° +VosB + V90° +VosA - V270° +VosB
V90° -V270°
= =α (3)
V0° -V180° + V90° -V270°
B. FD Capacitor Mismatch and SF Non-linearity
Suppression Technique
The reflected signal charges are stored in the FD after
phase sampling, and then are transmitted to the SS-ADC
through the SFs. Due to the body effect of the SFs, the outputs
of SFs will produce a nonlinear error. Normally this problem
can be solved by connecting the SF substrate to the source to
suppress the body effect with deep n-well structure. However, Fig. 3. Auto-zero Comparator structure.
it increases the size of the SF and decreases the pixel fill
factor. In addition, due to process deviations, the FD current module is connected to the A point of all 240 dummy
capacitors of different pixels will have deviations. These pixel, so that the 240 FD capacitor deviations is averaged.
deviations will cause the same charge to produce different Compared with conventional Ramp, the ranging RMS noise
voltages. When the distance measured in the same plane, there is caused by capacitor mismatch will be reduced by square
is RMS noise in depth image. root of 240 in this structure. Moreover, the Vramp is produced
by the voltage of A point through SFs, so that the Vramp non-
To avoid these issues, this work proposes a new design of linearity is similar to the pixel output. Fig. 3 shows the auto-
the SS-ADC structure, which can eliminate the FD capacitor zero comparator which can cancel the offset of preamplifier
mismatch and SF non-linearity. As shown in Fig. 2, the SS- and non-linearity of comparator.
ADC Ramp consists of three modules, voltage-controlled
current source circuit, self-calibration circuit and dummy III. MEASUREMENT RESULTS
pixel array. The self-calibration module calibrates the output The designed 320×240 I-ToF image sensor was fabricated
range of Ramp from 3.3V to VL with Vfb after the end of each in 110nm 1P6M process. Fig. 4 shows the die micrograph of
quantization period. The output of the voltage-controlled the proposed TOF imaging chip. The chip size is 3.5×3.3mm2

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 demonstrated using a light source of 940nm IR Laser with the
modulation frequency from 500KHz-20MHz to achieve a
frame rate of 30 frames/s. Fig. 7(b) shows the captured 3D
image of three plaster model placed at a distance from 0.3m-
1m.

Fig. 4. Micrograph of the TOF imaging chip.

(a)

(a)

(b)
Fig. 6. (a) Measured distance and accuracy changing with the real distance.
(b) The RMS noise versus real distance.

(b)
Fig. 5. Reflection time delay versus different phase sampling voltage at the
modulation frequency of 20MHz (a) without toggle (b) with toggle.

including the I/O pads. The pixel size is 5.6×5.6μm2 with a fill
factor 45%. The chip also integrates LVDS with 1.2Gbps
throughput and I2C interface for data transmission and Laser
control. The chip power consumption is 200mW.
Fig. 5 shows reflection time delay versus different 4 phase
sampling voltage at the modulation frequency of 20MHz.
Without toggle mode as shown in Fig. 5(a), the 0° and 90° (a)
samplings are readout by B channel, while the 180° and 270°
samplings are readout by A channel. Due to SF mismatch, SS-
ADC offset and transmission line delay, the output voltage of
A channel and B channel have a 70mV offset. Fig. 5(b) shows
the offset of different channel was canceled by toggle mode.
Fig. 6(a) shows the measured distances and accuracy
versus the actual depth ranging from 0.12m to 5m. The
maximum non-linearity, defined as the maximum accuracy
error of each data point normalized to its actual distance, is
1.02 % measured from 0.12m to 5m. Fig. 6(b) shows the
relative precision, defined as the RMS error normalized to the
maximum distance, is 1% at 5m.
(b)
The sensor can capture 2D and 3D images. Fig. 7(a) shows
the captured 2D image of three plaster model placed at a Fig. 7. (a) The measured gray scale image in 2D mode. (b) The measured
depth image in 3D mode.
distance from 0.3m-1m. The depth 3D imaging operation is

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 TABLE I.
Table I summarizes the performance comparison of the I-
TOF sensors. In I-TOF sensor, this work shows the smallest
pixel size and the lowest chip power consumption. The non-
linearity and relative precision are competitive to other
sensors with 30fps.
IV. CONCLUSIONS
A 320x240 I-ToF image sensor with 5.6μm pixel pitch has
been implemented. The proposed TOF sensor with mismatch
and non-linearity suppression technique has demonstrated a
competitive depth performance. The detectable distance range
is 0.12~5m with a non-linearity of 1.02% and the achieved
relative precision is 1% at 5m. Furthermore, the chip power
consumption is only 200mW.
ACKNOWLEDGMENT
This work was supported by the National Natural Science
Foundation of China under Grant of 61874085 and by the
Postdoctoral Research Funding Project of Shanxi Province
under Grant of 2018-140.
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COMPARISON WITH THE STATE-OF-THE-ART
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