A High Performance Linear Current Mode

Image Sensor
Chih-Cheng Hsieh1 Wei-Yu Chen2 and Chung-Yu Wu2
1 2
Institute of Electrical Engineering Institute of Electronics,
National Tsing Hua University, National Chiao Tung University,
Hsinchu, Taiwan Hsinchu, Taiwan

Abstract—A new linear current mode image sensor is proposed pattern noise, however, is found to be significant. In order to
in this paper. The proposed circuit features high linearity, low suppress the fixed-pattern noise, the threshold voltage must
power consumption, programmable multiple gain stages, wide appear as the first order term in the output current equation.
input swing and correlated double sampling (CDS) technology. Therefore, the active device is usually designed to operate in
The signal swing of the linear current mode sensor is enhanced
the triode region, and the output current equation is shown as
by the proposed multiple gain readout structure. A simple and
accurate front-end programmable gain structure is proposed to equation (1).
improve the signal-to-noise ratio (SNR) with low power W⎡ 1 ⎤
I pix = μeff Ccox ⎢(Vsg − Vtp )Vsd − Vsd 2 ⎥ (1)
consumption. The function and performance has been verified L⎣ 2 ⎦
by HSPICE simulation of 0.18um 3T sensor process.
The transconductance of Mtr is given by equation(2)
W
I. INTRODUCTION g m = μeff Cox Vsd (2)
L
Recently, the current mode image sensor has been widely The ID-Vg characteristic of both n-type and p-type active
researched and implemented in the CMOS technologies [1-5]. devices are simulated in the circuit as shown in Fig. 2.
The current mode image sensor can easily implement the
arithmetic computation, such as additions, subtractions, and
multiplications. This can help to reduce the design complexity
of the back-end current mode ADC [6].
In image sensor readout, the fixed-pattern noise is usually
suppressed by the correlated double sampling (CDS) operation.
The CDS is usually implemented by current mirrors in current
mode readout. The accuracy of current mirror is a possible
issue when biased at a small signal (low light) or due to the
channel length modulation effect. Compared with voltage
mode readout, the current mode is usually suffered by the non-
linear response due to mobility degradation. Moreover, due to
the current operation request, the possible extra dc current
path needs to be well controlled for low power consumption.
In this paper, we proposed a new linear current mode Figure 1. The general current mode sensor pixel.
sensor. It achieves a programmable front-end gain, high
linearity, multiple-gain option and low power consumption
with CDS operation. The circuit structure and simulation
results are presented in the following.

II. THE PROPOSED LINEAR CURRENT-MODE IMAGER

A. Analysis of current mode pixel
In general, the current mode sensor pixel is composed of a
reset MOS (Mreset), a photodiode and an active device (Mtr),
as shown in Fig. 1. The active device serves as a front-end
gain stage to amplify the small signal current generated by Figure 2. (a) NMOS active device (b) PMOS active device.
photodiode. The effect of threshold voltage (Vt) on the fixed-

978-1-4244-3828-0/09/$25.00 ©2009 IEEE 1273

Authorized licensed use limited to: INDIAN INSTITUTE OF TECHNOLOGY DELHI. Downloaded on April 05,2022 at 20:16:59 UTC from IEEE Xplore. Restrictions apply.
 Figure 3. (a) NMOS Vg versus Ipix with different Vds
Figure 4. Vg versus gm with different channel length of PMOS active device

The current gain of the n-type active device would be

changed from low to high, and the current gain of the p-type
active device would be changed from high to low. It is found
that the PMOS active device can provide a gamma-like
transfer curve referred to the input light density. This will
result a better sensitivity in the low light and a higher dynamic
range. Therefore, the PMOS active device operated with a
smaller Vds is chosen to be a better choice in the application of
current mode sensor pixel.
From the Fig. 3(a) and (b), the Ipix reveals a better linearity
when Vds is increased and the active device is operated in the
Figure 3. (b) PMOS Vg versus Ipix with different Vsd saturation region. It is due to the velocity saturation effect in
deep submicron devices. The ID equation in saturation region
Fig. 3 (a) shows the relationship between Vg and output can be rewritten as [7]
current Ipix of the NMOS active device. The similar result can I D = ν satWCox (VGS − VT ) (5)
be also observed for the PMOS in Fig. 3(b) .The linearity is gm = ν satWCox (6)
not good when Vds is smaller than 1.8V due to the mobility
degradation [7]. With the mobility degradation effect as It is shown that the threshold voltage Vt appears as the first
described in equation (3), the drain current Ipix in the triode order term, and the Vt variation can be eliminated by the
region can be re-written as equation (4). following CDS operation. However, the necessary current is
μ0 too large and consume power when operates in the velocity
μeff = (3) saturation region. It can be chosen on applications need high
1 + θ (Vsg − Vt )
linearity but with adequate power consumption budget.
μ0 W ⎡ 1 2⎤
I pix = Ccox ⎢(Vsg − Vtp )Vsd − 2 Vsd ⎥ (4)
1 + θ (Vsg − Vt ) L ⎣ ⎦

As shown in equation (4), both the p-type and n-type active

device could not convert the Vpd to Ipix with perfect linearity. It
can be improved by utilizing the active device with a long
channel length [2]. The Fig. 4 shows that gm is more
independent of Vg change when the channel length is
increased. That is, the Vpd － Ipix linearity is improved with
longer channel length of the active device (Mtr). However,
there exists a tradeoff between the sensitivity and channel
length. The longer channel length would result in higher
capacitance in the Vpd.
The operation of the circuit in Fig. 1 is described as
following. First, the switch Mreset turns on and reset the node
Vpd to Vresetin. After a fixed integration period, Vpd would be
discharged by the photocurrent of the photodiode and Figure 5. NMOS and PMOS active device Vpd versus Ipix when Vds = 0.1V.
decreased from a high potential voltage to a low potential
voltage.

1274

Authorized licensed use limited to: INDIAN INSTITUTE OF TECHNOLOGY DELHI. Downloaded on April 05,2022 at 20:16:59 UTC from IEEE Xplore. Restrictions apply.
 Figure 6. The proposed linear current mode circuit.

B. Operation and analysis of the proposed gain pixel
The proposed programmable gain pixel is shown in Fig. 6
[3], which is composed of a NMOS transistor, a PMOS
transistor, an operational amplifier, and two NMOS
transistors. The active device Mtr acts as a transimpedance
amplifier. It converts and amplifies the diode signal Vpd to the
output current Ipix. The operation amplifier, M1 and M2
establish a negative feedback configuration and make Vi+
equal to Vref1. The output current Ipix is given by equation (7).
μ0 W ⎡
I pix = Ccox ⎢(Vsg − Vtp )Vsd − 2 Vsd ⎥ (7)
1 + θ (Vsg − Vt ) L ⎣
Vsg = Vref 2 − V pd
Vsd ≅ Vref 2 − Vref 1
The transconductance of Mtr is
μ0 W L
gm = Cox Vsd
1 + θ (Vsg − Vt ) L W
It is shown that the programmable gm, as well as current
gain, can be easily implemented by tuning Vsd, without extra
hardware. With the front-end gain stage, the signal current is
amplified and fed into the following current mirroring and
subtraction stage. It can improve the current operation
accuracy when the signal is small at low light condition.
Moreover, the SNR can be improved by the proposed front-
end gain stage.
The swing of Vpd is described in equation (11). Compared
to voltage mode readout, it shows an almost x2 signal swing,
that is, x2 full-well capacity based on a specified operating
supply voltage. The higher gain, set by a larger Vsd bias
condition, will decrease the available signal swing at node Vpd.
0 < V pd < Vref 2 − Vtp − Vsd
We propose a current-mode readout circuit with multiple-
gain device to solve this design tradeoff.
C. The proposed current mode readout circuit with
multiple-gain device
The proposed current mode readout circuit is shown in
Fig.6. The operation of the proposed current mode readout
circuit is described as following. First, the Vpd is reset to the
Vresetin by device Mreset. After a fixed period of integration time,
the amplified signal current Isig is readout and sampled at Cs.
Then, by turning on the reset Mreset, the Ireset is output and
mirrored to the Mr11. The correlated double sampling (CDS) is
implemented by the current subtraction Iout = Isig - Ireset , and
1 2⎤ the result is sampled to the current memory Mo [8] and stored
⎦ on the capacitor Cout. After the CDS operation, the output
current Iout can be described as following.
(8)
W ⎡ 1 2⎤
I sig = μ p Cox ⎢(Vref 2 − Vsig − Vtp )Vsd − 2 Vsd ⎥ (12)
(9) L ⎣ ⎦
W ⎡ 1 2⎤
I reset = μ p Cox ⎢(Vref 2 − Vreset − Vtp )Vsd − 2 Vsd ⎥ (13)
⎣ ⎦
(10)
I out = μ p Cox (Vreset − Vsig )Vsd (14)
L
The CDS function is used to eliminate the fixed-pattern
noise induced by the threshold voltage variation in pixel
circuit. It is shown in equation (14) that the threshold voltage
term is cancelled by the subtraction of two correlated
sampling. The cascode devices are used to enhance the
linearity and accuracy of the current mirror.
The bias voltages of cascode devices are self-generated
without additional circuit and dc path. Moreover, a low
standby power option is implemented by the switch swop. All
the dc current of current mirrors can be disabled after CDS
operation, and the operational amplifier will be disabled
synchronous. Therefore, there is no any dc current path in the
readout interval which results in an ultra-low power
(11)
consumption. The average power consumption of the
proposed current mode sensor depends on the clock period,
and it can be described as equation (15). PCDS is the average
power during CDS period (in this circuit about 3.2 × 10 −4 W),

1275

Authorized licensed use limited to: INDIAN INSTITUTE OF TECHNOLOGY DELHI. Downloaded on April 05,2022 at 20:16:59 UTC from IEEE Xplore. Restrictions apply.
 TCDS is the time during CDS period, and Ttotal is the total time
of a line time. For example, if the CDS interval is 5us and the
total time is 125us, the average power is 1.28 × 10 −5 W.
PCDS × TCDS (15)
Average power =
Ttotal
Figure 7. The control signal of the proposed current mode readout circuit
Figure 8. The photocurrent versus output current Iout.
Figure 9 The Vsd of the Mtr versus output current Iout with multiple-gain
option controlled by Mul.
Figure 10. (a) The chip micrograph (b) The measured linear gain tuned by
Vsd
The multiple-gain device is composed of Mr2, Mr22 Ms2,
Ms22 and a switch Mul as shown in Fig. 6. In the low light
level condition, the multiple-gain device can provide an
additional gain by switching on Mul. The total gain of the
proposed circuit can be enhanced. This additional gain option
can release the design tradeoff between frond-end gain setting
Vsd and the available signal swing.
1276
Authorized licensed use limited to: INDIAN INSTITUTE OF TECHNOLOGY DELHI. Downloaded on April 05,2022 at 20:16:59 UTC from IEEE Xplore. Restrictions apply.
III. SIMULATION RESULT
The proposed linear current mode imager has been
simulated with 0.18um 3.3V MOSFET SPICE model. The Fig.
7 shows the control signal of the proposed circuit. The Fig. 8
shows the output current from the proposed readout circuit for
different photocurrent, and the linearity is near 99.17%. The
shown input current range (0~12nA) in Fig. 8 is selected for
result demonstration. The largest input signal current range
depends on integration time, capacitance, and Vsd as well. The
gamma-like response curve is due to the PMOS active device
which can improve the dynamic range compared to linear
response voltage-mode readout. The simulated front-end gain
with different Vsd tuned by Vref1 is shown in Fig. 9. It shows a
x1 ~ x4 programmable current gain with a high linearity as
99.96%, and the additional x2 gain provided by multiple-gain
device MUL with a high linearity is also shown. Fig. 10(a) is
the micrograph of the 64x1 current-mode sensor test chip. The
pro-type silicon has been tested and the measurement result is
shown in Fig. 10(b). It shows a good linearity of the tunable
gain controlled by Vsd.
IV. CONCLUSION
A current mode readout circuit for CMOS sensor
including gain pixel and the multiple-gain device is proposed.
A programmable front-end gain and additional multiple-gain
option are implemented to solve the design tradeoff between
the signal gain and swing. It shows a good readout
performance with high gain, high linearity, high swing and
low power. The proposed circuit operates with no dc path and
consumes less power than the other circuits. The SNR in the
low-light level can also be improved. The proposed design is
suitable for the linear CMOS image sensor and two-
dimensional sensor array as well.
REFERENCES
[1] R.M. Philipp and R. Etienne-Cummings, “A 1V Current-Mode CMOS
Active Pixel Sensor,’’ Intl. Symp. Circuits and Systems 2005, Vol. 5,
pp. 4771-4774, May 2005.
[2] V. Gruev, R. Etienne-Cummings, and T. Horiuchi, “Linear current
mode imager with low fixed pattern noise,’’ Intl. Symp. Circuits and
Systems 2004, Vancouver Vol. IV, pp. 860-863, May 2004.
[3] R.M. Philipp, D. Orr, V. Gruev, J. Spiegel and R. Etienne-Cummings,
“Linear Current-Mode Active Pixel Sensor,’’ IEEEE. J. Solid-State
Circuits, vol. 42, pp. 2482-2491, NOV. 2007.
[4] J. Nakamura, et. al. “ On-Focal Plane Signal Processing For Current-
Mode Active Pixel Sensors ’’ IEEE Transactions on Electron Devices,
vol44,no. 10 ,pp.1747-1758, Oct. 1997.
[5] Z. Yang, V. Viktor and J. Spiegel, “Low Fixed Pattern Noise Current-
mode Imager Using Velocity Saturation Readout Transistors,’’ Intl.
Symp. Circuits and Systems 2007, pp. 2842-2845, May 2007.
[6] A. Agarwal, Y. Kim and S. Sonkusale, “Low Power Current Mode
ADC for CMOS Sensor IC,’’ Intl. Symp. Circuits and Systems 2005,
Vol. 1, pp. 584-587, May 2005.
[7] B. Razavi, Design of Analog CMOS Integrated Circuits, McGraw-Hill
Companies, Inc., 2001.
[8] S.J. Daubert, D. Vallancourt and Y.P. Tsavidis, “Current copier cells,’’
Electronics Letters, vol. 25, no. 10, pp.644-646, May 1989.
[9] V. Gruev, R.M. Philipp, J. Van der Spiegel and R. Etienne-Cummings,
“Image sensor with general spatial processing in a 3D integrated circuit
technology,’’ Intl. Symp. Circuits and Systems 2006, pp. 4, May 2006.