PRELIMINARY intel. 82526 CONTROLLER AREA NETWORK CHIP ‘Automotive = On-Board “MOTEL” 1 Global Interrupt Disable m Multimaster Architecture m Non-Destructive Bitwise Arbitration m Bus Access Priority by Message & Two 8-Bit 1/0 Ports © 2032 Different Message Objects @ NRZ Coding/Decoding with Bit Stuffing m Guaranteed Latency Time for High 1m Programmable Transfer Rate to Priority Messages 1 MBIt/Sec m Powerful Error Handling 1m Programmable Output Driver m Data Length to 8 Bytes Configuration m Message Configuration Flexibility m Programmable Clock Output um Broadcast Message Transfer eee m Ready Output @ Three Additional CS Outputs The 82626 Communication Controller is a highly integrated VLS! device which implements the CAN (Controller ‘Area Network) Protocol. Included on the chip are an Interface Management Processor (IMP), Bit Stream Processor (BSP), Sus Timing Logic (BTL), Transceiver Control Logic (TCL), Processor Interface Unit (PIU), Error Management Logic (EML), Clock Generator and a pseudo Dual Port RAM (DPRAM). These hardware modules implement all necessary features of a high performance serial communication protocol. When con- nected to a microprocessor, the 82526 performs the principal functions of the physical and data link layer. Figure 1 shows a block diagram of the 82526. ‘The 82526 uses an 8-bit multiplexed address and data bus optimized for operating with Intel's microcontrollers land microprocessors. Other architectures may also be used with the direct connect on board “MOTEL” circuitry. ’As shown in Figure 1, the BSP, TCL, BTL and EMAL are related with Bus Line Logic. The IMP, RAM and PIL are related to the CPU Interface Logic. The logic blocks BSP, BTL, TCL and EML are referred to as the “Serial Interface Unit”. ‘The CPU communicates with the 82526 through the on-chip pseudo dual port RAM which includes global status and control registers. The on-chip memory serves as the communication buffer interface between the CPU and the IMP. The CPU initializes the global status and control registers and creates a data structure (Communication Objects) within the communication buffer for reception and transmission of defined mes- sages. Commands, data and status transfers take place over the 8-bit parallel bus. The CPU writes data to the 82526 using CS, ALE and WA signals and reads the 82526 received data and status information using the CS, ALE and RD signals. The 82526 uses the interrupt line to alert the CPU of errors or data received. February 1992 3-40 (Order Number: 270573-00582526 PRELIMINARY (CPU INTERFACE RELATED BUS LINE RELATED 270873-1 Figure 1. 82526 Block Diagram WR S a P07 Pos. Pos Po Pos P02 Pot Poo oD ae 82526 a aap ice pis (ror vew) Ps wat va 0872-2 Figure 2, 44-PIN PLCC Package 3.41intel. fe PRELIMINARY ABSOLUTE MAXIMUM RATINGS Ambient Temperature under Bias = 40°C to + 125°C Storage Temperature —65°C to + 150°C ELECTRICAL CHARACTERISTICS DC CHARACTERISTICS Voc = 4.5V to +5.5V; Ta = 40°C to + 125°C Symbol Parameter Min | Typ Max Conditions [Vic | input Low Vottage Vss—05¥ oav (Allexcopt XTAL1) [Mar Input Low Voltage (XTAL1) Vss-0.5V 0.2Ve0-0.1 | Vin | Input High Vottage 20V Voo + 05 (Allexcept XTAL1, FST, ALE, CS) Vint Input High Voltage (FST) Voc + 0.5 Hysteresis on AST Vine __| Input High Voltage (ALE, CS) 05 Voc Veo + 05 Vira | input High Voltage (XTAL1) 07 Voc Voo + 05 Vo. | Output Low Vottage o4v | l= 16mA (All Outputs except ADO-7, INT, DY, CLKOUT, TXO, TX1) Voir | Output Low Voltage 04 | lo =32ma ___| ta00-7) Vou2 | Output Low Voitage av | t= Sma (ROY, INT) Von | OutputHigh Voltage | 5V Ton = —80 yA (All Outputs except ADO-7, C55, Si, CS2, 1X0, TX1, CLKOUT) Vout | Output High Voltage 06 Voc low = —400 nA (AD0-7, C30, C51, CBZ) ane Ton = 80 pA hic Input Leakage Current Vss < Vin < Voo (Except Port0/Portt) We Low Level Input Gurrent | 50 "A | Vin = 04V (Pono/Portt) | i Logical 1 to 0 Transition 750 WA | Vin= 2V Current (Port0/Portt) lct___| Latch-up Trigger Gurrent | £80mAa Cio_| Pin Capacitance 10 pF @1 MHz, 25°C tcc _| Supply Gurront ; 22mA |__33mA_| Fava, = 16MHe isM__| Sloop Mode Supply Current 12m] 22mA | Fra = 1 MHz “sma | 85mA_| Fxrar = 16MHz oc | Comparator Offset Current TMA [ec | comparator Bias Curent ta] 3-42intel. 82526 PRELIMINARY AC CHARACTERISTICS Conditions: Ta = —40°C to + 125°C, Vog = SV 10%, Vsg = OV, Port 2 outputs: CL = 150 pF, All other outputs: CL = 80 pF ‘Symbol Parameter Min Typ Max 4/Txrm._| Oscillator Frequency 1 MHz 16 MHz Tavur__| Address Valid to ALE Low 20ns Tuax__| Address Hold attor ALE Low 121s Tuov | ALE orTSt" Lowto 5 Txrat + 80 nst6) Valid Data Out Tanoz _| Data Float after AD Hi 6ns 50ns Truov | Valid Data Out Delay from 80 ns Read Control Tawi | Input Data Setup to WA 20ns High Twuox input Data Hold after WAL 18ns High Twaov | WR High to Output Data 4 Tata + 708 Valid on Port 0 or Port 1 Twau | WA High to Next ALE or 2Txrat + 5 ns. TS Low!t.2) Twawe_| Time between Writes atx + 508 Tuwn | ALE or St) Low to WA 4 Tata + 108 High Tata. | Time between ALE @TxtaL + 5 n8 Falling Edges (or CS") Tuy _ | End of ALE to RDY Setup [ 65ns Tun — | Endof ALE to RDY High(®) | 4Txrau + 65ns 6 Txrat + 65ns (with 1k External Pull-Up) Tres. | ALE orCS Lowto 45s SO-1-2 Lowlt. 5) THesH TS0.1-2 High after ALE 70ns of GS High(9.5) Taves | Address Valid to 40ns C50.1-2 Low) Tost | C8 Active Hold atter RD or WR High Ons NoTEs: 1. Whichove faling edge i ast 2, Some pipe.ining ofthe wna accesses is possible, This spec is important mainly when processor speed is higher than £82526 spoed (use ofthe ROY output) 8, Whichever rising edge comes frst 44 ROY le an open drain output a0 is IT) 5, Timings valid on ALE falling or rising edges only if ALE is used to strobe the TS0-1.2 outputs (default mode). If the other mode is programmed by writing 1 to bit 7 of address 253, the new state starts propagating to the CS0-1-2 outputs as soon as a stable address has been decoded (providing that CS is also valid). 6. Timing valid only when ALE is not used to stobe the CS0-t-2 outputs. In tis mode, Tucsu also applies on CS rising a Taste ape ust bo active low wih RD or WA rising edge for proper completion ofthe read or wre access 8. If Loy is too slow forthe host microcontroller, @ double read mochanism can be implementod. For detas, contact an Intl representative 3-43intel. 82526 PRELIMINARY al Layer Specifications Load Condition: 80 pF RXO/RX1 Min Max Conditions Input Voltage Ves — 0.5V Voo + 0.5V ‘Common Mode Range Veg + 1.0V Voc — 1.0V a Differential input Threshold | __£80 mV a TXO/TX15) Min Max Conditions ‘Source Current —3.0mA Vour = Voc — 0.4V =60mA Vout = Veo — 1.0V ‘Sink Current 10.0 mA Vour = 0.4V 20.0 mA, Vout = 1.0V Maximum Permitted Source —8.0 mA Current (TXO, TX1 Together) Maximum Permitted Sink 22.0 mA Current (TXO, TX1 Together) Rise Time 20ns @ Fall Time 15 ns 4) CLKOUT Specifications [eC 50) PF _ L Min Max Conditions: CLKOUT frequency (1/T) AXTAL/3009) 16 MHz Rise Time(4) 150 Fall Timel® 1508 Output Low Vottage 02 Voc — 0.1 ‘Output High Voltage | __ 07 Voc Output Duty Cycle is 50% if ani Glock Divider Register Not Equal ‘Output Duty Cycle Equal XTAL aay If Clock Divider Register Equal Internat Delay Time) | tan | Max | Minimum Diferentat | Common Mode tun) 187 ns 50 mV Vs + 1.0V to Voc ~ 1.0V tune) 1378 100 mv Ves # 1.0Vt0 Voo = 1.0¥ Ty 127 ns 100 mv Veg + 1.8V t0 Voo = 1.0V NoTes: 1, See Internal Delay Times. 2. The Internal Delay Time is given by the Sum: Yinernal logic) + 3. Four = Fxtaua with R= 1.2.46, ...2 x rand iyax = 1 4, Measured between 0.2 Voc ~ 0.1 and 0.7 Voc. 5. Push-pull mode, 6. The total delay time from transmit to sample point = teat! delay) ~ linterna delay) + Nextema! logic) + "propagation seta 3-44 intemal output diver) + {internal comparator)82526 intel. PRELIMINARY EXTERNAL CLOCK DRIVE Symbol Parameter Min Max Unite Tou. Oscillator Frequency 1 16 MHz Toucx High Time 20 ns Toucx Low Time 20 ns Toucn Rise Time 20 nS Toro Fall Time 20 ns EXTERNAL CLOCK DRIVE WAVEFORM 270873-10 Nye EXTERNAL ‘OSCILLATOR: SIGNAL wma | 2057911 Figure 1. External Clock Drive Configuration ‘AC TESTING INPUT, OUTPUT WAVEFORMS. Xow X_ anv. 0873-12 AC inputs during tasting avo crven at Voc OSV fora Logi "1" 1 Timing measurements ara made st Vig 1 Vo. ae fr a Logic "0 | 3-45 FLOAT WAVEFORMS Conn as Oo o toons For ting papoose « at wo moe Hal Sw Sep mara peor came owe eu when @ 100 mv change from tha Waded Von/ Vox Mvel occurs Toulon 2 420m82526 intel. READ ACCESS (TO DPRAM OR PORTO/PORT1) PRELIMINARY fost 270s79-3 270579-4intel. 82526 PRELIMINARY READY (RDY) OUTPUT TIMING Tuya ae ror oy 270819-5 TS0-1-2 OUTPUTS TIMING Mode programmed: outputs change on ALE or GS falling edge (whichever comes last). Thesy Tacs est Tres ate 0-1-2 270873-6 TS0-1-2 OUTPUTS TIMING ‘Mode programmed: outputs change when ALE is high. ae Port 270573-7, 3.47intel. 82526 PRELIMINARY FREQUENCY TRANSITION TIME FOR CLOCKOUT LOGIC “ | wore | [vera] 270573-8 NoTEs 1, Four = Frrat/Divider Register —> Four = Frat max Logie 2.Fout = Fxta, > Four ™ Fxrat/Dwvidor Registor 1.5 Ticrat I Divider Register = 2 (Divider Pegister — 1) XTAL if Divider Register > 2 RESET TIMING | Reavy Minimum 10 Oscillator Cycles Notes: 1, Ready must not be pulled low during reset 2. Reset liming measure trom rising edge to rising edge of OSC. DATA SHEET REVISION SUMMARY The following are the differences between the previous 82526 data sheet and this new data sheet (rev. -003): 1. log and lac added to page 3-42. 3-48