Middle East Technical University

Electrical-Electronics Engineering

EEE 414 – Introduction to Analog Integrated Circuits

Cadence IC Design Tutorial

Last updated on 2017-05-14 1

 TABLE OF CONTENTS

1. USING PC LABORATORY....................................................................................................................................3
1.1. Introduction ..............................................................................................................................................3
1.2. Running Cadence ......................................................................................................................................3
1.3. Setting Up Cadence Environment.............................................................................................................3
1.4. How to Log Out? .......................................................................................................................................3
2. SCHEMATIC ENTRY OF A CMOS INVERTER .......................................................................................................4
2.1. Create a New Library ................................................................................................................................4
2.2. Schematics of a CMOS Inverter ................................................................................................................5
2.3 Symbol of a CMOS Inverter .......................................................................................................................8
3. TRANSIENT SIMULATION OF SCHEMATIC ........................................................................................................9
4. BASICS OF LAYOUT DRAWING ........................................................................................................................13
4.1. What is LAYOUT? ....................................................................................................................................13
4.2. CMOS Process and Layout Drawing Step by Step...................................................................................13
4.2.1. Step 1 –Active Regions and Wells ............................................................................................13
4.2.2. Step 2 - Polysilicon ...................................................................................................................14
4.2.3. Step 3 – N+ and P+ Diffusion ...................................................................................................14
4.2.4. Step 4 - Contacts ......................................................................................................................14
4.2.5. Step 5 – Metal Deposition .......................................................................................................15
4.2.6. Final View.................................................................................................................................15
5. LAYOUT DRAWING USING CADENCE ..............................................................................................................16
5.1. Design Rules............................................................................................................................................16
5.1.1. Layers .......................................................................................................................................16
5.1.2. Design Rules Overview ............................................................................................................16
5.2. Layout of the Inverter .............................................................................................................................17
6. LAYOUT VERSUS SCHEMATIC CHECK (LVS) .....................................................................................................23
7. SIMULATION OF THE INVERTER LAYOUT........................................................................................................25
8. FULL DESIGN AND LAYOUT FLOW ..................................................................................................................28

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 1. USING PC LABORATORY

1.1. Introduction
There are 25 personal computers in the laboratory with Centos OS configuration. Cadence IC tools require the
use of Linux environment. You will therefore have to get familiar with using Linux OS. There are many
resources in the library and online. Remember to shut down Cadence when not in use.

1.2. Running Cadence

Cadence offers one of the most commonly used IC Design CAD (Computer-Aided-Design) tools. Cadence IC
Design suit contains many submodules, each of which is responsible for a different step in IC design flow. You
will practice with low-level (transistor level) design flows in the Cadence exercises.
1.2.1. Initializing Cadence Environment
With the steps in the previous part, you are connected to the server and ready to run Cadence. In order to run
Cadence for the first time, you need to initialize your working directory. For this purpose follow the next steps:
1. Turn on the computer if it is not, and log into Ubuntu by using your user name and password.
2. Open a terminal: Applications → System Tools → Terminal
3. mkdir Cadence
This will make a directory named Cadence.
4. cd Cadence
Enter newly created Cadence directory.
5. These commands below generate required files and folders to run Cadence first time.
source /sources/ic6.csh
xkit –tech xh018
6. Then you have to choose number metal layers we use in this technology. For the METALS module
choose “4” and for TopMETALS module choose “3” as show below. Your final module code must be
“1143”. You have to confirm the module code selection by writing “y” as shown below.

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 Run cadence for the first time, which is XFAB 180 nm technology with 6 metal and 1 poly layers.
So, you have a running cadence at the moment. Remember that, the previous steps are for initializing the
cadence for the first time, and they should be done once only. Now close cadence by File>Exit.
1.2.2. Running Cadence
You have initialized cadence in the previous part. After the first run, you need to do the following things to
run cadence:
1. Open a terminal
2. cd Cadence
3. source /sources/ic6.csh
4. xkit &
That is all. Cadence should be running.

1.3. How to Log Out?

When you log out, make sure that no programs are running. If cadence is running for example, close it (including
all windows). Then click on your name at upper right of the screen and click “Log out...”. After this, the login
screen should come back. So you logged out from Centos, and it waits for you to log-in again. Now you can
leave the lab.

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 2. SCHEMATIC ENTRY OF A CMOS INVERTER
In this tutorial, you will start using Cadence and design your first CMOS gate: An inverter. Believe or not, working
on the first inverter is the most important part of the overall laboratory work. You will learn a lot. Do not move on
to the next step until you have fully understood the previous. If you have a problem, do not hesitate to ask to your
instructor. You have to learn every step in this tutorial in order to be effective with your future CAD assignments.

2.1. Create a New Library

Before starting your first design, you need to create a library, which will contain all the circuits that you will
implement during this laboratory.

1. After you start Cadence Virtuoso

Tool, by typing the commands above
you should eventually see Cadence
IC design tool version 6.1.6
Overview window (on the right).
Close this window by clicking on
<File> and then <Close>. You should
now have the basic virtuoso window,
which looks like the one below.

2. Click on <Tools> and then <Library Manager> to start the library manager (below on the left):

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3. Click on <file>, <new>, and then click <library>.
4. Write down "EE414" to the name of the library as seen on the figure (above right). Click on
OK at the bottom.
5. Each library should be attached to a technology library (or technology file). A technology
library contains required information about the technology you are using, like DRC- Extraction-
LVS rules, contact dimensions, etc. We will be using XFAB 180 nm CMOS technology in our IC design
work this semester. On the newly appeared window, click on "Attach to an existing technology library" radio
button and click OK.
6. Again, a new window will pop up for selecting the technology library. Choose "TECH_XH018" from the
pull-down menu. This is the technology library for XFAB 180 nm process. Click on OK.

2.2. Schematics of a CMOS Inverter

After forming the new library, we will go on by making a new cell.

1. Click on library "EE414" you have added previously. On the library manager, there are 4 columns as you see.
Left most one contains the libraries; the middle one contains the categories of the cellviews, the next one
shows cellviews in the selected library, and the column on the right contains the views of the selected cell
view. Libraries are composed of cellviews (which are circuits that you will implement, like inverter, nand,
etc.). Each cellview should have different name in a library. Each cellview contains different views like
schematic, symbol, and layout. These are predefined names and you will learn what they are by following the
tutorials.
2. At the moment, there is no cellview in the "EE413" library yet. Click
on File –> New –> Cell View in order to create one. A small menu
should pop up (right). In the field for Cell, enter the name of the cell.
“inv” is used in this case. Although they are default, be sure that View
and Type are both "schematic". In the Application box that says
“Open with” click on the red pull down arrow. Then select
Schematics XL. Click on the box that says “always use this
application for this type of file”. Click OK. If you get a pop-up
window providing information about a license, click OK.

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3. Virtuoso Schematic Editing window should be opened. As default you will work with a black background.
Keep in mind this background is not ideal for printing/presentations. You can use the <Help> menu to change
colors whenever you need to include schematics/simulations to a report or get a printout. If a “Constraint
Manager” window pops up on the right side, you can close it for now.

4. First, add an NMOS

transistor. Select a
component by clicking
on the transistor symbol
(highlighted on the right
with a colored circle), or
press "I" from keyboard
for “insert”.

5. Click Browse in the small selection screen to choose “PRIMLIB” library under XFABLibs, “ne3” (basic N-
channel MOSFET that is tuned for 3.3 VDD supply) cell, and “symbol” view, as depicted below (left).

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 Width, length and other properties of the transistor can be changed in the open “Add Instance” window shown
above (right). Set total width= 2 um (should be the default) and leave length as default (minimum) size for
the time being (350nm). You may also add a specific instance name (m1, m2, etc.) for your transistor. If not,
a name will be assigned for you. You can now hide the “Add Instance” window by clicking on “Hide” below.
Move to the schematic editor, and insert one NMOS transistor by clicking anywhere in the window. Do the
same thing for "pe3" cell but change the total width to be 2 um, and then insert one PMOS transistor. Since
you are building a CMOS inverter, place the PMOS transistor to the top for better readability. Notice the cell
names appear on the left in a tree list, and the property editor is below that. You can just click on any device
name in the cell name list, and the properties will show up in the property editor. The device properties can
also be changed in the property editor (device sizes, names, etc).
6. Now select a component for vdd and gnd. And place them on the schematic. These are found in analogLib.
7. Select the symbol next (second from top right) to create pin. This may already be visible on your terminal if
your schematic editor window is large enough, or you will need to click on the >> symbol at the top right to
see the full symbolic menu options. Alternately, you could click on <create> and then <pin> items in the
menu. The tool bars generally allow single click selection. Give the pin a name, and select the desired
direction. In this case upper case ‘A’ (without quotes) for the name, and input for the direction. Upper and
lower case matter in some tools and not in others in the design system. It is important to always use the same
case in the names throughout the design to avoid problems. More than one pin of the same type can be entered.
Just put spaces between the names. If multiple signals will be connected together as is often the case in analog
design, then the direction should be input-output, not output. Place the pin on the schematic. Next, create an
output pin called upper case ‘Q’ (without quotes) and place it on the schematic.
8. Now time to add some wire to the schematic. The single width wire is just to the right of the transistor symbol.
Click on it (or use the short-cut “w” for wire), and then move the cursor to the first point to be wired. It should
highlight with a yellow diamond. Click, and then move the pointer to the second point and click to draw the
wire. Repeat this process to wire the schematic as shown below. You may not need to click on the thin wire
symbol each time as long as you stay in wiring mode. Cadence doesn't allow 4 connections at a point. If you
make a mistake, then press the escape key. Click on the wire in error if any is left, and then click on edit, then
delete. Now, click on the floppy disk with the green arrow (circled below). This will check for any un-
connected pin, and save the design. If you get some warning messages in the log window (the first window
that Cadence started with), check the yellow markers. If there is no problem, you will not get any warning or
error.

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2.3 Symbol of a CMOS Inverter

1. Every cell should have a symbol view in order to be used in other circuits. Click on <Create> in the schematic
editor; then cursor over to <Cellview> then choose <From Cellview>. Make sure the selection for “From
View Name” is “schematic” and “To View Name” is symbol (it normally is), and the Tool/Data Type is
“schematicSymbol”. Click on OK. This brings up a screen with the pins on the top, bottom, left and right.
You can move them where you like. If they are fine, you can click OK.
2. This opens the symbol editor, as depicted below. One can draw his/her own symbol by using tools in the top
menu, but it is not necessary. One can also select <Import> under <Create> pull-down menu to pick an
existing symbol in one of the libraries, modify it, and/or rename its pins. If you like the symbol, just press the
check and save floppy disk symbol with the green check mark. At this point, the symbol is created, so just
click on <file> and then click on <close>. The schematic and symbol views for the inverter are completed, so
close schematics window as well by switching to the Virtuoso Schematic Editor, and clicking on <file> and
then <close>. You can also close the schematic view.

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 3. TRANSIENT SIMULATION OF SCHEMATIC
The library manager should be on the screen, or it may be minimized on the toolbar. If so, bring it up on the screen.
In this section, you will simulate the schematics, and observe its characteristics. You need to define a test bench
that defines input, output, vdd, and gnd.
1. Click on <File>, <New>, then <Cellview>. Name this
schematic sheet inv_tb (for test bench). Use tool schematic Library Cell Name
XL, and close to open the schematic editor. Add the EE414 inv
components in the table (on the right), and draw the circuit
analogLib vdd
in the below figure. "vdc" will be used to apply VDD voltage.
"vpulse" will be used for applying a square wave to the input analogLib gnd
of the inverter and "cap" is capacitive load. analogLib vdc
analogLib vpulse
analogLib cap

2. Click on "vdc" and right click to change properties. Write "3.3" to "DC Voltage".
3. Set up the vpulse for a 1ns pulse train. You may have to scroll up and down to get to all the DC parameters.
The first set of things are for AC analysis. Voltage 1 is 0 V, Voltage 2 is 3.3 V, Period is 2n s, Rise and Fall
times are 50p s, and Pulse width is 1n s (note how the magnitude of numbers are listed with the number with
no spacing, while the units are listed after a space character).
4. Set capacitor value to 5 fF as inverter load.
5. It is in general a good idea to label important wires (e.g. input and output nodes) to help later in the simulation
and debug. Take a few moments, and give these nets a name. Use the <Create> <Wirename> option, or on
this window symbol menu click on the wire with abc above it. For example, you can label the inverter input
node “IN”, and output node “OUT”. The two signal names are typed as a list (with a space character in
between) in “Add Wire Name” tool. Then place the cursor over a wire and click. The name should switch to
the next one on the list.

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6. The pull-down menu gets updated once
you check and save the schematic. Click
on <Launch>, then <ADE XL>. When
the menu appears, select “Create New
View”. The setup should be OK. Click
on OK in the pop-up window. If a
message pops up to ask you to use GXL
tool instead for your licence, accept it.
You should now get the following
window (on the right):

7. To get to the design, click on the tab <inv_tb>. Click <ADE XL> from the top window menu, then <Create>
and <Test>. Two windows will pop up. Select “inv_tb” in “Choosing Design” window; click OK.
8. In the next window, setup the simulation by clicking on “Choose Analysis” button (circled below.) This pops
up a window with the simulation options. Make sure the transient analysis (tran) is selected, and set it up for
“10n” of simulation time (through Stop Time entry). All EE414 simulations should be performed in
conservative mode. Click OK. The simulation shows up in Test Editor as below. Note any given simulation
on the list can be enabled or disabled with the check mark.

9. Now, select the outputs. Click on top menu option <Outputs>, <To Be Plotted>, <Select On Design>. This
will select the schematic editor. There, you can click on the wires for the signals desired. If you want currents,
click on the terminals, and a circle is drawn on the schematic indicating what has been selected. For example,
you can select inverter input and output node voltages, and supply current at VO + terminal. This is the upper
terminal of the DC voltage supply. It is a good idea to monitor the current through the main voltage supply
for a design with power dissipation constraint. When you go back to the simulation setup screen, you should
see:

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10. Click top menu option <Session> and “ok” to save the state with the defaults. Click on <Session><Quit>.
11. Bring up the “adexl” tab in the ADE XL Editing window. On the left, you will see the simulation description
you just set up. Click on inv_tb under Tests to highlight. To the right of the upper symbol menu of the window
is a green circle with a play type button (triangle shape). Click on this to run the simulation. It may take a
while, but eventually the simulation will finish and a display screen will appear as below. If the visualization
window does not show up, you can select the test outputs and click on the waveform icon in the “Results” tab
under the “adexl” tab. Explore the display capabilities to find out how you can split the graph with 3
waveforms into 2 graphs, one for voltage values, and one for supply current, as depicted in the provided
figure.

12. When you are done, you can shut down the graph window, and the ADE XL for now. Click on <File> then
<Close> to shutdown the tool.

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 4. BASICS OF LAYOUT DRAWING
Till now, you designed your circuit and simulated it in the virtual environment. In order to prepare your design for
fabrication, you need to draw the layout for it. Layout drawing is not as easy as drawing wires in the schematics
because one needs to consider the real (physical) structure of the circuit. Layout drawing is quite an important
technical task, as well as art work. “Mask Designer” is the traditional job title in the VLSI design centers for those
who specialize in layout drawing.

4.1. What is LAYOUT?

Layout work involves drawing of masks to be used during the fabrication of the CMOS chips. Masks are filters
used to shape various layers. Each layer in CMOS fabrication, such as polysilicon layer or metal layer, is shaped
with a different mask. Considering our purpose as the designer, we have the ability to change very restricted
number of variables during design. For instance, we cannot change the thickness of the oxide layer in the gate, but
we can change the width of the gate. During layout drawing, we will thus in general consider only the width and
length of a layer, not the thickness.

4.2. CMOS Process and Layout Drawing Step by Step

In this part, we will consider the steps of layout drawing of
a CMOS inverter seen in the figure on the right. CMOS
process steps are much more complex than the ones we will
consider in this part. We are skipping many steps since we
do not need to know about these details as the circuit
designers. At each step, the physical structure and the
layout corresponding to this physical structure are given;
and then the process is explained.

4.2.1. Step 1 –Active Regions and Wells

Let's start the CMOS process flow. We have a p-type substrate with single well technology, which means that
NMOS transistors are implemented on p-type substrate, and PMOS transistors are implemented on NWELLs.
Nwells are the n-type doped regions as seen in the figure above. Normally, front sides of the wafers are initially
covered with very thick SiO2 layer (or Si3N4 layer) except the regions where some active elements, like the
transistors, will be implemented. A mask is used to shape these openings, which are called as Active Regions.
Another mask is used to shape the Nwell region. So, two layers are drawn in the layout.

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4.2.2. Step 2 - Polysilicon

Next step is to grow and shape polysilicon layers, which will form the gate of the transistor. For this purpose, we
need to draw one mask only, which is colored as green.

4.2.3. Step 3 – N+ and P+ Diffusion

In this step, n+ and p+ regions will be doped. Doping is done on entire wafer surface. Since SiO2 and PolySilicon
do not pass dopands (or impurities) to the substrate, these regions are not doped. First, a mask is used to determine
the regions to be doped with p+ impurities. After p+ doping, the rest of the surface is doped by n+ dopands. So,
only one mask is used.

One important point should be stated here. Nwell regions should be biased to high potential and p-substrate should
be biased to lowest potential in order to minimize the leakage current on the diode formed by Nwell and p-
substrate. For this purpose, a structure like the figure above is used, where the Nwell is biased with the same
potential to the p+ region on the left. Note that, contact to the Nwell should be n+ in order to decrease schottky
effect. See the p+ doping region mask on the right.

4.2.4. Step 4 - Contacts

As the next step, the entire wafer surface is again covered by a thick oxide layer in order to prevent the shorts

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between the substrate and metal layer deposited in the next steps. In order to take connection to the substrate, one
should use contacts, which are openings in the oxide layer. There are 3 different contacts. This contact is the first
one and it connects the substrate to the metal layer (metal layer is not shown here, it will be grown in the next
step).
Oxide layer is grown to the whole wafer surface and then the contacts are etched away. So, only contact openings
should be masked as seen on the right.

4.2.5. Step 5 – Metal Deposition

We are almost done with the process. The metal layer is grown and shaped in this step. Note that, the metals where
a contact exists touches to the substrate.

4.2.6. Final View

This is it. The process is completed and our layout is ready. As you see, layout is somehow similar to the top view
of a chip.
Remember the definition of the layout stated at the beginning of the tutorial. It is combination of masks used
during the process of the chip. So as the designer, you give the shapes of the layers that you want, and the process
engineer produces the corresponding chip for you. From the designer point of view, you do not deal with the
thickness of the layers, but you have to develop the x-y dimensions of the shape of the layers. So you are in a 2-
D world.

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 5. LAYOUT DRAWING USING CADENCE
In the previous part, layout drawing basics were provided. In this part of the tutorial, the layout will be drawn from
scratch using Cadence. At the end of the tutorial, the design will be checked in order to verify the physical structure
of the drawn layout.
5.1. Design Rules

XFAB 180 nm, 6 Metal 1 Poly NWELL process will be used (XFAB XH018). Each technology has its own layout
design rules, and they should be satisfied for successful production. Design Rule Check (DRC) tools are used to
determine whether the design rules are satisfied or not.

The following parts summarize the descriptions of the layers first, and then give the most important design rules.

5.1.1. Layers
There are a number of layers to be used in the layout view. Some of these layers, and abbreviated names are
summarized below:

 NWELL represents nwell

 DIFF represents "active" layer, active layers are regions on which transistors can be grown
 POLY1 represents the gate poly layer, which is used for constructing gates of transistors; it is a conductor
 PIMP represents p+ doping region
 NIMP represents n+ doping region
 CONT represents openings in oxide, which are used to get contacts between different layers like activemetal,
polymetal
 MET1 represents the first metal layer which is the main conducting path for routing
 MET2-4 represents second to fourth metal layers which provide alternative conducting paths for routing.
Since the metal layers are isolated with oxide, two different conduction paths routed with different metals can
cross over each other.
 METTP and METTPL represents two top metal layers
 VIA1 represents an opening in oxide between Metal 1 and Metal 2, hence connecting Metal 1 and Metal 2.

5.1.2. Design Rules Overview

The table below shows the design rules for various layers. Minimum width shows the minimum producible width
of the layers. Spacing and notch similarly show the minimum spacing and notch spaces of the layers.

Minimum
LAYER MIN. WIDTH (µM) SPACING (µM) Spacing
NWELL 0.86 0.6
DIFF 0.22 0.28 Minimum
POLY1 0.18 0.25 Width
CONT 0.22 0.25
MET1 0.23 0.23
Notch
MET2 0.28 0.28
VIA1 0.26 0.26

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Further design rules are stated below which are required for drawing a transistor. At the moment, you may not
understand all of the rules here. You will learn all of these rules while drawing the layout of the inverter. The
figure below illustrates the design rules.

1. Minimum GATE length 0.18 µ

NWELL
2. Minimum POLY1 extension of GATE 0.22 µ
3. Minimum DIFF – POLY1 spacing 0.1 µ
MET1 PO1
4. Minimum GATE width 0.2 µ (3) DIFF
5. Minimum PIMP extension of DIFF 0.18 µ CONT
6. Minimum NWELL extension of DIFF 0.43 µ PIMP (4)
7. Minimum DIFFUSION CONTACT to GATE (5) (7) (8) (6)
spacing 0.16 µ
(2)
8. Minimum DIFF extension of DIFFUSION
CONTACT 0.2 µ
(1)
9. Minimum PIMP extension of DIFFUSION
CONTACT 0.12 µ
You may not understand the meaning of this figure at the moment. Do not worry; you will go through all the steps
in the next part. Come back to this figure after you complete the whole tutorial.

5.2. Layout of the Inverter

1 . Open the library manager window (It may be minimized, but should still be open). Click on your library
EE414, then on the inv. This should show schematic and symbol. If you just double click on schematic, it
will open a lower level schematic editor. For most work, you should use the XL version of the editor. To
get this editor, right click on the schematic, and then use <Open With>. In the Application area, click on
the red down arrow, and select schematics XL. You can click “Always use this application for this type of
file”, but it doesn't seem to remember it all the time. Click OK. The schematic editor will appear.
2 . Click <Launch>, and <Layout XL>. The following will pop up:

Make sure “Create New” is selected, and click OK. Make sure the cell is inv in the next pop-up window,
and click OK. If any “Upgrade Licence” window pops up, select 'Yes' and continue. After a moment, you
should have a screen that contains the schematic on one side, and the layout on the other side. On the very

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 top of the layout window the title bar should say “Layout XL Editing: EEE413 inv layout”.
3. In the layout, you will only see frames of the layout cells, but not the details. Let's fix this: From the
Virtuoso <Options> menu, choose <Display> to open up the Display Options window. Set “Display Levels
Stop” to 10 as below. Virtuoso works with the placement grid, which is specified in the “Grid Controls”
menu. In our case, the objects are placed on a 10nm grid. Generally, the grid is about 5-10% of the
minimum feature size (180nm for our technology). It is recommended, for the purposes of this exercise,
to use Minor Spacing of 0.1, Major Spacing of 2, X-Y Snap Spacings of 0.005. In the “Display Controls”,
you can selectively choose which objects will be visible in the layout. Now click OK.

Now we can start drawing the layout of the inverter.

4. For transistor placement you can use add instance like the one in the schematic case but you should choose
layout as the view of the component. Width, length and other properties of the transistor can be changed in
this window, or you can leave default (minimum) sizes for the time being and change them later. You may
also add a specific name (m1, m2, etc.) for your transistor. If not, a name will be assigned for you. You can
now hide the “Add Instance” window by clicking on Hide below. Move to the layput editor, and insert one
NMOS transistor (ne3). Do the same thing for (pe3) cell, and insert one PMOS transistor. Since you are
building an inverter, put PMOS transistor to the top for better readability. The device properties can be
changed in the property editor. (Device sizes, names, etc). For our case we use 2 µm and 0.35 µm as width
and length of both NMOS and PMOS transistors. If you observe the transistor as a black box, you can press
shift+F to obtain regular view of the transistors. Another option to generate transistor is directly pick and
place them from schematic. In order to do this click Connectivity  Generate  Selected From Source.
Then select corresponding transistor from schematic and place it to the layout by clicking the layout window.
By this way transistor sizes are automatically determined with the schematic circuit.

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 5. Another point is the bulk connections. As you know, transistors are 4 terminal devices. The 4th terminal of
an NMOS transistor is the p-substrate, while that of PMOS transistor is the N-well. Since all the wafer is
(hence all the transistors are) built on the same substrate, all NMOS transistors must have the same bulk
terminal, which is the most negative voltage level in the circuit: ground, so you should consider threshold
variation effects for transistors whose most negative terminals are connected to voltages other than ground.
Similarly all the transistors in the same N-well have one common bulk terminal (usually VDD). However,
one can place isolated N-wells and can have different bulk voltages for isolated PMOS transistors. Although
this is possible, it is usually impractical to place isolated wells, since they should be placed apart from each
other.
6. We will also place one other contact for the bulk. In order to bypass Schottky diode effects (metal to silicon
direct connection), one should dope the silicon to guarantee a resistive contact (also consider latch-up). For
an NMOS transistor, bulk connection is made to the p-substrate, so we should dope the active layer with P+
for a resistive contact; similarly for a PMOS transistor, bulk connection is made to the N-well, so we should
dope the active layer below the contact with N+. Remember the discussion above (PPLUS layer is
implemented with a positive mask, while NPLUS layer is implemented with a negative mask), you can
conclude that we have to draw a PPLUS layer around the bulk contact for an NMOS transistor and NPLUS
layer around the bulk contact for a PMOS transistor.
7. To add the bulk connections you can use vias by clicking “Create”>>“Via” (or simply use “o” as short-cut).
A new window will be opened, here choose “Via Definition” as “ND_C” and “PD_C” for bulk connections
of PMOS and NMOS, respectively. You can increase number of contacts at the bulk by increasing the row
and column numbers at the same window (See Step 9). The figure below displays 3.3 V regular threshold
voltage PMOS and NMOS transistors with bulk connections on the left.

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 8. Now we have two transistors, what is left is connecting them together. We need to route power lines “VDD”
and “ground”, then connect the input “A” and output “Q”. This process is specified as six metal, one poly,
hence there are six different metal layers that can be used as conducting paths; however we are going to use
only four metal layers at this course. Since the resistance of polysilicon (POLY1) is high it is not preferred
to use it as a conducting path. In order to connect gates of PMOS and NMOS transistors “M1” layer is used.
The convention for two metal processes are routing power lines (VDD, gnd) with the first metal, and routing
signal paths (like input “A”, and output “Q”) with second metal. Hence, we will make metal 2 contacts for
“A” and “Q”. To create these vias select Create->Via. A window similar to the figure below will pop up.
There are a number of via types:

P1_C: Connection between POLY1 and MET1.

VIA1_C : Connection between MET1 and MET2.

So you may choose VIA1_C via from “Via Definition” section for input and output terminals. You can
also change width and length of the via and number of contacts used at the via.

As you may consider, we have not assigned names for the power or signal lines (remember ports in the
schematic) yet. In this step we will create pins for "vdd!, gnd!, A, Q" (the "!" signs are necessary). Click
Create->Pin. The following window pops up:

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 9. Write “vdd!” in "Terminal Name" field,
check “Display Terminal Name” and
check “inputoutput” in “I/O Type” list.
Click on “Display Terminal Name
Option” and write 0.5 as the height of the
terminal name. Then click hide. Select
“MET1” as the layer from the “Layers”
window. Draw a rectangle right onto the
metal line at the top of the layout (zoom
in with the right mouse button, in order
to place that exactly). Similarly place a
“gnd!” pin on the metal line at the
bottom.
10. To create input and output pins select
“MET2” as the layer and check “input”
and “output” as the “I/O Type”
respectively. When you are done "Hide"
the pop up window and draw ME2
rectangles to input and output. To check
the LVS of the layout properly we should
label the lines also. Click Create->Label and label all input, output and inputoutput lines with associated
label (MET1 for vdd! and gnd!, MET2 for A and Q). The final version of the layout is as follow:

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 11. Now we have to check whether we have violated any design rules or not. This step is called as the DRC and
is very important; any DRC error must be corrected before the layout is completed. In order to make DRC
we are using the Assura tool. After you click <Assura><Run_DRC> following window will be pop-up.
Be sure that you have saved schematic and layout of the design and click “OK” to run drc. Be sure that
there were no DRC error at your design before proceeding to next step.

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 6. LAYOUT VERSUS SCHEMATİC CHECK (LVS)
Till now, you designed the schematics and layout of a CMOS inverter. However, you did not check yet whether
the drawn layout is same as the schematics. In order to check whether the schematics and the layout are same, a
special check mechanism is used called as LVS. What it does is to compare the netlists of the schematic view and
the extracted view.
1. Click <Assura> <Run LVS>. The window below will pop up:

2. Give a random run name like “inv_LVS” and write “./AssuraLVS” as the Run Directory. Then choose
Technology as “XH018_1143” and the Rule Set as “default” the remaining parts are going to be filled
automatically. Then click “OK”.
3. After a short while, you will have a message box stating that the LVS check is completed. Figure below
shows the window that is showing that schematic and Layout matched. Note: There is an recent bug about
“unbound pin” errors in the layout. If you get mismatches in pins due to this error, most likely you did not
do the workaround correctly in the pin labeling step for input A and output Q pins. Remember to use
CreateLabel to label these pins in the layout.

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 4. After you click on “YES” LVS Debug window which is shown below will pop up:

5. If you have LVS error you can see the LVS report by clicking on <View> <LVS Error Report (Current
Cell)>.

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 7. SIMULATION OF THE INVERTER LAYOUT
In this tutorial, we will simulate the layout of the inverter, and see the differences, if any, compared to the schematic
simulation you completed earlier. This involves extraction of the actual parasitic components (e.g. resistive,
capacitive elements) based on the shapes drawn in the layout, and is therefore is in general more accurate than the
schematic simulation, which assumes some standard parasitic model. For the layout simulation we have to first
generate netlist with parasitic components through the process of extraction. For instance, the capacitance of the
metal lines crossing over another can be extracted, and added to the extracted view.

First let's generate extracted view of the layout:

1. Click on <QRC> <Run Assura-Quantus QRC>. A new window will be opened like shown on the figure
below. Choose Technology and Rule Set as "XH018_1143" and "default", respectively. Change the Output
to "Extracted View" and uncheck "Enable CellView Check".

2. Switch to the Extraction tab and select "Schematic Names" as the Name Space and write "gnd!" to the Ref
Node. Then click "OK".

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 3. After a short while you will get the message that extraction was completed. Now you can see your new
extracted cell view (analog_extracted) at the library. When you open that cell view by double clicking on
it you can you can see the extracted view of the layout similar to the one shown below.

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The extracted view of the layout is generated, in order to simulate layout of the inverter we are going to use inv_tb
schematic which we generated earlier.

4. Open the schematic of "inv_tb"

5. Arrange the vpulse such that it gives a square wave between 0 and 3.3 V, and with frequency 500 MHz.
Use a load of 5 fF (this should be already done from previous steps).
6. “Launch” <ADE XL>, using existing. Then select <Create> and <Test> under it. Two windows will pop
up. Select “inv_tb” in “Choosing Design” window; click OK.
7. Click <Setup> and <Environment>.
8. There is a list named Switch View List, this list determines the order of views Analog Environment will
search for. Priority is from left to right, so type av_extracted at the first place. Then click OK.

9. Select the analyses type as "tran" and enter "10n " for the simulation time.
10. Click <Output> <To be Plotted> <Select on Schematic>.
11. Click on the input and output wires of the inverter in the schematic, and click “OK” in the previous window
where the signals to be plotted have been annotated.
12. Simulate.

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 8. FULL DESIGN & LAYOUT FLOW
In the previous parts, you completed a simple transistor level design. Check the following design flow, and try to
understand which parts you have completed in the previous chapters.

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